1308390 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種金屬氧化半導體裝置及其製作方法， 詳言之，係關於一種具共振帶間穿隧二極體之金屬氧化半 導體裝置及其製作方法。 【先前技術】 習知技術中，可使用一電阻與一共振帶間穿隧二極體串 接之電路，用以產生兩個穩態工作點。該習知電路之該等 穩態工作點，其需將該電阻做得夠大，使負載線趨近水 平。但較大之該電阻會使負載電流降低，而使該電路無法 產生該等穩態工作點。因此，該習知電路必須使用較大電 壓及較大之該電阻，以得到該等雙穩態工作點’故該習知 電路會有操作電壓過大之問題。 另外，該4穩恶工作點之躍遷特性會因使用之該電阻作 為負載線而造成不對稱。該共振帶間穿隧二極體之特性曲 線斜率越大，則雙穩態點躍遷特性會越不對稱，將造成設 計電路時，脈衝電路須有不同準位之正脈衝及負脈衝，故 無法有效應用於實際電路。再者，需使用較大操作電壓， U成該電阻前端（接正電壓源端）之電壓會超過一般M〇S元 件之門檻電壓，故需另填入氧化物以壓制閘極因超過門檻 電壓而產生的電流。 因此，有必要提供一種創新且具進步性的具共振帶間穿 隧一極體之金屬氧化半導體裝置及其製作方法，以解決上 述問題。 111414.doc 1308390 【發明内容】 本發明之目的在於提供 屬氧化半導體” b $間牙随二極體之金 …該半導體裝置包括-基板、-第-氧 曰一共振帶間穿隧二極體、^ ^ u餸'一第一軋化層、一半導體 U三氧化層、-第二閘極層及-第四氧化層。= 板具有—第-源極部、1^ Hu 第一汲極部及一第一通道層，該 邊。哕第°,Γ弟—汲極部係形成於該第一通道層之兩側 1= 成於該基板上。該共振帶間穿随二極 及接觸Γ括一第一開極層、一共振帶間穿降二極體層 及-接觸層’該第一閘極 露該第-源極部及該第1=刀該第一乳化層’以顯 ^ 及極°卩上方相對位置之部分該第 乳化層，该共振帶間f随二極體層形成於該第一間極層 上4接觸層形成於該共振帶間穿随二極 氧化層形成於該接觸層 增 /弟- 及+導體層形成於該第二氧化 層上、’該半導體層具有-第二源極部、-第二汲極部及一 第-通道層’該第二源極部及該第二汲極部係形成於該第 二通道層之兩側邊。該第三氧化層形成於該第二通道層 上。該第二閘極層形成於該第三氧化層上。該第四氧化層 形成於該第二閘極層上。 本發明使刪元件具高速切換之功效，另外，也可使 M〇S元件更加微小化°特別是在門梭電壓（threshold 德㈨較低的刪元件’本發明之具共振帶間穿隧二極 體之金屬氧化半導體裝置，更具有優良的抗雜訊干擾能 力。另外’本發明之金屬氧化半導體裝置可改善傳統金屬 111414.doc 1308390 氧化半導體在工作時閘極電壓操作過小時，因雜訊干擾造 成間極電壓㈣’相對於原間極電㈣作比例甚大，並造 成工作電流大幅度地偏移，而影響電流控制器或數位電路 邏輯之問題。 本發明之另一目的在於提供一種具共振帶間穿隧二極體 之金屬氧化半導體裝置之製作方法。該製作方法包括以下 步驟：（a)提供一基板；（b)形成一第一氧化層於該基板 上；（c)形成一共振帶間穿隧二極體於該第一氧化層上，該 共振帶間穿隧二極體由下而上包括一第一閘極層、一共振 帶間穿隧二極體層及一接觸層；（幻形成一第二氧化層於該 共振帶間穿隧二極體上；（幻形成一半導體層於該第二氧化 層上；⑴形成一第三氧化層於該半導體層上；（g)形成一 第二閘極層於該第三氧化層上；（11)形成一第四氧化層於該 第二閘極層上；⑴以該第三氧化層為終止層，移除部分該 第四氧化層及部分該第二閘極層；⑴以該第一氧化層為終 止層’移除部分該第三氧化層、部分該半導體層、部分該 第二氧化層及部分該共振帶間穿隧二極體；（k)形成一第一 源極部及一第一汲極部於該基板，且形成一第二源極部及 一第二沒極部於該半導體層；⑴移除部分該第三氧化層及 部分該半導體層；及（m)以該第一閘極層為終止層，移除 部分該第四氧化層、部分該第二閘極層、部分該第三氧化 層、部分該半導體層、部分該第二氧化層、部分該接觸層 及部分該共振帶間穿隧二極體層。 本發明之金屬氧化半導體裝置可改善傳統金屬氧化半導 111414.doc •9- 1308390 體在進行切換時，因迴轉率（slew rate)的影響，從截止到 工作區間’經過—次臨界區域（sub-threshold region)時該 几件次臨界因子過大，電流驅動力較小而使得該元件要達 到穩態工作區的時間拉長，或該元件的切換速度過慢，以 及母次切換都要耗去極大的暫態或過渡時間（transient μ transition time)之問題。另外，本發明之金屬氧化半導體 裝置在閘極電壓操作許多小時後，亦不會有電流工作點之 雜訊飄移之問題。 此外，依序沉積出之該共振帶間穿隧二極體及低摻雜之 半導體層作為電阻，該共振帶間穿隨二極體與該電阻串聯 時，在適當操作電壓下會產±兩個穩態工作，點（一為電壓 南態，一為電壓低態）’且該等穩態工作點除非在足夠大 的激勵電流下才會跳至另一工作點，亦即該金屬氧化半導 體裝置具有較強抗干擾或雜訊的特性。㈣，閘極電壓因 會因該共振帶間穿隧二極體元 雜訊變動造成的電位改變 而消失，而使閘極電壓被箝制 無論閘極電壓操作多小時，電 件與該電阻串聯的電路特性 在一絕對穩定的電壓，亦即 流工作仍不會因雜訊而飄移。因&，穩態工作點除非在足 夠大的激勵電流下跳至另-工作點，其躍遷過程為穿随現 象’故能帶來極快的工作點切換(電壓高態和電壓低離的 切換)，故可使該金屬氧化半導體裝置亦具有高速的：換 過程，而克服傳統的迴轉限制。 【實施方式】 參考圖1A至圖1E， 其顯示本發明具共振帶間穿隧二極 111414.doc 10 1308390 體之金屬氧化半導體裝置之製作方法示意圖。參考圖ΙΑ， 首先提供一基板11，該基板11可為矽、鍺或III-V族晶圓基 板等。接著，形成一第一氧化層12於該基板11上。接著， 形成一共振帶間穿隧二極體13於該第一氧化層12上，該共 振帶間穿隧二極體13由下而上包括一第一閘極層131、一 共振帶間穿隧二極體層138及一接觸層137。 該共振帶間穿随二極體1 3係由下列步驟所形成。首先， 形成該第一閘極層131於該第一氧化層12上。接著，形成 一第一矽鍺化合物層132於該第一閘極層131上。接著，形 成一第一多晶矽層133於該第一矽鍺化合物層132上。接 著’形成一第二矽鍺化合物層134於該第一多晶矽層133 上。接著’形成一第二多晶石夕層13 5於該第二石夕鍺化合物 層134上。接著’形成一第三多晶矽層136於該第二多晶矽 層135上。最後，形成該接觸層137於該第三多晶妙層156 上。該第一矽鍺化合物層13 2、該第一多晶矽層丨3 3、該第 二矽鍺化合物層134、該第二多晶矽層135及該第三多晶矽 層136形成一共振帶間穿隧二極體層138。該第一閘極層 131及該接觸層137係利用化學氣相沉積方法所形成，例如 電t輔助化學氣象沉積（PECVD)或高溫氧化爐管暨低壓化 學氣象沉積（LPCVD)。該第一矽鍺化合物層132、該第一 多晶石夕層133、該第二矽鍺化合物層134、該第二多晶石夕層 1 35及該第三多晶矽層1 36係利用分子束磊晶製程所形成。 形成一第二氧化層14於該共振帶間穿隧二極體13上，在 該實施例中，該第二氧化層14係利用熱氧化方法形成。接1308390 IX. Description of the Invention: The present invention relates to a metal oxide semiconductor device and a method of fabricating the same, and more particularly to a metal oxide semiconductor device having a resonant inter-band tunneling diode Production Method. [Prior Art] In the prior art, a circuit in which a resistor and a resonant band tunneling diode are connected in series can be used to generate two steady-state operating points. These steady-state operating points of the conventional circuit require the resistor to be made large enough to bring the load line to a level. However, this larger resistance will reduce the load current, making the circuit unable to produce these steady-state operating points. Therefore, the conventional circuit must use a large voltage and a large amount of the resistor to obtain the bistable operating point. Therefore, the conventional circuit has a problem that the operating voltage is excessive. In addition, the transition characteristic of the 4 stable operating point is asymmetrical due to the use of the resistor as a load line. The greater the slope of the characteristic curve of the tunneling diode between the resonance bands, the more asymmetric the transition point of the bistable point will be, which will cause the pulse circuit to have positive and negative pulses of different levels when designing the circuit. Effectively applied to actual circuits. Furthermore, a large operating voltage is required, and the voltage at the front end of the resistor (connected to the positive voltage source) exceeds the threshold voltage of the general M〇S component, so an additional oxide is required to suppress the gate due to exceeding the threshold voltage. And the current produced. Therefore, it is necessary to provide an innovative and progressive metal oxide semiconductor device having a resonant inter-band tunneling body and a method of fabricating the same to solve the above problems. The object of the present invention is to provide an oxidized semiconductor "b $ between the teeth and the diode. The semiconductor device includes a substrate, a - oxo-resonance inter-band tunneling diode. , ^ ^ u餸 ' a first rolled layer, a semiconductor U three oxide layer, a second gate layer and a fourth oxide layer. = the plate has a - source-source portion, 1 ^ Hu first bungee And a first channel layer, the side. The °°°, the Γ-汲 部 部 is formed on both sides of the first channel layer 1= is formed on the substrate. The resonance band intersperses with the two poles and contacts The first open-pole layer, the inter-resonant inter-penetrating diode layer and the contact layer 'the first gate exposes the first-source portion and the first-knife the first emulsion layer' And a portion of the first emulsion layer at a position opposite to the upper portion, wherein the resonance band f is formed with the diode layer on the first interlayer layer, and the contact layer is formed between the resonance band and the gate electrode layer a contact layer is formed on the second oxide layer, and the semiconductor layer has a second source portion, a second drain portion, and a first channel layer The second source portion and the second drain portion are formed on both sides of the second channel layer. The third oxide layer is formed on the second channel layer. The second gate layer is formed on the second layer The third oxide layer is formed on the second gate layer. The invention has the function of high-speed switching of the deleted component, and can also make the M〇S component more miniaturized, especially in the gate shuttle voltage. (Threshold (9) lower deleted component' The metal oxide semiconductor device with inter-resonator inter-beam diode of the present invention has excellent anti-noise interference capability. In addition, the metal oxide semiconductor device of the present invention can improve the tradition. Metal 111414.doc 1308390 Oxide semiconductor operation when the gate voltage operation is too small, due to noise interference caused by the interpole voltage (four) 'relative to the original interpolar (4) ratio is very large, and the operating current is greatly offset, and the impact A problem of current controller or digital circuit logic. Another object of the present invention is to provide a method for fabricating a metal oxide semiconductor device having a resonant inter-band tunneling diode. The manufacturing method includes the following Step (a) providing a substrate; (b) forming a first oxide layer on the substrate; (c) forming a resonant inter-band tunneling diode on the first oxide layer, the inter-resonance tunneling The diode includes a first gate layer, a resonant inter-band tunneling diode layer and a contact layer from bottom to top; (a second oxide layer is formed on the tunneling diode between the resonance bands; Forming a semiconductor layer on the second oxide layer; (1) forming a third oxide layer on the semiconductor layer; (g) forming a second gate layer on the third oxide layer; (11) forming a first a fourth oxide layer on the second gate layer; (1) using the third oxide layer as a termination layer, removing a portion of the fourth oxide layer and a portion of the second gate layer; (1) using the first oxide layer as a termination layer Removing a portion of the third oxide layer, a portion of the semiconductor layer, a portion of the second oxide layer, and a portion of the inter-resonator tunneling diode; (k) forming a first source portion and a first drain portion Forming a second source portion and a second electrode portion on the semiconductor layer; (1) removing a portion of the third oxide layer and portion Dividing the semiconductor layer; and (m) using the first gate layer as a termination layer, removing a portion of the fourth oxide layer, a portion of the second gate layer, a portion of the third oxide layer, a portion of the semiconductor layer, and a portion The second oxide layer, a portion of the contact layer and a portion of the inter-resonant tunneling diode layer. The metal oxide semiconductor device of the invention can improve the traditional metal oxide semi-conducting 111414.doc •9- 1308390 body when switching, due to the slew rate, from the cut-off to the working interval 'passing through the sub-critical region (sub -threshold region), the critical factor of the several parts is too large, the current driving force is small, the time for the component to reach the steady-state working area is elongated, or the switching speed of the component is too slow, and the mother-to-child switching is consumed. Great transient or transition time problems. In addition, the metal oxide semiconductor device of the present invention does not have the problem of noise drift of the current operating point after the gate voltage is operated for many hours. In addition, the inter-resonator tunneling diode and the low-doped semiconductor layer are sequentially deposited as a resistor, and the inter-resonant band inter-passing diode is connected in series with the resistor, and is produced under appropriate operating voltage ± two Steady state operation, point (one for voltage south state, one for voltage low state)' and these steady state operating points will jump to another operating point unless the excitation current is large enough, that is, the metal oxide semiconductor The device has strong anti-interference or noise characteristics. (4) The gate voltage disappears due to the potential change caused by the noise of the tunneling diode between the resonant bands, and the gate voltage is clamped. The gate is voltage-operated in series, and the electrical component is connected in series with the resistor. The circuit characteristics are still drifting due to noise at an absolutely stable voltage, that is, the current operation. Because &, the steady-state operating point, unless it jumps to the other-operating point under a sufficiently large excitation current, the transition process is a follow-through phenomenon, so it can bring extremely fast operating point switching (high voltage and low voltage) Switching), the metal oxide semiconductor device can also have a high speed: change process, overcoming the conventional slew limit. [Embodiment] Referring to FIG. 1A to FIG. 1E, there is shown a schematic diagram of a method for fabricating a metal oxide semiconductor device having a resonant inter-band tunneling diode 111414.doc 10 1308390. Referring to the drawing, a substrate 11 is first provided, which may be a germanium, germanium or III-V wafer substrate or the like. Next, a first oxide layer 12 is formed on the substrate 11. Next, a resonant inter-band tunneling diode 13 is formed on the first oxide layer 12. The inter-resonant tunneling diode 13 includes a first gate layer 131 and a resonant band interpassing from bottom to top. A tunneling diode layer 138 and a contact layer 137. The inter-band interspersed with the diode 13 is formed by the following steps. First, the first gate layer 131 is formed on the first oxide layer 12. Next, a first germanium compound layer 132 is formed on the first gate layer 131. Next, a first polysilicon layer 133 is formed on the first germanium compound layer 132. Next, a second germanium compound layer 134 is formed on the first polysilicon layer 133. Next, a second polycrystalline layer 13 5 is formed on the second etched compound layer 134. Next, a third polysilicon layer 136 is formed on the second polysilicon layer 135. Finally, the contact layer 137 is formed on the third polycrystalline layer 156. The first germanium compound layer 13 2, the first polysilicon layer 丨3 3, the second germanium compound layer 134, the second polysilicon layer 135 and the third polysilicon layer 136 form a resonance Inter-band tunneling diode layer 138. The first gate layer 131 and the contact layer 137 are formed by a chemical vapor deposition method such as electro-tac assisted chemical weather deposition (PECVD) or high-temperature oxidation furnace tube and low pressure chemical weather deposition (LPCVD). The first bismuth compound layer 132, the first polycrystalline layer 133, the second bismuth compound layer 134, the second polycrystalline layer 135, and the third polysilicon layer 136 are utilized. Molecular beam epitaxy process is formed. A second oxide layer 14 is formed between the resonant band tunneling diodes 13. In this embodiment, the second oxide layer 14 is formed by a thermal oxidation process. Connect
111414.doc • 1U 1308390 . *，形成-半導體層15於該第二氧化層Η上，在該實施例 . 中’該半導體層15係利用化學氣相沉積方法（例如電漿辅 助化學氣象沉積或高溫氧化爐管暨低壓化學氣象沉積）形 成。接著，形成/第三氧化層16於該半導體層15上，在該 實施例中，該第三氧化層16係利用熱氧化方法形成。接 著，形成一第二閘極層17於s亥第三氧化層16上，在該實施 例中，該第二閘極層17係利用化學氣相沉積方法（例如電 魯 漿輔助化學氣象丨儿積或向溫乳化爐管暨低壓化學氣象、，一 • 積）形成。最後，形成一第四氧化層18於該第二閘極層17 ' 上，在該實施例中，該第四氧化層18係利用熱氧化方法形 成。參考圖1B，以該第三氧化層16為終止層，移除部分該 第四氧化層18及部分該第二閘極層17，移除之部分該第四 氧化層18及部分該苐一閘極層17係成一门字形。在兮實广 例中，係使用一第一光罩以活性離子蝕刻方法移除部分該 第四氧化層18及部分該第二閘極層17。 鲁 #考圖ic’以該第-氧化層12為終止層，移除部分該第 三氧化層16、部分該丰導體層15、部分該第二氧化層似 部分該共振帶間穿隨二極體13，使該第三氧化層^、該半 導體層15、該第二氧化層14及部分該共振帶間穿隨二極體 < 13形成—τ字形。在該實施例中，光罩以活 ‘ ㈣子㈣方法’移除部分該第三氧化層16、部分該半導 體層15、部分該第二氧化層14及部分該共振帶間穿隨二極 體13。上述步驟之後，可再利用化學氣相沉積方法（例如 電衆輔助化學氣象沉積或高溫氧化爐管暨低壓化學氣象沉 ni4l4.do, -12- 1308390 積）形成一氮化物保護層，再利用活性離子蝕刻方法移除 部分該氮化物保護層以形成一邊襯（圖未示出），該步驟為 非必要步驟，可視實際所需加入，故未顯示於圖式中。利 用離子佈植技術於該基板1丨形成一第一源極部丨丨1及一第 一汲極部112，該第一源極部丨1丨及該第一汲極部丨丨2之間 界定一第一通道層113。 參考圖1D，移除位於該第一通道層u 3上之相對位置之 部分該第二氧化層16及部分該半導體層15。在該實施例 中，係使用一第三光罩以活性離子蝕刻方法移除位於該第 一通道層113上之相對位置之部分該第三氧化層16及部分 該半導體層15。接著’再利用離子佈植技術於該半導體層 15形成一第二源極部151及一第二汲極部152，該第二源極 部151及該第二汲極部152之間界定一第一通填層153。 參考圖1E，最後，以該第一閘極層131為終止層，移除 部分該第四氧化層18、部分該第二閘極層17、部分該第三 氧化層16、部分該半導體層15、部分該第二氧化層14、部 分該接觸層137及部分該共振帶間穿隧二極體層138，以製 作完成該金屬氧化半導體裝置1 ^在該實施例中，係使用 一第四光罩以活性離子蝕刻方法，移除部分該第四氧化層 1 8、部分該第二閘極層1 7、部分該第三氧化層16、部分該 半導體層15、部分該第二氧化層14、部分該接觸層137及 部分該共振帶間穿隧二極體層138。其中，該第四氧化層 18、該第二閘極層17、該第三氧化層16、該丰導體層15、 該第二氧化層14、該接觸層137及該共振帶間穿隧二極體 1114I4.doc -13 - 1308390 層138與該第一閘極層13ι之一側邊13〇間隔一距離。 請再參閱圖1E，其顯示本發明具共振帶間穿隧二極體之 金屬氧化半導體裝置之示意圖。該半導體裝置丨包括一基 板11、一第一氧化層12、一共振帶間穿隧二極體13、_第 二氧化層14、一半導體層丨5、一第三氧化層16、一第二閘 極層17及一第四氧化層18。該基板η可為石夕、鍺或族 晶圓基板等。該第一氧化層12及該第三氧化層16係選自由 二氧化矽、氮化矽、氧氮氧、空氣腔或其他具有不同摻雜 質濃度之金屬矽化物所組成之群組。該半導體層15及該第 二閘極層17可選自單晶矽、多晶矽、低摻雜或純質砂等， 或亦可選自由第四族或III-V族材料所組成單層或多層之 群。 該基板11具有一第一源極部111、一第—汲極部112及— 第一通道層113 ’该第一源極部111及該第一汲極部112係 形成於該第一通道層113之兩側邊。該第_氧化層12形成 該基板11上。該共振帶間穿隧二極體13由下而上包括一第 一閘極層131、一第一妙鍺化合物層132、—第一多晶石夕層 133、 一第二矽鍺化合物層134、一第二多晶石夕層135、一 第三多晶矽層136及一接觸層137。其中，該第一石夕錯化合 物層13 2、該第一多晶石夕層13 3、該第二石夕鍺化合物層 134、 該第二多晶矽層135及該第三多晶石夕層136形成一共 振帶間穿随二極體層13 8。在該實施例中，該第一石夕錯化 合物層132為Ρ型之矽鍺化合物層，該第—多晶妙層133為 薄層摻雜硼層，該第二矽鍺化合物層134為無摻雜石夕鍺化 111414.doc -14- 1308390 合物層，該第二多晶矽層135為無摻雜多晶矽層，該第三 多晶石夕層136為薄層掺雜碟層。 •玄第一閘極層131覆蓋部分該第一氧化層12，且顯露該 第一源極部111及該第一汲極部112上方相對位置之部分該 第一氧化層12。該第一閘極層i 3丨具有一閘極部i 3 9及一延 展部140 ’該閘極部13 9係位於該第一通道層}丨3上方之相 對位置。該延展部140覆蓋部分該第一氧化層12，該延展 部140不覆蓋該第一源極部111、該第一汲極部u 2及該第 一通道層113上之相對位置之該第一氧化層12，且與該閘 極部139形成一 T型。該共振帶間穿隧二極體層138覆蓋該 閘極部1 3 9及部分該延展部140，且與該第一閘極層1 3丨之 一側邊130間隔一距離。該接觸層137覆蓋該共振帶間穿隧 二極體層138。該第二氧化層14形成於該接觸層ip上。 該半導體層15形成於該第二氧化層14上，且於該延展部 140上之相對位置。該半導體層15具有一第二源極部15ι、 一第二汲極部152及一第二通道層153。該第二源極部151 及該第二汲極部152係形成於該第二通道層153之兩側邊。 該第三氧化層16形成於該第二通道層153上。該第二閘極 層17形成於該第三氧化層16上。該第四氧化層18形成於該 第二閘極層17上。 本發明之該半導體裝置1可使MOS元件具高速切換之功 效’另外，也可使MOS元件更加微小化。特別是在門襤電 壓（threshold voltage)較低的MOS元件，本發明之該半導體 裝置1更具有優良的抗雜訊干擾能力。另外，本發明之該 111414.doc -15- 1308390 ' 導體裝置1可改善傳統金屬氧化半導體在工作時閘極電壓 . 操作過多小時，因雜訊干擾造成閘極電壓偏移，相對於原 閘極電壓操作比例甚大，並造成工作電流大幅度地偏移， 而影響電流控制器或數位電路邏輯之問題。 圖2顯示具共振帶間穿隧二極體之金屬氧化半導體裝置 之等效電路圖。圖3顯示具共振帶間穿隧二極體之金屬氧 化半導體裝置1之電壓·電流曲線圖。參考圖2,該金屬氧 _ 化半導體裝置所形成之該電路2亦會產生兩個穩態工作點111414.doc • 1U 1308390 . *, forming a semiconductor layer 15 on the second oxide layer, in this embodiment 'the semiconductor layer 15 is utilizing a chemical vapor deposition method (eg, plasma assisted chemical weather deposition or High temperature oxidation furnace tube and low pressure chemical meteorological deposition). Next, a / third oxide layer 16 is formed on the semiconductor layer 15, and in this embodiment, the third oxide layer 16 is formed by a thermal oxidation method. Next, a second gate layer 17 is formed on the third oxide layer 16 of the shai. In this embodiment, the second gate layer 17 is formed by a chemical vapor deposition method (for example, electric luma assisted chemical meteorology). Formed or formed into a temperature-emulsified furnace tube and low-pressure chemical meteorology, a product. Finally, a fourth oxide layer 18 is formed on the second gate layer 17'. In this embodiment, the fourth oxide layer 18 is formed by a thermal oxidation process. Referring to FIG. 1B, the third oxide layer 16 is used as a termination layer, a portion of the fourth oxide layer 18 and a portion of the second gate layer 17 are removed, and a portion of the fourth oxide layer 18 and a portion of the gate layer 18 are removed. The pole layer 17 is formed in a gate shape. In the tamping example, a portion of the fourth oxide layer 18 and a portion of the second gate layer 17 are removed by reactive ion etching using a first mask. Lu #考图ic' with the first oxide layer 12 as a termination layer, removing a portion of the third oxide layer 16, a portion of the abundance conductor layer 15, a portion of the second oxide layer-like portion of the resonance band interspersed with the second pole The body 13 is such that the third oxide layer, the semiconductor layer 15, the second oxide layer 14, and a portion of the resonant band pass through the diode <13 to form a -τ shape. In this embodiment, the photomask removes a portion of the third oxide layer 16, a portion of the semiconductor layer 15, a portion of the second oxide layer 14, and a portion of the inter-resonant interdigitated diode in a live '(four) sub-(four) method. 13. After the above steps, a nitride protective layer can be formed by chemical vapor deposition (for example, electric auxiliary-assisted chemical meteorological deposition or high-temperature oxidation furnace tube and low-pressure chemical meteorological sink ni4l4.do, -12- 1308390 product), and the activity is reused. The ion etching method removes part of the nitride protective layer to form a side liner (not shown), which is an unnecessary step, which may be added as needed, and is not shown in the drawings. Forming a first source portion 丨丨1 and a first drain portion 112 on the substrate 1 by using an ion implantation technique, between the first source portion 丨1丨 and the first drain portion 丨丨2 A first channel layer 113 is defined. Referring to FIG. 1D, the second oxide layer 16 and a portion of the semiconductor layer 15 are removed from portions of the first channel layer u 3 at opposite positions. In this embodiment, a portion of the third oxide layer 16 and a portion of the semiconductor layer 15 are removed by a reactive ion etching method using a third mask in a relative position on the first channel layer 113. Then, a second source portion 151 and a second drain portion 152 are formed on the semiconductor layer 15 by using an ion implantation technique. The second source portion 151 and the second drain portion 152 define a first A fill layer 153 is provided. Referring to FIG. 1E, finally, the first gate layer 131 is used as a termination layer, and a portion of the fourth oxide layer 18, a portion of the second gate layer 17, a portion of the third oxide layer 16, and a portion of the semiconductor layer 15 are removed. a portion of the second oxide layer 14, a portion of the contact layer 137, and a portion of the inter-resonator tunneling diode layer 138 to form the metal oxide semiconductor device. In this embodiment, a fourth mask is used. Removing a portion of the fourth oxide layer 18, a portion of the second gate layer 17, a portion of the third oxide layer 16, a portion of the semiconductor layer 15, a portion of the second oxide layer 14, and a portion by a reactive ion etching method The contact layer 137 and a portion of the inter-resonance band tunneling diode layer 138. The fourth oxide layer 18, the second gate layer 17, the third oxide layer 16, the rich conductor layer 15, the second oxide layer 14, the contact layer 137, and the tunneling diode between the resonant bands The body 1114I4.doc -13 - 1308390 layer 138 is spaced from the side 13 〇 of the first gate layer 13 ι by a distance. Referring again to Figure 1E, there is shown a schematic diagram of a metal oxide semiconductor device having a resonant inter-band tunneling diode of the present invention. The semiconductor device includes a substrate 11, a first oxide layer 12, a resonant inter-band tunneling diode 13, a second oxide layer 14, a semiconductor layer 5, a third oxide layer 16, and a second layer. The gate layer 17 and a fourth oxide layer 18. The substrate η may be a stone substrate, a germanium or a family of wafer substrates or the like. The first oxide layer 12 and the third oxide layer 16 are selected from the group consisting of cerium oxide, cerium nitride, oxynitride, air chambers or other metal bismuth compounds having different doping concentrations. The semiconductor layer 15 and the second gate layer 17 may be selected from single crystal germanium, polycrystalline germanium, low doped or pure sand, or the like, or may be selected from a single layer or multiple layers of a fourth or III-V material. Group. The substrate 11 has a first source portion 111, a first drain portion 112, and a first channel layer 113. The first source portion 111 and the first drain portion 112 are formed on the first channel layer. On both sides of 113. The first oxide layer 12 is formed on the substrate 11. The inter-resonator tunneling diode 13 includes a first gate layer 131, a first first germanium compound layer 132, a first polycrystalline layer 133, and a second germanium compound layer 134 from bottom to top. a second polycrystalline layer 135, a third polysilicon layer 136 and a contact layer 137. Wherein, the first rock compound layer 13 2, the first polycrystalline layer 13 3 , the second 锗 锗 compound layer 134, the second polysilicon layer 135 and the third polycrystalline slab Layer 136 forms a resonant inter-band across the diode layer 138. In this embodiment, the first Schindler compound layer 132 is a germanium-type germanium compound layer, the first polycrystalline layer 133 is a thin layer doped boron layer, and the second germanium compound layer 134 is absent. The doped yttrium 111414.doc -14 - 1308390 layer, the second polysilicon layer 135 is an undoped polysilicon layer, and the third polycrystalline layer 136 is a thin layer doped layer. The first first gate layer 131 covers a portion of the first oxide layer 12 and exposes the first source portion 111 and a portion of the first oxide layer 12 at a relative position above the first drain portion 112. The first gate layer i 3 丨 has a gate portion i 3 9 and an extension portion 140 ′ which is located at a relative position above the first channel layer 丨 3 . The extension portion 140 covers a portion of the first oxide layer 12, and the extension portion 140 does not cover the first position of the first source portion 111, the first drain portion u 2 and the first channel layer 113. The oxide layer 12 forms a T-shape with the gate portion 139. The inter-resonator tunneling diode layer 138 covers the gate portion 139 and a portion of the extension portion 140, and is spaced apart from one side 130 of the first gate layer 13 丨. The contact layer 137 covers the inter-resonator tunneling diode layer 138. The second oxide layer 14 is formed on the contact layer ip. The semiconductor layer 15 is formed on the second oxide layer 14 at a relative position on the extended portion 140. The semiconductor layer 15 has a second source portion 15i, a second drain portion 152, and a second channel layer 153. The second source portion 151 and the second drain portion 152 are formed on both sides of the second channel layer 153. The third oxide layer 16 is formed on the second channel layer 153. The second gate layer 17 is formed on the third oxide layer 16. The fourth oxide layer 18 is formed on the second gate layer 17. In the semiconductor device 1 of the present invention, the MOS device can be switched at a high speed. In addition, the MOS device can be further miniaturized. In particular, in the MOS device having a low threshold voltage, the semiconductor device 1 of the present invention has excellent noise immunity. In addition, the 111414.doc -15- 1308390 'conductor device 1 of the present invention can improve the gate voltage of the conventional metal oxide semiconductor during operation. The operation gate is excessively operated, and the gate voltage is shifted due to noise interference, relative to the original gate. The voltage operation ratio is very large, and the operating current is greatly shifted, which affects the problem of the current controller or the logic of the digital circuit. Fig. 2 is a view showing an equivalent circuit diagram of a metal oxide semiconductor device having a tunneling diode between resonance bands. Fig. 3 is a graph showing the voltage and current of the metal oxide semiconductor device 1 having the inter-resonator tunneling diode. Referring to FIG. 2, the circuit 2 formed by the metal oxide semiconductor device also generates two steady state operating points.
- V1、V2。該電路2係由一第一 MOS元件21(相對應於圖1E ' 中該半導體層15、該第三氧化層16及該第二閘極層17所構 成之MOS元件）、一共振帶間穿隧二極體13及一第：M〇s το件22(相對應於圖1E中該基板n、該第一氧化層i2及該 第一閘極層131所構成2M0S元件）所組成，其中，該第一 MOS元件21係作為一非線性電阻之用。 配合參考圖2及圖3，將源極及閘極連接之該河〇§元件21 # 之輸出特性曲線做為負載曲線L1，再選取一適當電流、電 壓之特徵值，使其與該共振帶間穿隧二極體13電性整合。 該源極及該閘極連接之該M〇s元件2丨作為一非線性電阻負 載，且與該共振帶間穿隧二極體13串接，則會產生該等穩 • 態工作點V1、V2。因為該MOS元件21形成之非線性電阻 能依跨壓而急速增加，故該非線性電阻之特性曲線u與該 " 共振帶間穿隧二極體13之特性曲線L2相交之該等穩態工作 點VI、V2，會有躍遷特性幾近對稱之特性，且其操作電 壓將因該非線性電阻之該M〇s元件21與該共振帶間穿隧二 111414.doc 16 1308390 極體13電性之藕合而大幅降低。 因此，本發明之該金屬氧化半導體裝置丨可以改善習知 技術工作電度過大之問冑，且可以改善已習知技術因需使 用較大操作電壓，造成該電阻前端（接正電壓源端）之電壓 會超過-般MOS元件之門檻電壓，而需另填入氧化物以壓 制閘極因超過門檻電壓而產生電流的問題。 本發明之金屬氧化半導體裝置Η改善傳統金屬氧化半 導體在進行切換時，因迴轉率（slew me)的㈣，從截止 到工作區間，經過-次臨界區域— Μ regi〇n)時 該元件次臨界因子過大，電流驅動力較小而使得該元件要 達到穩態工作區的時間拉長’或該元件的切換速度過慢， 以及每次切換都要耗去極大的暫態或過渡時間（transient〇r transition time)之問題。 此外，該等穩態工作點νι、ν·非在足夠大的激勵電 抓下才會跳至另一工作點，即該金屬氧化半導體裝置1具 有較強抗干擾或抗雜訊的特性。因此，閘極電壓因雜訊變 動造成的電位改變，會因該共振帶間穿隨二極體13與該 MOS元件21形成之非線性電阻之電路特性而消失，而使間 極電壓被掛制在-絕對穩定的電壓，亦即無論閘極電壓操 作多小時，電流工作仍不會因雜訊而飄移。因&，該等穩 態工作點Vi、乂2在足夠激勵電流下才會跳至另一工作 點’其躍遷過程為穿隨現象’故能帶來極快的工作點切換 (電壓高態和電壓低態的切換），故可使該刪元件2ι亦具 有高速的切換過程，而克服傳統的迴轉率⑽w威)限 111414.doc -17- 1308390 制。 惟上述實施例僅為說明本發明之原理及其功效’而非用 以限制本發明。因此，習於此技狀人士對上述實施例進 行修改及變化仍不脫本發明之精神。本發明之權利範圍應 如後述之申請專利範圍所列。 【圖式簡單說明】 圖1A為本發明於基板上依序形成一第一氧化層、一共振 帶間穿隧二極體、一第二氧化層、一半導體層、一第：氧 化層、一第二閘極層及一第四氧化層之示意圖； 圖1B為本發明移除部分該第四氧化層及部分該第二閘極 層之示意圖； 圖1C為本發明移除部分該第三氧化層、部分該半導體 層。卩刀該第一氧化層及部分該共振帶間穿隧二極體之示 意圖； 圖1D為本發明移除部分該第三氧化層及部分該半導體層 之示意圖； 圖1E為本發明具共振帶間穿隧二極體之金屬氧化半導體 裝置之示意圖； 圖2為本發明具共振帶間穿隧二極體之金屬氧化半導體 裝置之等效電路圖；及 圖3為本發明&共振帶間穿隨二極體之金屬氧化半導體 裝置之電壓-電流曲線圖。 【主要元件符號說明】 本發明具共振帶間穿隧二極體之金屬氧化半導 111414.doc 1308390 體裝置 2 本發明具共振帶間穿隧二極體之金屬氧化半導 體裝置之等效電路 11 基板 12 第一氧化層 13 共振帶間穿隧二極體 14 第二氧化層 15 半導體層 16 第三氧化層 17 第二閘極層 18 第四氧化層 21 第一 MOS元件 22 第二MOS元件 111 第一源極部 112 第一汲極部 113 第一通道層 13 0 第一閘極層之側邊 131 第一閘極層 132 第一石夕錯化合物層 133 第一多晶矽層 134 第二矽鍺化合物層 135 第二多晶矽層 136 第三多晶矽層 137 接觸層 111414.doc 19- 1308390 138 共振帶間穿隧二極體層 139 閘極部 140 延展部 151 第二源極部 152 第二汲極部 153 第二通道層- V1, V2. The circuit 2 is composed of a first MOS device 21 (corresponding to the MOS device formed by the semiconductor layer 15, the third oxide layer 16 and the second gate layer 17 in FIG. 1E'), and a resonant band interpenetrating a tunneling diode 13 and a first: M〇s τ 22 (corresponding to the substrate n in FIG. 1E, the first oxide layer i2 and the first gate layer 131 forming a 2M0S element), wherein The first MOS device 21 is used as a non-linear resistor. Referring to FIG. 2 and FIG. 3, the output characteristic curve of the channel 21 element 21 # connecting the source and the gate is used as the load curve L1, and then an appropriate current and voltage characteristic value is selected to be combined with the resonance band. The inter-via tunneling diode 13 is electrically integrated. The source and the gate connected to the M〇s element 2 are used as a non-linear resistive load, and are connected in series with the inter-resonator tunneling diode 13 to generate the stable operating point V1. V2. Since the nonlinear resistance formed by the MOS device 21 can be rapidly increased by the voltage across the voltage, the characteristic curve u of the nonlinear resistor intersects with the characteristic curve L2 of the tunneling diode 13 between the resonance bands. Points VI, V2, there will be a nearly symmetrical characteristic of the transition characteristics, and the operating voltage will be due to the non-linear resistance of the M 〇 s element 21 and the inter-resonance band tunneling 111414.doc 16 1308390 polar body 13 electrical The combination is greatly reduced. Therefore, the metal oxide semiconductor device of the present invention can improve the problem of excessive working power of the prior art, and can improve the prior art because of the need to use a large operating voltage, resulting in the front end of the resistor (connected to the positive voltage source). The voltage will exceed the threshold voltage of the MOS device, and an additional oxide is needed to suppress the problem that the gate generates current due to exceeding the threshold voltage. The metal oxide semiconductor device of the present invention improves the sub-criticality of the element when the conventional metal oxide semiconductor is switched due to the slew rate (four), from the cut-off to the working interval, through the sub-critical region - Μ regi〇n If the factor is too large, the current driving force is small, the time for the component to reach the steady-state working area is elongated or the switching speed of the component is too slow, and each switching requires a large transient or transition time (transient〇) r transition time). In addition, the steady-state operating points νι, ν· do not jump to another operating point under a sufficiently large excitation current, that is, the metal oxide semiconductor device 1 has strong anti-interference or anti-noise characteristics. Therefore, the potential change of the gate voltage due to the fluctuation of the noise is lost due to the circuit characteristic of the varistor formed by the diode 13 and the MOS element 21, and the voltage of the interpole is suspended. At an absolutely stable voltage, that is, no matter how many hours the gate voltage is operated, the current operation will not drift due to noise. Because of &, these steady-state operating points Vi, 乂2 will jump to another operating point when the excitation current is sufficient. The transition process is a wear-through phenomenon, which can bring extremely fast switching of the operating point (high voltage state). And the switching of the low voltage state, so that the deleted component 2ι also has a high-speed switching process, and overcomes the traditional slew rate (10) wW) limited to 111414.doc -17- 1308390 system. However, the above-described embodiments are merely illustrative of the principles of the invention and its effects, and are not intended to limit the invention. Therefore, it will be apparent to those skilled in the art that the above-described embodiments may be modified and changed without departing from the spirit of the invention. The scope of the invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A shows a first oxide layer, a resonant inter-band tunneling diode, a second oxide layer, a semiconductor layer, an oxide layer, and a first layer on the substrate. FIG. 1B is a schematic view showing a portion of the fourth oxide layer and a portion of the second gate layer removed according to the present invention; FIG. 1C is a third portion of the third oxidation of the present invention. Layer, part of the semiconductor layer. FIG. 1D is a schematic view showing a portion of the third oxide layer and a portion of the semiconductor layer removed by the first oxide layer and a portion of the same; FIG. 2 is a schematic diagram of a metal oxide semiconductor device having a tunneling diode; FIG. 2 is an equivalent circuit diagram of a metal oxide semiconductor device having a resonant inter-band tunneling diode; and FIG. 3 is a cross-section of the present invention A voltage-current graph of a metal oxide semiconductor device with a diode. [Description of main component symbols] The present invention has a metal oxide semiconducting diode with a resonant inter-band tunneling diode. 111414.doc 1308390 Body device 2 Equivalent circuit 11 of a metal oxide semiconductor device having a tunneling diode between resonant bands Substrate 12 First Oxide Layer 13 Interstitial Tunneling Diode 14 Second Oxide Layer 15 Semiconductor Layer 16 Third Oxide Layer 17 Second Gate Layer 18 Fourth Oxide Layer 21 First MOS Element 22 Second MOS Element 111 First source portion 112 first drain portion 113 first channel layer 13 0 side of first gate layer 131 first gate layer 132 first sinus compound layer 133 first polysilicon layer 134 second矽锗 compound layer 135 second polysilicon layer 136 third polysilicon layer 137 contact layer 111414.doc 19- 1308390 138 inter-resonator tunneling diode layer 139 gate portion 140 extension portion 151 second source portion 152 Second drain portion 153 second channel layer
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