TWI308376B - Method for making a semiconductor device including shallow trench isolation (sti) regions with a superlattice therebetween - Google Patents

Description

'1308376 41 Sidewall insulation layer 42 Annular implant zone 43 Annular implant zone 80 STI zone 82 Non-early grain bar 83 Non-early crystallized strips 8. When the case I has a chemical formula, please reveal the characteristics of the most inventive invention. Chemical Formula: IX. Invention Description: [Related Applications] This application is a priority of the US Patent Application Provisional Application No. 6/692 1〇1, which was filed on June 2, 2005, and This application is a part of the continuous application (Contmuation-m-part appiicati〇n) of U.S. Patent Application No. 1/992,422, filed on November 18, 2005, U.S. Patent Application No. 1/992 422 is the United States patent application No. 47, _, filed on August 22, 2003, and is now U.S. Patent No. 6,958, part of the gamma continuous _ request, US Patent No. 6,958, 486 ^ for June 2003 U.S. Patent Application Serial No. 1/6〇3,696 and No. 10/603,621, filed on the 26th, the contents of the above-mentioned claims are listed as references in the present invention. TECHNICAL FIELD The present invention relates to the field of semiconductors, and in particular to With engineering (energy bgnd engineering) has based its method of enhancing semiconductor characteristics related to the. [Prior Art] Various constructs and techniques such as enhancing the mobility of charge carriers to enhance the performance of semiconductor elements have been proposed. For example, in the case of US Patent Application No. 2003/0057416 to Curr et al., it is disclosed that silicon germanium, silicon-germanium, and relaxed silicon and including originally would cause 1308376 performance degradation. Strained material layers such as imperative-free zones. The biasiasi strain formed in the upper layer changes the mobility of the carrier and enables the fabrication of higher speed and/or lower power components. U.S. Patent Application Publication No. 2003/0034529 to Fitzgerald et al. discloses a CMOS inverter (CMOS invertei^) which is also based on a similarly-strained siiicon technology.

U.S. Patent No. 6,472,685, issued to U.S. Patent No. 6, 472,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, The valence band is subjected to a tensiie strain. An electron with a small effective mass and induced by an electric field applied to the gate electrode is confined to its second layer, so that its n-channel MOSFET can be considered to have a higher dynamic Sex.

U.S. Patent No. 4,937,204 to the disclosure of U.S. Patent No. 4,937, issued to the entire entire entire entire entire entire entire entire entire entire The mon〇layer)) structure is grown alternately in the form of epitaxial g〇Wth. The main current flow direction is perpendicular to the layers in the superlattice

A short period superlattice of si-Ge is disclosed in US Patent No. 5,357,119 to Wang et al., which is achieved by reducing the alloy scattering in the superlattice (all〇y scattering). Motivation. In accordance with a similar principle, U.S. Patent No. 5,683,943 to the disclosure of U.S. Pat. The substance appears alternately in the dream crystal, and the percentage of the composition is such that the channel layer is in a state of tensile stress.

U.S. Patent No. 5,216,262 to the disclosure of U.S. Patent No. 5,216,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, Each of the shielding zones consists of a single layer of SiO 2 /Si with a thickness ranging from approximately two to six. A thicker section of the Shi Xi material is also sandwiched between the shielding zones. Issued by Physic and Materials Science and Process (Applied 1308376

Physics and Materials Science &Processing; 391 - 402, in an article entitled "Phenomena in silicon nanostructure devices", Tsu reveals a kind of helium and oxygen. Semiconductor-atomic superlattice (SAS), a Si/O superlattice structure, has been unveiled as a useful quantum and luminescent element. It specifically reveals how to fabricate and test the construction of a green electroluminescence diode. The direction of current flow in the diode structure is vertical, that is, perpendicular to the level of the SAS. The SAS disclosed herein may comprise a semiconductor layer separated by adsorbed species such as oxygen atoms and c〇 molecules. The ruthenium formed outside of the absorbed oxygen monolayer is described as an epitaxial layer which has a relatively low defect density. One of the SAS structures comprises an enamel portion having a thickness of Unm which is about eight layers of germanium atoms, and the thickness of the tannin portion of the other structure is twice as thick as the thickness. Physics Review Letters, Vol. 89, No. 7 (August 12, 2002), published by Luo et al., entitled "Chemical Design of Direct Gap Luminescence" ("Chemical Design of The article "Direct-Gap Light-Emitting Silicon") further discusses the luminescent SAS construction of Tsu.

A shield construction block of thin tantalum and oxygen, nitrogen, nitrogen, fill, helium, arsenic or hydrogen is disclosed in the International Application Publication No. WO 02/103,767 A1 to Wang, Tsu, and Lofgren et al. The current of the crystal lattice is reduced by more than four tenth power orders (f〇ur orders of magnitude). The insulating layer/shield layer allows for the deposition of low-defect fibrites adjacent to the insulating layer.

Mears et al., in the published British Patent Application No. 2,347,52, discloses that aperiodic photonic band-gap (APBG) can be applied to electronic bandgap engineering. In engineering). In particular, the application discloses that 'material parameters, for example, the position of the band minimum, the equivalent mass, etc., can be adjusted to achieve a new aperiodic characteristic of the desired band structure. Sexual material. Other parameters, such as electrical conductivity, thermal conductivity, and didectric permittivity or magnetic permeability, are all claimed to be also designed into the material. SUMMARY OF THE INVENTION 1308376 A method of fabricating a semiconductor device can include forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. Further, a plurality of layers may be deposited to cover the substrate to define a superlattice covering the substrate between adjacent STI regions, and defining non-monocrystalline regions covering the STI regions, respectively. The method can further include selectively removing at least a portion of the non-single crystal region using at least an active area (AA) mask. In particular, the method can further include forming a plurality of PMOS transistor channels coupled to the superlattices such that the semiconductor component comprises a CM 〇 semiconductor component. Further, selectively removing the photoresist that can include patterning at least one AA mask,

In addition, the at least -AA fresh can be a - single-baseline μ mask. In other embodiments, the at least -AA mask may comprise a first oversized channel resistance for one of the ship's s transistors, a (firSt〇versizedChannd-St〇P) AA mask, and for a PMOS transistor. - The second oversized channel blocks the AA mask. Therefore, the method may further comprise: using a large channel of the factory to block the AA mask, performing a first channel blocking implant, and using the excessive channel to block the AA mask - the second channel blocks the intrusion. f who is a boat,

A non-semiconductor monolayer. Further, the at least one non-base semiconductor portion is within a crystal lattice. In some embodiments, the at least one non-rich name

The non-semiconductor monolayer can be a single single layer thickness. These are all less than the thickness of 8 single layers. The superlattice may be the same number of single layer thicknesses in one of the most base semiconductor portions

盍 layer. In some embodiments, all thicknesses, and in other embodiments, the thickness of the single layer. In addition, all of the base 7 '1308376 half 1 'each of the base semiconductor portions may each include a group consisting of a group IV semiconductor, a group III-V conductor, and a group II-VI semiconductor. Similarly, for example, each of the non-semiconductor layers may each comprise a non-semiconductor selected from the group consisting of oxygen, nitrogen, fluorine, and carbon-milk. [Embodiment]

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in detail in the following description of the specification of the invention. However, the invention may be practiced in many different forms, and the scope of the invention is of course not limited to the embodiments shown in the drawings. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and the scope of the invention. Throughout the description of the present invention, the same drawing reference numerals are used to designate the same or equivalent elements, and the addition of 2rime) or multiple twisting symbols are used to indicate similarities in different embodiments. element. The present invention relates to controlling the properties of a semiconductor material at the level of atoms or molecules to achieve improved performance of the semiconductor device. Moreover, the present invention is also directed to enhancing the identification, creation, and use of materials for application to the conductive paths of semiconductor components. The theory presented by the Applicant of the present application shows that certain superlattice configurations disclosed herein can reduce the equivalent mass of the charge carriers and, by virtue of such reduction, can result in higher charge carrier mobility, but applications It is also stated that the scope of the invention is not limited to this theory. Among the documents in the art to which the present invention pertains, there are various definitions of equivalent masses for description. As a measure of the improvement in equivalent quality, the applicant uses "conductivity reciprocal effective mass tensor" to represent electrons and holes, respectively, and Μ*1. Definition: M-1 (ET) = e>Ef bz------- e,iJ F, Σ ifmKn), EF,T)d3k e>ef bz is the definition of electrons, and

MitAEF,T) Σ j (Vk^(k,n)),. (Vk£(k,n)).(10)k:),%^3k E<Ef BZ 0tj X l(l-nE(k,nXEF, T))d\ BZ 8 Ί308376 is the definition of the hole, where f is the Fermi-Dirac distribution, EF is Fermienergy, T is temperature, and E(k,n) is electron Corresponding to the energy in the state of the wave vector k and the nth band, the subscripts 及' and 〖 are corresponding to the Cartesian coordinates x, y and ζ, and the integral is in the Brillouin zone (BZ) Brill〇uinzone) is carried out in the band of electrons and holes with energies above and below Fermi energy. °

Applicant's definition of the conductivity inverse equivalent mass tensor is the larger of the corresponding components of the conductivity inverse equivalent mass tensor of the material, and the tens〇rial component of the conductivity is also Can be bigger. The Applicant hereby reaffirms the theory that the superlattice described herein, which is set for the conductivity inverse equivalent mass tensor, enhances the conductive properties of the material, such as typically allows charge carrier transport. There is a better direction. The reciprocal of the appropriate number of tensor items is referred to herein as the conductivity equivalent mass. In other words, if the characteristics of the semiconductor material structure are to be described, the conductivity equivalent of the aforementioned electron/hole and the calculation result in the direction in which the carrier is intended to be transmitted can be used to distinguish that A has been improved. Some materials. Materials having a preferred energy band configuration can be selected for a particular purpose using the foregoing methods. An example of this may be a superlattice 25 material for one of the channel regions of a semiconductor component. A planar MOSFET 20 including a superlattice 25 in accordance with one of the present inventions will now be described with reference to FIG. There is depicted a planar MOSFET 20 comprising a superlattice 25 in accordance with the present invention. However, it will be understood by those skilled in the art that the materials referred herein can be applied to many different types of semiconductor components, such as discrete devices and/or integrated circuits. The illustrated M〇SFET 20 includes a substrate 21 having shallow trench isolation (STI) regions 80, 8 therein, and more particularly, a MOSFET device to be a complementary metal oxide semiconductor (CM〇S) device. It includes \ and? The channel transistor and the superlattice channel should be understood by those skilled in the art, wherein the STI region is used to electrically connect the adjacent transistor. For example, 'substrate 21 can be ambiguous-semiconductor (such as Shi Xi) coffin or an insulator on the substrate (silic〇n_〇n_insul s〇I), the substrate is reduced, like ^ oxygen cut, secret secretary The MOSFET 20 shown in the second embodiment of the invention may further include a lightly doped source/drain extension 22, 23, a more heavily doped source/drain region 26, 27, and a superlattice interposed therebetween. 25 channel areas provided. As shown, the annular implant region (here is included between the source and drain regions 26, 27 and below the superlattice 25. Source/dip metallization (8〇1!1^/(^118Xun(^%6)〇3〇, 31 covers the source/bungee area, which is familiar to those skilled in the art. As shown in the figure, the gate 35 includes a gate dielectric layer 37 adjacent to a channel region provided by superlattice 25, and gate electrode layer 36 is tied over the gate dielectric layer. In the illustrated M〇SFET2〇 A sidewall spacer 4, 4b, and a metal lithium layer 34 are also provided, which are above the gate g-layer 36.

To integrate the process of the superlattice into the prior art CM〇s process, the superlattice film 25 formed in the ST! area 8〇: 81 is removed to prevent a short circuit between the adjacent ^^= Or leakage. Referring more particularly to FIG. 2 to FIG. 2 and FIG. 3, the process can begin with material 21 having STI regions 80, 81 formed therein, and a sacrificial oxide layer 85 and a VT implant thereon. The object 84 (represented by a column "+,,"). In the case of the crystalline germanium superlattice, which will be further described below, when the sacrificial oxide layer 85 is removed, and the superlattice 25 is formed on the substrate 21 The strontium deposits cause (ie, polycrystalline or amorphous) stellate deposits 86, 87 to cover the STI region 8 〇, = above. However, as described above, the non-single crystal propagule needs to be removed from the structure. In the case of Na «Electricity. «The π piece is a fairly straightforward method for some single-baseline wire area'AA) photoresist mask 88 (shown in Figure 2C) to mask 86. Subsequent narration of 87 (as shown in Figure 2D) is acceptable, but the next 'doing so will cause some difficulties. More specifically, if the mask does not have a non-single-crystal deposit on the STI edge 86 $ Part of it is obscured by photoresist 88 or there is not enough over_etch in the process of plasma surname, then in S Some of the non-single-crystal deposits in the T and STI recesses may remain unsided. Therefore, the remaining is the parasitic element adjacent to the active device, and the adjacent STI region is the channel blocking the rare group. Do not bloom (4) lower ^ dopant creep (dopant creep) may occur unintentionally in adjacent non-single crystal 'eve, 86 = uneven metal fragmentation and source / drain junction leakage - leakage) The substrate may occur adjacent to the gap 89. 1308376 The f-cover and scribe operations can be advantageously modified to provide non-single-crystal semiconductor _ strips or un-protrusions at the edges of the STI regions 8. ^Qing 2, 83 绝 绝 绝 绝 绝 , , , , 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 。 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝 绝Preferably, the non-single-crystal street strips 82, 83 can be advantageously doped to prevent the doping of the cockroach, such as a coffee ride through several manufacturing models = reference to Figures 4 to 8 The first process for fabricating a semiconductor device will be described. Starting with the STI wafer at block 90, at step block 9 Vt Well

Min 塾 oxide 85,), and then at step 92, the remainder (i2 〇 A 2 5). Next, at step 93, exposure to HF of hydrofluoric acid (HF) is 1,5 〇Α). In particular, some of the dry etching of bismuth oxide 85 and the relatively short HF violent time, for example, can help reduce the STI concave ==, superlattice film is deposited, which will be further discussed. ;^ Block 95 is the cleaning step (spm/200:1, HF/RCA). ΛNo, the single-baseline Μ mask described above, at step block 96, - oversized Ν channel ΑΑ mask (as shown in Figure 5Α and Figure 6Α), followed by the step material, and at step block 98, _Over the AN financial channel to block the plantation (as shown in Figure IX). In Figs. 8A and 8B, the oversized mask is t-marked, the 1st edition 'and 88P' are indicated, and the N and P active zones (4) are denoted by reference numerals and 21p, respectively. In addition, the reverse N and P wells are assigned reference numerals (10). Next, at step 99, an oversized P-channel aa mask is formed (as shown in FIG. 5B) at step block 100' to plasma etch the single crystal semiconductor material over the STI region adjacent the p-channel region, and in steps Block UH, PFET channel blocking. NFET and FET channel shouting people to the Shaw or oblique money line, such as the % degree angle, as shown in Figure 6B, but other angles can still be used here. As shown in the figure, the arrow is blocked by the implanted line. For example, the nfet can be implanted, and arsenic or phosphorus can be used for PFET channel blocking implantation. In the stl area, 8〇, 81, the recess (divot) The inner rafter and the unfinished ridges of the STI edge are preferably 11 1308376 to prevent the implant from being highly counter-doped to neutralize or slow down from the source to the $ and the polar regions. The diffusion of the dopant into the non-single crystal yttrium in the STI recess, or the diffusion creep of the protrusion at the corner of the channel of the element, in order to advantageously allow the parasitic edge element to have a higher diode breakdown voltage , higher threshold voltage, and lower shutdown current for P and N channels Member using two different masks too large, may be advantageously protected AA in the non-single-crystal silicon etch alignment marks, and so that each block the channel if the active elements are protected when implanted at the opposite type element.

Once the PFET channel is blocked, complete the pre-gate cleaning (SPM/HF/RCA) in step 1〇2 (shown in Figure 8). Then in step 1〇3, gate oxide 37' is formed. (About 20A), and in step block 1〇4 (shown in Figure 8B) 'Perform a non-single crystal gate, pole 36 deposition and implant doping. At step block 〇5, gate imaging and touch are performed, then at step block 106', sidewall isolation layers 40, 41, (e.g., oxide of ιοοΑ) are formed, and at step block 107 (shown in Figure 8C), Light doping (LDD) 22, 23 ' and ring 42', 43' implantation are performed. Then, at step block 108 (e.g., 19 immersed oxidization), a residual is made for the sidewall isolation layer 40''41. The isolation layers 4, 41 are formed, followed by source/drain 26, 27, implant and temper at step 109 (eg, at 100 (TC lasts 10 seconds), and metal is formed at step block 110 Telluride to provide the element 20 shown in Figure 1 More specifically, the metal halide may be TiSi2 (e.g., deposited '钦, 锗, implant 锗, RTA@ 690. (:, selective stripping, followed by RTA) @75〇.〇.

Figures 12A and 12B show cross-sectional views of the element structure after forming a metallization parallel and perpendicular to the gate layer 36. In these figures, non-single-crystal rafters 82, 83, ^ have been mixed with channels. The remainder is the depth of the recess in the zone, which is related to the amount of the surname used to remove the = and 83 sides of the STI recess and the STI edge. In addition, those skilled in the art should be aware that excessive recesses may result in loss of contact between the increased string ^ and the LDD region, which may need to be adjusted depending on the depth of the implant. = In the eve of the second system, the bribe and Cong mask, the etching is located in the STI ^ gate oxidation early 87, and the step of the barrier to implant, etc., in the package ° in the proposed generation process, the above The method was modified such that the side of the non-single crystal dreams 86, 87 was followed by the isolation layer step 1 12 1308376, block 108,). In addition, this alternative process also uses an oxide or nitride cap film 78" over the inter-electrode layer 36" (as shown in Figure IB) to protect the gate polysilicon in the non-single The wafers 86", 87, are not engraved by the surname during the etching process. After the completion of the step 92', the cleaning is performed (sPM/2〇〇:1, HF (in the step block 12〇). 5〇AyRCA), followed by Xing pre-cleaning (O'D for about 1 minute. The NFET and PFET mask deposition steps (steps 96, and 99, saying 'in this example is using an oversized mixed photoresist mask ( 〇versizedhybridph〇t〇resist mask), as shown by ® l〇A. In addition, after the deposition of the non-single-crystal slab electrode layer in step block 〇4, the method of the figure includes an NSD masking step (step Block (2),), followed by step (2) 'and m' of N+ hybrid money layer oxide _. Other process variations different from the above method include, at step block 125, etching the STI region 8 〇", ^" Non-single crystal ♦ 86”, 87” (such as 3GGA), then in step 126, the cover layer The chemical layer (having high selectivity to germanium). The remaining process flow is similar to the process flow discussed in Figure 4, so it will not be described again. The following will describe another alternative process flow with reference to Figures 13A and 13B. The production process uses a universal oversized AA mask, which is used to name the STI area 8〇", 81,,, on the ^ stone eve 86", 87, '' ' followed by 2 independent mask steps for Let the protrusions open and image. More specifically, 'use the npet channel to block the mask 13〇n' to discard, block the cover 13Gp,, and the NFET and PFET mask steps are followed by channel blocking implants. Non-single (four) mixed in the opening of the protrusion. The foregoing steps can be performed before the inter-polar oxidation step. ^ It is understood that the exemplary process flow outlined above can advantageously etch the STI region after growing the gate On the non-single-crystal semiconductor material. In addition, the person with a suitable doping dose implanted in the channel, can electrically neutralize the dopant from the adjacent source ^ to avoid dumping to the bribe a non-single crystal material master whose t superlattice is not properly hidden on the STI oxide In the STI recess of the edge or protrusion of the moving area, the active area is surrounded by the excessive active area mask. Of course, it should be, in the embodiment of the embodiment, except for the material and process flow of the above example ^ Other suitable materials and process parameters can also be used. The improved material or structure for the channel region of MOSFET 20 will be discussed below, where 13 1308376 MOSPEJ, # has a band structure that allows proper conduction of electrons and/or holes. The effective mass is substantially less than the corresponding value of 矽. With additional reference to Figures 14 and 15, superlattice 25 has a configuration that is controlled at the atomic or molecular level and can utilize known atomic or molecular layer deposition techniques. Production formation. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in a stacked form, as described above, perhaps best understood by reference to the cross-sectional views illustrated by Figure 14. =曰^5^Axis layer group 45a_45n, such as a broken forest containing a plurality of stacked base semiconductor semiconductor layers 46a-46n, and a plurality of stacked base semiconductor monolayers 46, and thereon An energy-band modifying layer 50. For clarity, it can be modified

50 is indicated by a dotted line in FIG. In the figure, the 修改 tape modification layer 50 includes a non-semiconductor monolayer (the-semiconductor is formed in the crystal lattice of the base semiconductor portion adjacent thereto. ΐ方ΐίί ^ 祝 4511 opposed to the base semiconductor single For example, in the case of the tree single layer 46, a certain atom in the upper end or the top semiconductor monolayer of the group will be associated with the group 45a-45n, (c〇 vaJ^ conductor atoms (that is, some of the oxygen atoms in this example will be bound to non-half in other embodiments, more than one non-conducting band can modify the non-layer 5G The number of semiconductor single layers, $good = row. For example, 'layer, in order to provide the desired layer with modified layer characteristics, preferably less than about 5 monolithic blocks, if the body is That is, as will be understood by those skilled in the art, the semiconductors or semi-conductors t do not have to be laid out. 1 Applicant still claims that the invention 4 should not be limited to its theory, that is, the band Modifying the acoustic 5 〇 and its adjacent base semiconductor portion 46a-46n 'will cause the superlattice 25 to be flat The charge carrier of the > face = upward has a lower proper quality of conductance than the one without the arrangement. In another way, the parallel direction is orthogonal to the direction of the stack. It is possible that the superlattice 25 has a common energy band ((χ)η_η_^^" acts as a "heart" between the upper or lower regions of the Lai or superlattice. Again, as indicated above, this structure is also It can be beneficial to play the doping of the upper layer of the super-lattice 25 and/or the scattering or diffusion of the material, and the carrier flow. The theoretical age of the t-cell, the superlattice 25 is based on the lower The super-lattice 25 provides a higher charge carrier mobility. The characteristics of the superlattice 25 are not applicable in every application. For example, ,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,, (d) 1_52 is located in the upper end layer group 45 of the superlattice 25, the base semiconductor single layer 46. The cap layer 52 can have 2 to (10) ίίί = bottom + Conductors, and preferably should be 1G to 5G single layers. Other thicknesses can also be used, and the base semiconductor portions 46a-46n can contain conductors, and solutions to the mosquito body. Of course As can be understood by those skilled in the art, IV ^ lacks the family conductor. Youyi, the basic word "可 ΐ Ξ Ξ 非 非 包 包 包 有 有 有 有 有 包 包 包 包 包 包 包 包 包 包 组合 组合 组合 组合 组合 组合 组合 组合 组合 组合 组合 组合 组合 组合The layer is deposited _ residual inspection, "destination or r-r can be made to meet the specific semiconductor fabrication core 15 1308376 It should be noted that the word mono layer (mon〇layer) should also include the monoatomic layer (5) ngie = 11Clayer) and a single molecule layer (singlem〇lecular layer). It should also be noted that the band modification layer 5 provided by the early atomic layer should also include a single layer in the layer that is not completely filled with possible atomic positions. For example, reference is made to Figure ls, in which a 4/1, "structure" is used as a base semiconductor material and oxygen as an energy band modification material. Only half of the oxygen's possible locations in the dragon are filled. In the case of the application and/or in the case of different materials, as is familiar with this, the preferred position is from the occupant to the half of the possible position of oxygen is occupied,,,,, and other ranges It can also be used in a specific embodiment. = The current storage of sputum and oxygen is widely lying in - (4) 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕 匕The +conductor 70 piece of the conductor can be immediately utilized and implemented by the present invention. The superlattice 25 can be understood by the art. It can also be seen in the schematic diagram that i-specific atoms are not Exactly arranged along a plane. For example, the invention of the invention is based on its theory, namely - superlattice and +, upward electrons and electricity_new crane. For example, electronic fruit, _ body block _ The ^^ super-day grid with a value of ^ is 0.16, and the ratio of the two is 〇44. The bl/〇= characteristic may be advantageous for some semiconductor components, in the 1+conductor element, parallel to It may be more advantageous to group the groups of the layer groups. For those who are familiar with the art, the mobility of the holes is increased, or only increased. The charge _'2: ^^ electricity in the 4/1Si/0 embodiment of the superlattice 25, its lower conductivity equivalent mass may be more than 16 1308376 is; = 2f =, and this situation is in other real _ towel, the practice of the younger is in the cell 25 of the component towel - or more of the layer group 45 is substantially undoped __).

Referring additionally to Figure 16, at the same time, another embodiment of 25 having different properties will be described in accordance with the present invention. In this embodiment, a 3/1/5/1 overmolding mode is shown: the second is the 'bottom-base semiconductor portion gamma, which has three single layers, and the first and second base semiconductor portions. Part 46b' has 5 single layers. This combination pattern is repeated throughout the Super 25 25'. Each layer can be modified to include a single single layer. In the case of such superlattice t of t Si / O, the enhancement of the charge carrier kinetics is independent of the orientation in each. The other structural portions of the towel of Fig. 16 which are not mentioned herein are similar to those discussed in Fig. 14 and will not be discussed again. "/, in some components, the complement of 0, the superlattice 25 of the financial base 4 & 46n, the thickness may be the same number of single-stacked thickness. In other embodiments, some of the base semiconductors 46a_46n, The thickness may be the thickness of the lining of the forest. In other embodiments, all of the base semiconductor portions #46a-46n may be different thicknesses of a single stack. 〃 Figures 17A to 17C show the application of density function theory pensity Functi〇nal ^ DFT) The calculated energy band structure. The skill cap is widely known that the DFT is usually low; the ancient energy has an absolute value of the gap. Therefore, all the energy bands above the gap can be properly scissor-shaped. The repair ("seises correction") is offset. However, the shape of this energy band is more sinful than the δ. The vertical energy axis (verticai energy axes) should be considered under such cognition. Figure 17A It is the bulk silicon (indicated by the solid line) and the 4/1 Si/O superlattice 25 (indicated by the dotted line) shown in Fig. 4, which are calculated by the code point (6). Can be a structure of the curve. Although it is in the figure ( The direction of 〇1) does correspond to the (001) direction along the general unit cell, but the direction refers to the unit cell of the 4/1 Si/O structure rather than the general unit cell of Si and thus The expected position of the Si conduction band minimum is shown. The (100) and (010) directions in the figure correspond to the (110) and (_11〇) directions of the general unit cell of Si. It will be understood by those skilled in the art that In the figure, the energy bands of Si are shown in folds, and they are shown in Table 17 1308376 for the appropriate anti-grid direction of the 4/1 Si/O structure. It can be seen that the whole pet block i) Under her, 4/1 Si/〇 structure ^ is the location of the code point (G) 'and the smallest side of the Wei ribbon is the domain _) ^ Up: in the Briorin area (four) 丨 (10) 丨The edge of (4) is (3). It can also be noted that the curvature of the 4/1 Si/Ο structure and the material band of Si has a larger curvature, because the extra oxygen layer is introduced. The energy map made by human disturbance is the whole block Shi Xi (solid line) and the figure w/4/1, superlattice μ (dashed line), = the curve of the energy band structure calculated from the Z point Shown in this figure It is (the direction of the bond energy band increases the curvature. Figure 17f is the overall block Shi Xi (solid line) and the 5/1/3/isi/〇 superlattice shown in Figure 16] And the curve of the energy band structure calculated at the z-point. Due to the symmetry of the 3 structure, the obtained energy band is calculated in the _ and _) directions. Therefore, in the plane parallel to the layers, that is, Conductive equivalent mass and kinetics can be expected to be isotropic in the direction of the stacking perpendicular to the). It is noted that in the example of 5/lf/l Si/O, the material minimum and the maximum bond energy band are both at or near the Z point. Although the increase in the curvature is an index of the equivalent mass reduction, the appropriate age comparison and discrimination can still be performed by the conductivity inverse equivalent mass tensor. This allows the county applicant to enter a ==5/1/3/1 superlattice 25' which should be essentially a direct energy gap. As is familiar to the skilled person, _, can be transferred to ptiealtransitiGn (four) appropriate matrix early 7L (matnX element) is another indicator to distinguish between direct and indirect band gap behavior 0, the artist knows the case in the above description And the invention described in the accompanying drawings, it is to be understood that many modifications of the invention and the various embodiments of the invention can be deduced. Therefore, it is to be understood that the scope of the invention is not limited to the scope of the embodiments of the invention, and other modifications and other embodiments are still within the spirit of the invention. 18 1308376 [Simple Description of the Drawings] According to the present invention, the blunt element of the paste element has a potential difficulty in the package. The domain diagram shows the formation of the semiconductor component of FIG. 1 and its correlation = the semiconductor read of FIG. 1 is partially reflected by the gate electrode and the memory of the gate; Process flow of components. The view, applied to the method of Figure 4, is a cross-sectional view of the implanted step and the sturdy barrier. Circle 'its, (4) through Ϊ 0 and gate deposition / implanting steps, etc., heat conduction engraved 'channel blocking implant' ί 1=^2=-9=two-sitting age · the element depends on the top view and the interlayer After the parallel and vertical metallization, the elements 13A and 13B are the active regions of another process according to the fabrication of the semiconductor device of FIG. 1 by the ±φ, γ3·¢13⁄4 protrusion channel blocking step. And a larger scale enlargement cross-sectional view of another embodiment, the overall block of the ϋ7Βϋί〇 technique and the 4/1 si/0 super U shown in FIG. 14 are in the skill The overall block Shi Xi and the 5/1/3/lSi/O super cell shown in Figure 16 are calculated from the Gamma and Z-shapes. [Main component symbol description] 19 1308376

20 MOSFET 21, 21' substrate 21η' Ν active region 21ρ' Ρ active region.,

22 source region 22, LDD 23 pale region 25 superlattice 26, 26' source region 27, 27' > and polar region 30 source metal germanide layer 31 germanium metal telluride layer 32 source contact

33 bungee contact 34 metallization layer 35 gate 36, 36', 36" gate electrode layer 37, 37' gate oxide 38 gate electrode layer 40, 40' sidewall isolation layer 41, 41' sidewall isolation layer 42 , 42' annular implant region 43, 43' annular implant region 45a~45n, 45a'~45n' stacked layer group 46 base semiconductor monolayer

46a~46n, 46a'~46n' base semiconductor portion 50'50' can be modified with layer 52, 52' cap layer 78" oxide or nitride cap film 79n, reverse well 79ρ' reverse well 80 , 80', 80" STI area 81, 81', 81" STI area 82, 82' non-single crystal strip 83, 83' non-single crystal strip 84 VT implant 85 sacrificial oxide layer 85, pad oxide 86 , 86', 86" non-single crystal germanium deposits 20 1308376

87, 87', 87" non-single crystal slab deposit 88 photoresist 88 η 'over large Ν mask 88 ρ ' over large Ρ mask 89 gap 130 n ” NFET channel blocking mask 130 p ” PFET channel blocking mask flow of Figure 4 STI wafer 91 is implanted into VT well (through 150 Α pad oxide 85) 92 dry etched (120A oxide) 93 exposed to hydrofluoric acid (HF) (SCl/100: 1,5〇 A) 94 deposited superlattice film (5〇A) 95 Cleaning step (SPM/200:1, HF/RCA) 96 forms an oversized N-channel AA mask 97 to plasma etch the superlattice film over the STI region -98 NFET Channel Blocking 99 Oversized P-Channel AA Mask 100 to Plasma Etch Super-lattice Film on STI Area 101 PFET Channel Blocking Implant 102 for Pre-Gate Cleaning (SPM/HF/RCA) 103 forming a gate oxide (about 20A) 104 non-single crystal gate electrode deposition and implantation doping 105 gate imaging and etching 106 forming a sidewall isolation layer (100A) 107 LDD and annular implant 108 form a sidewall isolation layer ( 1900 people) 109 source / immersion implantation and tempering (last 丨〇 seconds in i〇〇〇〇c) 110 formation of metal telluride (deposited titanium (Ti), implanted 锗, RTA @ 690«>c, selective killing, followed by RTA@750°C) 〇, with the flow of Figure 9 'STI wafer 91 implanted in VT well (through 150A pad oxide 85,) 92 for dry money engraving (120A oxide) 12〇 for cleaning step (SPM/200:1, HF (5〇AyR_CA) 121'HF pre-cleaning (100:1) for about i minutes 21

Claims (1)

1308376 Patent Application No. 95122068 Chinese Patent Application Revision Revised January 2009 Revision 94' Deposition Superlattice Film (2〇〇人) 95' Cleaning Step (SPM/200:1, HF/RCA) 96' Overgrown The hybrid N-channel AA mask 97' is plasma-etched over the STI region of the superlattice film 98' NFET channel barrier implant 99' to form an oversized hybrid p-channel AA mask 100' to plasma etch the STI region Superlattice film 101'PFET channel blocking implant 102' for pre-gate cleaning (spm/HF/RCA) 103' for gate oxide formation (about 20 people) 104 non-earth crystal gate electrode deposition 122'NSD Mask 123 'N+ Gate Implant 124' Cap Layer Oxide Deposition 105' Gate Imaging and Residual 106' Forming a Sidewall Isolation Layer (1⁄4) 107' LDD and Annular Implant 108' Form a Sidewall Insulation Layer ( 1900A) 125' etched superlattice protrusions on STI (3〇〇A) 126' etched cap oxide layer (with high selectivity to germanium) 109' source/drain implanted and tempered (at 1 〇〇〇〇c lasts 1 )) ' Implant 锗: Patent application scope 1. A method for making a semiconductor component The method comprises: forming a plurality of shallow trench isolation (STI) regions in a semiconductor substrate. The substrate is at least between the adjacent _ super-crystals at least—to provide abutting on the non-single-crystal rafters Perform at least one channel block implant. 'More includes the formation of a plurality of super-lattice junctions that make the dragons turn over the tree - (10)s semi-dependent elements. AA mask. The method of the second item, wherein the at least one AA mask comprises a single baseline * 曰 2 f f 专 1 ?, 2 f method 'where the at least - AA mask contains NMOS One of the corpses of the corpuscles is a large-scale pass-through (flrst 〇versized channd_st〇p) AA mask, and is used in the revision of the PMOS transistor in January 2009. The second oversized channel blocks the Μ mask. 5. If the method of claim 4 of the patent scope is applied, the permanent barrier implant includes the use of the first over-channel obstruction U; early! ^ Conducting at least - the secondary channel and using the second over-channel to block the 1 1 H ' ' channel blocking implant, row - the first, and before the second channel blocking channel blocks the implant, the concave into the milking area a group, wherein each group includes a plurality of stacked single layers defining a plurality of stacked layers, and at least one non-semiconductor single-chip stacked semiconductor semiconductor having adjacent base semiconductor portions thereon One crystal & inside. "To", a non-semiconductor monolayer is defined in degrees. H). The method of claim 9, wherein each of the non-semiconductor layers is a single single layer thick single layer thick. The method of claim 9, wherein the towel-per-substrate rotating portion is less than eight ninth items, wherein the superlattice is on a topmost layer group and the same number of single-layer towels is the ninth item All of the silk affixed parts of the towel are the same as the method of the different months of the item, wherein at least some of the base semiconductor parts of the same number of single-layer towel range ninth method, shooting All of the base semiconductor portions are non-group semiconductors. The base portion of the substrate contains iv semiconductors. VI material conductors are composed of red group finances - base fluorine and carbon-oxygen iCf non-m The non-semiconductor layer comprises a plurality of shallow trench isolation (STI) regions formed by oxygen, nitrogen, and body portions, wherein a semiconductor CMOS element is formed by a substrate semiconductor in the adjacent layer group. Covering the substrate with a layer of three layers of deposition 3 to define the coverage of the substrate separately between adjacent sti Supercrystal 1308376 between the regions Patent Application No. 95122068 Patent Application Revision Revised January 2009 Revision: Single crystal region, each superlattice comprises a plurality of stacked layered reeds, defined as the base semiconductor portion a plurality of stacked base semiconductor monolayers, and wherein the at least one non-semiconductor monolayer is defined to selectively remove at least a portion of the non-single crystal region to provide abutment on the channel And the method of claim 19, wherein the at least one AA mask comprises a single baseline transistor, and the method of claim 1 is: Αλ1 〇 如 如 如 如 如 如 如 如 如 , , , , 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少 至少Thereafter, at least one of the masks includes a mask for the NM〇S channel, and a second pass for the PM0S transistor is implanted in the Shenhaiwei Carry out at least - pass 23 on the strip. For example, if the patent application scope is 22nd--------------------------------------------------------------------------------------------------------------------------------------------------------- Into the f into a non-single street The non-single-crystal regions of the STI regions are exposed to at least the non-single-crystal regions; and the 26.190 Group 3 m III-V semiconductors, and the ^-vi i semi-iif Containing a non-semiconductor selected from the group consisting of +conductor layers each comprising oxygen, nitrogen, fluorine and carbon-oxygen 24 1081308376 109 110 Figure 4 29 1308376 014 U roLnrv@vl_ 塾, Μ*1κ_ ,,υο卬U3@<h-DC: i AFi cage)iss^ ώοτ— •ZCH -SI. s Li set αα_1 I • sCSIl. (yooco)sffi^ 咬®-N,TllsKf# •9CSI1. 牛ST _uoo§ i 丽/驿晓► , c_霞s 1 stupid niwii every sir t<oJd/LLH/l/\lQ.s) s酲珉sfcl? (ys)Is-— 1 Her •SI. -s_- ,60 l· w neck qsn Ys 丽+N 丽 si_w -901. 6凾-96 cloud vss 40®e¥.国3⁄43⁄4 a« 豳STmi ®— i#.拟瓦的 d SSI 00 毒毒 - ^-ffilsTsl liss^,i Draw a Ί 1ΙΛ --1 rvjilyosl. Let SAYS i learn «£§) (vuy/c<os)IX.H, one;:00z/2ds) 丽—SI •T(T:00T)«1 (yooz) Let 8 read Li Sa: /U_H, -t:oorsl/wds) 0,S0 -06 Λ6 Z6 bCNIl. Λ31- -inch 6 •S6 1308376 41 1308376 wide 43 1308376 4/1 SiO band structure near the code point. Shrink/Λ3ς.0)®Η越 Figure 17A 44 1308376 4/1 SiO band structure near the Z point (Umbrella/>32)峒璲 1-(1001 S-_ Z-C010) Figure 17B 45 1308376 3/1/5Λ SiO band structure (^/Λ3Γ0) Ϊ- Figure 17C 46