TWI307218B - Low emi output driving circuit and method - Google Patents

Description

1307218 IX. Description of the Invention: [Technical Field] The present invention relates to a drive circuit and method for low-electromagnetic interference of an output drive circuit. In particular, [Prior Art] Conventional integrated circuit chip 'for example, a standard integrated circuit chip (reic) or a power integrated circuit, a gular moving circuit, in order to achieve a sufficiently large current drive energy output: (push-pull) The way, rm~. I wish to use ^ 利用 架构 架构 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 利用 ^ ^ ^ ^ ^ ^ After the transistor Μ2 is connected in series, and between the grounding node GND, the series connection of the electro-crystal core m2 is connected to the _ output pad 8G (_put (4), and the gate of the transistor μ and Μ is connected to one And when the control signal sin is at the same voltage level (Vdd), the transistor is in a conducting state and the transistor is in a non-conducting state, at which time the output is $8. When the control signal Sin is at a low voltage level (9), the transistor % is in a non-conducting state and the transistor M1 is in an on state. At this time, the output pad voltage level is VDD. In actual use, the buffer stage 9〇 is used to drive an output load, especially when the input When the load is a resistive load (resistive or large capacitive 1〇ading), the width and length ratio (W/L ratio) of the transistor % and ^^ will be very large, thereby increasing the driving capability. however,

01139-TW / HD-2005-0014-TW 5 1307218 When the buffer stage 90 is in the transition state, for example, the high level to the low level (1 to 〇) or the low level to the south level (〇 to 1), The transistor and m2 are simultaneously turned on at the same time to generate a transient current flowing from the voltage source Vdd to the ground node GNd, so that the power consumption is increased. In addition, during the transition state, a transient driving current from the power supply terminal Vdd to the output pad 8〇 is generated on the transistor; a current flowing from the output pad 80 to the ground node GND is generated on the transistor M2. Driving the current for a moment, it will produce a significant electromagnetic interference (emi) problem. Conventionally, in order to solve the problem that the voltage source Vdd flows to the grounded node gnd to save power, a non-overlapping buffer is added to the front end of the last stage buffer stage 9〇. 〇n_〇veriap buffe〇, as shown in Fig. 2a, the non-overlapping buffer 7〇 can control the transistor Μ and Μ respectively, and the control signal is shifted by a small amount on the time axis, as shown in the figure No, a control signal GPA is used to control the conduction and non-conduction of the transistor, and another control signal GNA is used to control the conduction and non-conduction of the transistor, and the non-overlapping buffer 7 can make the control signal The GPA and the GNA trigger the transistor (4) and %' at different time points, that is, the phase delay (10) between the control signals GPA and GNA is such that the transistors % and (4) are turned on at different times. Except during the transition state, the current is driven from the voltage source Vdd to the ground node Gnd. However, 'only adding the non-overlapping buffer 70 can not eliminate this; the crystal 吣 and the instantaneous driving current on M2, and thus still cannot solve the electromagnetic Drive based on the above Reason, it is still necessary to further improve the above output

01139-TW / HD-2005-0014*TW 6 1307218 =: Q: Can achieve elimination at the same time - transition current and electromagnetic [invention content] The road and the other side of the package are providing a low electromagnetic interference round The drive buffer stage is used to "use the final-stage buffer stage - multi-phase delay, rush, and to produce peak-to-peak drive current peaks with different phases. ", with reduced transients and this = It is also intended to provide a low-electromagnetic interference output-driven electrical buffer stage for hunting by using the final-stage buffer stage--multiphase delay to generate a phase-in different signal, to reduce electromagnetic interference. The above object, the low electromagnetic interference output driving circuit of the present invention, the eight kings should include a plurality of buffer stages, the

The mother-level of the %-level grading stage consists of a PMOS electric Japanese body and an NMOS transistor. 哕MMnc ^ 丨风°海 PM〇S transistor is connected in series with the NMOS transistor and configured in -% Between the voltage nodes, the series connection of the two transistors is connected to the lower - 铋螇 铋螇 & , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , Output one: - signal '· and a multi-phase delay buffer stage includes a round-in end and an output stand and 'the wheel-in terminal receives the second signal meter ^ 现 亚 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由 由The multi-phase delay buffer stage is used as the last stage of the turn-off drive circuit. The third signal includes an output signal of a complex array phase generated by the multi-phase delay buffer stage to reduce the peak of the third signal. value. The present invention further provides an output driving method for low electromagnetic interference, comprising the following steps: input-first-input signal to the first level of a plurality of buffer stages,

01139-TW / HD-2005-0014-TW 7 1307218

Each of the buffer stages is composed of a PMOS transistor and an NM0S transistor. The PMOS transistor is connected in series with the NM〇s transistor and disposed between a voltage source and a voltage node. The series connection is connected to the closed-end connection of the next-stage buffer stage, and outputs a second signal at the last stage; and provides a multi-phase delay buffer stage including an input end and an output end. The input end of the hai receives the second signal of the shai and outputs a third signal by the output end, and the p-phase phase delay buffer stage is used as the final output of the output drive circuit, and wherein the second signal includes more The phase delay buffer stage produces a complex number of output signals of different phases to reduce the peak value of the third signal. [Embodiment] In order to make the above and the present invention, the embodiments of the present invention are hereinafter described as follows. His purpose, characteristics, and advantages can be more clearly' and with the attached drawings, for details, refer to the 3rd and 3b drawings in March, and the output of the 4th _ 丄 low electromagnetic interference driver: More than 9 of the example. ,, - non-overlapping buffer 7. And: it comprises a plurality of buffer stages - a wheel drive circuit delay buffer stage u, and a common integrated circuit chip (not given - output drive circuit 10 receives from - χ ^ ^ 曰 not, such as a standard integrated circuit crystal #1 Power integrated circuit chip, chip or first-class to output pad 80. The second: number is generated - the wheel drive driving resistive load or the large capacitive negative cutting drive circuit 1 is preferably used to drive the buffer stage 9 〇, such as the crystal % and is disposed in the transistor % series connection - coffee s electric room 'the transistor =, and a voltage node GND, the series connection is connected to the lower-level buffer level 01139-TW/^-2〇〇5-〇〇, 4, rw 1307218, the gate junction of the transistor % and M2; the buffer stage 90, the first stage receives the driving signal of an integrated circuit chip [not labeled], and outputs the multi-phase delay buffer stage 最后i by the last stage The control signals gpb and GNB. The non-overlap buffer 70 is connected in series to the buffer stages 90 of the output driver circuit 10, between the two transistors of the last stage and the input of the multiphase delay buffer stage n. , which can cause a phase delay [τ of FIG. 3b] between the control signals GPB and GNB driving the multi-phase delay buffer stage 11 so that the polyphase delay buffer stage u is pM〇s • and NMOS It will not be turned on at the same time, so as to eliminate the transient current flowing from the voltage source VDD to the 3 sinus voltage node GND to reduce the power loss. The non-overlapping buffer 7 can be omitted, and the output of the last stage of the buffer stage 90' is directly connected to the input and output of the polyphase delay buffer stage. Referring to FIG. 3a again, the multi-phase delay buffer stage 11 of the preferred embodiment of the present invention is the buffer stage of the last stage of the output drive circuit i, which divides the last stage output stage into n parts. But the whole still has the same ►W/L ratio' to maintain the same driving capability, including a plurality of PMOS transistors p, p2 to Pn, a plurality of nm〇s transistors & N2 Up to Nn, a PMOS multiphase delay line j! and an NM〇s multiphase delay line 112. The multi-phase delay lines U1 and U2 can be selected as a current control delay line according to product requirements (Current c〇ntr〇1

Delay Line, CCDL), a voltage control delay line (v〇hage contr〇I Delay Lme, VCDL), an inverse buffer delay line (inverter buffei) delay line (sequential logic control delay line) And other phase delay lines that can achieve phase division, 01Ϊ 39-TW / HD-2005-0014-TW 9 1307218 and the way of phase division can be selected according to the production demand to be equal, equal phase difference) or unequal Splitting the knife edge! (Also J is looking for a knife cut (that is, one of the better ones when the unevenness is unevenly divided. #ί ea & brother, and [away from the output pad 80 ^ χ output pad 80 - end] Gradually become a brake method (that is, 'to gradually run a female eve; & i 曰 斤 s s big way to change the phase difference, to achieve the purpose of phase division. 夂祁 差 ) 以 以 以 以 以 以 以 以 以 以 以 以 以 以 以In the example, the PM〇s electricity

The connection between the emperor's 'T-day solar body, p2 to pn, NMOS electric corona body, N2 to Nn, PMOS passengers such as 仏M〇s 相 phase delay line 111 and NMOS polyphase delay line 112—, In total, the system is connected in series with a PMOS transistor by a NM0S transistor (for example, p and n, you, worm 1 and 乂), and then arranged in a voltage source Vdd, and an electrical node GND' The series connection between the blue s transistors and the nm 〇s transistors is connected to the output L. The pM 〇s transistors are connected to the PMOS multiphase delay line m, and the gates of the N 〇 Ms are connected. The pole is connected to the NMOS phase delay line 112 such that when the multiphase delay buffer stage 11 is in a transition state, the voltage source Vdd is divided and passed through the pM〇s transistors. 1,? 2 to Pn flow to the output pad 80 and the output current from the output pad 80 to the voltage node GND via the NM0S transistors N1, N2 to Nn, to generate an output signal with different phases to reduce electromagnetic interference. problem.

Referring to FIG. 3b again, the clock signals GpB i to GPBn are generated by dividing the PMOS polyphase delay buffer line 1丨1, and respectively controlling the pM〇s in the output driving circuit 1 The crystals Pi, h to Pn are turned on and off, and the clock signals GNBi, GNB2 to GNBn are generated by dividing the NMOS polyphase delay buffer line 112, and respectively controlling the NMOS powers in the output driving circuit 10. Crystal N!, N2 to N 01139-TW / HD-2005-0014-TW 10 1307218 • Conduction and non-conduction. Thus, by the non-overlapping buffer 70, the clock sequence number GPBi, GPB2 to GPBn and GNB, and GNB2 to GNBn can have a phase delay 'to eliminate the transient current to reduce the power loss; From the multi-phase delay buffer stage, an output signal having a different phase can be generated to reduce the peak value of the instantaneous drive current, thereby reducing the problem of electromagnetic interference. As shown above, the habits shown in Figures 1 and 2a

There is a problem that the peak value of the instantaneous driving current is too large, so that electromagnetic interference is generated. Compared with the conventional output driving circuit of FIGS. 1 and 2a, the output driving circuit of the low electromagnetic interference according to the embodiment of the present invention is as shown in FIG. 3 & By phase delay buffer stage η to produce output signals with different phases, the peak value of the drive current is actually reduced to reduce the problem of electromagnetic interference. Although the present invention has been disclosed in the foregoing preferred embodiments, it is not to be understood that the invention is defined by the appended claims. Wei. Target

01139-TW / HD-2005-00J4-TW 11 1307218 [Simple description of the diagram] Figure 1: Circuit diagram of the conventional output driver circuit. Figure 2a: Circuit diagram of another-used output driver circuit. The clock map of the drive signal of the output drive circuit of Figure 2a of the figure. Figure 3a is a circuit diagram of an output drive circuit and method for low electromagnetic interference in accordance with a preferred embodiment of the present invention. Figure 3b is a timing diagram of the driving signal of the low electromagnetic interference output driving circuit and method. [Description of the number] 1 〇 output drive circuit 111 Ρ Ο Ο S multiphase delay line 70 non-overlapping buffer 90 buffer stage PMOS transistor ΡπΡη PMOS transistor 11 multiphase delay buffer stage 112 NMOS multiphase delay line 80 output pad 90 'Buffered M2 NMOS transistor ΝπΝη NMOS transistor

01139-TW / HD-2005-0014-TW

Claims (1)

1307218 X. Patent application scope: - An output drive circuit with low electromagnetic interference, comprising: a plurality of buffer stages, each of the buffer stages having a pm 〇s transistor and an NMOS transistor, green ΡΜΓϊς φ a μ + ^ ° Hai PM〇S transistor is connected in series with the NMOS transistor and disposed between a voltage source and a voltage node, and the series connection of the two transistors is connected to the (four) connection of the lower-level buffer stage The first level of the buffer level receives a sneak peek and w ^弟5fL唬' and output a second signal at the last level; and the evening phase delay. The friend level includes an input terminal and an output terminal, the input terminal receives the second signal and outputs a third signal from the output terminal a signal, the multi-phase delay buffer stage is the last-stage output stage of the output drive circuit; wherein the δ-Hai second signal includes a plurality of output signals generated by the multi-phase delay buffer stage and having different phases to reduce the signal The peak value of the third signal. 2, according to the scope of application for patents 帛 1 low electromagnetic interference output drive circuit - in the D Xuan Di - chaotic number is an integrated circuit chip output stage drive information to express the patent scope 帛 2 low electromagnetic interference output drive The circuit wherein the δ 积 integrated circuit chip is one selected from the group consisting of a standard integrated circuit chip and a power integrated circuit chip. 4. According to the patent application section, the output of the low-electromagnetic interference of the J-track is one of the output of the electromagnetic interference, and the force 歹 一 & ° is used to provide the multi-phase delay buffer stage to generate the different phases of the wheel Signal. Busy application for the patented cofferdam 1 low electromagnetic interference wheel drive motor n39-TW/HD-2〇〇5-〇〇i4.TW 13 13.07218 « . Road, where the third signal is used to provide a Drive current. 6. The output drive circuit of the low electromagnetic interference according to the scope of the patent application section further includes a non-overlapping buffer connected to the most moxibustion of the plurality of buffer stages, and the tandem of the two crystals and the multiphase Between the inputs of the delay buffer stage such that there is a phase delay between the second signals. 7. According to the scope of the patent application, the low-electromagnetic interference wheel drive circuit 'these wheel-out signals are equal to the phase difference. According to the patent application, the output drive circuit of the low electromagnetic interference of item i is included, wherein the round signals are unequal in phase difference. The output drive circuit of the low electromagnetic interference according to item 8 of the scope of the patent is in which the circumscribing signals change the phase difference in an increasing manner. 10. The output drive circuit of low electromagnetic interference according to item 1 of the patent application scope, wherein the multi-phase delay buffer stage comprises: > a plurality of PMOS transistors; a plurality of NMOS transistors, the PM 〇s transistors are connected in series The NM〇s transistor is disposed between a voltage source and a voltage node, and the PMOS transistor and the NM〇S transistor are connected in series to the wheel terminal; a PMOS multiphase delay line is connected to The PM〇S transistors electrically control the conduction and non-conduction of the PMOS transistors; and an NMOS multi-phase delay line is connected to the poles of the n〇MS transistors and controls the NMOS transistors. Conducted and non-conducting. 01139-TW / HD-2005-0014-TW 14 1307218 11. Output drive with low electromagnetic interference according to item 10 of the patent application scope: circuit, wherein the PMOS multi-phase delay line and the NOMS multi-phase delay line are selected from a current A control delay line, a voltage controlled delay line, a reverse buffer delay line, and a sequence of logic control buffer lines. 12' A method for output driving of low electromagnetic interference, comprising the steps of: inputting a first input signal to a first stage of a plurality of buffer stages, each stage of the buffer stages having a PMOS transistor and a Nm〇s a transistor, the PMOS transistor is connected in series with the NM〇s transistor and disposed between a voltage source and a voltage node, and the series connection of the two transistors is connected to the gate connection of the next stage buffer stage, and A second signal is rotated in the last stage; and the multi-phase delay buffer stage includes a wheel terminal and a wheel terminal, and the input terminal receives the second signal and outputs a third signal from the output terminal, which is The phase delay buffer stage is used as the last stage output stage of the output driving circuit; wherein the second signal includes a different output signal of the complex array phase generated by the multi-phase delay buffer stage to reduce the peak value of the third signal. 13. The method of output driving of low electromagnetic interference according to item 12 of the patent application scope, wherein the first signal is an output stage driving signal of an integrated circuit. 14. The method of output driving of low electromagnetic interference according to claim 12 of the patent application, wherein the second signal is used to provide the multi-phase delay buffer stage to generate output signals having different phases. 01139-TW / HD^2005-0014-TW 15 1307218 ‘15. The method of low-electromagnetic interference wheel-driven driving according to item 12 of the patent application scope, wherein the third signal is used to provide a driving current.依申: The low-electromagnetic interference output driving method of the 12th patent range, further providing a non-overlapping buffer connected to the tandem of the last-level two transistors of the plurality of buffer stages and the multi-phase delay buffer Between the wheels of the stage, so that there is a phase delay between the second signals. 17. According to the 12th item of the patent application scope, the low-electromagnetic interference wheel-driver method is the same as the phase difference. 18. The method of driving low-emission electromagnetic interference according to item 12 of the patent application scope, wherein the round-off signals are unequal in phase difference. 19, according to the scope of the patent application of the 18th low electromagnetic interference wheel drive method 'method', these output signals are gradually increased to change the phase 01139-TW / HD-2005-0014-TW 16