TWI306289B - Fabrication method of non-volatile memory - Google Patents
Fabrication method of non-volatile memory Download PDFInfo
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- TWI306289B TWI306289B TW95115852A TW95115852A TWI306289B TW I306289 B TWI306289 B TW I306289B TW 95115852 A TW95115852 A TW 95115852A TW 95115852 A TW95115852 A TW 95115852A TW I306289 B TWI306289 B TW I306289B
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- volatile memory
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- 238000000034 method Methods 0.000 title claims description 45
- 230000015654 memory Effects 0.000 title claims description 26
- 238000004519 manufacturing process Methods 0.000 title claims description 15
- 230000008569 process Effects 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 18
- 239000004020 conductor Substances 0.000 claims description 14
- 230000003647 oxidation Effects 0.000 claims description 12
- 238000007254 oxidation reaction Methods 0.000 claims description 12
- 125000006850 spacer group Chemical group 0.000 claims description 9
- 239000002131 composite material Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 claims description 2
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims 2
- 229910000420 cerium oxide Inorganic materials 0.000 claims 1
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical group [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims 1
- 229910001936 tantalum oxide Inorganic materials 0.000 claims 1
- 229910052727 yttrium Inorganic materials 0.000 claims 1
- VWQVUPCCIRVNHF-UHFFFAOYSA-N yttrium atom Chemical compound [Y] VWQVUPCCIRVNHF-UHFFFAOYSA-N 0.000 claims 1
- RUDFQVOCFDJEEF-UHFFFAOYSA-N yttrium(III) oxide Inorganic materials [O-2].[O-2].[O-2].[Y+3].[Y+3] RUDFQVOCFDJEEF-UHFFFAOYSA-N 0.000 claims 1
- 230000015572 biosynthetic process Effects 0.000 description 5
- 238000001459 lithography Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 230000008901 benefit Effects 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000010168 coupling process Methods 0.000 description 3
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 241000272517 Anseriformes Species 0.000 description 1
- 241000293849 Cordylanthus Species 0.000 description 1
- YZCKVEUIGOORGS-OUBTZVSYSA-N Deuterium Chemical group [2H] YZCKVEUIGOORGS-OUBTZVSYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 238000009825 accumulation Methods 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052805 deuterium Inorganic materials 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002309 gasification Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 229910000449 hafnium oxide Inorganic materials 0.000 description 1
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000008267 milk Substances 0.000 description 1
- 210000004080 milk Anatomy 0.000 description 1
- 235000013336 milk Nutrition 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- -1 nitride nitride Chemical class 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002689 soil Substances 0.000 description 1
- 239000004575 stone Substances 0.000 description 1
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- Non-Volatile Memory (AREA)
Description
13062織 twf.doc/e 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體元件之製造方法，且特別 是有關於一種非揮發性記憶體之製造方法。 【先前技術】 非揮發性記憶體中可進行多次資料之存入、讀取、抹 除等動作，且存入之資料在斷電後也不會消失之功能，並BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a non-volatile memory. [Prior Art] Non-volatile memory can perform multiple functions such as storing, reading, erasing, etc., and the stored data will not disappear after power-off, and
兼具有存取速度快、質輕容量大、存取裝置體積小等優點， 所以已成為個人電腦和電子設備所廣泛採用的一種記憶體 元件。 田典型的非揮發性記憶體元件，一般是被設計成具有堆 疊式閘極(Stack-Gate)結構，其中包括以摻雜的多晶矽製作 浮置閘極(Floating Gate)與控制閘極(Contr〇1 Gate)。浮置閘 極位於控制閉極和基底之間’且處於浮置狀態，沒有和任 何電，相連接，而控制間極則與字元線(w〇rdLine)相接，It has the advantages of fast access speed, high light weight capacity, small size of access device, etc., so it has become a memory component widely used in personal computers and electronic devices. Typical non-volatile memory components are typically designed to have a stacked gate-Gate structure that includes a floating gate and a control gate with doped polysilicon (Contr〇) 1 Gate). The floating gate is located between the control closed pole and the substrate and is in a floating state, not connected to any electricity, and the control pole is connected to the word line (w〇rdLine).
此外還包括穿)¾介f層和介f層分懸於基底和浮置 閘極之間以及浮置閘極和控制閘極之間。 j元^^高7^件積集度的趨勢下，會依據設計規則縮 率之方法包括增加控雜= 性二鴨合率’習知技術提出了圖1的非揮發 (生仏體結構。圖知的—種非揮發性記憶體的= 不意圖’請夢照圖i，此非揮發性記憶體包括基底ι〇〇、穿 隧介電層搬、浮置閘極1G4、卩相介電層跡導體層⑽、 祕/汲極區m及氧化層112。浮置閑極⑽ 馳及導體層·，導體層1G8是做為控制祕。其中導 體層104a與lG4b為不同層。導體層取 形成-摻雜多㈣層覆蓋在導體層綱a ; 匕 ί===，以定義此摻_層。 帝声L的面;與控制閑極之間所夾閘間介 私層106的面積。但在疋義導體層1〇4 不斷微縮的趨勢’上述的微影製程 ：牛：尺寸 旦有對不準之問題’後續的飿刻製程就；導體 層_，而導體層1〇4b(浮置閑n刀剔¥體 (Bridge)現象。再者，因為圖案化 s曰發生橋接 制困難，可能會造成閘間介電層八' "_之製程控 極耦合率不—致。 电“〇6分佈不均勾，而使閘 【發明内容】 依據本發明提供實施例之目的一 記憶體的製造方法，透過自行對 /、、—種非揮發性 化層，簡化製程並增加製程裕度。本;亡式源極氧 性記憶體的製造方法，可增加 ^種非揮發 能’此外，該方法避免增加微影製二;^改善元件效 接現象及閘極_合率因製程難度而變 ς而緩和橋 為達上述或是其他目的，本發出二種。 憶體的製造方法’包括於基底上依序4第 1306嫩— 一導體層及罩幕展必 部分第一介電厚:二除部分罩幕層、部分第-導體層及 上形成間瞻。於^成數個開口。然後’於開口的側壁 進行熱氧化製程氣化源極/沒極區。 區上方形成一屌奶綠t開口所暴路之基底，以於源極/汲極 間介電層覆莒;θ。之後，移除罩幕層，並形成一閑 著，於表=敝表面。接 在本發明之—實上層弟二¥體層。 幕層後，更包括移除於移除罩幕層時或於移除罩 括於ΐΐίίίΓίϊ财’上叙間雜的形成方法包 電層，直到是ίΓί 刻製程，以移除部分第二介 之間隙 約攝种’上叙魏化抛的溫度是 氧化石^本1明之一貫施例中，上述之絕緣層的材質例如是 如是==例中’上述之絕緣層的厚度範圍例 切之邮料層例如是氧 如電層的厚度例 .1306¾¾^ ，由於本發明的方法係利用自行對準的方式來形成埋 ^式沒極氧化層，因此省略微影製程的步驟，使製程得以 簡化；且製程裕度與可靠度更因自行對準而提高。再者， 由於非揮發性記憶體製程中定義各浮置閘極僅需一次微影 製程’因此減低了微影製程的困難度，避免疊對誤差的問 題與橋接的現象，各浮置閘極的結構均一而形成較均勻的 問間介電層，致使非揮發性記憶體具有均一的閘極耦合率。In addition, a layer is formed between the floating substrate and the floating gate and the floating gate and the control gate. Under the trend of j-element ^^ high 7^ piece accumulating degree, the non-volatile (raw carcass structure) of Fig. 1 is proposed according to the method of designing the scaling factor including increasing the controllability = sex two ducks. Figure of the non-volatile memory = not intended to please dream map i, this non-volatile memory including the substrate ι〇〇, tunneling dielectric layer, floating gate 1G4, 卩 phase dielectric The layer conductor layer (10), the secret/deuterium region m and the oxide layer 112. The floating idler (10) is connected to the conductor layer, and the conductor layer 1G8 is used as a control secret. The conductor layers 104a and 1G4b are different layers. The formation-doping multi-(four) layer covers the conductor layer a; 匕ί=== to define the doping layer. The surface of the emperor L; and the area of the inter-package layer 106 between the control idle electrodes. However, in the case of the 导体 导体 导体 导体 不断 不断 不断 ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' ' The phenomenon of "Bridge" is saved. In addition, because of the difficulty in bridging the patterning s ,, it may cause the gate dielectric layer 八' " The combination rate is not the same. The electric "〇6 distribution is unevenly distributed, and the gate is made. [Inventive content] According to the present invention, the method for manufacturing a memory is provided by a self-aligning/,----a non-volatile layer Simplify the process and increase the process margin. This method of manufacturing a dead source of oxygen memory can increase the non-volatile energy'. In addition, the method avoids the addition of the lithography system; The _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Part of the first dielectric thickness: two part of the mask layer, part of the first conductor layer and the upper part of the formation. In the ^ into a number of openings. Then 'on the side wall of the opening for thermal oxidation process gasification source / no-pole area Above the area, a base of the milk green t opening is formed to cover the dielectric layer between the source and the drain; θ. After that, the mask layer is removed and a free space is formed. The surface is connected to the body layer of the present invention. After the curtain layer, it further includes Removed from the cover layer when removing the mask layer or removed from the ΐΐ ί ί ' ' 上 上 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , The temperature of the Weihua throwing is in the consistent embodiment of the oxidized stone. The material of the insulating layer is, for example, in the case of the thickness of the above-mentioned insulating layer. For example, the thickness of the mail layer is, for example, the thickness of oxygen such as an electric layer. For example, the method of the present invention utilizes a self-aligned manner to form a buried gateless oxide layer, thereby omitting the steps of the lithography process to simplify the process; and the process margin and reliability are more self-contained. The alignment is improved. Furthermore, since the floating gates are defined in the non-volatile memory system, only one lithography process is required, thus reducing the difficulty of the lithography process and avoiding the problem of stacking errors and bridging. The structure of each floating gate is uniform to form a relatively uniform inter-intermediate dielectric layer, so that the non-volatile memory has a uniform gate coupling ratio.
為讓本發明之上述和其他目的、特徵和優點能更明顯 易I*董’下文特舉較佳實施例，並配合所附圖式，作詳細説 明如下。 【實施方式】 圖2A至圖2E是本發明一實施例的非揮發性記憶體的 製造流程剖面圖。 首先，請參照圖2A，提供一基底2〇〇。基底2〇〇的材 質例如是矽。於基底200上形成一層第一介電層2〇2。第 一介電層202例如是随穿氧化層，且第一介電層2〇2的形The above and other objects, features, and advantages of the present invention will become more apparent. [Embodiment] Figs. 2A to 2E are cross-sectional views showing a manufacturing process of a non-volatile memory according to an embodiment of the present invention. First, referring to FIG. 2A, a substrate 2 is provided. The material of the substrate 2 is, for example, ruthenium. A first dielectric layer 2〇2 is formed on the substrate 200. The first dielectric layer 202 is, for example, a transparent oxide layer and a first dielectric layer 2〇2
成方法例如是熱氧化法。於第—介電層搬上形成一 體層綱。導體層204的材質例如是掺雜多_，且^ 層204的形成方法例如是臨場換雜的化學氣相沉程。~ 接著，在導體層204上形成—層罩幕層遍。罩幕居 的材質例如是氮化石夕’且罩幕層2%的形成方 學氣相沉積法。 以疋化 接著，請參照®1 2B，移除部分罩幕層施， 幕層206a。移除部分罩幕層2〇6 以形成罩 的方法例如是先於罩幕厚 ，1306氣“ 206上形成—層圖案化光阻層（未圖示），再進行一非等 钮刻衣& ’以圖案化罩幕層2Q6，之後移除圖案化光 ^二’ 2成罩幕層2Q6a。接著，以罩幕層2Q6a做钱刻 綦Ά導體層2〇4及第-介電層2〇2，而形成浮置 閘極204a、牙隧介電層2〇2a及數個開口 2⑽。其中，圖案 化的方法例如是非等向性蝕刻製程，而以 做蝕刻終止層。 外"电e • 太恭日卜’在本實施例中’開口 2〇8暴露基底200，然而 :、’不以此為限。換言之，在另—實施例中，開口 208 底4仍保留有部分介電層搬而未暴露基底2〇〇。 ，續參照圖2B，形成—層共形的第二介電 層210復服開口 2〇8表面及罩幕層ma頂表面。介 例如是氮切，且第二介電層210的形成綠 例如疋化學氣相沉積法。 繼之，凊參照圖2C，回钱第二介電層210而於開口 2⑽的·上形成間隙壁廳。間隙壁通的形成方法例 籲如是進行非等向性凝刻製程，直至開口 208中基底200表 面及/或罩幕層206a頂表面露出。另外，間隙壁210a的厚 度耗圍例如是約50埃至4〇〇埃，其中較佳的範圍是1〇〇 埃至200埃。之後，於開口 2〇8下方的基底勘中形成源 極級極區2】2。源極/沒極區212的形成方法例如是離子 入製程。 之後，請參照圖2D，進行熱氧化製程214，以氧化 口 208中所暴露之基底200表面，而於源極/汲極區212上 13 06289fttwf.doc/e 方形成絕緣層216。熱氧化製程214例如應用矽局部氧化 法（LOCOS)之技術；而反應溫度約為攝氏7⑽度_11〇〇 度。絕緣層216例如是氧化矽層，而厚度範圍約介於2〇〇 埃至600埃間。其中較佳是在3〇〇埃至400埃之間。而應 用矽局部氧化法技術所形成之絕緣層216之表面略高於基 底200表面，且其鳥嘴結構更有助於隔絕效果。絕緣層216 疋用來當作埋入式沒極氧化層（buried drain oxide layer), 由於利用熱氧化製程214來製作絕緣層216 ,其隔離品質 優於利用化學氣相沈積所形成的絕緣層。 、 利用熱氧化製程214的另一個好處是，絕緣層216是 以自行對準的方式在源極/汲極區212上方形成，因此可以 省略微影製程，麵免前制疊雜差(Qv咖eiT〇r)的問 題。由於間隙壁210a形成在浮置閘極2〇4a之側壁，因此 可以避免浮置卩雜204a的表面被氧化n面，源極/ 汲極區212的摻質在經過熱氧化製程214之後，向基底2〇〇 内進一步擴散，而會形成更大的分佈輪廓。 隨後，請參照圖2E，移除罩幕層2〇6a。移除罩幕層 20=的方法例如是以熱磷酸為侧液⑽式朗製程。在 本只施例中，移除罩幕層2Q6a同時移除了間隙壁m 但疋本發明亚不以此為限。換言之，在另一實施例中，間 隙土 21Qa是在罩幕層2Q6a被移除之後，以另—澄式餘刻 除。然後，形成—層關介電層218覆蓋浮 甲° &之表面及絕緣層216之表面。閘間介電層218 的材質例如是氧切/氮化魏切(⑽〇)複合層，且問間 10 ，1306聊一 :電:。218的厚度例如介於約麻25〇埃之間，較佳約是 然後，於閘間介電層218上形成一声 =丨=做為此非揮發性刚的控：二 浮置閘極2。二7:接：積^ 率。 牧j W有效地增加了閘極耦合 法至列ίΓ所提出的非揮發性記憶體之製造方 層，：此===的方式來形成埋入式汲極氧化 了閘極耦合率。 4 3的面積，因此增加 一而:無次 揮發性記憶體具有“間=率勻=介，而使非 作速度與效能。 祸口羊進而，改善元件操 雖然本發明已以較佳實施例揭露如上，料並非用 以 twf.doc/e 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1是習知的一種非揮發性記憶體的剖面示意圖。 圖2A至圖2E是本發明一實施例的非揮發性記憶體的 製造流程剖面圖。 【主要元件符號說明】The method of formation is, for example, a thermal oxidation method. A body layer is formed on the first dielectric layer. The material of the conductor layer 204 is, for example, doped, and the formation method of the layer 204 is, for example, a chemical vapor deposition process. Then, a layer of the mask layer is formed on the conductor layer 204. The material of the mask is, for example, a nitride nitride and a 2% formation of a mask layer. After deuteration, please refer to ®1 2B to remove part of the mask layer, curtain layer 206a. The method of removing part of the mask layer 2〇6 to form the cover is, for example, prior to the thickness of the mask, forming a patterned photoresist layer (not shown) on the 1306 gas “206”, and then performing a non-equal buttoning &; 'To pattern the mask layer 2Q6, then remove the patterned light ^ 2' into the mask layer 2Q6a. Then, the mask layer 2Q6a is used to engrave the conductor layer 2〇4 and the first dielectric layer 2 〇2, forming a floating gate 204a, a tunnel dielectric layer 2〇2a, and a plurality of openings 2 (10), wherein the patterning method is, for example, an anisotropic etching process to form an etch stop layer. e • In the present embodiment, 'the opening 2〇8 exposes the substrate 200, however: ', not limited thereto. In other words, in another embodiment, the opening 208 bottom 4 still retains a partial dielectric. The layer is moved without exposing the substrate 2A. Referring to FIG. 2B, the second dielectric layer 210 conforming to form a layer is re-applied to the surface of the opening 2〇8 and the top surface of the mask layer ma. The second dielectric layer 210 is formed by a green, for example, germanium chemical vapor deposition method. Subsequently, referring to FIG. 2C, the second dielectric layer 210 is returned to the opening 2 (10). The gap wall is formed thereon. The method of forming the gap wall is for example an anisotropic encapsulation process until the surface of the substrate 200 and/or the top surface of the mask layer 206a are exposed in the opening 208. In addition, the thickness of the spacer 210a is consumed. The circumference is, for example, about 50 angstroms to 4 angstroms, and the preferred range is from 1 angstrom to 200 angstroms. Thereafter, the source-level polar region 2] 2 is formed in the underlying substrate below the opening 2〇8. The formation method of the /pole region 212 is, for example, an ion implantation process. Thereafter, referring to FIG. 2D, a thermal oxidation process 214 is performed to oxidize the surface of the substrate 200 exposed in the port 208, and on the source/drain region 212. The 06289fttwf.doc/e side forms the insulating layer 216. The thermal oxidation process 214 is applied, for example, to the technique of local oxidation (LOCOS); and the reaction temperature is about 7 (10) degrees Celsius to 11 degrees. The insulating layer 216 is, for example, a hafnium oxide layer. The thickness ranges from about 2 angstroms to 600 angstroms, preferably between 3 angstroms and 400 angstroms. The surface of the insulating layer 216 formed by the partial oxidation technique is slightly higher than the substrate 200. Surface, and its bird's beak structure is more conducive to isolation. The layer 216 is used as a buried drain oxide layer, and the insulating layer 216 is formed by the thermal oxidation process 214, and the isolation quality is superior to that of the insulating layer formed by chemical vapor deposition. Another benefit of utilizing the thermal oxidation process 214 is that the insulating layer 216 is formed over the source/drain regions 212 in a self-aligned manner, so that the lithography process can be omitted and the front side stacking noise is eliminated (Qv coffee eiT The problem of 〇r). Since the spacer 210a is formed on the sidewall of the floating gate 2〇4a, it is possible to prevent the surface of the floating doping 204a from being oxidized by the n-plane, and the dopant of the source/drain region 212 is subjected to heat. After the oxidation process 214, it further diffuses into the substrate 2, and a larger distribution profile is formed. Subsequently, referring to FIG. 2E, the mask layer 2〇6a is removed. The method of removing the mask layer 20 = is, for example, a hot phosphoric acid as a side liquid (10) type process. In the present embodiment, the mask layer 2Q6a is removed while the spacer m is removed, but the present invention is not limited thereto. In other words, in another embodiment, the gap soil 21Qa is removed after the mask layer 2Q6a is removed. Then, a layer-forming dielectric layer 218 is formed to cover the surface of the floating surface and the surface of the insulating layer 216. The material of the inter-gate dielectric layer 218 is, for example, an oxygen-cut/nitrided Wei-cut ((10)〇) composite layer, and the inter-10, 1306 chat: electricity:. The thickness of 218 is, for example, between about 25 angstroms, preferably about 00. Then, a sound is formed on the inter-gate dielectric layer 218. = 丨 = control for this non-volatile: 2 floating gate 2. Two 7: pick: the rate of accumulation. Shepherd j W effectively increased the gate coupling method to the manufacturing layer of the non-volatile memory proposed by the column: this === way to form the buried gate oxidized gate coupling ratio. The area of 4 3 is therefore increased by one: the non-volatile memory has "intermediate = rate uniformity", and the speed and performance are not made. In addition, the improvement of the component operation, although the preferred embodiment of the present invention has been As disclosed above, it is not intended to limit the invention to twf.doc/e, and any person skilled in the art can make some modifications and retouchings without departing from the spirit and scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view of a conventional non-volatile memory. FIG. 2A to FIG. 2E are non-volatile memories according to an embodiment of the present invention. Sectional view of the manufacturing process of the body.
100、200 :基底 102、202a :穿隧介電層 104、204a :浮置閘極 104a、104b、108、204、220 :導體層 106、218 :閘間介電層 110、212 :源極/汲極區 112 :氧化層 202 :第一介電層100, 200: substrate 102, 202a: tunneling dielectric layers 104, 204a: floating gates 104a, 104b, 108, 204, 220: conductor layers 106, 218: inter-gate dielectric layers 110, 212: source / Bungee region 112: oxide layer 202: first dielectric layer
206、206a :罩幕層 208 :開口 210 :第二介電層 210a :間隙壁 214 :熱氧化製程 216 :絕緣層 12206, 206a: mask layer 208: opening 210: second dielectric layer 210a: spacer 214: thermal oxidation process 216: insulating layer 12
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