TWI305373B - Circuit board and method for fabricating the same - Google Patents

Description

1305373 16270twf.doc/g IX. Description of the Invention: [Technical Field] The present invention relates to a circuit board and a method of manufacturing the same, and more particularly to a circuit board having a multilayer wiring layer and a method of manufacturing the same . [Prior Art] - At present, in the semiconductor package manufacturing, the circuit board has the advantages of fine wiring, compact assembly, and good performance, so that the circuit substrate has become a component for use in the financial system. In general, the circuit substrate is mainly composed of a plurality of circuit layers (patterned dreuitlaye and multi-layer dielectric layer (sulfur-resistant layer) fathers for the combination of 'the middle of the circuit layers through the conductive vias to achieve each other 1A to 1C are shown as flow diagrams of a conventional method for fabricating a circuit board. Referring to FIG. 1A, a substrate 11 is first provided, wherein the substrate 11 is = epoxy resin ( Epoxyresin) or gyssfiber oxyresin. Then, by electroplating, ', f35' is formed on the substrate UQ, and then the conductive layer is patterned by lithography and engraving to form a patterned conductive Layer 12〇. Referring to FIG. 1B, a dielectric layer m is formed on the patterned conductive layer 12A. Then, a plurality of blind vias are formed on the dielectric layer 1; 3〇. After FIG. 1C', an electroconductive layer is used to form a conductive layer on the wall of the dielectric layer 13 and the blind hole 135, and the conductive layer is patterned by using a shadow and a residual pattern. To form a patterned conductive layer and a blind hole for the money separately Plated blind via) 145. Then, 1305373 16270twf.doc/g forms a dielectric layer 150 on the patterned conductive layer 140 and the plating via 145. Then, a plurality of blind vias 155 are formed on the dielectric layer 150. 1D, a conductive layer is formed on the walls of the dielectric layer 15 and the via hole 155, and the conductive layer is patterned by lithography and lithography to form the patterned conductive layer 160 and the electric ore, respectively. Blind hole 165. Next, a solder mask 170 is formed on the patterned conductive layer 16 and the plating via 165, and a plurality of openings 175 are formed on the solder mask layer 17 to expose the wiring layer 16G. The plurality of contact regions 167 are completed, and the lands are completed. In the circuit substrate 100, in order to enable the patterned conductive layer 14 to be electrically connected to the scribe wire layer 16G, the conventional technology is blind. The holes are separated from the conductive blind holes 145 by an appropriate distance. However, the circuit substrate _ has a larger _ and lower cloth non-conductive blind holes 145 and 165 are not easy to manufacture and the quality is unstable 因此 so the conductive blind holes 145 and 165 are not Fabric substrate "which has a higher aspect of the invention" is intended to The method is to improve the manufacturing of the circuit substrate H by the 'circuit substrate. The body of the W 4 degree and the small circuit substrate is based on the above object and the other purpose. The present invention proposes the manufacture of the circuit substrate 1305373 I6270twf.doc/g. The method includes first providing a core board, a first metal composite layer, a second metal composite layer, a first dielectric layer and a second dielectric layer, wherein the upper and lower surfaces of the core board are electrically connected to each other a first circuit layer and a second circuit layer, the first metal composite layer comprises a first metal layer, a second metal layer and a first residual barrier layer, and the first etch barrier layer Conductively disposed between the first metal layer and the second metal layer, the second metal composite layer includes a third metal layer, a fourth metal layer and a second etching barrier layer, and the second etching barrier The layer is electrically conductive and disposed between the third metal layer and the fourth metal layer, and the first dielectric layer and the second dielectric layer respectively have a plurality of first through holes and a plurality of second through holes. Thereafter, the second metal layer is patterned to form a plurality of first bumps, wherein the positions of the first bumps are corresponding to the positions of the first uniform holes. Next, the fourth metal layer is patterned to form a plurality of second bumps, wherein the positions of the second bumps are corresponding to the positions of the second through holes. Thereafter, the patterned first metal composite layer is laminated to the first circuit layer with the first dielectric layer, so that the first metal layer is electrically connected via the first bumps inserted into the first through holes. The first circuit layer. And bonding the patterned second metal composite layer and the second dielectric layer to the second circuit layer, so that the third metal layer is electrically connected via the second bumps inserted into the second through holes. Two circuit layers. Next, the first metal layer and the third metal layer are patterned to form a third circuit layer and a fourth circuit layer, respectively. A method of manufacturing a circuit substrate according to a preferred embodiment of the present invention, wherein before the patterning of the first metal composite layer, the first dielectric layer and the first circuit layer, for example, the first circuit is further included The layer and the patterned first metal composite layer will contact the surface of the first dielectric layer to perform a roughening. 1305373 16270twf.doc/g buried and the second circuit layer is a layer: the second layer of the second dielectric layer The metal composite layer will be in contact with the material. The surface of the electric layer enters the 仃-roughening method, and the + forms some t-bases (4) to form the barrier layer as a barrier, and the second obstruction is preferably in accordance with the present invention. . a method in which the manufacturing barrier layer of the circuit substrate in which the second convex surface is formed is used as a residual barrier, and the fourth metal ==== residual etching method, the rrr embodiment is formed in the first embodiment. :=4=Layer has a plurality of contact regions respectively, - after the third layer of the solder mask layer, for example, an opening, these openings expose the contact region. : Exterior: = 陶有后后', for example, including the formation of a solder mask layer on these contact regions. The method, wherein the third circuit layer is formed by the circuit substrate of the Chu Yanggu aβ, and forms the third circuit layer and the fourth secret; the second plurality of contact regions 'on the surface of the metal layer and the third metal layer' 'For example, it is included in the first: is located in the subsequent formation of the third line layer 'anti-oxidation addition' in the formation of the third line layer and the fourth line two = 1305373 16270twf.doc / g including covering a rape early increase in the third line layer with On the fourth circuit layer, the i cover layer has a plurality of openings, and the 4b opening|exposed @八'dry" the first dielectric layer of the electric layer, the third circuit screen, only the plurality of first bumps, and a plurality of The second bumps are two: two; there are electrically connected - the first circuit layer disk - a plurality of first through holes. The second dielectric layer is disposed on the nuclear surface and 2: more: the second through hole. The three-layer layer is matched with: a layer: a second dielectric layer on the T. The first bump-first block is bonded to/electrically connected to the first circuit layer and the third circuit layer. The first bump is disposed in the second layer a through-hole layer of a convex line. The residual barrier layer is disposed on the road layer and the fourth portion, and the first bumps and the second and second layers of the second and fourth layers are electrically conductive. Between 9 and etch barrier layer according to a preferred embodiment of the present invention: a solder mask layer covering at least the third line reverse', for example, a second circuit layer and a fourth circuit layer respectively and a fourth circuit layer, wherein the first Multi-smoke openings, these openings are exposed: the two-bonded contact area' and the solder mask layer includes the circuit substrate described in the example, for example, more than one connection, and the anti-oxidation layer: the layers have respectively According to the preferred embodiment of the present invention, the material of the barrier layer includes, for example, the circuit substrate as described in the example, and the material of the material is 10 1305373 16270 twf.doc/g, for example, including copper.

Since the bump used in the present invention is a solid structure, the present invention has the advantage of reducing the power: the advantage of the point: ^^ into the circuit layer due to the point-and-point technology. The present invention can directly directly implement the second layer; To shorten the pitch between the contact areas, the middle::: is connected to the area occupied by the area. Therefore, the present invention is more capable of manufacturing a wiring within a twist and miniaturizing a circuit board. The above and other objects, features and advantages of the present invention will become more apparent and understood. [Embodiment] Figs. 2A to 2G are diagrams showing the manufacture of a circuit board according to an embodiment of the present invention. Referring to Figure 2A, this embodiment includes providing a metal composite layer 210 first. The metal composite layer 21A includes metal layers 212, 214 and an etch barrier layer 216, wherein the etch barrier layer 216 is electrically conductive, and the etch barrier layer 216 is disposed between the metal layers 212 and 214. In a preferred embodiment, the material of the metal layers 212, 214 is, for example, copper, and the etch barrier layer 216 is, for example, nickel. Referring to FIG. 2B, the photoresist layers 310a and 31b are respectively formed on the metal by, for example, applying a dry film photoresist, using a spin coating liquid crystal or other means. On the surface of layers 212 and 214. Thereafter, for example, by means of lithography and etching, 1305373 16270twf.doc/g:=: layer 216 is a barrier, and the metal layer is formed, ΐ: 'then, remove the residual photoresist layer hall,未被 ί ί ί ί ί ί ί ί ί ί ί Covering 1 Insect resistance 1 2曰30 as αΪ Note that although this embodiment has a convex shape with a trapezoidal cross section. As a silk ship, but the section of the fortune-defining bump 23G 220 spoon clear ingf 兀 ' provides a metal composite layer 220. The metal composite layer has included the 1 genus layer 222, 224 and the money 刿p and the land 厗? The barrier layer 226 is electrically conductive, while the day-to-earth layer 6, which is 厗 and the etch barrier layer 226, is disposed between the (four) 24 of the metal. In a preferred embodiment, the metal layer 222 ′ = material is, for example, copper, and the remaining barrier layer is, for example, recorded. 2D 'for example, by attaching a dry film photoresist, using spin coating or the like, The photoresist layer 315 & and the 315b wheel are respectively on the surface of: Γ2ίΐ22: after that, for example, by using the method of lithography H and (10) the layer 226 is a (four) barrier, the gold 2 224 is patterned to form a plurality of bumps of the first resist layer 315a and the dish. Alternatively, the etch barrier layer 226 may be covered by 24 Å. It is worthwhile. The main 咅 is that the bump = the trapezoidal bump is exemplified as "the bump 240" Section shape. The month I is not limited to the layer: f: provides the core board 250 ’ of which the core board 250 is inside? σ is a molecular polymer, a polymer containing glass fiber, an epoxy resin or other materials. The core board 25〇人 1305373 16270twf.doc/g is electrically connected to each other. In the present embodiment, the wiring layer 252 is electrically connected to the wiring layer 252 via the via hole 256.介 Continue to provide dielectric layers 260 and 265 with reference to Figure 2E'. The dielectric layers 260 and 265 have a plurality of through holes 262 and 267, respectively, wherein the through holes 262 and 267 are formed by mechanical drilling, laser drilling or other drilling methods, for example. It should be noted that the positions of the through holes 262, 267 correspond to the positions of the bumps 23 〇, 24 上 on the metal layers 212, 222, respectively, so that the metal layers 212, 222 are respectively oriented in the directions 314, 316. When the electrical layers 26, 2 are slid, each of the bumps 230, 240 can be inserted into the corresponding through hole 262 or 267. 'Please refer to 2E and 2F together, and the patterned metal composite layer 22〇 and the dielectric layer 260 are pressed in the direction 314 with the core plate 250, and the patterned metal composite layer 210 and the dielectric layer 265 are along Direction 316 Pantoxin* 250 is pressed so that each of the bumps 230 is in the corresponding = 262 or 267, wherein the pressing is performed by, for example, heating and pressing. As such, the metal layers 212, 222 and the circuit layers 252, 254 can be electrically connected to each other (as shown by ^2F) by the bumps 230, 240 and the plated through holes 256. In a preferred embodiment, the surface of the patterned metal composite layer 21 facing the dielectric layer 265 may be roughened before the pressing, so that the patterned metal composite layer 21 is patterned. There is a good bond between the germanium and the dielectric layer 265, wherein the roughening treatment is, for example, brown oxidation or black oxidation. Alternatively, the surface of the metal composite layer 220 after the dielectric layer 26 can be roughened before the press-bonding is performed to make the patterned metal composite layer 220 and the patterned metal composite layer 220 There is a good bond between the electrical layers 260, wherein the roughening treatment is, for example, brown oxidation or black oxidation. Of course, in this embodiment, the surface of the patterned metal composite layers 21 and 220 may be roughened at the same time before the pressing. ', please refer to ® 2G, for example, in the form of lithography and money engraving, the metal layers 212 and 222 are formed to form the circuit layer fairy and 222 & to complete a ^

Road substrate 200. In addition, since the metal layers 214 and 224 are respectively used to form the protrusions 24〇 and 23() through the dielectric layers 260 and 265, and the metal layers 212 and 222 are used to form the wiring layers 212a and 222a, respectively, the metal Layers 214 and 224 have a greater thickness, while metal layer 2 and thickness from it are too large. It should be noted that if the real complement is not shouted by the bump 230, the surname barrier layer 216 not covered by the bumps 230 and 24〇 is removed. This embodiment can also form the circuit layers 212a and 220a. In the knowledge, the (four) barrier layers 216 and 226 are removed. In a preferred embodiment, the wiring layers 212a and 222a are formed to selectively form a solder mask layer 7 on the wiring layers 212a and 2. The dry cover layer and the milk have a plurality of openings (4), and the beans: expose the contact layer of the circuit layer 212a and the heart. The anti-oxidation layer 29〇a and the lining line 2a are connected to the contact area 280. In the middle, the & β /, zzza 4 is for example an electric mine. Correction, r ^ layer 29Ga and 29% formation mode disk 八 思 m several holes 290a, for example, including a nickel layer 292a 2;;: 'antioxidant layer 29%, for example, including - nickel layer _ and - to layer b . The right side is formed by electroplating to form anti-oxidation layers 290a and 290b, 1305373 16270twf.doc/g, and the surface layer j 12a and 222a may be designed with a short stub (not shown) or used to form an entire antioxidant. Layer 27〇.

Fig. 2H~21! will be shown as another method of completing the circuit layer and the oxidation resistant layer after the step shown in Fig. 2F. Referring to FIG. 2H, in this embodiment, before the formation of the circuit layers 2 and 2, the metal layer 212 may be used first. The surface of 222 forms an anti-oxidation layer 29〇a and 29〇b, and the method of forming f oxide layer bird and 2 times in the basin is, for example, an electric ore, and the anti-oxidation layer=column includes a nickel layer 292 continuous-gold layer (10) The anti-oxidation layer 鸠 includes, for example, a nickel layer 292b and a gold layer 294b. Referring to FIG. 21, the oxidation resistant layer a" 290b is patterned, for example, by using a lithography process, wherein the patterned anti-oxidation layer 2 is placed at the position of the metal layers 212 and 222 to be formed. On the contact region 280 of the circuit layers 212a and 222a, it is worth mentioning that if the patterned anti-oxidation layers 270 and 275 are formed by the method of FIGS. 2H to 2J, the electroplated short segments may not be needed in the subsequent process. As can be seen from FIG. 2G, the circuit substrate 2 of the present embodiment includes a core board 250, dielectric layers 26 and 265, circuit layers 212a, 222a, 252 and 254, a plurality of 230 and 240, and an etch barrier. The upper and lower surfaces of the layer 216 and the board (4) respectively have circuit layers 252 and 254 electrically connected to each other. The dielectric layer 260 is disposed on the upper surface of the core board 25 and has a plurality of 262 through holes. The dielectric layer 265 It is disposed on the lower surface of the core plate 25B and has a plurality of through holes 267. The circuit layer 222a is disposed on the dielectric layer 26, and the circuit layer 212a is disposed on the dielectric layer 265. The bumps 24 are disposed in the through holes

15 1305373 16270twf.doc/g 2 and electrically connect the circuit layers 222a and 252. The bumps 23 are disposed in the = two via holes 267 and electrically connected to the circuit layers 212a and 254. The etch resistance P is pre-disposed between the bump 23 and the wiring layer 2Ha, and between the bumps 24 and the wiring layer 2, and the side barrier layers 226 are electrically conductive. Figure 2J is a cross-sectional view of a circuit substrate according to another embodiment of the present invention. Referring to Figure 2J, since the circuit substrate 2 of the present embodiment is similar to the above-mentioned circuit substrate fan, the same reference numerals are used. The same elements will not be described again here. The circuit substrate 2A of the present embodiment differs from the above-mentioned circuit substrate 2GG mainly in the electrical connection of the circuit layers 252 and 25. In addition to the electric mine through hole 256 shown in FIG. 2G, the prior art can utilize the previous The disclosed method of fabricating the bumps 230 and 240 is electrically connected to the 252 circuit layers 252 and 254. In other words, although the embodiment of the present invention electrically connects the layer 252 to the circuit layer 254 by the electric ore via 256 or the bump 258, the embodiment may further utilize a conductive layer or Other conductive media are used to complete the electrical connection between layers 252 and 254. In summary, since the present invention utilizes a semiconductor process, it is fabricated directly on the wiring layer. Therefore, the present invention has a relatively simple advantage in the process of the present invention. The shovel and the shovel of the shovel are solid structures. Therefore, the present invention has the principle of reducing the signal noise by connecting the second layer of the circuit layer. More can be directly; on the bump. In this way, the present invention can shorten the & distance between the contact area 16 1305373 16270twf.doc/g and reduce the contact area. =: The circuit substrate has a high density of interconnecting: 2 (4) has been better The embodiment disclosed above is not intended to be used by those skilled in the art to make some modifications and retouchings without departing from the spirit of the present invention.

The scope is subject to the definition of the scope of the patent application attached. D

BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1A to m! show the flow of a conventional method of manufacturing a circuit board. 2A to 2G are schematic diagrams showing the fabrication of a circuit substrate according to an embodiment of the present invention. 2H to 21 illustrate another method of forming a wiring layer and an oxidation resistant layer after the step shown in Fig. 2F is completed. 2J is a cross-sectional view of a circuit substrate according to another embodiment of the present invention. ΠNot [Main component symbol description] 100, 200: circuit substrate 110: substrate 112, 262, 267: through hole 114: opening 120a, 120b: conductive metal layer 130, 256: plated through holes 140a, 140b, 252, 254, 212a, 222a: circuit layer 1305373 16270twf.doc / g 150a, 150b, 270, 275: solder mask layer 210, 220: metal composite layer 212, 214, 222, 224: metal layer 216, 226: etch barrier layer 310a, 310b, 315a, 315b: photoresist layer 230, 240: bump 2 50. core board 260, 265: dielectric layer 290a, 290b: oxidation resistant layer 292a, 292b: nickel layer 294a, 294b: gold layer 160, 280 : Contact area 310, 312, 314, 316: direction

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Claims (1)

1305373 16270twf.doc/g X. Patent Application Range: 1. A method for manufacturing a circuit substrate, comprising: providing a core board, a first metal composite layer, a second metal composite layer, a first dielectric layer and a a second dielectric layer, wherein the upper and lower surfaces of the core board respectively have a first circuit layer and a second circuit layer electrically connected to each other, the first metal composite layer comprising a first metal layer and a second a metal layer and a first etch barrier layer, the first etch barrier layer being electrically conductive and disposed between the first metal layer and the second metal layer, the second metal composite layer comprising a third metal a layer, a fourth metal layer and a second photoresist layer, the second etch barrier layer is electrically conductive and disposed between the third metal layer and the fourth metal layer, and the first dielectric The layer and the second dielectric layer respectively have a plurality of first through holes and a plurality of second through holes; patterning the second metal layer to form a plurality of first bumps, wherein the first bumps The position is corresponding to the position of the first through hole; the fourth metal layer map Forming a plurality of second bumps, wherein the positions of the second bumps are corresponding to positions of the second through holes; • patterning the first metal composite layer and the first dielectric Laminated to the first circuit layer, such that the first metal layer is electrically connected to the first circuit layer via the first bumps inserted into the first through holes, and the patterned first layer The second metal composite layer and the second dielectric layer are laminated on the second circuit layer, so that the third metal layer is electrically connected to the second metal via the second bumps inserted into the second through holes. a second circuit layer; and the first metal layer and the third metal layer are patterned to form a third circuit layer and a fourth circuit layer, respectively. 19 1305373 16270twf.doc / g method, 4 manufacturing circuit board according to the first item, the first layer - metal composite layer, the first dielectric -= 2. a composite layer that will contact the surface of the first dielectric layer The method, the manufacturing circuit layer of the circuit substrate according to item 1 of the first aspect, and the second metal composite layer and the second dielectric layer after the invention, further comprising the second circuit layer and the pattern- The roughening method and the plexus layer contacting the surface of the second dielectric layer, and the method for manufacturing the circuit substrate according to the first aspect of the patent to form the first bumps includes: performing a 1 (four) barrier The layer is used as a thin barrier, and the second gold layer is widely etched. Unlawful, the method for manufacturing the second substrate of the circuit substrate described in the Dragon Patent 1 includes: performing a two-dimensional m barrier as a similar, turning, the fourth gold shoulder Engraving process. The method of manufacturing a circuit board of the circuit board according to the first aspect of the patent, and having a plurality of replacements in the fifth circuit layer and the fourth circuit layer respectively forming the third circuit layer and After the fourth circuit layer, the package #: medium read-welding layer is on the third circuit layer and the fourth circuit layer, and the core 7 has a plurality of openings in the cover layer, and the openings expose the contact regions . The method of manufacturing a circuit board according to claim 6, wherein the forming of the solder mask layer further comprises: forming an anti-oxidation layer on the contact regions. 8. The method of manufacturing a circuit substrate according to claim 1, wherein the third circuit layer and the fourth circuit layer respectively have a plurality of contact regions, and the third circuit layer and the fourth are formed. Before the circuit layer, the method further includes: forming an anti-oxidation layer on the surface of the first metal layer and the third metal layer, the anti-oxidation layer being located in the subsequently formed third circuit layer and the fourth circuit layer Some contact areas. 9. The method of manufacturing the circuit substrate of claim 8, wherein after forming the third circuit layer and the fourth circuit layer, the method further comprises: covering a third wiring layer with the solder mask layer The fourth circuit layer, wherein the solder mask layer has a plurality of openings, the openings exposing the anti-oxidation layer on the contact regions. 10. A circuit board, comprising: a core board having a first circuit layer and a second circuit layer electrically connected to each other; and a first dielectric layer disposed on the core board a first dielectric layer having a plurality of first through holes; a second dielectric layer disposed on a lower surface of the core plate, the second dielectric layer having a plurality of second through holes; a third circuit layer disposed on the first dielectric layer; a fourth circuit layer disposed on the second dielectric layer; a plurality of first bumps disposed in the first through holes, and Electrical connection 21 1305373 16270twf.doc / g the first circuit layer and the third circuit layer; a plurality of second bumps disposed in the second through holes, and electrically connected to the second circuit layer and the a fourth circuit layer; and an etch barrier layer disposed between the second bumps and the fourth circuit layer and between the first bumps and the third circuit layer, the etch barrier layer has Electrical conductivity. 11. The circuit substrate of claim 10, further comprising a solder mask layer covering at least the third circuit layer and the fourth circuit layer, wherein the third circuit layer and the fourth circuit layer respectively have A plurality of contact regions, and the solder mask layer has a plurality of openings that expose the contact regions. 12. The circuit substrate of claim 10, further comprising an oxidation resistant layer, wherein the third circuit layer and the fourth circuit layer respectively have a plurality of contact regions, and the oxidation resistant layer is disposed on the These are on the contact area. 13. The circuit substrate of claim 10, wherein the material of the etch barrier layer comprises nickel. 14. The circuit substrate of claim 10, wherein the material of the first circuit layer, the second circuit layer, the third circuit layer, and the fourth circuit layer comprises copper. twenty two