TWI304635B - - Google Patents

Description

Ι Ό Ό Ό Ό Ό Ό 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 91 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The x layer (0<χ<1) forms a low resistance, adjustable contact. In modern semiconductor manufacturing technology, traditionally by forming ohmic connections

Contact with Ohmic contact or diffusion contact to form MS (metal-semiconductor; metal-semiconductor) contact. In the former technique, a push fabric is implanted into the MS interface layer to a concentration above the solid solubility limit (ie, N(n, p) > 102 G cm_3) to form a tunneling barrier (tunneling). Bar^ri er ). As for the latter technique, the dopant is diffused into the interface layer to reduce the height of the Schottky Barrier Height (Schottky Barrier Height; 矽 is a commonly used semiconductor with a high intrinsic SBH (or Eg (energy gap)), Eg = l· 11 eV. Therefore, when using germanium, a relatively high doping concentration (usually using high energy implants) is required on the Ms interface layer to lower the SBH and thus form a better contact. high

The 3D ruler does not require a deep contact junction, which causes the device to be subjected to a Sh〇rt channel effect (SCE) or a punch-through (leakage). SUMMARY OF THE INVENTION The present invention is directed to such a semiconductor device. One of the objectives of the invention is to provide a metal/semiconductor dielectric comprising low resistance contacts in order to solve the above problems.

1304635 ------9Πηΐπ;ρ/[ V. INSTRUCTION DESCRIPTION (2) genus/semiconductor. A low-resistance contact is formed on the I surface, which protects the device from short-channel effects and prevents leakage. It is yet another object of the present invention to provide a low resistance, adjustable contact suitable for use in CMOS devices. To achieve the above object, a semiconductor device of the present invention includes a semiconductor-dielectric layer on the semiconductor substrate having a contact opening exposing the half-body substrate; a SixGei_x layer in which the contact opening is shaped, wherein 0<χ<1; and a metal plug on the 3, (X) X layer, filled in the contact opening. The invention also provides a method to form a two metal contact on the metal/semiconductor interface. Forming a dielectric layer on a semiconductor substrate. A contact opening is formed in the n-electrode layer to expose the semiconductor substrate. In the contact, a -SixGei_x layer is formed in the port, #w<x<1. Finally, a metal is inserted The base is filled in the x layer of the contact opening.

BRIEF DESCRIPTION OF THE DRAWINGS X Figures la to le show cross-sectional views of a manufacturing process for fabricating a metal contact on a metal/semiconductor interface in accordance with a first embodiment of the present invention. 2a to 2d are cross-sectional views showing a manufacturing process for fabricating a metal contact on a metal/semiconductor interface in accordance with a second embodiment of the present invention, in which a consumable polysilicon layer is selectively formed on the KSi_Ge layer. Figures 3a through 3e show cross-sectional views of a fabrication process for fabricating a metal contact on a metal/semiconductor interface in accordance with a third embodiment of the present invention, wherein a compliant consumable polysilicon layer is formed. 4a to 4e are diagrams showing the manufacture of a fourth embodiment in accordance with the present invention

Ι3Ό4635 _;_Case No. 91101584_年月曰 Correction _ V. Description of invention (3) Cross-section of the manufacturing process of CMOS. Figure 5 is a cross-sectional view of a CMOS according to a fifth embodiment of the present invention. Figure 6 is a cross-sectional view of a CMOS according to a sixth embodiment of the present invention. DESCRIPTION OF REFERENCE NUMERALS 1 0~ semiconductor substrate, 2 0~ dielectric layer, 3 0~ contact opening, 40~SixGe Bu x layer (0<χ<1), 5 0~metal layer, 5 2~adhesive layer, 5 4 ~ diffusion barrier layer, 90, 92, 94 ~ metal telluride layer, 60 0 ~ diffusion region, 7 0 ~ metal plug, 8 0, 8 2 ~ consumable polysilicon layer; 1 0 0 ~ semiconductor substrate, 120~N well, 140~P well, 2 2 0~ gate oxide, 240~polycrystalline layer, 610, 62 0~ source/drain region, 2 0 0~ dielectric layer, 3 0 0~ Contact opening, 400~8^6 divination layer (0<also <1),

0593-6873TWFl;90030;Cathy.ptc Page 6 1304635 Amendment No. 91101584 V. Invention description (4) 5 0 0~ metal layer, 5 2 0~ adhesive layer, 540~ diffusion barrier layer, 320, 340~ light Resistive layer, 920, 940, 960~ metal telluride layer, 630, 640~ diffusion region, 700~ metal plug, 8000, 8 2 0~ consumable polycrystalline stone layer. Detailed description of the invention

The six (^-X2 band gap) range is from 0.67 (x = 〇) to 1.11 eV (x = l). That is, the energy of the sixthGeix (0<x<1) is purer. The main feature of the present invention is that a layer of semiconductor material having a low energy band gap energy is formed in one of the contact openings of the metal/semiconductor interface (0<χ<1). Lower band gap energy reduces the metal. —Semiconductor X(M^)X^ Fermi level, which in turn reduces the SM of the interface. Lower, SBH reduces the contact resistance, so moderate doping can form good contact on the metal/semiconductor interface. This protects the device from short path effects and does not leak. > ~ First, the first to elth figures show a manufacturing flow diagram for fabricating a metal contact on a metal/semiconductor interface in accordance with a first embodiment of the present invention. In the first drawing, a dielectric layer 2 is formed on a semiconductor substrate 10. A contact opening 3 is formed in the dielectric layer 20 to expose the semiconductor substrate 10. Then, a SixGei_x layer is formed in the contact opening 30. 40.

1304635 ___ _ Case No. 91101584__年月日日_Amendment_ V. DESCRIPTION OF THE INVENTION (5) The SixGe^x layer 40 can be formed by various methods, such as MBE (molecular beam epitaxy), UHV-CVD (ultra) -high vacuum chemical vapor deposition), RT-CVD (rapid thermal CVD), and LRP-CVD (limited reaction processing CVD 'restriction reaction process cvd). For example, the S LGeh layer 40 can be formed by a selective epitaxial growth method at a relatively low temperature range (<8〇〇.C). 3込〇61_5 (layer 40 is preferably a rich 矽 (^^(:〇11一1^(:^)3]^(^1 layer' is similar in nature to pure 。. This will reduce the difference ( The opportunity of dislocation. For example, χ is preferably in the range of 〇·5<χ<〇· 95. A previous report pointed out that a thin layer of SiGe thinner than the critical thickness (with its stoichiometry and deposition) Conditions related), , process, will not produce a difference row in the Shixi substrate. Therefore 吏 =; = 疋 lxGei-x layer 40 thickness should be controlled to be less than critical thickness to maintain it in strain (strained In the state of the state, it is not caused by the lattice mismatch between the two, otherwise there will be leakage on the joint surface.

The SixGei_x layer 40 is preferably a differential row of strained Si G within the semiconductor substrate 10. This Si Γρoff/wide does not cause the thickness of the germanium layer 40 to be preferably greater than or exclusively for 5 nm and less than or equal to 3 〇 nm. Next, in the figure, on the SixGeix layer 4〇5〇. For example, the metal layer may be composed of a 篓 至 warfare layer, i, ς r 耆 耆 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 52 Formed on.

1304635 Case No. 91101584 修正 Amendment 5. Invention Description (6) The adhesive layer 52 may be a titanium (Ti) layer which has good adhesion to the dielectric layer 20. The diffusion barrier layer 54 can be a TiN layer to protect the semiconductor germanium substrate 10 from attack by fluorine in the post tungsten deposition process (post tungsten deposition P r o c e s s ). Alternatively, the adhesion/diffusion barrier layer can also be a W/WN layer. Next, in Figure 1c, a dopant cloth is implanted into the metal layer 5 and the SixGei_x layer 40. This implant can be performed at low energy (1〇〇eV to 1〇KeV) and low dose (1E14 atoms/cm2 to 1E15 atoms/cm2), or at high energy (20 KeV to 80 KeV) and low dose. It is carried out under (5E14 to 3E15 atoms/cm2). Alternatively, the planting can be carried out by ion mixing. That is, first, low-energy (1〇〇eV to 丨〇KeV) and high-dose (1E15 to 1E16 atoms/cm2) are implanted, and then high energy (2〇Kev to 80 keV) and low dose are performed. (5E1 3 to 5E14 atoms/cm2). This low-energy 'Southern planting can be carried out by PLAD (plasma doping; plasma doping) or ion (plasma ion immersion implantation). This high-energy, low-dose implant can be performed by conventional beam-line ion implantation (HI). Then, in the first Id diagram, annealing is performed to convert the metal layer 50 into the metallization layer 90' and the dopant is diffused into the SADS (salicide as a doping source) Inside the semiconductor substrate 10, a diffusion region 6A is formed. As can be seen from the figure, the Si ix Ge1-X layer 40 of a 4 is consumed to form a metal telluride layer 9 〇. Thus, the SixGei_x layer 40 is thinner and has a negative impact on the SM of the SixGei layer. Therefore, a thicker SixGei x layer 4 〇 can be formed, for example, greater than 3 〇

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Nm is used to supplement the part consumed by the mussel in the purification process. Thus, it is still possible to go down to the thick enough SixGei X layer to maintain the low SBII. Finally, in Figure 1e, a metal plug 70 is filled into the metal layer 50 of the contact opening 30 2 . For example, a tungsten layer is formed by selective tungsten deposition. After that, the chemical mechanical polishing method (CMp) is performed to planarize the tungsten layer, and the metal layer 5 on the dielectric layer 20 is removed. Figures 2a through 2d show a manufacturing flow diagram for fabricating a metal contact on a metal/semi-gastric conductor interface in accordance with a second embodiment of the present invention. Unlike the first specific embodiment, this embodiment is selectively in the si-Ge layer.

A consumable layer of polycrystalline germanium is formed thereon. The same reference numerals as in the drawings 丨a to 丨e denote the same elements. In Fig. 2a, a dielectric layer 2 is formed on a semiconductor substrate 1A. A contact opening 3 is formed in the dielectric layer 20 to expose the semiconductor substrate 10. Then, a siGeh layer 40 (0<χ<1) is formed in the contact opening 30. Then, a consumable polysilicon layer go is formed only on the SixGei-x layer 40. Next, in Fig. 2b, a metal layer 50 is formed on the consumable polysilicon layer 8A. For example, the metal layer may be formed by an adhesive layer 52 and a diffusion barrier layer 504 which are formed on the side of the consumable polycrystalline layer 8 and on the side of the contact opening 3 . The adhesive layer 52 can be a Ti (Ti) layer, and the diffusion barrier layer 54 can be a TiN layer. Next, a doped cloth is implanted into the metal layer $ 〇, which can be used in the composite layer, the germanium layer 80, and the SixGe layer 40. The planting conditions can be the same as those described in the first embodiment. Next, in FIG. 2c, annealing is performed to convert the metal layer 50 into the metal-lithium layer 92, and the dopant is diffused into the semiconductor substrate in the form of SADS.

0593-6873TWFl;90030;Cathy.ptc Page 10 1304635

1 inside the crucible to form a diffusion zone 60. As can be seen from the figure, a portion of the consumable polysilicon layer 80 is consumed to form a metal germanide layer. Thus, in the deuteration step, the polycrystalline germanium layer 8 is consumed instead of the SixGe layer 4 Consumption. Ting can maintain the integrity of the SixGei_x layer 40 without thinning, thus maintaining a low SBH. In order for the consumable polysilicon layer 8 to be consumed in the deuteration step without being consumed, the depleted polylayer layer 8 must be thick enough that its thickness is preferably between 10 _ and 5 〇 nm.

In the second drawing, a metal plug is filled in the metal layer 50 in the contact opening 3A. For example, a tungsten layer is formed by selective tungsten deposition. Then, a chemical mechanical polishing method (CMp) is performed to planarize the tungsten layer, and the metal layer 5 on the dielectric layer 20 is removed. Figures 3a through 3e show a manufacturing flow diagram for fabricating a metal contact on a metal/semiconductor interface in accordance with a third embodiment of the present invention. In contrast to the first specific embodiment, this embodiment forms a compliant consumable polycrystalline layer on the SixGei x layer. The same reference numerals as in Figures 1 a to 1 e represent the same components. In Fig. 3a, a dielectric layer 20 is formed on a semiconductor substrate 10. A contact opening 3 is formed in the dielectric layer 20 to expose the semiconductor substrate 10. Then, a SixGe layer 40 (0<χ<1) is formed in the contact opening 30. Then, a consumable polysilicon layer 8 2 is conformally formed on the side of the SixGe layer 40 and the side of the contact opening 30.

Next, in Fig. 3b, a metal layer 50 is formed on the consumable polysilicon layer 82. For example, the metal layer can be a diffusion barrier layer, such as a TiN layer.

1304635 ΛΜ 91101584 月 、 发明 发明 发明 、 、 、 、 、 、 、 、 、 、 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 曰曰 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The planting conditions can be the same as those described in the first embodiment. The picker is annealed in the 3D view to convert the metal layer 5 turns into the metal telluride layer 94, and the dopant is diffused into the semiconductor substrate 10 in a SADS manner to form a diffusion region 60. As can be seen, a portion of the consumable polysilicon layer 82 is consumed to form a metal halide layer 94. Thus, in the Shi Xihua step, the polycrystalline germanium layer 82 is consumed rather than being consumed. This maintains the integrity of the SixGe(R) layer 40 without thinning the SixGei_x layer 40' thus maintaining a low SBH. In order to cause the consumable polysilicon layer 82 to be consumed in the deuteration step without consuming the SixGei_x layer 4, the consumable polysilicon layer 82 must be thick enough to have a thickness between 10 nm and 50 nm. Finally, in Fig. 3e, a metal plug 70 is filled into the metal layer 50 in the contact opening 30. For example, a tungsten layer is formed by selective tungsten deposition. Then, a chemical mechanical polishing (CMP) is performed to planarize the tungsten layer, and the metal layer 5 on the dielectric layer 20 is removed. In this embodiment, the consumable polysilicon layer 82 is conformally formed, i.e., it is formed on the SixGei_x layer 40 and on the side of the contact opening 30. Since the polysilicon layer is a good adhesion layer for the dielectric layer 2, the titanium layer or other adhesion layer for the ILd (inter layer dielectric) can be omitted, which can save manufacturing costs. The metal contacts of the present invention can be easily integrated with the CM〇s apparatus. Figures 4a through 4e show a manufacturing process for fabricating a CMOS in accordance with a fourth embodiment of the present invention. In Figure 4a, by selective implantation in each well region

0593-6873TWF1; 90030; Cathy.ptc Page 12 1304635 __ Case No. 91101584_年月曰__ V. Description of Invention (10) Proper doping, and forming a separate N well 120 in a semiconductor substrate 100 and P well 1 40. Then, a shallow trench isolation region (STI) is formed to isolate the active device region 'field effect transistor (F E T ) from the active device region. Then, a thermal oxide is grown to form a gate oxide 2 2 0. Then, a polycrystalline layer 2 4 0 ' is formed to constitute a gate structure of the N channel and the P channel J? e T s . Then, the source/drain region 6 1 形成 is formed in the N well 1 2 0, and the source/drain region 62 0 is formed in the p well 14 4 分别. Next, a contact opening 3 〇 q connecting the source/drain regions 610 and 620 is formed on the semiconductor substrate 100 to form a contact opening 3 〇 q of the source/drain regions 610 and 620 to expose the semiconductor substrate 100. Then, an 8 込〇 6 yoke layer 40 0 is formed in the contact opening 300 ( 0< χ < 1) 〇 Next, a metal layer $ 〇 形成 is formed on the S ix G layer 400. For example, the metal layer may be formed of an adhesive layer 520 and a diffusion barrier layer 5 4 , formed on the SixGe^x layer 400 and on the side of the contact opening 30 0 . The adhesive layer 520 may be a titanium (Ti) layer which has good adhesion to the dielectric layer 2 &. The expanded barrier layer 540 can be a T1N layer to protect the semiconductor substrate from attack by I during the post-titanium deposition process. Alternatively, the barrier layer can also be a W/WN layer. 〃 Next, in Figure 4b, a photoresist layer 32 is formed. The semiconductor substrate 1 is then implanted, i.e., a p% (e.g., boron or boron fluoride) cloth is implanted into the "layer 40" in the N-well 120 region. The metal layer 500 and the SixGei_x connector in "·, in the figure 4c, form a light M, > region. Then, the semiconductor substrate 100 is implanted, and the N-well 1 (such as arsenic or phosphorous) cloth is implanted into the P-well 140 region of the entire sound-mode type dopant---- and "πΑ-χ layer 4 〇〇

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1304635 Case No. 91101584 曰修” V. INSTRUCTION DESCRIPTION (Π) 〇 Next, in Figure 4d, annealing is performed to convert the metal layer 5〇〇 into a metal lithium layer 9 2 0, and in the form of SADS The dopant diffuses into the semiconductor substrate 100 to form a diffusion region 630 in the source/nothing region βίο in the N well 120, and a diffusion region 640° in the source/drain region 620 in the P well 140. In Fig. 4e, a metal plug 7 is filled into the metal layer 500 in the contact opening 300. For example, a tungsten layer is formed by selective tungsten deposition. Then, a chemical mechanical polishing (CMP) is performed to planarize the tungsten layer, Φ and remove the metal layer 500 on the dielectric layer 200. The figure 5 is not based on the c μ 〇 s sound ΐ plan of the specific embodiment of the present invention. This CMOS construction is substantially the same as the fourth embodiment, but this embodiment has one more layer, and a layer of selectivity between the Si-Ge layer 400 and the metal layer 500 is represented by a CMOS to 2d diagram representing the phase diagram. Consumption, shape, consumption, complex, SixGei-x layer, SBH °, now CMOS咅丨J, but this is more than a consumable polycrystalline stone layer 800. The numbers are the same as those of Figures 4a through 4e. The steps of manufacturing the CMOS of Fig. 5 are similar to the steps of manufacturing the 4e, and therefore there is no mention here. Please also refer to Section 2a. As described above, a portion of the consumable polysilicon layer 8 〇 is destroyed by the metallurgical layer 940. Thus, in the Shi Xihua step, the spar layer 800 is used instead of the S ix G layer 400. This maintains the integrity of the 400 without thinning and thus maintains a low reference Fig. 6, which shows a sixth embodiment of the present invention. This CMOS construction is substantially the same as the fourth embodiment, and the embodiment has an additional layer of a consumable compensable polysilicon layer 820 in the Si-Ge layer 400 and the metal layer 500. Label and 4a to

0593-6873 曹l;90030;Cathy.ptc Page 14 Amendment 1304635 V. Description of Invention (12) The same figure in Figure 4e represents the same component. The steps of manufacturing the CM0S^^ of Fig. 6 are similar to the steps of manufacturing the CMOS of Fig. 4e, and therefore there is no need for more. Please also refer to Figures 3a to 3e. As described above, a portion of the ruthenium-consuming cermet layer 820 is consumed to form a metal ruthenide layer 960. Thus, in the Shi Xihua step, the consumable polysilicon layer 820 is consumed instead of the SixGe layer 40. This maintains the integrity of the SixGei_x layer 40 0 without thinning it, thus enabling dimensionality

Hold low SBH. Moreover, in this embodiment, the consumable polysilicon layer 820 is formed conformally, that is, it is formed on the side of the S ixGe^ layer 400 and the contact opening 300. Since the polysilicon layer is a good adhesion layer for the dielectric layer 2, the titanium layer or other adhesion layer for the ILD can be omitted. This saves manufacturing costs. Although the present invention has been disclosed in the above preferred embodiments, it is not intended to be used in the practice of the present invention, and the skilled artisan will not depart from the arsenic and the scope of the invention, and may be modified and retouched, thus the present invention. 2. The date defined in the attached patent application shall prevail. "Sighing

Claims (1)

1304635 A semiconductor device comprising: a semiconductor substrate; a dielectric layer 'on the semiconductor substrate' having a contact opening exposing the semiconductor substrate; and a SlxGeh layer ' formed in the contact opening Wherein 〇<χ<1; a medium metal plug on the sixGelx layer, filling the contact opening u 2 s · the semiconductor device according to claim 1, wherein the nlxR ei~x layer is One icon (Sil icon-rich) SixGei x layer, and 〇·5<x<〇· 95. The semiconductor device according to claim 1, wherein the layer is a strained layer, which does not cause dislocation in the earth slab. The semiconductor device of claim 1, wherein the χ 1 χ layer has a thickness greater than or equal to 5 rim and less than or equal to 30 nm. The semiconductor device according to claim 1, further comprising a metal lithium layer located between the SixGei 4 layer and the metal plug. The semiconductor device of claim 1, further comprising an adhesive layer and a diffusion barrier layer located in the sixGei x layer and the metal plug] wherein the adhesive layer and the diffusion barrier layer are formed On the S ix G e!_x layer and on the side of the contact opening. 7. The semiconductor device of claim 5, wherein the thickness of the SixGeh layer is greater than 3 〇 _. 1304635 ____ Case No. 91101 FiR4____-Day_only 4_____ VI. Patent Application Scope 8. The semiconductor device of claim 5, further comprising a diffusion region located in the semiconductor substrate below the SixGe layer. 9. The semiconductor device of claim 1, further comprising a consumable single crystal layer disposed above the S ix G e^x layer. The semiconductor device of claim 9, further comprising a metallization layer between the polycrystalline layer and the metal plug. The semiconductor device of claim 2, further comprising an adhesive layer and a diffusion barrier layer between the consumable polysilicon layer and the metal plug, wherein the adhesive layer and diffusion A barrier layer is formed on the germanium-consuming germanium layer and on the side of the contact opening. The semiconductor device of claim 9, wherein the consumable polysilicon layer is formed on the SixGei_x layer and on a side of the contact opening. The semiconductor device of claim 2, further comprising a metallization layer between the polycrystalline layer and the metal plug. The semiconductor device of claim 3, further comprising a diffusion barrier layer between the consumable polysilicon layer and the metal plug, wherein the diffusion barrier layer is formed The consumable polysilicon layer is on the side of the contact opening and on the side of the contact opening. The semiconductor device according to claim 9, wherein the thickness of the <| consumable polysilicon layer is between 10 nm and 50 nm. The semiconductor device according to claim 1, wherein the semiconductor device is a CMOS device. , ^ 17 · - a metal / semiconductor interface to create a metal contact 0593-6873TWFl;90030;Cathy.ptc Page 17 1304635 The method includes the steps of: forming a dielectric layer on a semiconductor substrate; forming a contact opening in the dielectric layer to expose the semiconductor substrate to form an 81 (1 layer) in the contact opening, wherein 〇 <χ<1; and a metal plug is filled into the SixGei_x layer of the contact opening. 18) A method of making a metal contact in a metal/semiconductor interface as described in claim 17 The X layer is formed by a selective stretching method. 1. A method of fabricating a metal contact on a metal/semiconductor interface as described in claim 7 of the patent application, wherein the metal plug is a tungsten plug formed by selective tungsten deposition. 20. The method of fabricating a metal contact on a metal/semiconductor interface as described in claim 17, after forming the SixGeix layer and before filling the metal plug, further comprising the steps of: forming on the SixGeix layer a metal layer; implanting a dopant cloth into the metal layer and the layer; Annealing is performed to convert the metal layer into an X metal oxide layer, and the 4 dopant is diffused into the semiconductor substrate to form a diffusion region. 21. A method of making a metal contact on a metal/semiconductor interface as described in claim 2, wherein the implant is performed at a high energy and a low dose, wherein the germanium energy is 20 KeV to Between 80 KeV, the low dose is between 1E14 atoms/cm2 and 1E15 atoms/cm2. 22·A metal/semiconductor interface as described in claim 20 0593-6873TWFl;90030;Cathy.ptc p.1304635 Case No. 91101584 Λ_3 曰 Amendment 6. A method of manufacturing a metal contact on the patent application scope, wherein the implant is performed by an ion mixing method, and the ion mixing method is included in the low a first implant performed at energy, at a high dose, and a second implant at high energy, low dose, wherein the low energy is between 100 eV and 10 KeV, and the high dose is between 1 Ε 15 and 1 E16 atoms/ Between cm2, the high energy is between 20 KeV and 80 KeV, and the low dose is between 5 E 1 3 and 5 E1 4 atoms/cm 2 . 23. A method of fabricating a metal contact on a metal/semiconductor interface as described in claim 17, wherein after the formation of the SiGe+ layer, before filling the metal plug, the method further comprises the step of: Inside the opening, the Si^Geh layer is formed to form a consumable single crystal layer. 24. A method of fabricating a metal contact on a metal/semiconductor interface as described in claim 23, after the formation of the consumable polysilicon layer, before filling the metal plug, further comprising the steps of: Forming a metal layer on the consumable polysilicon layer; implanting a dopant cloth into the metal layer, the germanium layer, and the Si/eh layer; and performing annealing to convert the metal layer into a metal halide layer The dopant is diffused into the semiconductor substrate to form a diffusion region by means of SADS (salicide as a doping source; metal as a doping source). 25. A method of fabricating a metal contact on a metal/semiconductor interface as described in claim 23, wherein the step of forming a consumable polysilicon layer comprises conformally on the SixGepx layer and the side of the contact opening The consumable polysilicon layer is formed thereon. 0593-6873TWFl;90030;Cathy.ptc第19页