TWI304219B - Clock control device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock control device; and more particularly, to a method capable of reducing a two-state trigger in an internal state of a conductor memory. The technology of current consumption of the clock. [Prior Art] Generally speaking, 'synchronous-clock processing-semiconductor memory. There is a need for high speed computing memory to improve the performance of the memory system. For this high speed operation, an attempt has been made to reduce the number of external clock surges but at the same time increase the internal clock transition. However, the current consumption is increased due to the clock transition in the semiconductor memory. Therefore, there is a need for memory features that allow for high speed operation but consume low power. 1 is a diagram of a conventional clock control device configuration. The conventional clock control device includes a setting circuit 10 and a shift register 20. The setting circuit 10 sets an input address Ai to provide a bit address AYi depending on a row address strobe (CAS) signal CAsp. The shift register 2 has a plurality of D flip-flops DFF1 to DFF4 connected in series. The D flip-flops DFF1 to DFF4 sequentially perform one of the forward and reverse operations of the address AYi in synchronization with an internal clock iCLK to output the address ΑΥΙ_χ. The conventional clock control device configured as above allows one and an external clock to be synchronized to input a signal that is recognized as being synchronized to an internal clock iCLK in a semiconductor memory operating at a low frequency external clock. The time interval between the input timing of the signal synchronized to the external clock and the identification timing of the signal synchronized to the internal clock iCLK is defined as an internal latency. 112501.doc 1304219 In particular, in a memory such as a synchronous double data rate dynamic random access memory (DDR3 SDRAM), the user can properly program and utilize the internal latency that depends on a clock cycle. As shown in an operation timing chart of Fig. 2, in the DDR3 SDRAM, a write command WT is synchronously input by the next clock CLK after the enable command ACT and then data is input after a certain time delay. After inputting the data, a write operation is performed in one of the core areas of an actual DRAM. In this case, once the write command WT is input at the start of the write operation in the core area of the actual DRAM, the address data corresponding to the internal latency must be fed in order to identify the address data input. For this purpose, once the write command WT is input, the address AYi is output by triggering the external input address Ai in response to the CAS signal CASP synchronized to the clock CLK. Next, the D flip-flops DFF1 to DFF4 are sequentially synchronized with the forward and reverse operations of the address AYi triggered by the internal clock iCLK, thereby outputting the address AYI_x. That is, the D flip-flops DFF1 to DFF4 sequentially perform the forward and reverse operations of the address AYi in accordance with the CAS signal CASP_WT enabled in synchronization with the clock CLK at the time of the write operation in the core region of the DRAM. However, the above-described structured general-purpose clock control apparatus operates by constantly applying the internal clock iCLK to the D flip-flop DFF regardless of the current state of the wafer. For the above reasons, the current consumption increases due to the periodic transition of the internal clock iCLK. In the case where only one shift register 20 is operated as shown in Fig. 1, the current consumption amount is minute. However, since the actual DRAM should process multiple address and command signals simultaneously, there are a large number of circuits in the DRAM that are configured as shown in Figure 1. A disadvantage of conventional devices due to λ is that current consumption increases with the speed of the memory. & [Summary content]

SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a method for reducing a state in a precharge/standby state by controlling a clock to toggle an internal clock in only one of the semiconductor memory states. A technique that triggers current consumption of an internal clock that allows an externally input command signal and address to be applied to a core after an internal latent time. According to an aspect of the present invention, a clock control apparatus is provided, comprising: a setting circuit for triggering an input address in response to an internal command signal to output a first address; a shift temporary storage The device includes a plurality of flip-flops connected in series, wherein some of the flip-flops are synchronized with - the internal clock performs one of the first addresses to provide a second address, and the remaining The counter synchronizes with a synchronization clock to sequentially perform a forward and reverse operation of the second address to generate an internal address; an enable signal generator for enabling the activation based on the - finger # per group (4) And outputting an enable signal to the state of the signal and a precharge control signal; and a clock generator for generating the synchronization clock depending on the internal clock and the enable signal. According to another aspect of the present invention, a clock control apparatus is provided, comprising: a 疋 circuit for triggering an input address in response to an internal command signal to output - a first address; The register includes a plurality of flip-flops coupled in series, wherein some of the flip-flops are synchronized with an internal clock to perform one of the first addresses of the first address, and (6) a total of - the second bit iS.. 112501.doc 1304219 address, and the remaining flip-flops sequentially perform one of the second address forward and reverse operations in synchronization with a synchronization clock to generate an internal address; an enable signal generator for An enable signal is outputted as a status of the enable control signal indicating a start of each group and a precharge control signal; a flip flop for synchronizing the one of the enable signals with the internal clock to perform a forward and reverse operation Providing a delay enable signal; and a clock generator for generating the synchronization clock depending on the internal clock and the delay enable signal.

[Embodiment] Hereinafter, a preferred embodiment of the present invention will be described in detail with reference to the accompanying drawings. Fig. 3 is a block diagram showing the configuration of one of the clock control devices according to the present invention. The clock control apparatus of the present invention comprises a setting circuit, a shift register 200, an enable signal generator 300 and a clock generator 4A. Specifically, the setting circuit 100 triggers an input address Ai in response to a CAS signal CASP to provide a bit address AYi. The shift register 200 includes a plurality of D flip-flops DFF1 to DFF4 coupled in series. Among the plurality of D flip-flops DFF1 to DFF4, the D flip-flop DFF1 is synchronized with an internal clock iCLK, and the forward and reverse operations of the address AYi are performed to output the address Ayi_a. The D flip-flop DFF2 is synchronized to the internal clock iCLK, and the forward and reverse operations of the address Ayi-a are performed to provide a bit address Ayi_b. And the D flip-flops DFF3 and DFF4 are synchronized to a synchronous clock SCLK, and the forward and reverse operations of the internal address Ayi_b are performed to generate an internal address AYI_x. The enable signal generator 300 is based on an enable signal ACTP<0:i>&-precharge control signal? 00卩<0:丨> generates an enable signal RATVD, wherein the start 112501.doc 1304219 signals the memory to be in an enabled state. The clock generator 400 generates a synchronous clock SCLK depending on the internal clock iCLK and the enable signal RATVD. 4 is a detailed circuit diagram of the setting circuit 1A shown in FIG. As shown in Fig. 4, the setting circuit 1 〇 〇 has a transmission gate τ 1 and a plurality of inverters IV1 to IV5. Specifically, the transmission gate T1 is used to selectively output the input address Ai based on the CAS signal CASP and one of the CAS signals CASP inverted by the inverter IV1. Inverters IV3 and IV4 latch the output of the transmission gate T1 for a predetermined period of time. Inverter IV5 inverts the output of the latch comprising inverters IV3 and IV4 to produce an internal address AYi. FIG. 5 shows a detailed circuit diagram of the shift register 2A shown in FIG. Each D flip-flop DFF includes transmission gates T2 and T3 and a plurality of inverters IV6 to IV10. The transfer gate T2 selectively outputs the internal address AYi in response to the internal clock iCLK and by inverting one of the internal clocks iCLK of the IV6. Inverters IV7 and IV8 latch the output signal of transmission gate T2 for a predetermined time. The transfer gate T3 operates concurrently with the transfer gate T2 based on the internal clock iCLK and the internal clock iCLK inverted by the inverter IV6 to selectively control the output of the latch including the inverters IV7 and IV8. A latch comprising inverters IV9 and IV10 latches the output of transmission gate T3 to provide an output signal OUT. Figure 6 provides a detailed circuit diagram of the enable signal generator 300 depicted in Figure 3. The enable signal generator 300 includes a plurality of enable controllers 310 to 330 and a logic operator 340. Each of the enable controllers 310 to 33A logically operates an enable control signal ACTP <0:i> and a precharge control message 112501.doc 1304219 PCGP<0:i>. The plurality of enable controllers 310 through 330 have the same configuration; and thus only one controller 3 10 will be described in detail below. As shown in FIG. 6, the enable controller 310 has an inverter ivil and NAND ("reverse") gates ND1 and ND2. The NAND gate ND1 performs a NAND operation of one of the control signals eight (??<0> and one of the NAND gates ND2 by the inversion of the inverter IV11. The NAND gate ND2 performs the precharge control signal PCGP<0> A NAND operation with the output of the NAND gate ND1. The logic operator 340 includes a NOR (NOR) gate NOR1 and an inverter IV12. The NOR gate NOR1 performs a NOR operation on the outputs of the plurality of enable controllers 310 to 330. The inverter IV12 inverts the output of the NOR gate NOR1 to generate an enable signal RATVD. Figure 7 is a detailed circuit diagram of the clock generator 400 shown in Figure 3. As shown in Figure 7, the clock generator 400 is equipped with a NAND. Gate ND3 and an inverter IV13. NAND gate ND3 operates a NAND operation on internal clock iCLK and enable signal RATVD. Inverter IV13 inverts the output of NAND gate ND3 to provide synchronous clock SCLK. 7 and the operation timing diagram shown in Fig. 8 to describe in detail the operation of the present invention configured as above. First, the setting circuit 100 synchronously latches the input address Ai of a clock signal CLK input when the CAS signal CASS is started to output bits. Address AYi. With an internal command signal, write The CAS signal CASP generated by the read command is used to sense the external input address Ai. Then, the shift register 200 synchronizes with the internal clock iCLK to perform a forward and reverse operation of the address AYi to output the internal address Ayi_b and is synchronized with Synchronous clock U250l.doc -10- 1304219 SCLK sequentially applies a positive and negative operation to the address Ayi-b to provide an internal address AYI_x 〇 in a plurality of sets of DRAM, and an enable operation can be performed for each group. The enable signal generator 300 is provided with a plurality of enable controllers 310 to 330 for controlling the enable status data of each of the groups. The enable signal generator 300 logically operates the enable signal person (: D? < 0 > and each of the precharge control signals PCGP<0:i>$ to provide an enable signal RATVD indicating that the memory is in an enabled state. Therefore, if all groups are in a precharge state, the enable signal RATVD is logic Low, and if any of the groups is enabled, the enable signal RATVD is enabled to logic high. Next, the clock generator 400 generates a synchronization clock SCLK based on the clock signal RATVD and the internal clock iCLK. If the enable signal RATVD is in the startup state, the synchronization clock SCLK is output synchronously with the internal clock iCLK. The present invention controls the operation of the shift register 200 depending on both the internal clock iCLK and the synchronization clock SCLK. The enable signal RATVD is activated by an enable control signal ACTP indicating an external enable command. Therefore, once the high speed operation is performed, the internal delay time separated from the clock CLK of the input enable control signal ACTP is extended to an extended clock t A . Therefore, in order to reduce the current consumption, the synchronous clock SCLK which is operated only when the wafer is in the enabled state is generated only after the time. If all of the D flip-flops DFF1 to DFF4 of the shift register 200 are controlled by synchronizing with the sync clock SCLK, the first D flip-flop DFF1 senses the internal address AYi, which is internally 112501.doc -11 - 1304219 The address AYi is the output of the setting circuit 100 by the synchronization clock SCLK generated after the delay time tA. In this case, the transmission of the effective information becomes substantially slower than the time at which it will be resynchronized, thereby causing a failure. Therefore, the present invention controls the operation of the shift register 200 by separating the internal clock iCLK from the synchronous clock SCLK to ensure high speed operation. At this time, the delay time tA varies depending on the process, voltage, and temperature (PVT); and therefore, the internal clock iCLK and the synchronous clock SCLK are distributed by considering the situation when the synchronous clock SCLK is generated after the delay time. . Therefore, the present invention can appropriately control one of the clocks in the precharge state during the high speed operation, thereby reducing the current consumption in the precharge state (in SDRAM, the average current consumption is defined by IDD2N). Figure 9 is a block diagram of a clock control apparatus in accordance with another embodiment of the present invention. The embodiment of FIG. 9 includes a setting circuit 100, a shift register 200, an enable signal generator 300, a clock generator 400, and a D flip-flop 500. Compared with the structure of FIG. 3, the above structure is as follows. The embodiment of FIG. 9 further includes a D flip-flop 500. The D flip-flop 500 performs one of the forward and reverse operations of the enable signal RATVD output from the enable signal generator 300 to provide a delayed enable signal RATVD. By doing so, the synchronization clock SCLK can be generated more stably by allowing the enable signal RATVD applied to the clock generator 400 to be synchronized with the falling edge of one of the internal clocks iCLK. In other words, when the enable signal RATVD is synchronized with the internal clock iCLK, 112501.doc • 12- 1304219, the enable signal RATVD is delayed by one of the internal delays and the internal clock iCLK is dependent on an external clock. Interworking one of the internal clock signals. Therefore, there may be a state in which the internal clock iCLK becomes logic high when the enable signal RATVD is enabled to be logic high. In this case, the sync clock SCLK can be generated as a short-time pulse waveform interference signal having an incomplete pulse width.

Therefore, the embodiment of FIG. 9 can be prevented from being short by separating the φ D flip-flop 500 synchronized with the internal clock iCLK and the D flip-flop DFF of the shift register 2 同步 synchronized with the synchronous clock SCLK. A fault caused by the synchronous clock of the pulse waveform interference component. • Although the embodiment of the present invention is described with respect to the address Ai as the input signal, it should be noted that the input signal may be the address, control signal or data of the present invention, and is not limited thereto. As described above, the present invention can reduce the current consumption of an internal clock by a two-state trigger in a precharge/standby state by triggering an internal clock only in one of the enabled states of the semiconductor memory. This enabled state allows the application of an externally input command signal and address to a core after an internal dive. This application contains information about the Korean Intellectual Property Office, September 29, 2005 and December 02, 2005. The subject matter of the Korean Patent Application No. 2005-91673 and No. 2 GG5_117137, the entire contents of each of which are incorporated herein by reference. Although the present invention has been described with respect to the specific embodiments, it will be apparent to those skilled in the art that the present invention can be carried out without departing from the spirit of the above-mentioned patent application, 112501.doc -13 - 1304219 > A variety of changes and repairs [simplified description of the drawings] is a block diagram of the configuration of a normal clock control; FIG. 2 is a timing diagram of the operation of the ordinary clock control device; FIG. 3 is a diagram illustrating the operation according to the present invention. - a block diagram of the configuration of the clock control device of the embodiment;

Figure 4 is a detailed circuit diagram of the setting circuit shown in Figure 3; Figure 5 is a detailed circuit diagram of the shift register shown in Figure 3; Figure 6 is a detailed circuit diagram of the enabled signal generator depicted in Figure 3; 3 is a detailed circuit diagram of a clock generator shown in FIG. 3; FIG. 8 is an operation timing diagram of a clock generator according to an embodiment of the present invention; and FIG. 9 is a timing control device according to another embodiment of the present invention. Block diagram.

One of the defining devices of the present invention [Description of main component symbols] 10 setting circuit 20 shift register 100 setting circuit 200 shift register 300 enable signal generator 310, 320, 330 enable controller 340 logic operator 400 clock generator 112501.doc -14- 5001304219 DFF1, DFF2, DFF3, DFF4 IV1, IV3, IV4, IV5, IV6, IV7, IV8, IV9, IV10, IV11, IV12, IV13 ND1, ND2, ND3 N0R1 ΤΙ, T2, T3

D flip-flop D flip-flop inverter NAND gate NOR gate transmission gate

112501.doc -15-

Claims (1)

130 Lai 23911 Patent Application Requires Patent Renewal (August 97) X. Patent Application Range: bUJI Page A clock control device, comprising: a setting circuit for triggering in response to an internal command signal An input address to output a first address; a shift register comprising a plurality of flip-flops connected in series, wherein some of the flip-flops are synchronized with an internal clock to execute the first address Positive and negative to provide a second address, and the remaining flip-flops Performing a positive and negative operation of the second address sequentially to generate an internal address in synchronization with a synchronization clock; enabling an apostrophe generator for indicating whether each of the plurality of memory groups is based on a And a pre-charge control signal is activated to output an enable signal; a pulse generator is configured to generate the synchronization clock according to the internal clock and the enable signal. 2. The clock control device of claim 1, wherein the setting circuit comprises: a first-transmission gate for selectively outputting the input address based on one of the internal command signals; and a register for latching the round of the first transmission gate; and a first-inverter for inverting the first address of the latch. &丨,, must be 3. The clock control device of the request item 1 is reversed. Wherein the plurality of flip-flops are D-positive 4. If the request item is in a clock control device of one, wherein the plurality of memory banks are fully pre-charged, the enable signal generator outputs a logic low of 112501-970814. The doc 1304219 13⁄4 pull replacement page enables the δίΐ ' and the enable signal generator outputs a logic high enable signal if at least one of the plurality of memory banks is in an enabled state. 5. The clock control device of claim 4, wherein the enable signal generator comprises: a plurality of enable controllers for logically combining the enable control signal and the precharge control signal; and the logic operator The plurality of enabler-directed outputs are logically operated to provide the enable signal. 6. The clock control device of claim 5, wherein the number of enabled controllers corresponds to the number of the plurality of memory banks. 7. The clock control device of claim 5, wherein each of the plurality of enable controllers comprises: a second inverter for inverting the enable control signal; a first NAND gate a NAND operation for performing the output of the second inverter and a first signal to output a second signal; and a second NAND gate for applying the precharge control signal to the second signal A NAND operation is performed to generate the first signal. 8. The clock control device of claim 5, wherein the logic operator comprises: a NOR gate for NOR operation of the plurality of enable controller outputs; and/or a third inverter for use The output of the NOR gate is inverted to output the enable signal. 9. The clock control device of claim 1, wherein if the enable signal is in an active state, the clock generator synchronizes with the internal clock output to output the same 112501-970814.doc 1304219 Step clock. The clock control device of claim 9, wherein the clock generator comprises: a third NAND gate for NAND operation of the internal clock and the enable signal; and a fourth inverter, It is used to invert the output of the third NAND gate to output the synchronization clock. 11 . A clock control device, comprising: a setting circuit for triggering an input address to output a first address in response to an internal command signal; and a shift register comprising series coupling a plurality of flip-flops, wherein some of the flip-flops are synchronized with an internal clock to perform the first-to-reverse operation to provide a second address, and the remaining flip-flops are synchronized a synchronization clock sequentially performs one of the second address positive and negative operations to generate an internal address; an enable signal generator for indicating whether each group is based on _ Initiating an enable signal of the enable control signal and a centroid and precharge control signal to output an enable signal; the flip-flop 'which is used to synchronize the internal master code σ Μ Μ pulse to perform one of the enable signals To provide a delay enable signal, and a clock generator for extracting, graying, and generating the synchronization clock depending on the phase clock and the delay enable apostrophe. 12. The clock control device of claim U, 1 ^ π Τ the flip-flop has a D-positive state. 1 3. A clock control device comprising: 112501 - 970814.doc 1304219 9Τ a setting circuit for triggering an input address in response to an internal command signal to output a first address; a bit register comprising a plurality of flip-flops connected in series, the plurality of flip-flops being configured as an internal address in response to the _internal clock and the _synchronous clock; - start: signal generator, The method is configured to output an enable signal based on a state indicating whether each of the plurality of memory groups is activated by the activation control signal and a precharge control signal; and the pulse is generated for use according to the internal The synchronization clock is generated by the clock and the enable signal. 14. The clock control device of claim 13, wherein some of the flip-flops in the shift register are synchronized with the internal clock to perform a positive and negative operation of the first address to provide a The two addresses sequentially perform the lifetime of the internal address in the synchronization clock. And the 荨 remaining flip-flop synchronizes one of the two addresses with a positive and negative operation to produce 15. The clock control device of claim 14, wherein the setting circuit comprises: a first transfer gate for use based on the internal command One of the signals is activated to selectively output the input address; - the register 'which is used to latch the output of the first transfer gate; and the first reverse benefit, which is used to invert the latch Output to provide the first address. Wherein the plurality of flip-flops are D. If the plurality of memory banks are all 16, the clock control device of the request item 14 is a flip-flop. 17. The clock control device of claim 14 112501-970814.doc 1304219 "After the lion 197, 8, the i M j portion is in a pre-charge state, the enable signal generator outputs a logic low enable signal" and if The at least one of the plurality of memory groups is in an enabled state, and the enable signal generator outputs a logic high enable signal. 1 8. The clock control device of claim 17, wherein the enable signal generator comprises: a plurality of enable controllers for logically combining the enable control signal and the precharge control signal; and a logic operator for logically computing the output of the plurality of enabler controls to provide the enable signal. The clock control device of claim 18, wherein the number of enabled controllers corresponds to the number of the plurality of memory banks. 20. The clock control device of claim 18, wherein each of the plurality of enabled controllers One includes: a second inverter for inverting the enable control signal; a first NAND gate for performing an output of the second inverter and a NAND of a first signal Calculating to output a second signal; and a second NAND gate for applying a NAND operation to the precharge control signal and the second signal to generate the first signal. 21 · When requesting item 18 a pulse control device, wherein the logic operator comprises: a NOR gate 'which is used for NOR to differentiate the outputs of the plurality of enable controllers; and a second phase of the second phase is 'which is used to invert the output of the nor gate The round-robin control device is rotated. The clock control device of claim 14, wherein if the enable signal is in a 112501-970814.doc 97. 97. 1304219 is replacing the page 1 4 startup state, the clock generator The synchronization clock is output in synchronization with the internal clock. 23. The clock control device of claim 22, wherein the clock generator comprises: a third NAND gate for NAND operation of the internal clock and the enabling And a fourth inverter for inverting an output of the third NAND gate to output the synchronization clock. 112501-970814.doc