TWI303828B - A method and a system for erasing a nonvolatile memory - Google Patents
A method and a system for erasing a nonvolatile memory Download PDFInfo
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1303828 九、發明說明·· 【發明所屬之技術領域】 寫時 本發m—觀,紐她寫方法, 間的記憶«寫方法。 $種TI抹 【先前技術] 常會 L隹宜快閃魏體的抹寫都找複數個記憶區段逐個 此品要花長的咖,而輔極 日:2 生有過度抹寫(〇vei•個e)的情形,因在抹寫奸會發 雜。 ^目此在抹寫動作上會更為複 【發明内容】 本^明的目的為提供一種記彳音體的 體的抹寫時間。 A體的抹寫方法,用以減少記憶 種適用於一非揮發性記憶體的抹寫方法,盆中 每一該記憶胞的内容為〇;對該非揮發體。程序,使 序,對該非揮發性記憶體執 體中執行一編組程 的每一記憶胞的内容為1;對執行f旱該快閃記憶體中 數個過度抹寫的記憶胞執行-軟編程程段r複 的記憶胞的一臨界電壓大於焚。于母μ過度抹寫 【實施方式】、文 第1圖為根據本發明之一記憶體架 ^ ^1303828 IX. Invention Description·· 【Technical field to which the invention belongs】 When writing, this is the m-view, the new method of writing, the memory of the «writing method. $ kinds of TI wipe [previous technology] Regularly L 隹 快 快 魏 魏 魏 魏 魏 都 都 都 都 都 都 都 都 都 都 都 都 魏 魏 都 都 都 都 都 都 都 都 都 都 都 都 都 都 都 都 都 辅 辅 辅 辅 辅 辅 辅In the case of e), it will be mixed because of smearing. ^ This will be more complex in the smear action [Summary] The purpose of the present invention is to provide a scribe time for recording the body of the syllable. The smear method of the A body is used to reduce the memory. The smear method for a non-volatile memory, the content of each of the memory cells in the basin is 〇; the non-volatile body. The program, the sequence, the content of each memory cell performing a grouping process in the non-volatile memory body is 1; performing memory programming on a plurality of over-scraping memory cells in the flash memory A critical voltage of the memory cell of the segment r is greater than that of the combustion. Excessive smear of mother μ [Embodiment], FIG. 1 is a memory frame according to the present invention ^ ^
Clients Docket No.:94-〇37 木構圖。在弟1圖中,記憶 TT s D〇cket No:0492-A40576-TW/finaMDrent 3/2/2006 ^ 1303828 -區&中的任—記憶胞’便可由位址線仙00〜ADD12來決定。 ΓητνΓ郝記,隨段巾的每—個記憶胞,便可對位址線Clients Docket No.: 94-〇37 Wood composition. In the picture of brother 1, memory TT s D〇cket No:0492-A40576-TW/finaMDrent 3/2/2006 ^ 1303828 - any memory cell in the area & can be determined by the address line 00~ADD12 . ΓητνΓ Hao Ji, with each memory cell of the scarf, you can right on the address line
可。少〜AiD12由【0000000000000】計數到【lllnilnim】即 二二為21為一 3對8的多工器,接收位址線ADD13〜ADDH 、 别^刀別輕接對應之及閘24a到24h的輪出端。 ίρο" ^ 斷伴F0 F7曰 另一輪入端输至或間22的輪出端。遮 _ W.唬F0〜F7疋從體19在接收一驗證 抹寫赫#^ 若驗證通過則設為0,—般在 =寫知序或軟編程程序時,則FG〜F7全設為卜細U 二 :入端’分獅接至—抹寫錢咖犯 二 物Μ觸纽_,鱗觸 令輸出4口唬為1,使得控制信號A〇 古 第一,憶區段至第八記憶區段全部。“電Μ位’用以選擇 圖。在—牛二tri康本务明之一非揮發性記憶體的抹寫方法的流程 】,==_9接受一預先編程伽—)程 0 0 833"5 焉矛序’使仔吕己憶體19内的印橋旳6岛:欠把、士 設為1。當記憶體19在接受抹富寇心士〆的。己k、胞的貝科被 一記#•胞的萨界寫#序4,係將記憶體19内的每 位 =己憶胞的電位小於〇。因此,在步驟= 來體會=雜 軟編程(牆㈣卿)程序 4體19接文一 的電位上拉到大約為電位〇。 、σ思、見電位小於〇的記憶胞can. Less~AiD12 is counted from [0000000000000] to [lllnilnim], that is, 22 is a 3-to-8 multiplexer, receiving address lines ADD13~ADDH, and other knives are not connected to the corresponding gates 24a to 24h Out. Ίρο" ^ Broken F0 F7曰 Another round of the input to the round or the end of the 22 round. Cover _ W. 唬 F0 ~ F7 疋 slave 19 in receiving a verification wipe er # ^ If the verification is passed, set to 0, generally in the = write order or soft programming program, then FG ~ F7 are all set to Fine U II: The end of the 'lion to pick up to - wipe the money to commit the two things touch the New Zealand _, the scale touch output 4 mouth 唬 to 1, making the control signal A 〇 ancient first, recall the segment to the eighth memory All sections. "Electric Μ" is used to select the map. In the process of the smear method of non-volatile memory of one of Niu Erkang, the ==_9 accepts a pre-programmed gamma-) course 0 0 833"5 焉The spear order's make the dynasty of the dynasty in the 19th of the dynasty of the dynasty of the dynasty: the yin and the singer are set to 1. When the memory 19 is accepted by the sorrowful sorrow, the singer of the singer The cell's Sajie write #序4, the potential of each person in the memory 19 = memory cell is less than 〇. Therefore, in the step = to experience = miscellaneous soft programming (wall (four) Qing) program 4 body 19 received a text The potential is pulled up to approximately the potential 〇., σ思, see the memory cell with potential less than 〇
Client's Docket No. :94-037 3/2/2006 TT5s Docket No:0492-A40576-TW/iinaL^rent 1303828 inr抹寫方法 二始狀心界; 二臨界電齡被上拉啦 臨界賴。當記憶體19接受抹寫程序時,記憶低 fe、胞,臨界電齡被τ拉到大約技位G的部分,如曲線α所己 更传π己L、l的e品界電屋低於〇v,因此 =軟編_序將被過度抹寫的複數個記憶胞㈣位提升到^ 界電if_受第3圖的抹寫綠時,記憶胞的臨 界的文化不思圖。在時間tl時,記憶胞接受一預先編程程序, 使知记憶胞的臨界電壓被上拉大於一電位乂卜在時間β時,記 憶胞接收-抹寫程序,使得記憶胞的臨界電壓被下拉到電位〇, 但是記憶胞發生過躲寫的獅,使得記·壓位於小 於〇的電位。為改善記憶胞過度抹寫的情形,在時間t3時,記憶 胞接叉一軟編程程序,將記憶胞的電位提升到大約〇v。 第6圖為根據本發_預先編程程序的—實施例的流程圖。 在步驟S60中,先對圮憶體19進行一反編組(un-gr〇Up)程序。 以第2及3圖為例說明,此時抹寫信號ERASE及軟編程信號 STPGM為0,因此控制信號AG〜A7錢由自動累加器⑺的^: 線ADD13〜ADD15控制。記憶體19在接受反編組程序後,由自 動累加器10對位址線ADD0〜ADD15逐一計數,用以逐一選擇記Client's Docket No. :94-037 3/2/2006 TT5s Docket No:0492-A40576-TW/iinaL^rent 1303828 Inr smear method Second start heart; Second critical age is pulled up Critical. When the memory 19 accepts the stenciling process, the memory is low, the cell, and the critical age is pulled by the τ to the part of the gage G. For example, the curve α is more than π, L, and l is lower than the e-house. 〇v, so = soft _ sequence will be over-written multiple memory cells (four) bit to ^ jie electric if_ by the third picture of the smear green, the critical culture of memory cells do not think. At time t1, the memory cell accepts a pre-programming procedure so that the threshold voltage of the memory cell is pulled up by more than a potential. At time β, the memory cell receives-wipe the program, so that the threshold voltage of the memory cell is pulled down. To the potential 〇, but the memory cell has been escaping the lion, so that the pressure is less than the potential of 〇. In order to improve the over-scraping of the memory cell, at time t3, the memory cell is switched to a soft programming program to raise the potential of the memory cell to approximately 〇v. Figure 6 is a flow diagram of an embodiment of a pre-programmed program according to the present invention. In step S60, an un-gr〇Up program is first performed on the memory. Taking the second and third figures as an example, the rewritable signal ERASE and the soft programming signal STPGM are 0 at this time, so the control signals AG~A7 are controlled by the ^: lines ADD13 to ADD15 of the automatic accumulator (7). After the memory 19 receives the anti-grouping program, the automatic accumulator 10 counts the address lines ADD0 to ADD15 one by one for selecting one by one.
Client’s Docket No.:94-037 TT5s Docket No:0492-A40576-TW/finam)rent 3/2/2006 1303828 * 的—9記憶胞。在步驟啦中,驗證被選擇到的記憶胞所 各值是否為g ’ ^是則跳到步驟啦,選擇下-個記憶胞 驗證=====鲍⑽,觸_再次進行 驗證失敗跳到步驟S65。通過則跳到步驟啦,若 # τ驟65中,判斷該記憶胞的編程次 二預^次數n,若是,則跳到步驟啦,_是,則 跳到步驟S66,_記憶胞再次進行編程。 在預先編料1序巾,彻位址線ADDQ〜ADD15 記 流程逐一驗證每一記憶胞,直到記憶體19中的所 有5己铖胞都完成預先編程程序。 驟圖桃據本發_—抹寫程序的實關的流程圖。在步 \ 士社Γ ’二對記憶體19進行一編組程序。以第2及3圖為例說明, 4 ¥抹寫信號ERASE為1,使得控制信#uA〇〜A7皆為i,同時選 ^又,進行(步驟S72),較以往一次只能對一個記憶區段進 订抹寫的方式,大幅減少抹寫時所需的時間。在步驟S7 記憶體19進行-反編組程序,並利用位址、線娜13〜_15來 區段(步驟S74) ’驗證該記憶區段中的每—記憶胞 :合值疋否為1(步驟S7”。對記憶區段中記憶胞的驗證方式 糸利用由自動累加器10對位址線ADD〇〜ADDi2逐一計數,用以 逐-選擇記憶ϋ段中的每—記憶胞,此時_只有其—記憶區段 的位兀線被選來驗證,故可以增進驗證時的準備性,確保不被其 他七個已過度抹寫的記憶區段之干擾。若驗證騎,則跳到步驟 判岐否全部區段都已驗證鮮,若是,縣絲寫程序, 若不是則跳到步驟S77。在步驟S77巾,將驗證通過的記憶區段Client's Docket No.: 94-037 TT5s Docket No:0492-A40576-TW/finam)rent 3/2/2006 1303828 * -9 memory cells. In the step, verify whether the selected values of the memory cells are g ' ^ Yes, skip to the step, select the next - memory cell verification ===== Bao (10), touch _ again to verify the failure to jump to Step S65. If it is skipped to the step, if # τ 65 65, it is judged that the memory cell is programmed to be the second time n, and if so, the process jumps to the step, _Yes, then the process goes to step S66, and the _ memory cell is programmed again. . In the pre-programming 1 sequence, the address lines ADDQ~ADD15 are used to verify each memory cell one by one until all 5 cells in the memory 19 have completed the pre-programming process. According to the flow chart of the actual _----------- In the step \ 士社 Γ 二 two pairs of memory 19 a grouping process. Taking the second and third diagrams as an example, the 4 rewritable signal ERASE is 1, so that the control letters #uA 〇 〜 A7 are all i, and at the same time, the selection is performed again (step S72), which can only be one at a time. The way in which the memory segment is programmed and erased greatly reduces the time required for erasing. In step S7, the memory 19 performs an anti-grouping process, and uses the address, line 13 to _15 to segment (step S74) 'verify each memory cell in the memory segment: the value is 1 No 1 (step S7”. The verification method of the memory cells in the memory segment is counted one by one by the automatic accumulator 10 for the address lines ADD〇~ADDi2, for selecting each memory cell in the memory segment by time. The bit line of the memory segment is selected for verification, so the readiness during verification can be improved, and it is ensured that it is not interfered by the other seven over-wrenched memory segments. If the ride is verified, jump to the step judgment. Otherwise all the sections have been verified fresh, if yes, the county silk writing program, if not, then jump to step S77. In step S77, the verified memory section will be verified.
Client’s Docket No.:94-037 3/2/2006 TT5s Docket No:0492-A40576-TW/finaVbrent 1303828 '遮蔽起來,並選擇下—個記憶區段。以第2圖為例說明 圮憶區段通過驗證,則將遮斷信號F〇設為〇。利用 使得驗證通過的記憶區段不會再次被抹寫,減少過度勺2 形二在步驟S75中,若記憶區段驗證失敗,則跳到步ς j : ίϋ19進打編組程序’並對記憶體19中未通過驗證的記情區 又再-人進行抹寫程序(步驟S79),再跳回步驟S75 ^ 再次^證,-直到所有的記憶區段都通過驗證。 4仏 第8圖為根據本發明的—賴程程序的實施例的流程圖 .々驟S81中,對記憶體19進行一氣址程序。以第2及3 明’此時軟編程信號STPGM為i,使得控制信號α〇〜α7皆" =同喊取所有的記憶區段。在步驟S82中,驗證每一記情區段 H記憶蚁否有過絲寫,並記觸麟寫的胞 在步驟S83中,對記憶體19進行—反編組程序。在步驟= 中,對過度抹寫的記憶胞進行一軟編程程序,並在步驟嫩 ,過度抹寫的記憶胞再次驗證並判斷是否驗證通過(步驟s 。 右所有過度抹寫的記憶胞都驗證通過,聰編程程賴束。若 證仍有未通過的記憶胞,則跳到步驟聊,記錄驗證失敗的記情 胞的位址,並跳到步驟S84。 〜 雖然本㈣已以較佳實施_露如上,然其並_以限定本 ^ ’任何沾習此技藝者,在不脫離本發明之精神和範圍内,當 =些,之更動與潤飾’因此本發明之保護範圍當視後附之 專利乾圍所界定者為準。 【圖式簡單說明】 第1圖為根據本發明之一記憶體架構圖。 第^為根據本發明之-自動累加器1G與—並列控制單元 11之一貫施例的示意圖。Client’s Docket No.: 94-037 3/2/2006 TT5s Docket No:0492-A40576-TW/finaVbrent 1303828 'Cover up and select the next memory segment. Taking Fig. 2 as an example, the 遮 区段 section is verified, and the occlusion signal F 〇 is set to 〇. With the memory segment that causes the verification to pass, it will not be erased again, reducing the excessive scoop 2 shape. In step S75, if the memory segment verification fails, then skip to step j: ϋ19 into the grouping program' and the memory The grammatical area that has not passed the verification in 19 is again subjected to the smear program (step S79), and then jumps back to step S75^ again, until all the memory segments pass the verification. 4A is a flowchart of an embodiment of a finder program according to the present invention. In step S81, an air address program is performed on the memory 19. In the second and third descriptions, the soft programming signal STPGM is i, so that the control signals α〇~α7 both " = all the memory segments are called. In step S82, it is verified whether each of the vocal sections H memory ants have been overwritten, and the cells written by the lining are recorded. In step S83, the memory 19 is subjected to an anti-grouping process. In step =, a soft programming procedure is performed on the over-scraped memory cell, and in the step, the over-scraped memory cell is verified again and judged whether or not the verification is passed (step s. Right all over-transcribed memory cells are verified Pass, Cong programming process depends. If there are still unsuccessful memory cells, skip to the step to record, record the address of the failed cell, and skip to step S84. ~ Although this (4) has been better implemented _ As above, it is intended to limit the scope of the present invention to those skilled in the art, and the scope of protection of the present invention is to be attached to the appended claims without departing from the spirit and scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS [FIG. 1] FIG. 1 is a memory structure diagram according to the present invention. The first embodiment of the automatic accumulator 1G and the parallel control unit 11 according to the present invention. Schematic diagram.
Client’s Docket No.:94-037 3/2/2006 TT^ Docket No:0492-A40576-TW/finaVbrent 1303828 圖 第3圖為雜本個之—麵發性記憶體的抹寫方法的流程 第5圖為一記憶胞接接受第3圖的抹寫 界電壓的變化示意圖。 ~ 方法時,記憶胞的臨Client's Docket No.:94-037 3/2/2006 TT^ Docket No:0492-A40576-TW/finaVbrent 1303828 Figure 3 is a flow diagram of a smear method for a face-to-face memory. A diagram of the change of the strobe boundary voltage of FIG. 3 is accepted for a memory cell. ~ Method, the memory cell
第 第 第 6圖為根據本發_預絲程財的—實施例的流程圖。 7圖為根據本發_-抹寫程序的實施例的流程圖。 8圖為根據本發明的—軟編程程序的實施例的流程圖。 【主要元件符號說明】 10 :自動累加器 11 :並列控制單元 12a ' 13a ' 14a ' 16a、17a ··開關裝置 15 :解碼器 18a :第一記憶區段 A0〜A7 :控制信號 21 :多工器 22、23a〜23h ··或閘 24a〜24h :及間 F0〜F7 :遮斷信號 SM〜對記憶體執行一預先編程程序 S33〜對έ己憶體執行一抹寫程序 S35〜對記憶體中過度袜寫的記憶胞執行一軟 編程程序Fig. 6 is a flow chart of an embodiment according to the present invention. 7 is a flow chart of an embodiment of a smear-writing program according to the present invention. 8 is a flow diagram of an embodiment of a soft programming program in accordance with the present invention. [Description of main component symbols] 10: Automatic accumulator 11: Parallel control unit 12a ' 13a ' 14a ' 16a, 17a · Switching device 15 : Decoder 18a : First memory section A0 to A7 : Control signal 21 : Multiplex 22, 23a~23h ·· or gates 24a~24h: and F0~F7: interrupt signal SM~ perform a pre-programming procedure S33 on the memory to perform a smear program S35~ to the memory Excessive socks write memory to execute a soft programming program
Client’s Docket No. :94-037 TTs Docket No:0492-A40576-TW/fiQal/brent 3/2/2006 1303828 對元憶體進行一反編組程序 S61〜驗證記憶胞的内容值是否為〇 S62〜選擇下一個記憶胞 S63〜對記憶胞進行一編程程序 S64〜驗證記憶朗崎值是否為〇 S65〜纪憶胞的編程次數是否大於n ? S66〜對記憶胞再次進行編程程序· S71對冗憶體進行一編組程序 S72〜對記憶體進行一抹寫程序 S73〜對記憶體19進行一反編組程序 S74〜選擇一記憶區段 S75〜對記憶區段中的每一記憶胞進行驗證 S76〜是否全部區段都已驗證完畢? S77〜遮敝驗證通過的記恃區 S78^ _ 選擇下一個記憶區段 己憶體19進行編組程序 行祙寫種 序 S79〜對記憶體19中未通過驗證的記憶區段再次進 S81〜對記憶體進行一編組程序 S82〜驗證記憶體中每一記憶胞並記錄過度抹寫的$憶胞的位 S83〜對記憶體進行一反編組程序 S84〜對過度抹寫的記憶胞進行一軟編程程序 S85〜對進行軟編程程序後的記憶胞進行驗證 S 86〜是否全部記憶胞都驗證通過Client's Docket No. :94-037 TTs Docket No:0492-A40576-TW/fiQal/brent 3/2/2006 1303828 Perform an anti-grouping procedure on the meta-memory S61~ Verify whether the content value of the memory cell is 〇S62~Select The next memory cell S63~ performs a programming procedure on the memory cell S64~ Verify whether the memory Langsaki value is 〇S65~ The number of programming times of the memory cell is greater than n? S66~Programming the memory cell again · S71 to the redundant body Perform a grouping process S72~ perform a smear program S73 on the memory~ perform an anti-grouping process S74 on the memory 19~ select a memory segment S75~ verify each memory cell in the memory segment S76~ whether or not all areas The segments have been verified? S77~ 敝 敝 通过 S S S 78 78 78 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 选择 78 78 78 78 78 78 78 78 The memory performs a grouping process S82~ to verify each memory cell in the memory and record the over-storing bit of the memory cell S83~ perform an anti-grouping process on the memory S84~ perform a soft programming on the memory cell of the over-erase Program S85~Verifies the memory cell after performing the soft programming procedure. S86~ Whether all memory cells are verified and passed
Client’s Docket Νο·:94-〇37 3/2/2006 TT^s Docket Ν〇:〇492.Α40576^/^Γ6ηί 12 1303828 " S87〜記錄驗證失敗的記憶胞的位址 參Client’s Docket Νο·:94-〇37 3/2/2006 TT^s Docket Ν〇:〇492.Α40576^/^Γ6ηί 12 1303828 " S87~ Recording failed memory cell address
Client’s Docket No·:94-037 TT5s Docket No:0492-A40576>TW/final/brent 3/2/2006 13Client’s Docket No·:94-037 TT5s Docket No:0492-A40576>TW/final/brent 3/2/2006 13
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9298606B2 (en) | 2011-09-30 | 2016-03-29 | Intel Corporation | Statistical wear leveling for non-volatile system memory |
| TWI588651B (en) * | 2011-02-02 | 2017-06-21 | 美光科技公司 | At least semi-autonomous modules in a memory system and methods |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI588651B (en) * | 2011-02-02 | 2017-06-21 | 美光科技公司 | At least semi-autonomous modules in a memory system and methods |
| US9298606B2 (en) | 2011-09-30 | 2016-03-29 | Intel Corporation | Statistical wear leveling for non-volatile system memory |
| TWI578157B (en) * | 2011-09-30 | 2017-04-11 | 英特爾股份有限公司 | Method and apparatus of wear leveling for memory array |
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