13〇38^^^/§ 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種液晶顯示裝置及其主動陣列基 板的結構，且特別是有關於一種可降低電源消耗並增加反 應速度之主動陣列基板。 【先前技術】 一般的液晶顯示面板主要是由一主動陣列基板、一對 向基板以及一夾於前述二基板之間的液晶層所構成。其 • 中，主動陣列基板主要包括基板、陣列排列於基板上之晝 素結構、掃描線(scan line)與資料線(data line)。前述的晝素 結構主要係由薄膜電晶體、晝素電極(pixel Electrode)、儲 存，谷(Cst)所構成。一般而言，掃描線與資料線係分別傳 送定址信號電壓與顯示信號電壓至對應之晝素結構，使液 晶顯示面板能達到顯示之目的。13〇38^^^/§ IX. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device and an active array substrate thereof, and particularly relates to a method for reducing power consumption and increasing reaction Active array substrate for speed. [Prior Art] A general liquid crystal display panel is mainly composed of an active array substrate, a pair of substrates, and a liquid crystal layer sandwiched between the two substrates. In the above, the active array substrate mainly comprises a substrate, a pixel structure in which the array is arranged on the substrate, a scan line and a data line. The aforementioned halogen structure is mainly composed of a thin film transistor, a pixel electrode, a storage, and a valley (Cst). Generally, the scan line and the data line respectively transmit the address signal voltage and the display signal voltage to the corresponding pixel structure, so that the liquid crystal display panel can achieve the display purpose.
為了增加液晶顯示面板的使用壽命，一般的液晶顯示 面板大夕採用點反轉（_ inVersi〇n)、列反轉（r〇W • mvers·)、行反轉（column inversion)、圖框反轉（frame inversion)等方式進行驅動，不論是點反轉、列反轉、行反 轉或囷忙反轉’透過資料線而提供至液晶顯示面板中每個 晝素單福顯示信號會隨著每-〗0__(ftameby • f:ame)而切換其極性(polarization)。換言之，在第τ個圖框 、日$間以及第Τ+1個圖框時間内，施加於畫素單元中之液晶 層的電壓極性會相反。因此，資料線輸入顯示信號電壓至 畫素結構時，將會面臨耗電量較高與充電時間較長等問題。 I30380ewf.d〇c/g 【發明内容】 ^鑑於此，本發明的目的就是在提供一種主動 板，，、具有耗電量低且充電時間短之特性。 土 上述目示裝置，其具有 耗電量低之=基板’此液晶顯示裳置具有應答時間快與 u /、 拎描線、貧料線與晝素單元 =基板上。此外’每一晝素單元包括一主動元件與一 線以及:應晝素電極係透過主動元件與對應之掃瞄 於至少部;的每另=電荷中和電路配置 和電路與相鄰之晝素電極、相鄰之;===:中 =性連接，且每—電荷中和電路係藉由對應之掃描線= 陣列顯示裝置’其係包括前述之主動 於主動陣列基板:二板與一液晶層。其令，對向基板配置 與對向基板之間。此外==〜置於主動陣列基板 光基板。 1述之對向基板例如為-彩色濾 置於基板上之丘中’主動陣列基板例如更包括一配 壓源。 且共用配線係電性連接於參考電 7 I3〇380#twfdoc/g 本發明之一實施例中，每一 個或=同:條掃描線控制之薄例如包括— 本毛明之一貧施例中，杏备一 電路與相鄰之晝素電極電性:接時荷中和 偶數列或奇數列之畫素單元内。 電何中和電路係位於 本發明之一實施例中，者查 電路與相鄰之畫素電極電“I,透過電荷中和 偶數行或奇數行之晝素單元了巾和電路係位於 所有的畫素單元内。 Ϋ冑何中和電路係位於 電路畫素電極透過電荷中和 =畫;c電性連接時’電荷中和電路係位於所 電路二=例中’當每-晝素電極透過電荷中和 源電性連接時，電荷中和電路係位於所有 電行3例中’每—畫素單元内之主動元件與 電何t和電路係猎由不同之掃描線來開啟。 接兩：本發明之主動陣列基板，其具有可電性連 晝，之電荷中和電路，且此電荷中和電路可 在1素單凡顯不下一_查二， 元中所《之H減將兩相鄰之畫素單 電月b，而且可以縮短畫素單元之充電 13 03 8 ❺ d〇c/g 時間。 ▲為讓本發明之上述和其他目的、特徵和優點能更明顯 易懂，下文特舉較佳實施例，並配合所附圖式，作詳細說 明如下。 【實施方式】 第一實施 ® 1繪不為本發明第一實施例之液晶顯示裝置示意 圖。明參考圖1，本實施例之液晶顯示裝置100包括一主 • 動陣列基板110、一液晶層120與-對向基板130。其中， 對向基板130配置於主動陣列基板11〇上方，而液晶層 配置於主動陣列基板丨1〇與對向基板之間。上述之對向基 板130例如為一彩色濾光基板。 圖2A繪示為本發明第一實施例之主動陣列基板示意 圖’而圖2B繪示為本發明第一實施例之主動陣列基板之 電路示意圖。為了圖示的簡明，將在後續所繪製的主動陣 列基板之電路示意圖中，僅繪示出屬於主動陣列基板上的 φ 儲存電容及電路。請參考圖2A與圖2B，本實施例之主動 陣列基板110包括一基板112、多個畫素單元114、多條掃 描線10、多條資料線2〇、與多個電荷中和電路(charge neutralization circuit)30。其中，掃描線 10、資料線 20 與 • 晝素單元114配置於基板112上。此外’每一畫素單元114 • 包括一主動元件116與一畫素電極118。在本實施例中， 主動元件116例如為薄膜電晶體，而畫素電極118係透過 主動元件116與對應之掃瞄線10以及對應之資料線20電 13 03 8^0twf d〇c/g 性連接。 由圖2A與圖2B可知，電荷中和電路30係配置於炱 少部分的晝素單元114中，而每一電荷中和電路3〇例如包 括一個或多個（在本實施例中為一個）藉由同一條掃描線 10控制之薄膜電晶體32。此外，每一畫素電極118係透過 電荷中和電路30與相鄰之晝素電極118a電性連接，然而’ 在其他貫施例中，晝素電極118亦可與相鄰之資料線2〇 或一參考電壓源電性連接，在本實施例中係舉畫素電 極118與相鄰之晝素電極n8a電性連接之例子來作説明， 而其餘的狀況將在其他實施例中詳述。 承上述，每一晝素電極118係透過電荷中和電路30 與相鄰之晝素電極118a電性連接，而電荷中和電路30例 如係位於偶數行或奇數行之晝素單元114内。具體而言， 主動陣列基板11G例如更包括—配置於基板112上之共用 配線L，其中共用配線L係電性連接於參考電壓源(如 圖2B所示）。 • 3 圖2A與圖2B中的主動陣列基板110所構成之液晶 』示衣置100可採用行反轉（column inversi〇n)或是點反 轉（dot lnversi〇n)的方式來驅動，當晝素單元中之 兀件116以及與其同一列之主動元件116被同一條掃 • 啟時’位於晝素單元U4b與晝素單元114c之間 ， 中]：和電路30會連帶被開啟，進而使晝素單元114b 素電極118能夠與晝素單元114c中的晝素電極 &通。換言之，在本實施例中，位在第N列之畫素單 I3O38#0twfd〇c/g 元（畫素單元lHb或畫素單元114c)中的電荷中和電路 30能夠藉由第條之掃描線10來開啟。 一般而言，透過資料線20而提供至液晶_示裝置1〇〇 中每個畫素單元1H的顯示信號電壓會隨著每一彳^圖框時 間而切換其極性。換言之，在第τ個圖框時間以及第丁+1 個圖框時間内，施加於晝素單元114中之液晶層12〇的電 壓極性會相反。 舉例來說，在第τ個圖框時間，相鄰之各查素單元 • 114b與114C中，各自保留了第τ個圖框時間之^示信號 電壓，由於採用行反轉或是點反轉的方式來驅動，因而此 兩者（114b與114c)所保留之第T個圖框時間之顯示作 就電壓之極性是相反的（以參考電壓源^^。阳為失考電 壓）。此外，在第T+1個圖框時間，透過資料線2〇所提 供至晝素單元114b之顯示訊號電壓與在第τ個圖框時 間，資料線20所提供至畫素單元i14b之顯示訊號電壓之 極性會互相對調。同樣地，晝素單元114c在第個圖 • 框時間所接收到顯示訊號電壓與在第Τ個圖框時間所接二 到顯示訊號電壓之極性也會互相對調。 因此，在第Τ個圖框時間電荷中和電路30被開啟後 =使得晝素單it 114b與114e各自保留之相反極性之顯示 * 信號電壓電性中和。換言之，透過資料線20傳輸第T+1 ' 個圖框時間之顯示信號電壓至畫素單元114b與114c前， 此兩晝素單元114b與114c所保留之顯示信號電壓已被電 性中和。In order to increase the service life of the liquid crystal display panel, the general liquid crystal display panel uses dot inversion (_inVersi〇n), column inversion (r〇W • mvers·), row inversion, and frame inversion. Drive in the form of frame inversion, whether it is dot inversion, column inversion, row inversion, or busy inversion. The data supplied to the liquid crystal display panel through the data line will be displayed with each pixel. Switch the polarity of each -0__(ftameby • f:ame). In other words, the voltage polarity applied to the liquid crystal layer in the pixel unit will be reversed during the τth frame, the day $, and the +1th frame time. Therefore, when the data line input shows the signal voltage to the pixel structure, it will face problems such as high power consumption and long charging time. SUMMARY OF THE INVENTION In view of the above, an object of the present invention is to provide an active board having characteristics of low power consumption and short charging time. The above-mentioned visual device has a low power consumption = substrate 'this liquid crystal display skirt has a response time fast with u /, a drawing line, a lean line and a halogen element = substrate. In addition, each of the pixel units includes an active component and a line and: the pixel electrode is scanned through the active component and correspondingly scanned at least in part; each of the charge-neutralizing circuit configurations and circuits and the adjacent germanium electrode ???adjacent; ===: medium=sexual connection, and each charge-neutralization circuit is corresponding to the scan line=array display device', which includes the aforementioned active active array substrate: two plates and a liquid crystal layer . This causes the opposing substrate to be placed between the opposing substrate. Also ==~ placed on the active array substrate light substrate. The opposite substrate is, for example, a color filter disposed in the mound on the substrate. The active array substrate further includes, for example, a pressure source. And the common wiring is electrically connected to the reference power. In the embodiment of the present invention, each thinning control of the scanning line is included, for example, in one of the embodiments of the present invention. Apricot-a circuit and adjacent elemental electrode electrical: in the pixel unit of the time-in and even-numbered columns or odd-numbered columns. The electric neutral circuit is located in an embodiment of the present invention, and the circuit and the adjacent pixel electrode are electrically "I, the charge unit is neutralized by even or odd rows of the unit. The towel and the circuit are located at all. In the pixel unit, the neutralization circuit is located in the circuit pixel electrode through the charge neutralization = drawing; c is electrically connected when the 'charge neutralization circuit is in the circuit 2 = example' when the per-alkali electrode is transmitted When the charge neutralization source is electrically connected, the charge neutralization circuit is located in the "per-pixel unit" of all the electrical circuits, and the active components and the electrical circuit are opened by different scanning lines. The active array substrate of the invention has an electric charge connection and a charge neutralization circuit, and the charge neutralization circuit can be displayed in a single element. The neighboring pixels are single-month b, and can shorten the charging of the pixel unit by 13 03 8 ❺ d〇c/g. ▲ In order to make the above and other objects, features and advantages of the present invention more obvious, the following DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The preferred embodiments, together with the drawings, are described in detail below. The first embodiment of the present invention is a schematic diagram of a liquid crystal display device according to a first embodiment of the present invention. Referring to FIG. 1, a liquid crystal display device 100 of the present embodiment includes a main array substrate 110 and a liquid crystal layer 120. And the opposite substrate 130. The opposite substrate 130 is disposed above the active array substrate 11A, and the liquid crystal layer is disposed between the active array substrate 丨1〇 and the opposite substrate. The opposite substrate 130 is, for example, a color. 2A is a schematic diagram of an active array substrate according to a first embodiment of the present invention, and FIG. 2B is a schematic circuit diagram of an active array substrate according to a first embodiment of the present invention. In the circuit diagram of the active array substrate, only the φ storage capacitor and the circuit on the active array substrate are shown. Referring to FIG. 2A and FIG. 2B, the active array substrate 110 of the embodiment includes a substrate 112 and a plurality of The pixel unit 114, the plurality of scan lines 10, the plurality of data lines 2〇, and a plurality of charge neutralization circuits 30. wherein the scan lines 10 and the data lines 20 are The pixel unit 114 is disposed on the substrate 112. Further, each pixel unit 114 includes an active element 116 and a pixel electrode 118. In this embodiment, the active element 116 is, for example, a thin film transistor and a pixel electrode. The 118 series is electrically connected to the corresponding scan line 10 and the corresponding data line 20 through the active device 116. As can be seen from FIG. 2A and FIG. 2B, the charge neutralization circuit 30 is disposed on the 炱. In a small portion of the halogen unit 114, each charge neutralizing circuit 3 includes, for example, one or more (in this embodiment, one) thin film transistor 32 controlled by the same scanning line 10. In addition, each of the pixel electrodes 118 is electrically connected to the adjacent halogen electrode 118a through the charge neutralizing circuit 30. However, in other embodiments, the pixel electrode 118 may also be adjacent to the adjacent data line 2〇. Or a reference voltage source is electrically connected. In the embodiment, the executor pixel 118 is electrically connected to the adjacent halogen electrode n8a. The remaining conditions will be described in detail in other embodiments. In the above, each of the halogen electrodes 118 is electrically connected to the adjacent halogen electrode 118a through the charge neutralizing circuit 30, and the charge neutralizing circuit 30 is, for example, located in the even-numbered rows or odd-numbered rows of the pixel units 114. Specifically, the active array substrate 11G further includes, for example, a common wiring L disposed on the substrate 112, wherein the common wiring L is electrically connected to a reference voltage source (as shown in FIG. 2B). • The liquid crystal display device 100 formed by the active array substrate 110 in FIG. 2A and FIG. 2B can be driven by a line inversion or a dot inversion (dot lnversi〇n). The element 116 in the pixel unit and the active element 116 in the same column are located between the pixel unit U4b and the pixel unit 114c during the same sweeping, and the circuit 30 is turned on, thereby enabling The pixel unit 114b element electrode 118 can be connected to the halogen electrode & In other words, in the present embodiment, the charge neutralization circuit 30 in the pixel list I3O38#0twfd〇c/g element (the pixel unit 1Hb or the pixel unit 114c) of the Nth column can be scanned by the strip Line 10 is turned on. In general, the display signal voltage supplied to each pixel unit 1H in the liquid crystal display device 1 through the data line 20 switches its polarity with each frame time. In other words, the polarity of the voltage applied to the liquid crystal layer 12A in the pixel unit 114 is reversed during the τth frame time and the +1st frame time. For example, in the τth frame time, each of the adjacent element cells 114b and 114C retains the signal voltage of the τth frame time, due to line inversion or dot inversion. The way to drive, so the second frame time reserved by the two (114b and 114c) is the opposite of the polarity of the voltage (to the reference voltage source ^ yang is the missed voltage). In addition, at the T+1th frame time, the display signal voltage supplied to the pixel unit 114b through the data line 2〇 and the display signal supplied from the data line 20 to the pixel unit i14b at the τth frame time. The polarity of the voltage will be reversed. Similarly, the polarity of the display signal voltage received by the pixel unit 114c at the time of the first frame and the time at the second frame time is also reversed to the polarity of the display signal voltage. Therefore, after the time-character neutralization circuit 30 is turned on in the second frame = the display of the opposite polarity of the respective pixels 112 and 114e are kept *the signal voltage is electrically neutralized. In other words, before the display signal voltage of the T+1'th frame time is transmitted through the data line 20 to the pixel units 114b and 114c, the display signal voltages retained by the two pixel units 114b and 114c are electrically neutralized.
I3〇38#0twfdo^ 於是對晝素單元11仆與114c輸入第T+l個圖框時間 之顯不信號電壓時，不需要自第τ個圖框時間所保留之相 反極性電壓開始充電，僅需要從中和後的電壓開始充電， 因而所需要改變的電壓量減少。換言之，本發明之資料線 ^0便可在較短的時間内將晝素單元⑽與114c充電至預 。又之位準。此外，相較於習知技術本發明之 裝置100更可提高電源的使用效率。 ，貝丁 第二實施例 圖3A緣示為本發明第二實施例之主動陣列基板示意 3 ’而圖⑴會示為本發明第二實施例之主 電路示意圖。請同時參考圖3A盥冃⑶—〜 一 3A與圖3B，第三實施例與第 ’主要不同之處在於：本實施例之電荷中和 lUh叙⑴二 内，且相鄰之晝素電極 '透過兩個電荷中和電路4G而電性連接。 虽旦素mi4a中之主動元件116以及與其同一列 之主動元件116被同一條播ρ綠】Λ 114h盥圭去篷-条知描線10開啟時，位於晝素單元 ”旦，、70 Mc之間的電荷中和電路4〇合連帶被開 二’而=素單元"仙中的畫素電極心= 中位在第Ui極i18a電性連接。換言之，在;實施例 114c)中^Γ 早70 U4b或晝素單元 1〇 Ιπΐ! Γ, ίο來開啟。如此一來，此兩者（114b與u 之顯示訊5虎電壓之電性會相互中和。 ,、 在此實施例中由於每一個晝素單元都具有中和電 12 13 03 8^0twf d〇c/s 路母個旦素單元彼此間的佈局（lay〇ut)較相近，因此顯 示上較不容易出現顏色不均(Mura)之異常。 第三實施例 圖4A繪示為本發明第三實施例之主動陣列基板示意 圖，而圖4B繪示為本發明第三實施例之主動陣列基板之 電路示思圖。凊同時參考圖4A與圖4B，第三實施例與第 一實把例非常類似，其中不同之處在於：電荷中和電路5〇 係位於偶數列或奇數列之晝素單S 1M内，且本實施例之 液曰B顯示裝置可採用列反轉（r〇w inversi〇n)或是點反轉 (dot inversion)的方式來驅動。本實施例之電荷中和電路 50連接晝素單元i14a巾之畫素電極118以及與其位於同 行中相鄰之晝素電極118a(位於晝素單元114b)。 由於採用列反轉或是點反轉的方式來驅動，因而此兩 者（114a與114b)所保留之顯示信號電壓之極性是相反 的。當晝素單元ll4a中之前一條掃描線1〇 (第。⑹)條)開 啟时，位於晝素單元114a之電荷中和電路50會連帶被開 啟’進而使畫素單元H4a中的畫素電極118能夠與晝素單 元114b中的里素電極11 導通。換言之，在本實施例中， 位在第N列之晝素單元（例如是畫素單元114a)中的電荷 中和電路50能夠藉由第G(N-d條之掃描線10來開啟。如此 一來，本貫施例之主動陣列基板31〇也可與第一實施例之 主動陣列基板11〇具有相同之功效。 第四實施例 圖5A繪示為本發明第四實施例之主動陣列基板示意 13 13 03 8®0twf d〇c/g 圖’而f 5B緣示為本發明第四實施例之主動陣列基板之 電，不思B。請同時參考圖5A與圖5B，第四實施例與第 -貝關非常類似，其巾主要不同之處在於：每—晝素電 極118係透過電荷中和電路6〇與相鄰之資料、線施電性連 接。此外，電荷中和電路60係位於所有的畫素單元114 中。本實施例之液晶顯示裝置可採用以晝面反轉（frame inVersi〇n )、列反轉（row inversion )或是點反轉（d〇t inversion)的方式來驅動，當晝素單元114a中之主動元件 116以及與其同一列之主動元件116被同一條掃描線1〇開 啟時’位於晝素單元114b中之電荷中和電路60會連帶被 開啟，進而使晝素單元114b中的晝素電極118能夠與資料 線20a導通。 換言之，在本實施例中，位在第N列之晝素單元（例 如是晝素單元114a)中的電荷中和電路60能夠藉由第G(N… 條之掃描線10來開啟。詳細地說，資料線20a在對晝素單 元114d傳輸第τ個圖框時間之顯示信號電壓時，也會將 相同的顯示信號電壓充入晝素單元114b中。因而，原先保 留於晝素單元114b中之第T-1個圖框時間之顯示信號電 壓，其會被晝素單元114d的第T個圖框時間之顯示信號 電壓所覆蓋，使得晝素單元114b中呈現與第T-1個圖框時 間之顯示信號電壓之相反極性（在畫面反轉、列反轉或是 點反轉的驅動方式下，畫素單元114b的第T-1個圖框時間 之顯示信號電壓以及畫素單元114d的第T個圖框時間之 顯不彳§ 5虎電壓之極性相反）。 14 I3038_twfdoc/g 因此’資料、線20在對晝素單元充入第丁個圖框 日守間之顯示訊號電壓前，晝素單元丨丨仆所保留之 電壓已被畫素單it md的第τ個圖框時間之顯示作= 壓所覆蓋，並且由於晝素單元114b的第τ個圖框^ 顯示信號電壓與晝素單元114d的第τ個圖框時間 信號電壓極性相同。亦即資料線2〇在對晝素單元11扑、$ 入第Τ個圖框時間之顯示訊號電壓前，晝素單元⑽ 保留之顯示信號電壓極性已經與第丁個圖框時 > 號電壓極性相同，因此充電至預設之電壓二 ，壓量減少。換言之’藉由上述之方式即可二^ 早兀114b充電至預設之電壓位準所需的時間。 羞^五實施例 圖6A繪示為本發明第五實施例之主動陣 圖’而圖6B缘示為本發明第五實施例之主動陣=板: 電^示意圖。請同時參考圖6A與圖6B，第五實施二 四貫施例非常的類似，其中不同之處在於：每 川係透過電荷中和電路7〇與本身所對應之資料旦線素電 H妾。。此外，電荷中和電路70係位於所有的晝素單元 = 實施例之液晶顯示裝置採用圖框反轉或是行反 得的方式來驅動，當位於畫素單元U4a中之主動元件ιΐ6 ^及與其同—列之主動元件116被同—條掃描線'開啟 位於晝素單元114b之電荷中和電路70會連帶被開啟， 、而使晝素單το 114b本身所對應之資料線2〇傳輸顯示信 15 130380^^°°^ 號電壓至晝素單元114b中。換言之，在本實施例中，位在 第N列之晝素單元（例如是晝素單元114b)中的電荷中和 電路70能夠藉由第g(n-1)條之掃描線1〇來開啟。 詳細地說’當資料線20傳輸第T個圖框時間至晝素單元 114a的同時’也會將相同的之顯示信號電壓傳輸至晝素單 元 114b 〇 艰上遲，在晝面反轉或是行反轉的驅動方式下，由於 晝素單元114b原先所保留之第τ-1個圖框時間之顯示信號 電壓之極性與資料線2〇在第τ個圖框時間傳輸至晝素單 元114a之顯示信號電壓之極性相反。因此，位於晝素單元 =:原先所保留第w個圖框時間之顯示信號電壓會被 的第τ個圖框時間之顯示訊號電壓所覆 ==1=4㈣竭W自綱間之顯示 顯示则框時間之 性已經與第Τ__間之顯 t之顯示信號電馳 於習知技術更可縮短資料線20對°佥";電壓極性相同，相較 設電壓位準所㈣時間。 I素早元114b充電至預 名六實施何 圖7A緣示為本發明第丄者 圖，而圖7B綠示為本發^2之主動陣列基板示意 電路示意圖。請同時夾老岡=/、Λ知例之主動陣列基板之 一實施例類似，1中Α與圖7Β，第六實施例與第 -中不同之處在於··每—晝素電極118係 13〇3800^场 透過電荷中和電路80係藉由共用配線L (圖7A中所示） 與參考電壓源Vc〇m (圖7B中所示）電性連接。此外，電 荷中和電路80係位於所有的晝素單元114中。 當位於第N-1列之畫素單元114a之主動元件116以 及與其同一列之主動元件116被同一條掃描線開啟時， 位於第N列之晝素單元ii4b之電荷中和電路8〇也會被連 帶開啟，進而導致晝素單元114b之晝素電極118與參考電 壓源Vc〇m導通。換言之，在本實施例中，位在第N列之晝 鲁 素單元（例如是晝素單元114b)中的電荷中和電路8〇能 夠藉由第G(n_i)條之掃描線1〇來開啟。 當資料線20傳輸第τ個圖框時間之顯示訊號電壓至晝 素單兀114b之前，不論畫素單元114b之晝素電極118所 保留之顯示訊號電壓之極性為何，在晝素單元U4b之書素 電極118與參考電壓源VcQm導通後，晝素電極丨以會^參 考電壓源Vcom等電位。因此，當本實施例之資料線2〇傳 輸第T個圖框時間之顯示訊號電壓時，藉由上述之方式 • 彳縮短資料線2G對晝素單元114b充人顯示訊號電壓^需 的時間。 綜上所述，本發明之液晶顯示裝置至少具有下述優 點：本發明液晶顯示裝置中之主動陣列基板，因其包括電 • 荷中和電路，此電荷中和電路可在晝素單元顯示下一㈣ • 蚊前，預先將保留於兩相鄰之畫素單元中用以顯示上2 2晝面之電荷進行電性中和。因此，本發明之液晶顯示裝 置可驗畫素早70之充電時間並可減低液晶顯示裝置之耗 13〇380©twfdoc/g 電量。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作些許之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 圖1繪示為本發明之液晶顯示裝置示意圖。 圖2A繪示為本發明第一實施例之主動陣列基板示竞 圖。 圖2B繪示為本發明第一實施例之主動陣列基板之電 路示意圖。 私 圖3A繪示為本發明第二實施例之主動陣列基板示竟 圖。 圖3B繪示為本發明第二實施例之主動陣列基板之電 路示意圖。 圖4A繪示為本發明第三實施例之主動陣列基板示竟 圖。 圖4B繪示為本發明第三實施例之主動陣列基板之電 路不意圖。 圖5A繪示為本發明第四實施例之主動陣列基板示竟 圖。 圖5B繪示為本發明第四實施例之主動陣列基板之電 路示意圖。 圖6A繪示為本發明第五實施例之主動陣列基板示意 I3〇3800twfdoc/g 圖。 圖6B繪示為本發明第五實施例之主動陣列基板之電 路示意圖。 圖7A繪示為本發明第六實施例之主動陣列基板示意 圖。 圖7B繪示為本發明第六實施例之主動陣列基板之電 路示意圖。 【主要元件符號說明】 • 10 :多條掃描線 20 :多條資料線 20a ·相鄰之貢料線 30、40、50、60、70、80 :電荷中和電路 32 :薄膜電晶體 100 ·液晶顯不裝置 110 :主動陣列基板 112 :基板 120:液晶層 130 :對向基板 114、114a、114b、114c、114d :晝素單元 116 :主動元件 . 118 :畫素電極 118a :相鄰之畫素電極 ' VeQm ••參考電壓源 L :共用配線 19 I3038(^)wfd〇c/gI3〇38#0twfdo^ Then, when the display signal of the T+1 frame time is input to the pixel unit 11 and 114c, it is not necessary to start charging from the opposite polarity voltage retained by the τ frame time, only It is necessary to start charging from the voltage after neutralization, and thus the amount of voltage that needs to be changed is reduced. In other words, the data line ^0 of the present invention can charge the pixel units (10) and 114c to a predetermined time in a short period of time. Another level. Further, the apparatus 100 of the present invention can improve the efficiency of use of the power source as compared with the prior art. The present invention is shown in Fig. 3A, which is a schematic diagram of an active array substrate according to a second embodiment of the present invention, and Fig. 1(1) shows a schematic diagram of a main circuit according to a second embodiment of the present invention. Please refer to FIG. 3A盥冃(3)—~3A and FIG. 3B at the same time. The third embodiment differs from the first one in that: the charge in this embodiment neutralizes lUh (1) and the adjacent elemental electrode It is electrically connected through two charge neutralizing circuits 4G. In the case of the active element 116 in the same mi4a and the active element 116 in the same column, the same piece of green Λ Λ Λ 盥 盥 盥 盥 - - 条 条 条 条 条 条 条 条 条 条 条 , , , , , , , , , , , , , , , , , , , The charge-neutralizing circuit 4 is coupled to be turned on by two's and the prime element is "the pixel of the pixel" = the median is electrically connected at the Ui pole i18a. In other words, in the embodiment 114c) U4b or 昼 单元 〇Ι Γ Γ Γ Γ Γ 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 如此 如此 如此 如此 如此 如此 如此 如此 如此 114 114 114 114 114 114 114 114 114 114 114 114 114 114 The halogen elements have the neutralization power 12 13 03 8 ^ 0twf d〇c / s. The layout of the matrix elements is similar to each other, so the color unevenness (Mura) is less likely to appear on the display. 3A is a schematic diagram of an active array substrate according to a third embodiment of the present invention, and FIG. 4B is a schematic diagram of a circuit of an active array substrate according to a third embodiment of the present invention. 4A and FIG. 4B, the third embodiment is very similar to the first embodiment, in that the difference is: The neutralization circuit 5 is located in the even-numbered column or the odd-numbered column, and the liquid 曰B display device of the embodiment can adopt column inversion (r〇w inversi〇n) or dot inversion (dot). The charge neutralization circuit 50 of the present embodiment is connected to the pixel electrode 118 of the pixel unit i14a and the pixel electrode 118a (located in the pixel unit 114b) adjacent to the same. Reverse or dot inversion is used to drive, so the polarity of the display signal voltage retained by the two (114a and 114b) is reversed. When the previous scan line 1 in the pixel unit 1144a is 〇 ((6) When turned on, the charge neutralizing circuit 50 located in the pixel unit 114a is turned on, and the pixel electrode 118 in the pixel unit H4a can be turned on to the inner electrode 11 in the pixel unit 114b. In other words, In this embodiment, the charge neutralization circuit 50 in the pixel unit of the Nth column (for example, the pixel unit 114a) can be turned on by the Gth (the scan line 10 of the Nd strip). The active array substrate 31 of the embodiment can also be the main body of the first embodiment. The array substrate 11A has the same effect. Fourth Embodiment FIG. 5A is a schematic diagram of an active array substrate according to a fourth embodiment of the present invention, 13 13 03 8® 0 twf d〇c/g FIG. The power of the active array substrate of the fourth embodiment is not considered to be B. Please refer to FIG. 5A and FIG. 5B at the same time, the fourth embodiment is very similar to the first-before-off, and the main difference of the towel is that each of the halogen electrodes 118 It is electrically connected to adjacent data and lines through the charge neutralization circuit 6〇. In addition, the charge neutralization circuit 60 is located in all of the pixel units 114. The liquid crystal display device of this embodiment can be driven by means of frame inversion, column inversion or dot inversion, in the pixel unit 114a. When the active device 116 and the active device 116 in the same column are turned on by the same scanning line 1 ', the charge neutralizing circuit 60 located in the pixel unit 114b is turned on, thereby enabling the pixel electrode in the pixel unit 114b. 118 can be turned on with the data line 20a. In other words, in the present embodiment, the charge neutralization circuit 60 in the pixel unit (e.g., the pixel unit 114a) of the Nth column can be turned on by the Gth (the scanning line 10 of the Nth column. It is said that when the data line 20a transmits the display signal voltage of the τth frame time to the pixel unit 114d, the same display signal voltage is also charged into the pixel unit 114b. Therefore, it is originally retained in the pixel unit 114b. The display signal voltage of the T-1th frame time is covered by the display signal voltage of the Tth frame time of the pixel unit 114d, so that the pixel unit 114b is presented with the T-1th frame. The opposite polarity of the display signal voltage of time (in the driving mode of screen inversion, column inversion or dot inversion, the display signal voltage of the T-1th frame time of the pixel unit 114b and the pixel unit 114d The T-frame time is not the same as § 5 The polarity of the tiger voltage is opposite.) 14 I3038_twfdoc/g Therefore, 'data and line 20 are in front of the display signal voltage of the day-to-day frame of the pixel unit. The voltage reserved by the 昼素 unit 丨丨 servant has been drawn as a single m md The display of the τth frame time is covered by the voltage, and since the τth frame of the pixel unit 114b shows that the signal voltage is the same as the voltage of the τth frame time signal of the pixel unit 114d. The data line 2〇 has the same polarity as the voltage of the display signal voltage of the prime unit (10) before the display signal voltage of the pixel unit 11 and the time frame of the second element. Therefore, the battery is charged to the preset voltage 2, and the amount of pressure is reduced. In other words, the time required for charging 114b to the preset voltage level can be as long as the above method. The active array diagram of the fifth embodiment of the present invention is shown in FIG. 6B. The active array=board according to the fifth embodiment of the present invention is shown in FIG. 6A and FIG. 6B, and the fifth embodiment is implemented. The examples are very similar, the difference is that each channel passes through the charge-neutralization circuit 7〇 and its corresponding data-liner H. In addition, the charge-neutralization circuit 70 is located in all the halogen elements = The liquid crystal display device of the embodiment adopts a frame inversion or The row is reversed to drive, when the active component ιΐ6^ located in the pixel unit U4a and the active component 116 of the same column are turned on by the same scanning line 'on the charge in the pixel unit 114b and the circuit 70 is associated with It is turned on, and the data line 2 corresponding to the pixel το 114b itself transmits the voltage of the display signal 15 130380^^°° to the pixel unit 114b. In other words, in the embodiment, the bit is at the Nth. The charge neutralization circuit 70 in the column of the pixel unit (for example, the pixel unit 114b) can be turned on by the scanning line 1〇 of the gth (n-1). In detail, when the data line 20 transmits the Tth The frame time to the same time of the pixel unit 114a will also transmit the same display signal voltage to the pixel unit 114b. It is difficult to delay, in the driving mode of the face reversal or the line reversal, due to the halogen The polarity of the display signal voltage of the τ-1 frame time previously reserved by the unit 114b is opposite to the polarity of the display signal voltage of the data line 2 传输 transmitted to the pixel unit 114a at the τth frame time. Therefore, in the pixel unit =: the display signal voltage of the first w frame time is retained by the display signal voltage of the τth frame time ================== The time of the frame time has been compared with the display signal of the display __ between the first __ and the conventional technique can shorten the data line 20 to the same voltage polarity, compared with the voltage level (four) time. The first element 114b is charged to the pre-named six implementation. Figure 7A shows the second figure of the present invention, and Figure 7B shows the schematic circuit diagram of the active array substrate of the present invention. At the same time, the embodiment of the active array substrate is similar to that of the old grid. The first embodiment is different from the first embodiment. The sixth embodiment differs from the first one in that the per-alkaline electrode 118 is 13 The 〇3800^ field is electrically coupled to the reference voltage source Vc〇m (shown in FIG. 7B) through the charge neutralization circuit 80 via the common wiring L (shown in FIG. 7A). In addition, the charge neutralization circuit 80 is located in all of the halogen elements 114. When the active device 116 of the pixel unit 114a in the N-1th column and the active device 116 in the same column are turned on by the same scanning line, the charge neutralizing circuit 8 of the pixel unit ii4b located in the Nth column will also It is turned on, which in turn causes the halogen electrode 118 of the halogen unit 114b to be electrically connected to the reference voltage source Vc〇m. In other words, in the present embodiment, the charge neutralization circuit 8〇 in the arsenic unit of the Nth column (for example, the pixel unit 114b) can be turned on by the scanning line 1〇 of the Gth (n_i)th column. . Before the data line 20 transmits the display signal voltage of the τth frame time to the pixel unit 114b, regardless of the polarity of the display signal voltage retained by the pixel electrode 118 of the pixel unit 114b, the book of the pixel unit U4b After the element electrode 118 is turned on with the reference voltage source VcQm, the pixel electrode 等 is referenced to the potential of the voltage source Vcom. Therefore, when the data line 2 of the present embodiment transmits the display signal voltage of the Tth frame time, the time required for the data line 2G to display the signal voltage for the pixel unit 114b is shortened by the above method. In summary, the liquid crystal display device of the present invention has at least the following advantages: the active array substrate in the liquid crystal display device of the present invention, because it includes an electric current neutralization circuit, the charge neutralization circuit can be displayed under the pixel unit One (four) • Before the mosquito, it will be pre-retained in two adjacent pixel units to display the charge of the upper 2 2 surface for electrical neutralization. Therefore, the liquid crystal display device of the present invention can detect the charging time of 70 times and can reduce the power consumption of the liquid crystal display device by 13 〇 380 © twfdoc / g. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view of a liquid crystal display device of the present invention. 2A is a diagram showing an active array substrate according to a first embodiment of the present invention. 2B is a schematic circuit diagram of an active array substrate according to a first embodiment of the present invention. FIG. 3A is a diagram showing the active array substrate according to the second embodiment of the present invention. 3B is a schematic diagram of a circuit of an active array substrate according to a second embodiment of the present invention. 4A is a schematic diagram of an active array substrate according to a third embodiment of the present invention. 4B is a schematic diagram showing the circuit of the active array substrate according to the third embodiment of the present invention. FIG. 5A is a schematic diagram of an active array substrate according to a fourth embodiment of the present invention. FIG. 5B is a schematic diagram of a circuit of an active array substrate according to a fourth embodiment of the present invention. 6A is a schematic diagram of an active array substrate according to a fifth embodiment of the present invention, I3〇3800twfdoc/g. 6B is a schematic diagram of a circuit of an active array substrate according to a fifth embodiment of the present invention. FIG. 7A is a schematic view of an active array substrate according to a sixth embodiment of the present invention. FIG. 7B is a schematic diagram of a circuit of an active array substrate according to a sixth embodiment of the present invention. [Explanation of main component symbols] • 10: Multiple scanning lines 20: Multiple data lines 20a • Adjacent tributary lines 30, 40, 50, 60, 70, 80: Charge neutralization circuit 32: Thin film transistor 100 Liquid crystal display device 110: active array substrate 112: substrate 120: liquid crystal layer 130: opposite substrate 114, 114a, 114b, 114c, 114d: halogen unit 116: active device. 118: pixel electrode 118a: adjacent painting Prime electrode ' VeQm ••Reference voltage source L :Common wiring 19 I3038(^)wfd〇c/g
N_1 :第N-l列之晝素單元 N:第N列之畫素單元 :第N條掃礙線 Gosm):第N-1條掃瞄線 20N_1 : pixel unit in column N-l N: pixel unit in column N: Nth line of obstruction Gosm): line N-1 scanning line 20