TWI303868B - A plate having a chip embedded therein and the manufacturing method of the same - Google Patents

Description

1303868 IX. Description of the Invention: [Technical Field] The present invention relates to a carrier board embedded with a wafer and a method of manufacturing the same, and more particularly to a method for improving the bending of a board caused by asymmetric buildup. A carrier board structure in which a wafer is buried and a method of fabricating the same. [Prior Art] • The booming electronics industry has been booming. Electronic products are gradually entering the direction of multi-functional and high-performance research and development. In order to meet the packaging requirements of semiconductor package high integration 10 and miniaturization, most active and passive components and circuit-connected circuit boards are also gradually evolved from single-layer boards to multi-layer boards to make them limited. Under the space, the interlayer wiring area is used to expand the available wiring area on the board to meet the requirements of the integrated circuit of the south electron density. 15 However, the general semiconductor device process is firstly produced by a wafer carrier manufacturer for a wafer carrier suitable for the semiconductor device, such as a substrate or a wire. The wafer carriers are then transferred to a semiconductor package manufacturer for crystallization, stamping, and ball placement. Finally, the semiconductor device for the electronic functions required by the client can be completed. During the period, different manufacturers are involved, so in the actual manufacturing process, not only the steps are cumbersome but the interface integration is not easy. Moreover, if the client wants to change the function design, the change and integration level is more complicated, and it does not meet the elasticity of change of demand and economic benefits. Another conventional semiconductor package structure is to adhere a semiconductor wafer to the top surface of the substrate, perform wire bonding or flip-chip bonding, and then implant a solder ball on the back surface of the substrate to perform electricity. Sexual connection. In this way, you can achieve the goal of high number of feet. However, when it is used at a higher frequency or at a high speed, it is not possible to increase the performance of the electrical characteristics due to the long wire connection path. In addition, the conventional package requires multiple connections to increase the complexity of the process. For this reason, many studies have embedded the crystal moon into the package substrate. The embedded wafer in the package substrate can be directly connected to external electronic components to shorten the electrical conduction path and reduce signal loss and signal distortion. And upgrade _ high-speed operation ability. As shown in FIG. 1 , the carrier board structure in which the wafer is embedded includes: a carrier 1 〇 1 ' and the carrier 1 〇 1 is formed with an opening; a wafer 1 〇 2, the wafer is accommodated in the opening, The active surface of the wafer 1〇2 is formed with a plurality of electrode pads 1〇3; formed on the carrier substrate 1〇1 embedded with the wafer 102, and corresponding to the protective layer 1〇4 of the electrode pad 103; A plurality of metal layers 105 formed on the surface of the electrode pad 103; and a line build-up structure 106 formed on the carrier 101 and the surface of the wafer 102. The line build-up structure 1〇6 is formed on the surface of the wafer φ102 and the carrier 〇1, and is electrically connected to the carrier pad 101 and the electrode pad 103 of the wafer 102. At present, the material of the carrier 1 〇 1 • 20 which is commonly used in the carrier board structure in which the wafer is to be buried is copper or BT resin (Bismaleimide Triazine Resin). However, when the above material is used as the material of the carrier 1 〇1, the carrier-embedded structure in which the wafer is embedded may form a line build-up structure 106 on one side, and the stress is not caused by both the line addition and the non-level increase. Both of them have a problem of bending the plate, and the guide 303868 is not easy to produce, and the finished product is also low in yield due to excessive bending of the plate, and the reliability is not good. Therefore, in order to reduce the warpage of the board in which the wafer-embedded board is embedded due to the one-side build-up, and to improve the production yield, the carrier board made of copper or BT resin 5 cannot meet the requirements for use. SUMMARY OF THE INVENTION Φ A plurality of conductive structures, and at least one pad 0. In view of the above-mentioned disadvantages, the present invention provides a carrier-embedded board structure embedded with a wafer, comprising: a first inscription carrier having a first opening The second aluminum carrier has a second opening, and the position of the second opening corresponds to the position of the first opening; a dielectric layer is sandwiched between the first aluminum carrier and the second aluminum carrier a wafer embedded in the first opening and the second opening and having an active surface; a plurality of electrode pads disposed on the active surface of the wafer; and a line The build-up structure, the line build-up structure is disposed on the upper surface of the first aluminum carrier, the active surface of the wafer and the surface of the electrode pad, wherein the line build-up structure has the conductive structure electrically connected to The electrode

That is to say, in view of the fact that the industry uses copper or yttrium resin (Bismaleimide 20 Triazine Resin) as a carrier plate in which a wafer-bearing carrier structure is embedded, the present invention adopts the carrier material of the "Ilu" carrier structure, and the industry In the production of embedded wafers, the solution often results in severe plate warping. Or "aluminum alloy" as a substrate embedded with a wafer can significantly improve the bending of the plate, and solve the long-standing problem when the sheet-bearing plate structure is solved. • 1303868 曰 In addition, the present invention uses "sau" & "|g alloy" as a carrier material for a carrier board structure in which a wafer is embedded to improve the bending of the board. It can also be matched with different real-life styles (see examples - to four), and the $-step of the board of the carrier plate is improved to make the carrier board flat. 5 The substrate-embedded carrier structure of the present invention, wherein the material of the first aluminum carrier and the second inscription plate may be an alloy of Ming or Ming, preferably a chain. In addition, in the wafer-bearing carrier structure of the present invention, an aluminum oxide layer may be selectively formed on the upper surface or the lower surface of the first aluminum carrier. Similarly, the upper surface or the lower surface of the second aluminum carrier may be selectively formed with an aluminum oxide layer. The alumina/aluminum composite carrier plate formed by surface oxidation treatment can increase the rigidity of the carrier plate, and thus can be used as a core substrate of the embedded chip package to further improve the plate warpage caused by the asymmetric buildup structure. . The wafer-filled panel structure of the present invention, wherein the thickness of the first (a) aluminum plate and the second (four) plate is not particularly limited, depending on the rigidity or the growth required of the carrier plate, and the oxygen (four) The method of controlling the layer thickness is also not particularly limited 'can be achieved by different oxidation methods or conditions. The substrate-embedded carrier structure of the present invention, wherein the thickness of the first aluminum carrier and the second aluminum carrier is not limited, and preferably the surface is formed with a thickness of the first carrier formed by the circuit-added structure. Less than the thickness of the second carrier. Because the structure of the carrier plate embedded with the wafer does not form a line layer structure, it will slightly bend toward the direction of the second board. After forming the line structure, the two aluminum carrier boards will be stressed after the layer is added. Offset, "the structure of the carrier plate embedded with the wafer is more flat. 20:1303868 The carrier of the present invention is embedded in the carrier, wherein the material of the electrode pad is not limited to any metal, preferably one. Aluminum-plated metal or copper metal. The wafer-mounted carrier structure of the present invention, wherein the first aluminum carrier and the wafer, and the second aluminum carrier and the wafer are filled with an adhesive 5 The material or the dielectric layer interposed between the two aluminum carriers is filled in the gap between the wafer and the two aluminum carrier plates by pressing to fix the wafer in the first opening and the second opening. The wafer-embedded carrier structure of the present invention, wherein the wiring enhancement layer structure comprises at least one insulating layer, a wiring layer 10 stacked on the insulating layer, and a plurality of conductive structures, and at least one of the conductive layers The structure is electrically connected to the electrode Moreover, the material of the insulating layer of the line build-up structure is not limited, and preferably at least one selected from the group consisting of ABF (Ajinomoto Build-up Film), bismuth bismuth succinimide/triazine trap (BT, Bismaleimide triazine) ), benzocylobmene (BCB), liquid crystal polymer (Uquid heart two (4)

Polymer), Polyimide; ρι, Phenyiene ether, PTFE, argon, olefin A group consisting of any of the materials such as glass fiber. The circuit layer and the material of the conductive 20 structure are not limited, and are preferably copper, tin, chain, sinter chrome, titanium, copper/cobalt alloy or tin/slant alloy. The carrier board structure of the present invention for embedding a wafer further includes a plurality of solder bumps, and at least the conductive structure of the line build-up structure is connected to the solder bumps. Ί 303868 The load-bearing plate structure of the wafer is immersed in the hair of the month. The thickness of the oxidized layer of the first aluminum carrier and the second inscription plate is not particularly limited, depending on the rigidity or the edge of the carrier. Moreover, the method for controlling the thickness of the oxidized underlayer is not particularly limited and can be achieved by different oxidation methods or conditions. 5. The wafer-bearing carrier structure of the present invention, wherein the thickness of the first aluminum carrier and the second aluminum carrier is not limited, and preferably the surface is formed with a first layer formed by the formation of the 胄 line. The thickness of the carrier plate is less than the thickness of the second inscription carrier. The invention also provides a method for manufacturing a carrier plate for burying a wafer, the steps comprising: (A) providing a first aluminum carrier and a second aluminum carrier; (B) An aluminum carrier plate forms a first opening, and the first aluminum carrier y is formed into a first opening, wherein the position of the second opening corresponds to the position of the first opening; (C) the first-name carrier board and the a dielectric layer is disposed between the second inscription plates; (D) a wafer is embedded in the first opening and the second opening, wherein the active surface of the wafer has a plurality of electrode electrodes, and then pressed The first carrier plate and the second inscription carrier plate combine the two aluminum carrier plates, and simultaneously press the layer of the reference f to fill the first inscription carrier plate, the second inscription carrier plate, and the wafer. a gap between the first opening and the second opening by fixing the wafer; and (E) forming a surface on the upper surface of the first chain carrier, the active surface of the wafer, and the surface of the electric pole a line build-up structure, wherein the line build-up structure has at least an insulating layer, a circuit layer stacked on the insulating layer, and a plurality of conductive junctions 'And at least - the conductive structure is electrically connected to the electrode Sook. The method of the present invention is based on the "Ming" or "In Lu alloy" as a carrier material for embedding a wafer-bearing carrier structure, and the improvement is only in the case of a reverse bend: 1303868, and the industry is embedded in production. There is a problem with the buried silicon. 7 When the board structure is long, this is the manufacturing method of the carrier board in which the wafer is embedded. The material of the cough board and the second board can be Ming or Ming alloy, preferably: ,; Further, the wafer carrier board of the present invention is manufactured by: selectively forming a gasification layer on the upper surface or the lower surface of the first carrier. The same 'the upper surface of the second carrier or the lower table = selectively formed with - oxidized (four). The surface is formed with the first inscription of the oxidation of the first board or the second! The ruthenium plate can be formed by any oxidation method, preferably by anodization. Oxidation/Ming composite carrier plates formed by surface oxidation treatment increase the rigidity of the carrier plate. Therefore, it can be used as the core substrate of the embedded wafer package to further improve the plate warpage caused by asymmetric buildup. The method for manufacturing a wafer-mounted carrier board according to the present invention, wherein the material of the 15 electrode pad is not limited to any metal, and is preferably an aluminum metal or a copper metal. The method for manufacturing a wafer-embedded carrier plate according to the present invention, wherein, in the step of fabricating the line build-up structure, the material of the insulating layer is not limited, and preferably at least one selected from the group consisting of ABF (Ajinomoto Build-up Film) ), Bis 20 bismuth bisphosphonimide / BT (Bismaleimide tdazine), benzocylobutene (BCB), liquid crystal polymer (Liquid Crystal Polymer), poly-branched amine ( Polyimide; PI), P〇ly (phenylene ether), polytetrafluoroethylene (poly-tetrafluoroethylene), aromatic polyamide (Aramide), ring 11 l3〇3868 oxyresin and glass fiber a group consisting of any one of them. The method for manufacturing a wafer-embedded carrier sheet according to the present invention, wherein the material of the electroplated metal layer is not particularly limited in the step of fabricating the wiring build-up structure, and is preferably copper, tin, nickel, chromium. , palladium, titanium, tin/lead or alloys thereof, more preferably copper. /, this test X month ^ for a carrier board to be buried with a chip, the steps including (A) provide a first aluminum carrier and a second aluminum carrier; (B) press a An electric layer is formed between the first aluminum carrier and the second aluminum carrier to form a composite aluminum carrier; (C) forming an opening in the composite aluminum carrier; (D) embedding and fixing a wafer In the opening, wherein the active surface of the wafer has a plurality of electrode pads; and (8) forming a line build-up structure on the upper surface of the first carrier, the active surface of the wafer, and the surface of the electrode pad, wherein The line build-up structure has at least an insulating layer, a circuit layer stacked on the insulating layer 15 20 , and a plurality of conductive structures, and at least the conductive structure is connected to the electrode. The method of the present invention can improve the bending condition of the board by using "shao" or "aluminum alloy" as the carrier material of the carrier plate structure of the embedded cymbal, and the industry is capable of producing the embedded embedded wafer. There is a long-standing problem when carrying the structure of the board. The manufacturing method of the carrier board in which the wafer is embedded, wherein the step (D) is to insert a solid wafer into the opening, and then fill in the day of the wafer and the opening. The gap between # people to fix the wafer. 12.1303868 The method for manufacturing a wafer-embedded carrier plate according to the present invention, wherein the material of the first aluminum carrier and the second aluminum carrier is aluminum or aluminum alloy, preferably aluminum alloy. Further, in the method of manufacturing a wafer-embedded carrier plate of the present invention, wherein the upper surface or the lower surface of the first-type carrier is selectively formed with an aluminum oxide layer. Similarly, an aluminum oxide layer may be selectively formed on the upper surface or the lower surface of the second aluminum carrier. The first aluminum carrier or the second aluminum carrier on which the surface is formed with aluminum oxide can be formed by any oxidation, and the school is formed by anodization. The oxygen-formed aluminum/aluminum composite carrier plate formed by surface oxidation treatment can increase the rigidity of the carrier plate, and therefore can be further improved as a core substrate for the 10-input wafer package due to asymmetric buildup. The board is bent. The method for manufacturing a wafer-embedded carrier plate according to the present invention, wherein the material of the electrode is not limited to any metal, and is preferably an aluminum metal or a copper metal. The method for manufacturing a wafer-embedded carrier plate according to the present invention, wherein, in the step of fabricating the line build-up structure, the material of the insulating layer is not limited, and preferably at least one selected from the group consisting of ABF (Aj inomoto Build- Up Film), Shuangchuan Beiding, Bismaleimide triazine, benzocylobutene (BCB), Liquid Crystal Polymer (Liquid • 20 Crystal Polymer), Poly Among the materials such as Polyimide (PI), P〇ly (phenylene ether), Poly (tetra-fluoroethylene), Aramide, Epoxy and Glass Fiber Any group of groups. 13 l3〇3868 A method of manufacturing a carrier board embedded with a wafer, wherein in the step of adding a layer structure of the special line, the material of the metal layer of the electric clock is not re-integrated. It is steel, tin, nickel, chromium, handle, titanium, tin/wound or alloy thereof, and more preferably, steel. [Embodiment] Embodiment 1 FIG. 2a to FIG. 2e are schematic cross-sectional views showing a method of fabricating a wafer-incorporated plate structure of the present embodiment. 10, as shown in Fig. 2a, a first aluminum carrier 1 and a second aluminum carrier 11 are first provided. The first aluminum carrier 10 and the second aluminum carrier 11 are each formed with a first opening 12 and a second opening 13, and the position of the second opening also corresponds to the position of the first opening. Then, as shown in FIG. 2b, a dielectric layer 14 is then provided between the first 15 aluminum carrier 10 and the second aluminum carrier 11, and then as shown in FIG. 2c, one is completed. The wafer integrated circuit process and the die-cut wafer 21 are embedded in the first opening 12 and the first opening 13 and then pressed. The main surface 22 of the wafer 21 has a plurality of electrode pads 23, and the material of the electrode pads 23 is copper. During the pressing process, the dielectric layer 14 is overflowed between the first aluminum carrier 20 W and the second aluminum carrier 11 to fix the wafer 21 to the first opening 12 and In the first opening 13 of the younger one, the first carrier plate iq and the second aluminum carrier 11 are fixed at the same time. The dielectric layer 14 is finally sandwiched between the first inscription board, the second inscription board 11, and the wafer 21, and its structure is as shown in Fig. 2c. In this embodiment, the inactive surface 24 of the wafer 21 is exposed to facilitate heat dissipation from the wafer. (£) 14 Ϊ 303868 - Further, in the present embodiment, the thickness (D1) of the first aluminum carrier 10 is smaller than the thickness (D2) of the second aluminum carrier 11. Therefore, the carrier board structure in which the wafer is embedded has not yet formed the line build-up structure 31 (as shown in Fig. 2d), and the carrier board is slightly bent downward. After θ 5 70 is formed as described above, as shown in Fig. 2e, a line build-up structure 31 is formed on the upper surface 15 of the first aluminum carrier 10, the active surface 22 of the wafer 21, and the surface of the electrode pad 23. The method for forming the line build-up structure 31 is as shown in FIG. 3, and an insulating layer 32 is formed on the lower surface 15 of the second aluminum carrier 11, the active surface 22 of the wafer 21, and the surface of the electrode pad 233. The material of 32 is 10 ABF (Ajinomoto Build-up Film) material, and a plurality of insulating layer openings 33 are formed by laser drilling on the insulating layer 32, wherein at least one insulating layer opening corresponds to the position of the electrode pad 23 of the wafer 21. However, when using the technology of laser drilling, a de-smear operation is required to remove the slag remaining in the opening of the dielectric layer due to the drilling. Then, a patterned 15 resist layer 34 is formed on the insulating layer 32. The patterned resist layer 34 forms a plurality of resistive openings 35 in an exposure and development manner, and at least one resist opening 35 corresponds to the age of the wafer 21. The position of the pole pad 23. Next, a plurality of electroplated metal layers 36 are plated on the plurality of barrier openings 35, and the resist layer 34 is removed. The line build-up structure 31 can be laminated to form a multi-layer structure using a build-up technique according to the number of layers required. The line build-up structure 31 shown in FIG. 20 is formed by a build-up technique using a layer-up layer to form a multi-layered structure, wherein the electron-mirror metal layer 36 includes a wiring layer 37 and an electrode pad 23 with the wafer 21. Connected conductive structure 38. Finally, a patterned solder resist layer 39 is formed on the surface of the build-up structure 31, and a plurality of solder bumps are formed on the patterned solder resist layer 39 to expose the electrical connection pads 15.133868 of the build-up structure 3丨. Block 39, that is, the carrier board in which the wafer is embedded in this embodiment is completed. 3 The carrier-embedded board structure embedded in the embodiment is a single-sided build-up layer. Therefore, the structure of the carrier board in which the wafer is embedded has not yet formed the line build-up structure h 5 (as shown in FIG. 2e). Bending, and after forming the line build-up structure 3 i (as shown in Figure 2e), the bend will be pulled back to form a flat carrier-embedded board structure. φ Embodiment 2 10 Please refer to the figure to 牝, which is a schematic cross-sectional view showing the structure of the carrier-embedded board embedded with the wafer of this embodiment. As shown in Fig. 4a, a first aluminum carrier 4 and a second aluminum carrier 41 are first provided. A dielectric layer 42 is further disposed between the first aluminum carrier 4 and the second aluminum carrier 41 and is pressed. Thereby, the dielectric layer 42 fixes the first aluminum carrier 15 and the second inscription plate 41 to form a composite carrier 43. Accordingly, as shown in Fig. 4b, a through opening 44 is formed in the composite carrier 43. Then, a wafer 21 which has been subjected to the wafer integrated circuit process and is cut and formed is embedded in the opening 44 of the composite carrier 43. The wafer 21 has a plurality of electrode pads 23 on the active surface 22 of the wafer 22, the material of which is copper. Next, the adhesive 25 is filled into the gap between the composite carrier 43 and the wafer 21, and the wafer 21 is fixed in the opening 払 of the composite carrier 43 as shown in Fig. 4c. The adhesive material 25 may be epoxy vinegar. In the present embodiment, the inactive surface 24 of the wafer 21 is exposed to facilitate heat dissipation of the wafer. Further, in the present embodiment, the thickness (D1) of the first aluminum carrier 40 is smaller than the thickness (D2) of the second aluminum carrier 41. Therefore, before the carrier build-up board embedded with the wafer 1613003868 has not formed the line build-up structure 3丨 (as shown in Fig. 4c), the carrier board will be slightly bent downward. After the stomach 70 has been subjected to the above steps, as shown in Fig. 4d, a line 5 buildup structure 31 is formed on the upper surface 45 of the first aluminum carrier 4, the active surface 22 of the wafer 21, and the surface of the electrode pad 23. The line build-up structure 31 includes a wiring layer 37 and a conductive structure 38 connected to the electrode pads 23 of the wafer 2!, which are formed in the same manner as the implementation Z. Finally, a patterned solder resist layer '39' is formed on the surface of the build-up structure 31, and the patterned solder resist layer 39 is exposed to electrically connect the build-up structure 31. A plurality of solder bumps are formed at the pad. That is, the carrier board in which 10 wafers are embedded in this embodiment is completed. The carrier-embedded board structure embedded with the wafer in this embodiment is a single-sided build-up layer. Therefore, the load-bearing board structure in which the wafer is embedded has not yet formed the line build-up structure 31. Previously (as shown in FIG. 4c), the curve is slightly bent downward. Awkward, and in the formation of the line build-up structure 31. W will be plated back to form a flat wafer-bearing t-structure 15 The third embodiment of the embodiment of the embedded chip-bearing board manufacturing method is very similar to the embodiment - Except for the upper surface of the second and second inscription plates, the surface of the surface is already oxidized, and the other steps are the same as those of the first embodiment of the .20. Referring to Figures 5a to 5e, there are shown schematic cross-sectional views of the method for fabricating a wafer-mounted carrier sheet of the present embodiment. As shown in Fig. 5a, first, a first inscription carrier 5'' and a second (four) board 51 are provided. The first aluminum carrier 5〇 and the second aluminum carrier 51 are placed in the electrolysis cell 25 to perform an oxidation reaction, so that the carrier plate 5() and the second (four) plate are 17 • 1303868 = surface and bottom The surface is oxidized to form oxidation (IV)%. 4 The two layers of oxides are naturally sandwiched with _ layer 57. In the present embodiment, the first-stage carrier 50 and a fourth carrier 51 are placed in an electrolytic cell to perform an anodizing reaction, and the thickness of the oxide layer 56 is controlled by adjusting the anodization time. 1 The sergeant Sl5b shows that the first opening 52 and the second opening 51 are formed with the - opening 52 and the opening: and the position of the second opening corresponds to the position of the first opening. . Then, a dielectric layer 54 is disposed between the first plate 5 () and the first: |g carrier 51.

10 15 , followed by the figure field. Then, the wafer 21 which has been subjected to the sub-cutting of the wafer integrated circuit is embedded in the first opening 52 and the second opening 再 to be pressed together. Wherein the active surface 22 of the wafer 21 has a plurality of electrodes 23'. The material of the electrode pads is copper. During the pressing process, the dielectric layer 54 will overflow between the first aluminum carrier 50 and the second aluminum carrier 51 to fix the wafer 21 to the first opening 52 and the second. In the opening 53, the first-plate 5A and the second (four) plate 51 are simultaneously fixed. The dielectric layer is sandwiched between the first aluminum carrier 5, the second aluminum carrier, and the wafer 21, as shown in FIG. 5d. In this embodiment, The exposure of the non-active surface 24 of the wafer 2 facilitates heat dissipation of the wafer. In the present embodiment, the thickness (D1) of the U carrier 50 is equal to the thickness _ of the second aluminum carrier. .20 After the above steps are completed, as shown in FIG. 5e, on the upper surface 55 of the first aluminum carrier 50, the active surface 22 of the wafer 21 and the surface of the electrode 23 are formed with a line build-up structure 31, including the circuit layer. The conductive structure 38 connected to the electrode pad 23 of the wafer 21 is formed in the same manner as in the first embodiment. Finally, a patterned solder resist layer 39 is formed on the surface of the 6-thickness layer structure 31, and the patterned anti-solder 18 1303868

Hr reveals a plurality of 蝉 A 3 9 at the electrical connection pads of the build-up structure 31, that is, the carrier plate embedded with the wafer in the cost embodiment. Since the first and second carrier plates 5G and the second inscription plate 51 form an aluminum oxide layer 56 (aluminum oxide is a ceramic material) by oxidation, the first aluminum carrier 5 plate 5曰0 and the second inscription carrier plate can be added. 51 rigidity. Therefore, although the carrier board structure of the embodiment to be buried is a single-sided build-up layer, it is still possible to form a flat load-bearing board structure in which the wafer is buried. • Embodiment 4 10 The manufacturing method of the embedded wafer 4 carrier plate is very similar to that of the first embodiment except that the upper surface and the lower surface of the first and second carrier plates have been oxidized. The remaining steps are substantially the same as in the second embodiment except that each of the formations is formed by oxidation (iv). Please refer to FIG. 6a to FIG. 6d, which are schematic cross-sectional views showing a method for fabricating a carrier-embedded 15-plate structure of the present embodiment. As shown in Fig. 6a, a first aluminum carrier 6 and a second aluminum carrier 61 are first provided. The first aluminum carrier 60 and the second aluminum carrier 61 are placed in an electrolytic cell to perform an oxidation reaction, so that the first aluminum carrier 60 and the second aluminum carrier 61 are oxidized on the upper surface and the lower surface. An aluminum oxide layer 66 is formed, and an aluminum layer 67 is naturally interposed between the two layers of alumina "20. In this embodiment, the first aluminum carrier plate 60 and a second aluminum carrier plate 61 are placed in an electrolytic cell. Anodizing is performed, and the thickness of the aluminum oxide layer 66 is controlled by adjusting the anodization time. Next, a dielectric layer 62 is provided between the first aluminum carrier 6 and the second aluminum carrier 61. And the pressing layer is applied. Thereby, the dielectric layer 62 fixes the first inscription carrier 60 and the second carrier board 61 to form a composite carrier 63. 19 25 1303868 Then, as shown in FIG. 6b Then, a through opening 64 is formed on the composite carrier, and then a wafer immersed in the wafer integrated circuit board 63 is embedded in the opening σ64 of the composite carrier 63. The crystal moon (1) is in

10 The active surface 22 of the wafer 22 has a plurality of electrical (four) 23, and the material of the electrode is copper. Then, the adhesive material 25 is filled in the gap between the composite carrier 63 and the wafer η, so that the wafer is set in the happyness of the composite carrier 63, as shown in Fig. 6c. The adhesive material 25 may be epoxy vinegar. In the present embodiment, the inactive surface 24 of the wafer is exposed to the heat dissipation of the material wafer. In the present embodiment, the thickness (D1) of the 'fourth plate 60' is equal to the thickness of the first carrier plate 61. After the above steps are completed, as shown in FIG. 6d, the surface 65 of the first inscription (4), the active surface of the wafer 21 22. Forming a line build-up structure 31' with the electrode pad surface. The conductive structure 38 including the circuit layer 37 and the electrode 塾^ of the crystal (10) is formed in the same manner as in the first embodiment. Finally, a patterned solder resist layer 39 is formed on the surface of the build-up structure 31, and a plurality of solder bumps are formed on the patterned solder resist layer 39 to expose the electrical connection of the build-up structure 31. 39 ^ That is, the carrier plate embedded with the wafer of this embodiment is completed. Since the first-loading plate 60 and the second inscription plate 61 are formed by oxidation in the form of an oxidized inscription layer 66 (oxidized for the ceramic material), the first plate can be added to the 20th plate 6曰0 and the second inscription. The rigidity of the carrier plate 61. Therefore, although the carrier structure of the buried 2 wafer of the present embodiment is a single-sided build-up layer, a flat carrier-embedded board structure can be formed. The invention is not limited to the above-described embodiments, but is intended to be illustrative only, and the scope of the claims is based on the above-mentioned embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic view of a conventional embedded embedded wafer surface; a cross section of an electrical connection structure of a carrier plate

2a to 2e are schematic cross-sectional views showing a method of fabricating a carrier board in which a wafer is embedded after a preferred embodiment of the present invention; and Figs. 3a to 3c are schematic cross-sectional views showing a method of fabricating a line build-up structure according to a preferred embodiment of the present invention; 4a to 4d are schematic cross-sectional views showing a manufacturing method of embedding in another preferred embodiment of the present invention;

5a to 5e are schematic cross-sectional views showing a manufacturing method of embedding a wafer according to still another preferred embodiment of the present invention, and Figs. 6a to 6d are schematic cross-sectional views showing a manufacturing method of embedding a wafer according to still another preferred embodiment of the present invention. . Carrier plate of carrier board • 2〇 [Main component symbol description] Second aluminum carrier board 11, 41, 51, 61 Second opening 13, 53 Upper surface 15, 45, 55, 65 First aluminum carrier board 10, 40 , 50, 60 first opening 12, 52 dielectric layer 14, 42, 54, 62

21 : 1303868

Wafer 21 Electrode pad 23 Adhesive material 25 Line build-up structure 3 1 Insulation layer opening 33 Resistive layer opening 35 Circuit layer 37 Solder bump 39 Opening 44, 64 Aluminum layer 57, 67 Wafer 102 Protective layer 104 Line build-up structure 106 Active surface 22 Inactive surface 24 Insulation layer 32 Patterned resist layer 34 Electroplated metal layer 36 Conductive structure 38 Composite carrier plate 43, 63 Alumina layer 56, 66 Carrier plate 101 Electrode pad 103 Metal layer 105 Patterned solder resist layer 39'

twenty two

Claims (1)

*1303868 X. Patent application scope: 1. A carrier board structure in which a wafer is embedded, comprising: 〆 a first inscription carrier having a first opening; a second inscription carrier having a second opening, and a position of the first opening 5 corresponding to the position of the first opening; a dielectric layer sandwiched between the first aluminum carrier and the second aluminum carrier; a wafer embedded in the wafer The first opening and the second opening are in view and the wafer has an active surface; 10 a plurality of electrodes 塾 are disposed on the active surface of the wafer; and a line build-up structure, the line is added The structure is disposed on the upper surface of the first aluminum carrier, the active surface of the wafer, and the surface of the electrode pad, wherein the "Hay line build-up structure has a plurality of conductive structures, and at least one of the conductive structures Sexually connected to the electrode pad. 2. The substrate-embedded carrier plate according to claim 1, wherein the material of the first aluminum carrier and the second aluminum carrier is aluminum or aluminum alloy. 20 fiber 3_ The carrier plate embedded with the wafer as described in claim 1 of the patent scope: the thickness of the first-slide carrier is less than the thickness of the second inscription plate 23: 1303868 oxidized inscription layer And the _ 4 .. oxidation layer. Brother-Ming board is formed on the upper surface and the lower surface - Structure 5:: Zhongshen II special interest range item 1 _ 5 10 15 ', w di an aluminum carrier board and the wafer, and the Chu A paste between the carrier plate and the wafer is filled with an adhesive material to fix the wafer in the opening of the first opening and the second opening. The invention has embedded a crystal structure, wherein a dielectric layer is filled between the first carrier and the wafer, and between the carrier and the wafer. The gap is formed by pressing the sheet of dielectric material and the two mounting plates to fix the wafer in the first opening and the second opening. 7. The wafer-embedded carrier structure as described in claim 1, wherein the circuit build-up structure comprises at least an insulating layer, a wiring layer overlying the insulating layer, and a plurality of The conductive structure, 至少 at least one of the conductive structures is electrically connected to the electrode pad. 8. A method of manufacturing a carrier board embedded with a wafer, the step package thereof (Α) providing a first aluminum carrier and a second aluminum carrier; • 20 W forming a first opening in the first carrier, and forming a second opening in the second mounting carrier a position of the second opening corresponding to the position of the first opening; (C) a dielectric layer is disposed between the first carrier plate and the second name carrier; 24 10 15 • 20 1303868 (D) embedding a wafer in the first opening and the second opening, wherein the crystal active surface has a plurality of electrode pads, and then pressing the first aluminum carrier 〃 uhai first aluminum carrier Bonding the two aluminum carrier plates while pressing the dielectric layer to fill the gap between the first (four) plate, the second (four) plate, and the (four) of the wafer, thereby fixing the wafer to the first opening and the second opening a towel, and a coin (E) forming a line build-up structure on the upper surface of the first aluminum carrier, the active surface of the wafer, and the surface of the pad, wherein the line build-up layer has at least An insulating layer, a stack of circuit layers disposed on the insulating layer, and a plurality of conductive structures, and at least - the conductive structure is electrically connected to the electrode. The method for manufacturing a wafer-embedded carrier plate according to claim 8, wherein in the step (4), the upper surface and the lower surface of the first aluminum carrier are each formed with an oxidized layer, and the An aluminum oxide layer is formed on each of the lower surface of the upper surface of the carrier. 2. The method for embedding a wafer-bearing carrier 1 ° according to claim 9 of the claim, wherein the oxidized layer is formed by anodization. 11· A method for manufacturing a carrier plate embedded with a wafer The steps include: (A) providing a first aluminum carrier and a second aluminum carrier; (B) pressing a dielectric layer between the first aluminum carrier and the second aluminum carrier, and Forming a composite aluminum carrier; (C) forming an opening in the composite aluminum carrier; (D) embedding and fixing a wafer in the opening, wherein the active surface of the wafer has a plurality of electrode pads; and 25: 1303868 (E) forming a line build-up structure on the upper surface of the first aluminum carrier, the active surface of the wafer, and the surface of the electrode pad, wherein the circuit build-up structure has at least one insulating layer and a stack a circuit layer on the insulating layer, and a plurality of conductive structures, and at least one of the conductive structures is electrically connected to the pad of the electrode 5. I2. The carrier embedded with the chip according to the scope of the patent application, Manufacturing method in which step (D) embeds a wafer in the opening After the mouth, a gap between the wafer and the opening may be filled in to fill the wafer, thereby fixing the wafer. The method of preparing the wafer-embedded carrier plate described in claim 11 of the patent application, Wherein, in the step (Α), the first aluminum carrier plate has an oxidized insole layer formed on the upper surface and the lower surface, and the upper surface of the second inscription plate and the second surface are each formed with an oxide layer. 15 • The method for manufacturing a wafer-embedded panel according to claim 13 of the patent application, in the Fu Shi Qiu, the alumina layer is formed by anodization. 26