TWI302706B - Circuit and method for reducing power usage in a content addressable memory - Google Patents

Description

(i) 1302706, the description of the invention (there is a technical field, prior art, content, embodiments, and drawings of the invention). The present invention generally relates to addressable content memory (CAM). The field, in particular, relates to circuits and methods for reducing power usage during a search operation in a CAM. Prior Art CAM is a memory device in which access to and modification of data is based on the location of the stored bedding rather than the location of the stored data. Typically, a typical CAM search job involves receiving a search data block and comparing the search data block with all items in the CAM to determine if there is a single match between the search data block and all items in the CAM. Multiple matches or no matches. All of the storage locations in the CAM column are connected to a harness that indicates a comparison of the mismatched results of the stored data block with the search data block. All match lines indicating the match condition are typically processed by a priority encoder (PE) to determine the highest priority match address provided as the output of the CAM. Within the CAM, each data block and match line combination has a unique n-bit address. Therefore, up to 2N pieces of wiring can be activated for any search cycle. A priority sequencer is coupled to the match lines and produces an N-bit address corresponding to the most south-first order enable match line. The N-bit address is then used, for example, as an indicator in the Internet Protocol (IP) routing table query, compression and decompression implemented in a microprocessor system or in a fully combined cache memory implementation. Because Ternary CAM has the ability to store logic, 1", logic "0&", and "arbitrary value", it is widely used in network applications. The benefits of CAMS for a wider data width increase. On the market 1302706 (2) Description of the invention Continued page The CAM with a data width (marked by )) of 72 bits, 144 bits and the nearest 288 bits can usually be purchased. As the data blocks are incremented, the power consumption or current consumption during the search for jobs in the CAM is becoming more and more important. The reasons are explained below. In the search job, the data is provided to the CAM to compare the stored data. The CAM unit is typically designed such that the match between the search data and the stored data provides a non-conductive path that does not match to provide a conductive path. A column of CAM consists of cells coupled in parallel between the match line (ML) and the tail line (TL). Each individual match line (ML) is connected to one unit (where Μ is the number of bits, or usually the data width). In general, in a search operation, the meta-search data is provided to a search data path consisting of a search line coupled to the corresponding CAM unit. Then, in each unit that is typically implemented as a mutually exclusive or (XOR) operation comparison block, all the queues of the CAM compare the search data with the stored data at the same time, and provide the comparison result to each column of the CAM. Each match line. Next, the match line on the match line is typically sensed, amplified, and latched to provide a logical level result for the search job. There are two main sources during the search operation in the CAM that are substantially power consumption: the power consumed by the match lines and the power consumed by the search lines. By convention, all match lines are precharged to a logical 'FT (high level) state (matching condition), and then search data comparison is allowed to cause the match lines to fall to a logic (low level) state (mismatch condition) . In most CAM applications, the frequency of "miss" is higher than 1302706. (3) The frequency of occurrence of "hit". When the match line is precharged to the logic W彳 high level) and the match line is discharged to the logic f L ' (low level) for mismatch, due to the current consumption associated with all match lines for each search operation charging and discharging It is easy to cause high power consumption. In addition, because the number of cells connected to each match line is increased in a wide block CAM application, the capacitance of the match line will increase, resulting in an increase in the current required to charge and discharge the match. Various solutions have been proposed for reducing power consumption during a search operation, for example, segmenting a match line into a plurality of segments, and continuously starting the segments based on matching or mismatching results of the previous segment. A segmented match line architecture is disclosed in U.S. Patent No. 6,243,280 (Wong et al.), which divisions the CAM column into a plurality of segments. A first segment of the plurality of match lines is precharged for each match line, and a search job is performed in the first segment. In the event that the first segment matches, the first match line segment is selectively pre-charged and the search job proceeds to the second segment. If the second segment is matched, the third segment is pre-charged and the search job continues in a similar manner until all segments of a match line have been searched. Therefore, precharging a subsequent segment will only occur if the previous segment is matched. If all segments match, each segment is selectively precharged to logic Η' (high level), however a large amount of current is still required. In addition, there is a significant delay in the seek time since it is necessary to wait for the selective precharge of the segment to occur before proceeding with the actual comparison in the segmentation. In US Patent No. 6,191,970 (Pereira), a match line is divided into multiples 1302706 ____ (4) Ming: Continued page _ —·~~ segments, before starting the search job, 'all segments first'顇 Charge to logic, Η, (high level) state. In addition, each CAM cell has a / correlation discharge circuit for selectively discharging its corresponding match line segment in response to a disable signal from a previous match line segment. Therefore, only one segment will be mismatched, and all subsequent segments will be precharged to logic, H, (high level), and a segment will be discharged. As a result, a segment's mismatch condition propagates along the remaining segments of the column without discharging all other segments along the column. While this approach slows the delay caused by selective pre-charging segments, the potential problem of high current consumption still exists because all memory must be pre-charged to a logic, H, (high level) state. In addition, the match detection for each segment must be synchronized to a clock signal, providing a clock from pre-charging of the match line to hit. As a result, some internal time earning must be generated, or the system clock must be used to increase system wait time. Finally, to prevent discharge prior to enabling segmentation, a tandem device is added to each CAM cell, thereby increasing wafer area and reducing overall operating speed. In the 1997 "Use of Selective Precharge for Low Power on the Match Lines of Content Addressable Memories" by Zukowski et al., a method for pre-charging small segments of the entire match line is published and used in execution. Some of the first segment segments are compared, and only when the first segment segment matches, the other segments of the match line are pre-charged, and finally the search is performed. The article also suggests 'theoretically should extend the selective pre-charging technique to cover more than one level, but during a single-level selective pre-charging, the additional signal 1302706 _ rs, I invention continuation (overhead), extra The clock phase and additional buffering do not cause any significant extra gain. This approach does not consider the possibility of multiple line segments being continuously operated, but considers independent clock cycles, which can be fast enough to implement the necessary circuits. In addition, Zukowski et al., published practices still rely on pre-charging to a logical f 3 ΗΓ (high level) state, while still consuming a large amount of current, as described above. Therefore, there is a need for a CAM that consumes less power during a search operation than conventional search techniques. φ SUMMARY OF THE INVENTION According to the present invention, there is provided a method for selectively enabling at least one match line segment of a plurality of 'match line segments' in a column of an addressable content memory (CAM) array during a search operation, Each of the match line segments has a plurality of CAM units coupled thereto, the method comprising the steps of: (a) setting the match line segments to a first search result condition; (b) targeting one Second search result status, evaluate a first match line segment;

(c) selectively enabling a second match line segment responsive to the second search result condition in the first match line segment such that the second search result condition can be detected. According to another aspect of the present invention, the present invention provides an addressable content memory (CAM) comprising a plurality of columns, each column comprising: (a) a plurality of matching line points having a plurality of CAM units coupled thereto (b) - a circuit for precharging the matching line segments to a first search - 10 Description of the Invention Page 1302706 (6) Result status (mismatch); a sensing circuit for detecting a second search result condition (hit); (ii) a circuit for enabling a pre-charging path in a subsequent segment to detect the second search result status (matching) ). Embodiments In the following description, like reference numerals represent like structures in the drawings. Referring now to Figure 1a, there is shown a simplified block diagram of a typical CAM 100 for use in reference to the main components discussed herein. It will be apparent to those skilled in the art that CAM devices include many other blocks that are not directly related to the present invention to various other functions and are therefore omitted based on simplicity. The CAM 100 includes a CAM array 102 of CAM cells 104 arranged in a matrix, and wherein the cells in each column are coupled to a common match line (ML). In the case of Ternary CAM, each unit stores one of three states: logic "Γ" (or logical fIT (high level), logic "〇, ' (or logic, l, (low level) and "any value, (or called 'X,)), used to actually store two bits of data. In general, a column of data is stored in each column of the CAM. The address of the address is 106 for any column in the remote CAM array 102 to allow data to be written or read from the selected column. The most common case is to write or load data into the CAM. The bidirectional data access circuit 114 transfers data between the array 1 and the CAM chip data pins (not shown) for access by an external processor (not shown). Adjacent to the CAM array 1〇2 is a match line sensing private path, 'and block 110, the match line sensing circuit block 11 〇 contains N pins 1302706 ι_ m I invention description of the renewed wiring sensing circuit, and used in the search An N-bit result 112 is output during the job and comparison jobs. The match line sense circuit block outputs for all columns are processed by a priority sequence encoder 114 to produce the highest priority match address (i.e., the lowest physical address) corresponding to the location of the matched block. Multiple match detection circuit 116 is also coupled to receive the output from match line sense circuit 110, and then generate a two bit output Q 0, Q 1 for indicating a match, only one match or multiple matches.

Referring now to Figure lb, a small subset (i and i + Ι) of the ternary CAiM cell array is shown. As shown, each column (i, i + Ι) of cells in the array together with each cell 104 coupled to a column i of a match line MLi constitutes a data block. Each ternary unit 104 (j, j + Ι...) contains two storage element units A, B for storing two bits and for comparing the stored bits

The transistor 120 is compared to the exclusive or (XOR) of the search bit. The storage component unit A and the unit B may belong to any one of a static random access memory (SRAM) unit or a dynamic random access memory (DRAM) unit, both of which are well-known techniques (such as familiar with this). As known to the skilled artisan, a 6-Chip SRAM cell implementation explicitly requires an additional pair of complementary bit lines). The XOR transistor 126 is an n-channel type device for matching the line ML if a mismatch occurs, and the level is lowered to ground. The general architecture of CAM arrays has been provided to date as a background for expressing the specific problems addressed by the present invention. In addition, in the following description, specific embodiments of the present invention are discussed in the context of CAM architecture 100 for simplicity only. It will be appreciated that the specific embodiments of the present invention are equally applicable to other content configurations having other configurations and/or employing any suitable CAM unit -12 - 1302706 (8). In addition, the logic level is assigned to various signals as desired in the following description. Therefore, the polarity of the associated device can be reversed as needed to be modified. For example, the implementation of the lip-type x〇R circuit HQ as shown in (c). Referring now to Figure 2(a), Figure 1 shows a schematic diagram of a segmented match line in a selected column of a CAM in accordance with an embodiment of the present invention. Based on Qing Chu, the bit line, word line, search line and related circuits are not depicted in the figure. The n-bit (eg, 72-bit) match line is split into a plurality of match line segments MLS〇, MLS,,..., MLSn, eg, 'each segment has a length of 18 bits (hence, in the first term) In a specific embodiment, there are 4 match line segments, each match line segment having a length of 18 bits, forming a block of 72 bits in width). Each segment of the eight segments MLSQ to MLSn is respectively coupled to one end of each of the sensing deer to enlarge the crying 2 1 0. In the embodiment shown in Figure 2(a), the inductive amplification cry 2 1 〇 includes a CMOS inversion sense amplifier. More complex inductive amplifiers can be used to provide a low threshold sensing capability, thus providing operational speed. The output of each CMOS inversion sense amplifier 210 is coupled to a respective match line circuit 212' wherein the match line circuit 212 is comprised of a controlled inverter 2 14 connected in series with a current source 2 16 . The controlled inverter 214 of the match line circuit is composed of a P-channel type device and an n-channel type device coupled in series, and the P-channel type device and the N-channel type device are used along the device for enabling the n-channel type device 2 The additional matching lines of 1 8 are coupled in series. Each of the gates for enabling the additional match line of the n-channel type device 2 1 8 is controlled by a corresponding match line segment enable signal MATLO1, MATALn, where n is the number of bit line segments in a column . The match line segment enable signal MATLO is continuously -13 - 1302706 (9) I invented to start and revoke, as described in further detail below. As shown in Fig. 2(a), the first segment MLS0 is coupled to the match line head terminal circuit 22 (also composed of a controlled inverter 224 connected in series to a current source 216). The inverter 224 is also controlled by an enabled N-channel type device 222, which is then controlled by an enable signal MATLOO. A general enable signal (eg, MLEN\) can be used to enable all segments simultaneously with the first segment, and all segments are maintained in the boot time slot until the entire block has been searched 'but this practice consumes The power is higher than the preferred embodiment shown in FIG. 2. Each of the segments MLSG to MLSn may have an equal number of bit cells 104, however, the number of bit cells may be selected in accordance with the statistical power division principle. In the CAM shown in Figure 2, the cell is a P-channel type SRAM architecture CAM cell as shown in Figure ic, in which case the match line level is reduced to VDD (positive supply voltage) if a mismatch occurs. In the first segment ML SQ, the matching line header circuit 2 2 0 pre-charges the sub-section to a non-small state. In the case of the match line head circuit 220, both the channel type and the channel type transistor of the controlled inverter 224 are controlled by the match line enable signal MLEN\ (the signal generated at the start of the search operation). Next, the operation of the segmented match line shown in Fig. 2(a) will be explained. Before the start of the search job, all match line segments MLSq, MLS !, . . . , MLSn in a match line are precharged to a mismatched state, ie, in a specific embodiment, through each match line circuit The P-channel split-twist crystal in 2 12 is precharged to logic, H, (high level). When the MLEN\ signal is asserted as logic fL, (low level), the match line head circuit 220 will begin pre-charging, thereby turning on the reverse of the splicing head-end circuit 220 at the end of the sigma-14-1302706 (10) A P-channel type device in the rotator 224. As a result, the first match line segments the MLS. Pre-charged to a logic high level), and the first segment provides the logic f H ' (high level) signal to the first inverter 2 1 0 and the first matching line circuit 2 i 2 (basically As a repeater and propagate logic (high level) to MLS,). The second segment MLS!'s inverter and the second match line circuit perform the same function, and so on, until the entire harness is precharged to logic 'ΡΓ (high level), i.e., mismatched condition. At the beginning of the search job, the MATLO signal is maintained at logic (low level) and the search data is supplied to the search line (not shown). By comparing the MATLOO signal of the match line segment MLSQ to a logical low level, the comparison search data and the stored data are initiated, thereby enabling the current source in the match line head circuit 220. The search result of the first match line segment will produce a mismatch or match. In the first case, a mismatch in the first segment causes the MLSq segment to be precharged to a mismatched state, ie, will remain at the logic Mf (high level) because of the match line segmentation and precharge voltage There will be at least one cell between VDD providing a conductive path. The signal path between the match line segment and VDD produces a current greater than the current supplied by the current source 217 of the match line head circuit 220, thus overriding the current current source. As a result, the input signal input to the inverter 210 of the first match line circuit is logic f IT (high level), and the output of the match line circuit output to the subsequent segment is maintained at a logic high level, thereby stopping Search for subsequent segments. In the second case, if a match is detected in the first segment MLSQ, the matching line head circuit current source will drop the level of the segment to logic -15 - 1302706 (11) f L, (low level) to form a descending path to ground. When the level reaches the switching threshold of the inverter inductive amplifier 2 10 of the first segment, the inverter sense amplifier switches its output from logic Τ ' (low level) to logic 'ΙΓ (high level) Then, the Ρ channel type pull-up transistor of the match line circuit 212 is forcibly turned off, and the level down path of the next stage MLSi is enabled (assuming that the match line segment enable signal MATL01 of the next stage is enabled). As described above, all MATLO signals can be simultaneously enabled to logic (high level), or sequentially, as described in further detail below. As a result, each match line segment uses the search results from the previous segment to determine whether to continue searching along the match line. This process is repeated from MLSQ to MLSn along the full length match line, after which the final match of a match line is provided to the priority encoder for further processing. Therefore, in general, T will use the search result of the previous match line segment to enable the search for the next match line segment. If there is a mismatch in a segment, the next and all remaining segments will continue to be precharged to a mismatch condition. If there is a match in a segment, the match is propagated to the next segment, and then a match for a subsequent segment is searched, and the search continues with the next segment until the last segment has been searched. In the foregoing general description, the start and revocation of the match line enable signal MATLO is continuously performed. Each enable signal can be activated to substantially match the search results of the previous segment, and the enable signal is revoked once the search result is obtained. Alternatively, all segment enable signals can be initiated at the same time, and the segment enable signal is sequentially cancelled once the previous segment has been searched. Reference will be made to Figure 2(b), which shows the production according to the method as described above - 16 - 1302706 1 J. May May Continue to buy ~- —— as the ribbon factory power transmission with the matching The circuit displays the circuit for enabling the signal for each segment. Again, the typical match line Mu is segmented into n segments of tf of Figure 2(a), and the current source 216 is implemented using a gate connected to the VDC^々N-channel type of power 230. Each segment has an associated match line private path 212 (shown in Figure 2(a)) and a "sticky" latch that includes a reverse sense amplifier 21〇 And an N-channel pull-down crystal 232 for preserving the matching condition, that is, when the matching line segment is placed to ground. Even after the matching line segmentation number MATLO of the relevant match line segment has been deactivated, the "adhesive" latch can still pass the feedback connection between the reverse 210 and the pull-down transistor 232. Its associated line segmentation remains at logic, L, (low level). Each segment receives its associated line segment enable signal MLS〇,...,MATL〇r^ timing control block turn from the match line timing control block 25〇 to receive the reference or dummy match line 26〇 (also Segmented into n segments) timing signal. The dummy match line segment DMLS〇··· DMLSN is identical to the rule match line segment, that is, also has the associated dummy match line circuit and the wire head circuit, except at the beginning of the search operation, matching the line head end and The dummy match line circuit receives the dummy match line enable signal DMLEN\ generated by the search control circuit (not shown). The dummy cells 262 connected to a dummy match line segment are hard-wired to match, that is, for the P-channel type SRAM CAM cell shown in FIG. 1(c), both the search and compare XOR gates are hardwired. To VDD. The function of the dummy match line is exactly the same as the operation of the normal match line, so that it is used to cancel the appropriate timing of the corresponding normal match line segment. By detecting the matching of the dummy match line and the sensing according to the dummy match line -17 - 1302706, the continuation page is configured to time the undo timing of the current source of the associated normal match line for sensing the normal match line segmentation. The appropriate length of time, and the revocation is complete (segmented match line sensing, in this way reduces power consumption. In addition, the use of dummy match lines for the self-time of the regular match line ensures that the consistent timing of all relevant MLKs is not processed. Program or temperature change effects. Next, the general operation of the self-timed match line segment discussed in Figure 2(b) is explained. The operation of the segmented match line has been discussed above with reference to Figure 2(a). The additional control function of the specific embodiment shown in 2(b) is the timing to initiate the MATLO signal. During the pre-charge period, both the regular match line segment and the dummy match line segment are precharged to a mismatch, condition 'as above The search control circuit (not shown) confirms the normal match line enable signal MLEN\ & dummy match line enable signal when the cam receives a search command dmleN \, to enable match

And start searching for the first fastest flow path. Wiring strap circuit 2 12. Enable the signal at the head of the search match match line. At the same time, the matching line has other segments MATL01 to MATLOn, and the result provides a segment from one segment to another.

Segment DMLS0 is logical, L, (low level), 篆, statistically, if there is no matching condition in the subsequent segment with the matching line of the first segment (ie, the first dummy matching line is divided by Inverter sense amplifier -18- 1302706 Description of invention Page (14)

The output confirms the "complete MALOTO" signal. The "Complete MATLOO" signal is provided to the match line timing control circuit, and then the match line timing control circuit deasserts the match line head enable signal MATLOO by undoing the first match line segment MLSQ. Once the match result is detected in the second dummy match line segment, the "Complete MATL01" signal is supplied to the match line timing control circuit 250, and then the match line timing control circuit 250 cancels the second wire segment MLSi. The dummy match line segment continues to sense and provide a "complete MATLO" signal in this manner until all dummy match line segments have been sensed, thereby providing a corresponding normal match line segment for successive undo. Alternatively, the segment after the first segment can be revoked only after the last segment has been searched and sensed.

Note that as described above, the start and revocation of each match line segment is selectively controlled by segmenting the match line into a plurality of segments and also in conjunction with precharging each match line segment to a match condition. A significant power saving effect can be achieved. In addition, the search for results from one segment to another allows for very fast search operations. As the block width increases, this approach can be extended to use the pipe hierarchy between the match line segment groups, as described in further detail below. Referring to Figure 3(a), there is shown another embodiment in accordance with the present invention comprising an N-channel type ML repulsion or (XOR) pull-down device. For the sake of simplicity, the typical ternary CAM cell shown in the figure uses only mutually exclusive or (X〇R) pull-down transistors. Each of the matching strip circuits 212 includes a p-channel type current source transistor connected in series and an intermediate P-channel type transistor in which an inverter (for example, P 3 , P4, N2, respectively) is matched to the line end circuit. Hardwire to -19- 1302706 Description of the invention (15) Grounding. Each of the match line segments ML 1, ML 2, etc. has an associated inverter sense amplifier (as shown in Figure 2 (a)), and the output of each inverter sense amplifier is labeled as MLSOl, MLS02, etc. Wait. The enable signal /EN is supplied to all of the match line circuits 2 1 2 at the same time.

The general operation of this embodiment will now be described with reference to the timing diagrams of Figures 3(a) and 3(b). During precharge, the enable signal is at logic fH彳 high, so all match line segments are precharged to a mismatched state. Pre-charge chopping until all match line segments, as previously discussed with reference to Figure 2(a). When the enable signal is at a high level, new search data can be provided to the search data path (not shown). The first match line segment ML1 is enabled when the enable signal is asserted as a logical T彳low level i. The transistor P2 is adjusted such that a single bit mismatch will maintain the match line segment at logic f L ' (low level), i.e., the match line will continue to be precharged to the unmatched state. Therefore, the current drive capability of transistor P2 must be significantly lower than any two series of pull-down mutual exclusion or (X〇R) devices in the CAM cell. If all the cells on the match line segment match, the match line segment ML will slowly rise to the logical Hf (high level), ie, the match state. These P2 devices, which are relatively weak in current drive capability, cause a relatively slow rise. Once ML 1 exceeds the switching threshold of the static matching line segmented sense amplifier (the simple invertor is shown, but a more complex circuit can be used to provide a lower threshold, thus speeding up the operation); The second match line segment. Referring to Figure 3(b), the timing diagram shows a first search in which the second segment has a match after the first segment has a match. Any number of segments can be implemented, and only the speed is shown in Figure 3(a) for matching line segments 1 and 2). In a letter -20- 1302706, the description of the continuation (16) / ΕΝ logic "L' (low level) cycle (usually a clock cycle), as long as the matching result has enough time to propagate to all match line segments The specific embodiment shown in Figure 3(a) is well suited to provide search result circulation operations across the matching line segments. Figure 3(b) also shows a second search in which the first match line segment has a mismatch. No further signal transitions will occur in the next segment, resulting in savings.

As mentioned above, the advantages of using this method to segment the matching line include: achieving power saving effect by eliminating unnecessary signal transitions after detecting the previous segment mismatch; increasing the operating speed, wherein the matching line resistance/capacitance The RC delay is extremely important (this technique shortens the RC/η delay, where η is the number of segments and RC is the time constant of the full match line ML before segmentation). In addition, the cylinder leakage depth sub-micron processing, the leakage current of the device in the "offn" state may be very significant, especially when connecting a 72-bit or 144-bit CAM cell to a single match line. If the accumulated leakage current is close to a single When the bit does not match the current, it is impossible to judge the match and the mismatch. By subdividing the match line into several segments, the number of potential leakage current paths connected in parallel can be reduced, and the problem can be solved. When there is no match, there will be a quiescent current flow between the p-channel pull-up transistor in the associated match line circuit and one or more series pull-down paths in the CAM cell itself. By disabling the login mismatch This current waste can be eliminated by segmentation and all subsequent segments. As shown in Figure 4, in accordance with another embodiment of the present invention, such a disable signal is generated directly by a reference or dummy match line. The terms "reference match line" and "dummy match line" are used interchangeably and represent the same structure. -21 · 1302706 (17) Description of the Invention As explained with reference to Figure 3, the number of reference match lines is exactly the same as the number of cells and match line circuits to match the capacitance of the line normal match line, but all CAM cells They are hardwired to the t-data so that a match is established. When a match is detected on the reference match line segment, the current of all relevant normal match lines in the segment is cut off by the associated DISABLE signal. The associated DISABLE signal is also used to disable reference match line segmentation via the feedback connection shown in Figure 4. There should be sufficient timing edges between when the match line exceeds the match threshold detectable by the associated inverter sense amplifier and when the p-channel current source is turned off, to account for the match line segmentation between the enable and the enable The inconsistency between the relevant reference match line segments. By driving the time delay of the disable signal through the inverter chain, or by designing a lower switching threshold in the normal match line sense amplifier and designing a higher switching threshold in the reference match line sense amplifier, Achieve sufficient timing edges. Another way to turn off the current source is to turn off all levels of the segmented match line array using only the output of the final level of the reference match line, as described in the short description of Figure 2(b). Because the earlier level is enabled for a longer period of time, it is slightly more wasteful of electronics, but results in a simpler undo mechanism. Referring to Figure 5(a), there is shown a further embodiment in accordance with the present invention for achieving faster operating speeds. In this embodiment, each match line segment has an entire clock cycle to complete the search and compare jobs for each segment. Thus, in the present embodiment, each of the match line segments is piped so that a whole period of time between the clock cycles can be used to form a match or match indication. The static match line sense amplifier associated with each match line segment (like the inverter implemented in the specific embodiment shown in Figures 3 and 4 above) is replaced by a D-type flip-flop, which is a positive and negative D-type The clock is provided by the enable signal /EN, and the search results of the respective match line segments are stored. Alternatively, as described above, a more complex circuit can be used and then the output of the sense amplifier can be latched. As shown in Figure 5(a), the register is composed of a plurality of D-type flip-flops (one D-type flip-flop per row of CAM units) and associated logic gates for connecting the search data path to each CAM units. By using a scratchpad in the search data path, the search data is selectively sent to the next segment only if a match result is found in the previous segment. Or, if the previous segment does not match, the search data will be passed to the CAM unit of the subsequent segment, so that significant power savings can be achieved. The search data and mask information are converted to a ternary format and latched by a D-type flip-flop to drive a search line for accessing all of the column CAM cells in each array. For the first segment (i.e., the segment driven by the matching line head end circuit), since there is no previous segment search result, the search data signals are unconditionally latched. With the rising edge of /EN, the matching result is recorded in the D-type flip-flop at the end of the comparison job. The search data of the second pipeline level (i.e., the second match line segment) is unconditionally latched into the first register in the same manner as the first pipeline level. However, in order to use the previous level of search results to determine whether to continue the search, an additional register is required to delay the search until a first level match/mismatch indication is available. The second pipe is a register consisting of a plurality of D-type flip-flops, and each D-type flip-flop is used for the table -23 - 1302706 (19). The result of the segmentation match result is enabled, as described in further detail below, ie, the output of the D-type flip-flop is changed only if the /EN input is a logic T彳 low level. This prevents the current level of results from changing the search data if it does not match, and thereby saves a considerable amount of C V power, otherwise unnecessary changes in the search line can result in wasted power. For each additional ML segment, a further pipeline level must be added to the search data path. Only the last level needs to be controlled by the match line detection signal. The search data registers are enabled by wired "OR" (〇R) circuits controlled by all of the match lines in the segment of the array. Matching of any match line segment in the array segment will pull the \SLDEN signal down to logic Τ' (low level) to allow new search data to be recorded through the search line. ^ When a comparison job occurs on the match line segment, The OR node will be precharged by /ΕΝ. The self-timed turn-off of the p-channel current source as discussed with reference to Figure 4 can also be added to save more power in this embodiment. Figure 5b shows the general operating time of the embodiment shown in Figure 5a. While the invention has been described with respect to the specific embodiments and specific embodiments thereof The specific terms and phrases used in the specification are intended to be illustrative and not limiting, and the terms and phrases are not intended to be limiting, and any equivalent or part of the functions shown and described in the drawings. However, it should be understood that various modifications are possible and are within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS The function and advantages of the present invention are described by way of example, and any method of the present invention is not intended to limit the scope of the invention, and the specific embodiments of the invention are illustrated in the following drawings. Example: Figure 1(a) shows a simplified block diagram of a typical CAM; Figure 1(b) shows a schematic diagram of one part of the CAM array shown in Figure 1(a); Figure 1(c) shows the principle of a ternary unit. Figure 2 (a) shows a block diagram of a column in a CAM array in accordance with an embodiment of the present invention; Figure 2 (b) shows a diagram of a column in a CAM array in accordance with another embodiment of the present invention; 3(a) shows a diagram of a column in a CAM array according to another embodiment of the present invention; FIG. 3(b) shows a timing chart of a search operation in the CAM shown in FIG. 3(a); FIG. 4 shows the present invention. A self-timed embodiment of a specific embodiment; FIG. 5(a) shows a schematic diagram of a ducted CAM according to another embodiment of the present invention; and FIG. 5(b) shows a search in the CAM shown in FIG. 5(a) Work: Timing chart for reading. Schematic representation symbol description 100 addressable content memory (CAM) 102 CAM array 104 CAM unit 106 address decoder 114 bidirectional data access circuit 114 priority sequence encoder 1 10 matching line sensing circuit block - 25 - 1302706 Page (21) 112 N-bit result 116 Multiple match detection circuit 120 Mutual exclusion or (XOR) comparison transistor 210 Sensing amplifier 212 Matching line circuit 214, 224 Controlled inverter 216, 217 Current source

21 8,222 N-channel device 220 Matching line head circuit MLEN\ Matching line enable signal 230 1 N-channel transistor 232 N-channel pull-down transistor 250 Matching line timing control circuit 260 Reference or dummy match line 262 dummy unit

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Claims (1)

13 02 View No. 137849 Patent Application Replacing the Patent Scope (May 97) £ rigorously changing the page and reading the patent range 1. Selectively enable an addressable content memory (CAM) during a search operation A method of at least one match line segment of a plurality of match line segments in a column of the array, each match line segment having a plurality of CAM cells coupled thereto, the method comprising the steps of: (a) matching the matches The line segment is set to indicate a first search result condition that does not match; (b) evaluate a first match line segment for a second search result condition indicating a match; and (c) selectively enable only one The second match line segment is responsive to the second search result condition in the first match line segment. 2. The method of claim 1, wherein the second result condition in the first match line segment is propagated along the column to indicate a search result status for the column. 3. The method of claim 1, wherein the evaluating the first match line segment comprises initiating the first match line segment and sensing a voltage level of the first match line segment. 4. The method of claim 3, wherein the enabling step allows the matching line segment to be discharged to a matching condition. 5. The method of claim 1, wherein the first search result status is a high and low pressure level on the match line, and the second search result status is a low high pressure level on the match line, and only When the second matching result condition is present on the first matching line segment, the second matching line is allowed to be divided into 1302706. The __Bing page segment is discharged. 6. If the application is evaluated, the startup is 7. If the application is evaluated, the selection is 8 If the application is segmented 9. If the pressure on the application line is on time, the package is allowed to be a low voltage level. The method of clause 1, wherein the first match line segment is in a first clock cycle and the second match line segment is selected in a subsequent clock cycle. The method of claim 1, wherein the plurality of first match line segments are equal in a first clock cycle, and the plurality of second match line segments are periodically initiated on a subsequent clock cycle. The method of claim 1, wherein the first and second matching lines are adjacent to each other. The method of claim 1, wherein the first condition is a matching high voltage level, and the second condition is a low on the matching line, and only when the first matching line segment has the second state The second match line segment is discharged to a low voltage level. Addressable content memory (CAM) devices with complex columns, each column including: (a) a plurality of match line segments having a plurality of CAM cells coupled thereto; (b) a circuit for precharging the match line segments to a first search result condition; the segments include (i) a sensing circuit for detecting a second search result condition indicating a match; and (ii) a circuit for enabling a pre-charge path in a subsequent segment to detect the second Search results status. -2- < S ) Τ ^0?7Π^ι —Ί 申谵 97 97,.5,.1 6 11. A method for searching addressable content memory (CAM), which has a plurality of columns of CAM units, Each column is coupled to an associated match line, each match line having a plurality of match line segments, the method comprising: (a) precharging the plurality of match line segments to a first one indicating a mismatch a condition; (b) searching for a first segment of each match line; and (c) selectively searching for a second only if the search result of the first segment is a non-first condition Segmentation. 12. The method for searching for a CAM according to claim 11 of the patent application further includes an additional step of selectively searching for a search result of only one previous segment being a non-first condition Any segment after the second segment. 13. A method for searching for an addressable content memory (CAM) comprising a plurality of columns, each column being coupled to a correlation match line, each match line having a plurality of match line segments, the method comprising : (a) precharging the plurality of match line segments to a "mismatch" condition; (b) searching for a first match line segment; and (c) detecting only in the first match line segment When a "hit" condition is detected, a second match line segment is selectively searched. 14. The method of claim 13, wherein the "hit" condition is propagated to all match line segments to indicate a "hit" condition until a "mismatch" condition is detected to prompt deactivation Segmentation and any subsequent segments. 1302706 One-to-n 鐄 ____ page; year-and-month-day modified replacement ** 15. A method for performing a pipeline search operation in an addressable content memory (CAM) with segmented matching lines The method includes the following steps: (a) precharging all match line segments to a "mismatch" condition; (b) searching for a match line segment during a first clock cycle; and (c) A subsequent hit line segment is searched for during a subsequent clock cycle only if a "hit" condition is detected in a previous match line segment. 16. The method of claim 15, further comprising a deactivation step of deactivating a subsequent match line segment if a "mismatch" condition is detected in a previous match line segment.如 The method of claim 15, further comprising a selective deactivation step for deactivating and subsequently matching the line once a "mismatch" condition is detected in a previous match line segment Segment related search line driver. -4- <S) 1302706 Patent Application No. 091137849 Chinese Illustration Replacement (July 96) Pickup, Drawing οξ η • Day f Replacement Page 1302706 -2 - 1302706 96. 7, one 24 ΠΜ- Ϊ. thick lion Hs hs wide Γ αα> a-nLUo V ---- winter § 0>| <Ή3ο L· ha hs 1302706 H Jf fiber tribute Ζιζ ζιζ ζιζ S 4- 1302706 «V •I m target L· 0SS il stM 1302706 θ*.2νυ ^$^0 se匾 尔犹 -6- 1302706 s year cd 9 -ci change #· 正修, 曰, •3SK- ilH [4Λ, I hw Osd I\J0S12 (q)e i 1302706 leap year ;Ί r‘independence Rni^j RML2, [> lh[ Disable CAM unit DISABLE 2 DISABLE Figure 4 ί·Ξ ΞΖ Disable CAM unit 1302706 »-· z z 2, it t aliJ? z I 2< i < Q O a *♦* *♦ 2: Z o o * , Z 2 o o a g ^lOSIW >1 2UJ TN6I^ 72b ”Geaoaoa ΠΜΗΓπΜ I T J NUJ<t=! i TlUJo:;ldo 4 1 j •>m NUJ -9- 1302706 CLK ΕΝ ΜίΊ HIT MISS MLSOL, ML2 HIT SL[0;N-1] X I SL[N:2N-1] NO TRANSITION register enabled giant All match lines in the array Segment record "does not match" " Figure 5(b) -10-