TWI300526B - Data recovery apparatus and method for reproducing recovery data - Google Patents

Description

I300^.doc/e IX. Description of the Invention: [Technical Field] The present invention relates to a data recovery device and method, and more particularly to a three quarter steps oversampling ) data recovery device and method. ^ [Prior Art] μ Electronic circuits have been flourishing in the direction of southerly speeding and miniaturization. At high speed data transfer speeds, how to correctly transfer data becomes a topic worth studying. In the case of a flat panel display, as the size of the flat panel display continues to increase, the color density and resolution provided by the display continue to increase. Resolution SVGA (800x600 pixels) and xGa (1024x768 pixels) are the most basic requirements for flat panel displays. The resolution is constantly improving, and it also means an increase in the amount of data transfer and data transfer. Especially in the flat display system, the bottleneck encountered in the data transfer between the direct connection of the display card to the liquid crystal display clock controller is most obvious. Figure 1 illustrates the data transfer interface between the timing controller and the display card in a typical flat panel display. Referring to FIG. 1, the transmitting end (here, the display card n〇) transmits a 28-bit wide image signal to the receiving end through a low-voltage differential signal (l〇w_v〇ltage differential signaling, referred to as LVDS for short). In • This is the timing controller 140 in the flat panel display. LVDS interface includes

The LVDS transmission unit 12 and the receiving unit 13 to the lvds transmission unit 丄 2 〇 use the four multiplexers MUX to convert the image signal outputted by the display card 11 以 into a 4-bit wide 7-bit image. The LVDS data of the meta-depth is transmitted to the LVDS receiving unit 130 in the form of a differential signal. In the LVDS 5 13005 orphaned doc / e ^ face to face the standard towel, the transmission end 丨 2. The more multiplexed phase loop PLL additionally transmits two, and the sigma pulse 4 is given to the receiving end. Therefore, the data of the receiving end 13Q is returned to the DRC to recover other data by using the current pulse, and the 4-bit width of these resources is converted into 28-bit width. Figure 2a is a timing diagram illustrating the operation of three times oversampling. The traditional clock and data recovery circuit is mostly _ using a double sampling architecture to recover the input signal to prevent errors caused by the skew between the clock and the data, so as to correctly recover the problem. Enter 5? information. Figure 3 illustrates the conventional architecture of the clock and data recovery circuitry in the receiving end 130 of Figure 1. Referring to FIG. 3 and FIG. 2A simultaneously, the pulse and data recovery circuit includes input buffers 205 and 210, data sampler 215, phase lock loop 220, synchronizer 225, phase detector 230, voter 235, and digital low pass. Filter 240 and phase selector 245. First, the input buffers 2〇5, 210 respectively convert the input data strings Din+, Din_ and the input clocks CLKin+, CLKin- of the LVDS type into a funn signal to be transmitted to the data sampler 215. And the phase locked loop 220. The phase-locked loop 220 locks the input clock of the full-width mode and provides a sampling of 21 different phases, the pulse to the lean sampler 215. Since the 21 different phase samples are used, the data sampler 215 samples three times each of the bit data d0-d0 to form a 21-bit wide data string. Synchronizer 225 then synchronizes the sampled data output by data sampler 215. By comparing the three samples of each step (e.g., d0 in Fig. 2A), the phase detector 230 can detect whether or not the input string is received.

I300?H Enter the clock first or behind. According to the detection results of the bit data d0-d6, the phase detector 230 correspondingly outputs 7 sets of signal pairs (each signal pair includes "up" bit and "down" bit). For example, when the sampling clock phase is behind the input data stream, as shown in FIG. 2B, the phase detector 230 detects that the third sampling result is different from the first in each step (eg, d〇) of the input data string. In parallel with the second sampling result, the phase detector 230 outputs an "up" signal to the voter 235 in the corresponding signal pair. Conversely, when the sampling clock phase leads the input data string, as shown in FIG. 2C, the phase detector 230 detects that the first sampling result is different from the second and third in each step (eg, d〇) of the input data string. As a result of the sampling, the phase detector 23 outputs a "down" signal to the voter 235 in the corresponding signal pair.

The voter 235 phase detector 230 outputs true "up" and "down" signals to the phase selector 245 depending on the number of "up" and "down" signals of the seven sets of signal pairs outputted. For example, in a clock cycle. If the 7 sets of signal pairs received by the voter 23S have an "up" signal and three "down" signals, the voter 235 outputs a true "down" signal to the phase selector 245. In order to prevent the jitter effect from affecting the detection result, the digital low pass filter 240 is used to pass the secret. The phase selector 245 receives the straight "up" signal output by the voter 235 through the digital low pass filter 240. If the phase selection n 245 receives the voter 235, "on the factory" signal, it is equivalent to the phase selector. 245 ς ς 串 串 领先 领先 CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK CLK If the phase selector 245 receives the straight "down" signal output by the voter 235, it corresponds to the phase selection n 245 receiving the detection result of "the input data string Din is behind the input clock CLKin" (as shown in the figure). 2C), so the phase selection 245 will shift the 21 sampling phases down (ie, rightward in the figure) by one phase in the down-cycle period (as shown in Figure 2A). Finally, the synchronizer 225 is based on the phase. The selected result of the selector 245 restores the received sample data to the 7-bit wide recovery data D〇ut. In the prior art, when the input data offset is close to one-half step, three times The sampling architecture will not be able to tell if the offset is leading or After sampling the clock, it may cause errors in the recovered data. In addition, the (10) phase selection architecture with triple sampling architecture requires 21 different phase sampling in the application of the flat display system low-power waste signal receiver. The clock, in this way, will increase the complexity of the circuit layout, and cause the expansion of the area. [Invention] The object of the present invention is to provide a data recovery device and method, which are sampled at three times and four steps. To enhance the tolerance of the eye diagram. 1. Another object of the present invention is to provide a data recovery device and method to greatly reduce the complexity of the layout, while reducing the overall layout area to achieve the goal of low cost. The delay selection architecture replaces the phase complement architecture, so the entire circuit greatly reduces the number of phases of the clocks that need to be used. Based on the above object, the present invention provides a data recovery device for receiving at least one original time provided by the transmitting end. Pulse with at least one original data 8 1300 fox 'd〇c/e = ' to output at least - recover data. The period of the initial clock τ 2 丄 original data string contains 步 step distance, Ν is an integer greater than q. This resource = county includes sampling unit and processing single original = pulse sampling original data string, which is in each step Taking τ/(' weeks, the corresponding data of the original data string is at least three times. The processing unit receives the sampling result output by the sub-comparison sampling unit, and restores the sampling result to the recovery data according to the aforementioned lighter result. In view of the above, the present invention provides a data recovery method for recovering at least a raw material pulse and at least a data string provided by a transmitting end into at least one recovered data, wherein the original data string is included in a period τ of the original clock. The step size is 整数, which is an integer greater than 〇. The data recovery method includes: at each step, the corresponding data of the original data string is sampled at least three times in a time period of Τ/(4Ν); and at each step of ten, The sampling results are compared, and the sampling results are restored to the recovery data. The present invention replaces the conventional phase selection architecture (phaseseiecting) by using a delay selection system. Therefore, only a small number of sampling phases with different phases are used in the entire circuit, which greatly reduces the complexity of the layout and reduces the entire layout area. Achieve the purpose of reducing costs. In addition, since the data is input in three-quarters of a step (Steps rsampling), the receiver can be more tolerant of the input signal eye diagram. The above and other objects, features and advantages of the present invention will become more <RTIgt; 17. i3〇〇m doc/e [Embodiment] How to correctly transmit data at a high-speed (four) transmission speed becomes an issue worthy of study. Taking a flat panel display as an example, as the size of the enamel on one side is continuously increased, the color density and resolution provided by the aging device are constantly increasing. Resolution SVGA (8〇〇χ_pixel) and XGA (1024x768 pixels) are the most basic requirements for flat panel displays. The degree of resolution continues to increase, and it also means an increase in data throughput and data transfer speed. Especially in the flat display system, the data transfer between the direct connection of the display card to the liquid crystal display clock controller (such as shown in Figure i) is most obvious. When the resolution reaches SXGA (ΐ28〇χΐ〇24 pixels) and UXGA (1600x1200 pixels), the data transfer capacity is up to 784 Mbps and II55 Mbps. At such a high speed data transfer speed, how to correctly transmit data becomes an important issue. In order to facilitate comparison with the prior art, the low-pressure differential signaling (hereinafter referred to as lvds) surface is still used as an embodiment of the present invention, but the present invention should not be limited thereto. Fig. 4 is a circuit diagram of the phase locked loop 22〇 in Fig. 3. The general phase-locked loops include the phase-frequency detector (phase frequenCy), the charge pump 42〇, and the partial house generator 43. The common phase-locked loop architecture is used to implement phase-locked loops. Loop 220, so the operation is not described here. In the phase-locked loop (10), the house-controlled vibrating cover II 44G is grouped by 21雠-seismic elements in series so as to be provided by these repeatedly controlled units in a clock cycle without a 10 i3〇〇md〇c The /e phase-sampling clock will give the data oscillating unit a large amount of circuit accumulation. However, a large number of voltage control embodiments will use three times four points: SS 0 ampling) 牟椹, ra L step sampling (three quarters need 28 not _ bit 彳 / for LVDS interface standards, The invention is in accordance with the data recovery circuit (it:: one of the steps of sampling one of the clock transmission 'end, 耒: two with the same day: Figure 5 and Figure 6A 'this data reply At least one original clock CLKin (including and at least "counter data" (including "+" in) provided by the circuit receiving factory, and not including, at least one recovery data D〇ut. In the original period T, the original data string Din contains N step sizes (N j is an integer of 〇 in the present embodiment Ν = 7). This data recovery device includes a sampling unit and a processing unit. The sampling unit includes input buffers 505 and 510, a data sampler 515, a phase-locked loop 52, and the like for sampling the original data string Din according to the original clock CLKin, in each step-by-step, with a 1V (4N) time period. Sampling the corresponding data of the original data string Din (for example, d0 in FIG. 6A) at least three times. In this embodiment The processing unit includes a synchronizer 525, a phase detector 530, a voter 535, a digital low pass, a waver 540 and a phase selector 545 for receiving and comparing the sampling results of the sampling unit, and comparing according to the foregoing As a result, the sampling result is restored to the recovery data Dout. ^ 11 13005 orphan doc / e In addition to the data sampler 515, the phase-locked loop 520, the synchronized crying embodiment shown in Figure 5, the clock and the data recovery ° 'this = The same, no longer mentioned. The phase-locked loop pulse is given to the data sampler 515. Since these 28 different phase clocks are used, the data sampler 515 will sample the stepping distance in the bit data coffee 6 four times (four) The 28-bit wide data string is output to the same 525. Then, the synchronizer 525 synchronizes the samples output by the data sampler 515. The synchronizer 525 takes each step (e.g., the bit data, for example, Selecting four of the four data to output three pens to the phase detector. FIG. 6D illustrates three times sampling (also "times oversampling" and three times one step sampling in accordance with an embodiment of the present invention. Eye diagram Of stand. In this embodiment, since the triple of four knives step from the sampled input data, and therefore more of the receiver can tolerate improve the signal eye diagram of the wheel, and then correctly recover the information of the input.

By comparing the three samples of each step (e.g., d0 in Fig. 6A), the phase detector 530 can detect whether the input string Din is leading or falling behind the input clock CLKin. In the period τ, the phase detector 530 outputs phase detection, and σ fruit with respect to each step (ie, bit data d0_d6) (here, 7 groups of 彳3 pairs, each signal pair includes an "up" bit) With the "down" bit). For example, when the sampling clock phase is behind the input data string Din', as shown in FIG. 6B, the phase detector 530 detects that the third sampling result is different from the first and second in each step (for example, d0) of the input data string Din. 12

13 Detecting the sampling result, the phase detector 530 outputs an "up" signal to the voter 535 in the corresponding signal pair. On the other hand, when the sampling clock phase leads the input data string Din, as shown in FIG. 6C, the phase detector 530 detects that each of the step sizes (for example, d〇) of the input data string Din is different from the second one. As a result of the third sampling, the phase detector 53 outputs a "down" signal to the voter 535 in the corresponding signal pair. The voting benefit 535 determines and outputs the periodic phase detection result based on the phase corresponding to each step in the current period τ. The digital low pass filter 54 filters the noise. The phase selector 545 receives the periodic phase detection result output by the voter 535 via the digital low-pass chopper 54〇, and selects one of the sampling clocks generated by the phase-locked loop 52〇 as the internal clock CLK. According to the selection result of the phase selector %, the sampling result of the sample output is selected (10) = the timing of the CLK and the selected seven: the recovery data D〇m. 2, the embodiment of the present invention illustrates the power of the phase-locked loop 520 of FIG. 5 = 71:=^ 752rj' phase-locked loop - including phase frequency detection 74〇. Here is generally common: generator 730 fine-air oscillator, so the shooting operation is not here (four) to the real-compensation loop shock 740 only by 14 health control, loop 520, pressure control each pressure The oscillation unit is controlled and connected in series with each other. Since the oscillating unit can be at the _ face, the 14 voltage controlled samples are supplied to the data sampler 515. 28 different phases take 13 1300 orphans. Compared with the conventional phase-locked loop of Figure 4, the _ loop 22 〇 must be loose, and the two voltage-controlled seismic units constitute the voltage-controlled shock absorber 440. = 4 7 G only * 4 pressure-controlled i units. Therefore, this embodiment I reduces the electric (four) product occupied by the age scale. Furthermore, since this embodiment is twice as many as four steps It is better to increase the acceptance of the input signal eye diagram by sampling the input data. For the convenience of comparison with the prior art, the following LVDs interface is used as an example. Figure 8 is another example according to the present invention. One embodiment illustrates a clock-and-data recovery circuit for sampling twice as many-steps as wood. Figure 9 is a timing diagram illustrating the use of triple-four-step sampling in accordance with an embodiment of the present invention. Referring to FIG. 8 and FIG. 9, the data recovery circuit receives at least the original clock CLKin (including CLKm+ and CLKin·) and at least one original data stream (including cell + and Dm-) provided by the transmitting end (instruction). In turn, at least one recovery data is said. Among them, in the period T of the original clock CLKin The data string Din contains n steps (n, an integer greater than G, where N=7). The data recovery device includes a sampling unit and a processing unit. The sampling unit includes input buffers 805 and 810, delay selection ^ 850, and Detect The window measuring unit 860, the data sampler 815, the phase-locked loop 820, and the like are configured to sample the original data string Dm according to the original clock CLKin, wherein the original data string Dm is sampled in a T/(4N) time period in each _ step distance. Corresponding data at least three times. The processing unit includes a synchronizer 825, a phase detector 830, a voter 835 and a shift selector 840 for receiving the sampling result output by the sub-prepared sampling unit, and according to the result of the comparison Sampling results are restored to recovery data

Dout ° 14 X3 OO^^^/f.doc/e The input buffers 805 and 810 respectively convert the input data string Din+, Dm- and the input clock CLKifl+ of the LVDS type into a full swing signal for transmission. The delay selector 85 is coupled to the phase locked loop 820. The phase-locked loop 82〇 clamps the input clock of the full-width mode and provides seven different phase sampling clocks dk〇~dk6 to the data sampler 8丨$. In addition, phase locked loop 820 generates an internal clock CLK to trigger synchronizer 825, voter 835, and shift selector 84A. The delay TD 850 receives the original data string Din for determining the delay time of the original data string Din according to the shift control signals s〇, S1 output by the shift selector 840, and outputs the selected delay data string ds . In the present embodiment, the delay selector 84A includes a first delay 851, a second delay 852, a third delay 853, and a multiplexer 854. The first delayer 851 receives the original data string Din via the input buffer 8〇5, and delays the original data string Dm to output the first delayed data string DS1. The second delay unit μ receives the first delay data string DS1 outputted by the first delay 851, and outputs the second delay data string DS2 after delaying the first delay data sequence DS1 (where the delay time is set to q). The third delay 853 receives the second delayed dragon string DS2 outputted by the second delayed crying 852, and delays the second delayed data string DS2 to output a third delayed data string. The multiplexer is off-shifted, and the signals SO, S2 select one of the first-delay data string (4), the second delay grazing string DS2, and the third delay data string DS3, and are input as the selected delay data string DS. For example, when the shift control signal S0=1, the multiplexer 854 selects the output of the first delay data string DS1 of the first delay 851 as the singular delay data string. If the shift control signal is phantom=1, 15 doc/ e 1300^2^ detects the timing of each step in the period τ of the original data string Din or the leading original clock CLKin by comparing the output of the synchronizer 825, and corresponding to each step in the period T Phase detection results. The phase detector 83G can detect whether the input data string Din is leading or falling behind the input clock by comparing the data of each step in the delay string DS (for example, the rib in FIG. 1A). CLKin. In the period τ, the phase state 830 is output relative to each step (ie, the bit data d〇_d6) = ancient detection, (in this case, 7 sets of signal pairs, each signal pair contains "upper" bits "bit". The voter 835 determines and outputs the periodic phase detection, :, based on the phase detection result corresponding to each of the current period τ. fruit. The shift selector 840 receives the periodic phase/measurement result 'output by the voter 835 and generates shift control Zheng/S1 and S2 based on the weekly_bit detection result, and determines the original &amp; delay time by (4). For example, when the sampling clock (for example, clk0) is out of phase with the Dm (for example, the bit dragon d0), as shown in the figure _, the phase detection = the illusion detects the input data string Din every step ( For example, d =) two = result (that is, the sampling result of the delay data string DW1) is different from the first: /, the young one sampling result (ie, the delay data string DW3 and fruit) 'the phase detection 183 is outputted in the corresponding signal pair = Voter 835. Conversely 'when sampling the clock (eg _) phase. When the grazing string Dm (for example, the bit data such as) is input first, as shown in FIG. 6c, the phase detector 830 detects that the input data _D is not, as in the case of d0), the first failure is in the step (example) of the parent (1). The brother takes u (that is, the sampling result of the delay data string DW3) 17 i3〇〇m • doc / e = and the third sampling result (ie, the delay data strings DW2 and DWl, the phase detector 53 is outputted in the corresponding signal pair) Refer to Figure u. The operation process of this related tiger can be &quot;, where 'synchronization 1^ 825 is based on the selection result of the shift selector 84〇, and the sampling result output by ns early m__15 is selected when the bucket is t'mount At the timing of the pulse clk, the selected 7 assets are rotated out as the recovery data Dout of 7-bit width. = The above-mentioned date is based on the use of delay selection (5) # sdectmg) Phase selection (phaseselecting), so only a small number of different phase sampling clocks need to be used in the whole circuit, which greatly reduces the complexity of the layout, and at the same time reduces the entire layout area and achieves the purpose of reducing costs. In addition, since the data is rounded up by three-quarters of the step-by-step sampling, it is possible to improve the acceptability of the receiver to the eye diagram. While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. [Simple description of the diagram] Figure 1 illustrates the data transmission interface between the timing controller and the display card in a typical flat panel display. 2A to 2C are operation timings illustrating three times oversampling. 18 i3〇〇md〇c/e Figure 3 System architecture. Explain the transmission of the clock and data recovery circuit in the receiving end of Figure 1.

Figure 4 illustrates a circuit diagram of the phase locked loop of Figure 3. Fig. 5 is a view showing the sampling type of the sample taken in accordance with an embodiment of the present invention. - (4) - Step size FIGS. 6A to 6C are timing charts illustrating the use of one-step sampling in accordance with an embodiment of the present invention. One of the β-knife The present invention provides a description of three recordings and three times four divisions. Figure 7$ illustrates a circuit diagram of the phase-locked loop of Figure 5 in accordance with an embodiment of the present invention. FIG. 8 is a diagram showing a clock and data recovery circuit using three-quarters of a step size sampling in accordance with another embodiment of the present invention. Knife Figure 9 is a timing diagram illustrating sampling with three times four-foot distance in accordance with an embodiment of the present invention. v (4) ^ ^ ~ 1% is a timing diagram of the data sampler in accordance with the embodiment of the present invention for detecting different phase data strings output by the early element. Figure U is a process for explaining the related signals of Figure 8 in accordance with an embodiment of the present invention. 0 /, [Main component symbol description] 11 〇 Display card 120: Transmitting unit/transmitting terminal 130: Receiving unit/receiving end 140: Timing controller 19

Claims (1)

D〇c/e X. Patent application scope: J· A data recovery device, using the initial clock and at least - the original capital: 3⁄4 provided to =, where the original clock cycle τ out to V recovery The data recovery device includes: a string, the second I:, the original clock sampling the original data processing unit, electrically connected to the _ sample 2 outputted by the sampling unit to receive and compare The result is the re-entry of the record. "Comparatively refer to the data recovery device described in the sample 1 of the sample, the same phase of the pulse is used to generate at least 4 of the original clock, and the electrical phase is connected to the phase-locked loop for Sampling the original data string according to the previous sampling results, and the data recovery device described in item 2 of the second application of the second application is included in the data unit, and the sample unit is used to make the sampling unit The thief is electrically connected to the synchronizer for detecting that the step τ of each of the period τ of the original data string lags behind or leads the original clock by comparing the output of the side synchronization. The phase detection of the corresponding phase is performed, and the phase detector is used to determine and output the noise according to the phase detection result corresponding to the phase detection phase of the target period. a low-pass chopper, electrically connected to the voter for filtering the connection to the digital low-pass ferrite to select the phase-locked phase detection result of the phase-locked phase, and according to the clock; Some of the sampling clocks - as - inside In the section, the synchronizer further selects the selection according to the selection of the phase selector, and selects the result in the result, and according to the data, the selected data is input (four) for the recovery. The data recovery device according to item 1 of the profit range, wherein the pulse disk ^^ road is used to generate at least the sampling clock of different phases of internal time and IN adjustment according to the Japanese plant of Shishi County; 'Receiving the original data string to determine the delay time of the original #-string according to a shift, and outputting a delay of 22 1 Jwmd 〇 c / e and delaying the delay selection to connect to the delay selector The data string used to connect the data of the same phase to output to a data sampling community, bud from the gui: t:: round (four) some data strings, and the =3⁄4 the delay = 2 special = range 4 The data recovery device, wherein the coarse-grained retarder ' is configured to receive the original data string, and the data is delayed to output a first-delay data string; and the surface is electrically connected to the first-delay , using the _ second delay string 'and delaying the first-delay data string to the rear wheel: the first 'electrically connected to the The second delay device is configured to receive the three delay data and delay the output of the second delay data string, and the output is electrically connected to the first delay device, and the second delay device is delayed: the delay is 'Selecting the first extension-, second, the second delay data string and the third delay data string according to the shift control signal as the selected delay data string. The data recovery device of the item, wherein 23 i3〇〇md〇c/e-shifting select n, electrically connected to the vote ^, the heart receives the detection result of the week and generates the shift according to the phase detection result of the period The bit ^ number controls the delay selector to determine the delay of the original data string, wherein the synchronizer selects (4) r=r according to the lion shift, and selects the N data of the (4) turn The output is provided as the recovery resource - the original transmission terminal is provided at least in the county clock τ 〃 〃 t distance: two major: 〇 integer, then the data recovery method package y: the corresponding one of the heart string = Ν) time period sampling the original data b. in each step, ratio Said sampling sister ... if recovery for data recovery. And 将该, the sampling method of the data processing method of claim 8, wherein the original clock is delayed to generate at least the sampling of the original capital according to the foregoing w (four), and sampling of different phases The data recovery method described in the ninth item of the patent application scope, wherein: · includes: synchronizing the sampling results of step a; = comparing the synchronized (four) sampling results The timing of each original step τ is behind or leading the original clock. The knot '=::=: every step _ 1: according to the phase detection result selects the sampling clocks. ; ^ The above selection result and select the time from the sampling results as the timing (4) The above selected suppression data output - the original ! ^ send end provided at least in the period of the original clock === : = material = with N steps 'N is greater than. Integer,: the; = a. According to the -shift system, at least three different phase data are obtained. ^ The phase of the original beetle string is pulsed according to the original clock, and at least one different phase is sampled. · According to the sequence of three data sequences of different phases obtained by N steps in step b, sample 13 13 〇〇 gas in step a. c/e 2d. Compare the sampling results in step c and restore the sampling results to the recovery data. 12. The data recovery method according to claim 11, wherein the phase difference between the three data strings of different phases in step a is T/(4N,) time. 13. The method for recovering data as recited in claim 11 of the claim, wherein: the phase difference between the N sampling clocks of different phases in step b is pi « time. 14) If the data recovery method described in the scope of claim 5, the step a includes: , , , , determining the delay time of the original data string according to the shift control signal, and obtaining the selected delay data string; And delaying the selected delay data string to obtain the data string of the at least three different phases. 15. If the data recovery method described in claim 11 of the patent scope, the step d includes: / generating an internal clock according to the original clock; synchronizing the sampling results of step c; The result of the aging is taken, and the period τ of the original sequel is detected, and the time interval of each step is backward or leading the original pulse; the result is that the phase detection corresponding to each step in the current period T is detected. , , , ° determine the periodic phase detection result; = according to the cycle phase detection result to generate the shift control signal to determine the delay time of the original string; 27 I3005^6vfd〇c / e according to the above selection results Selecting N pieces of data from the sampling results; and outputting the selected N pieces of data as the recovery data according to the timing of the internal clock. 28