1300240 九、發明說明： 【發明所屬之技術領域】 • 本發明係關於一種具有導電墊之系統。 【先前技術】 隨著電子產品之快速發展，對於用以作為使用者與機器間介面 之?、、頁示态之要求盈發嚴格。而液晶顯示器⑴职记CIyStai display，以 參下簡稱LCD)因具有外型輕薄、耗電量低、無輻射污染與其他優 點’已然成為市場主流，並廣泛使用於筆記型電腦、個人數位助 理(personal digit assistants，PDA)、數位相機、行動電話、以及其 他通訊與資訊用品中。更甚者，近年來液晶顯示器更趨向取代傳 統陰極射線管（cathode ray tube，CRT)監視器與CRT電視。 另方面’由於有機物質之研究及其自發光(self-light-emitting)、 面解析度、以及寬視角之優勢，有機發光二極體顯示器 • (orgamc-light-emitting-diode display，以下簡稱 OLED)亦頗引人注 目。由此可見液晶顯示器、有機發光二極體顯示器、以及其他平 面顯示器於通訊電子產品中已具有不可或缺之地位，並日漸廣泛 應用於日常生活中。 習知平面顯示器，不論是LCD或OLED ,皆包含有一像素陣 列區域與一周圍電路區域，其中更包含有複數個形成於周圍電路 區域用以電性連接至外部電路之導電墊。請參閱第1圖與第2圖。 第1圖係為一習知平面顯示面板10之上視圖，而第2圖係為第1 1300240 圖中平面顯示面板10之側視圖。平面顯示面板10係為—LCD， 包含有二層玻璃基板12、Η及一層設置於玻璃基板12、14之間 之液晶分子16。如第1圖所示，上玻璃基板12係小於下玻璃基板 14。因此，部分玻璃基板14係為玻璃基板12所覆蓋，並由此定 義出-覆蓋區域18。而玻璃基板14之其他部分係為_未覆蓋區 域，其定義為一周圍電路區20。覆蓋區域18包含有一像素陣列區 (主動區域，active area，ΑΑ)11與一控制電路區13。 周圍電路區20具有複數個周圍電路及導電墊22，用以電性連 接至外部電路，並藉由平面顯示面板1〇之内部電路如犯沉電 壓線或獅㈣彳訊號線傳遞訊號。第3 _繪示—習知導電塾之1300240 IX. DESCRIPTION OF THE INVENTION: TECHNICAL FIELD OF THE INVENTION The present invention relates to a system having a conductive pad. [Prior Art] With the rapid development of electronic products, the requirements for use as the interface between the user and the machine are strict. The liquid crystal display (1) CIyStai display, referred to as LCD) because of its thin appearance, low power consumption, no radiation pollution and other advantages, has become the mainstream of the market, and is widely used in notebook computers, personal digital assistants ( Personal digit assistants (PDAs), digital cameras, mobile phones, and other communications and information products. What's more, in recent years, liquid crystal displays have tended to replace traditional cathode ray tube (CRT) monitors and CRT televisions. On the other hand, due to the research of organic substances and their advantages of self-light-emitting, surface resolution, and wide viewing angle, orgamc-light-emitting-diode display (hereinafter referred to as OLED) ) is also quite eye-catching. It can be seen that liquid crystal displays, organic light-emitting diode displays, and other flat-panel displays have become indispensable in communication electronic products, and are increasingly used in daily life. A conventional flat panel display, whether an LCD or an OLED, includes a pixel array region and a surrounding circuit region, and further includes a plurality of conductive pads formed in the peripheral circuit region for electrically connecting to the external circuit. Please refer to Figure 1 and Figure 2. 1 is a top view of a conventional flat display panel 10, and FIG. 2 is a side view of the flat display panel 10 in the first 1300240. The flat display panel 10 is an LCD, and includes a two-layer glass substrate 12, a crucible, and a layer of liquid crystal molecules 16 disposed between the glass substrates 12, 14. As shown in Fig. 1, the upper glass substrate 12 is smaller than the lower glass substrate 14. Therefore, part of the glass substrate 14 is covered by the glass substrate 12, and thus the -covering region 18 is defined. The other portion of the glass substrate 14 is the _uncovered area, which is defined as a peripheral circuit area 20. The coverage area 18 includes a pixel array area (active area, ΑΑ) 11 and a control circuit area 13. The peripheral circuit area 20 has a plurality of peripheral circuits and conductive pads 22 for electrically connecting to external circuits, and transmits signals through internal circuits of the flat display panel 1 such as a sinking voltage line or a lion (four) signal line. The third _ picture - the known conductive
’小印丨糾几丨泜心金屬材料構成， 第二¥電層32則由高抗阻之金屬材料構成；而第三導電層％材 料之硬度係大於第二導電層30材料之硬度。 因此該部位係無法避免製作過程、 應力及外力影響。然而，由於第三 由於玻璃基板Η上之顯㈣未被麵基板U所覆蓋， •、組裝過程及運輸過程中產生之 三導電層32之材料較易脆裂，始 1300240 更易於應力或外力下損壞。-旦第三導電層32受到外 較柔軟的第二導電層30即因此受其觸或塌損；外力下、二 電層32甚至可能移動第二導電層3〇，導致第二導電層％接觸到 玻璃基板！4上的其他元件而造成短路。另外，當外力刮損第三導 電層32及第二導電層3G時’可能於導電墊μ表面造成刮痕，使 得平面顯示器10在視覺測試中成為—劣質產品。 因此，如何提供具有較佳結構，且在應力或外力下能避免刮 痕、移動或元件短路之設置於未覆蓋之卵電路區域之導電塾， 係為顯示n製造業者致力解決之重要課題之一。 【發明内容】 本發明係提供-種具有導電墊之系統。 ^發^所提供之具有導電㈣統之顯示器面板之一實 Γ=Γ基層設置於一基板上、-具有複數個溝槽之 基層上、一充填於該等溝槽内之第-導 電曰W及-覆蓋該第一導電層之圖案化第二導電層。 ，刪一絕緣層 第一道^ "成因此該第一絕緣層係作為固定該 “層位置之播牆’故具有較柔軟材質之第一 可避免被刮傷與移動位置。 、 曰 1300240 【實施方式】 電#，關於—具有導電塾之系統，鱗電塾具有—第一導 固二 4 —導電層之位置係由—作為擋牆之第-絕緣層所 面:Γ 4圖至第5圖。第4圖係為一與本發明所提供之顯示 =反_5〇連接之電子裝置應之方塊圖，而第5圖係為第4圖所示 〜面板5〇之不意圖。如第4圖所示，電子裝置1〇〇包含有一 炉器虞置102 ’ w—LCD裝置’且顯示器裝置102包含有一控 /器104以及—顯示面板50，其中控制器104係搞合於顯示面板 且控制器104係可操作用來控制顯示面板5〇，以根據輸入之 魏而提供影像。電子裝置刚可為—膝上型電腦、一行動電話、 一數位相機、-個人數位助理(Personal digital assistant，PDA)、 :桌上型電腦、一電視機、一車用顯示器或-攜帶式DVD播放 器因此’使用者可透過控制器1〇4控制電子裝i 1〇〇以操侧 示面板50。The small printed circuit is composed of a metal material, and the second electrical layer 32 is made of a highly resistant metal material; and the third conductive layer % material has a hardness greater than that of the second conductive layer 30. Therefore, the part cannot avoid the influence of the manufacturing process, stress and external force. However, since the third surface of the glass substrate is not covered by the surface substrate U, the materials of the three conductive layers 32 generated during the assembly process and transportation are more susceptible to brittleness, and the first 1300240 is more susceptible to stress or external force. damage. Once the third conductive layer 32 is exposed to the second conductive layer 30 which is softer, it is thus touched or collapsed; under the external force, the second electrical layer 32 may even move the second conductive layer 3〇, resulting in a second contact of the second conductive layer. To the glass substrate! Short circuit caused by other components on 4. In addition, when the external force scratches the third conductive layer 32 and the second conductive layer 3G, it may cause scratches on the surface of the conductive pad μ, so that the flat display 10 becomes an inferior product in visual inspection. Therefore, how to provide a conductive crucible provided with a preferred structure and capable of avoiding scratches, movement or short-circuiting of components in an uncovered egg circuit region under stress or external force is one of the important issues that the n-manufacturer is trying to solve. . SUMMARY OF THE INVENTION The present invention provides a system having a conductive pad. One of the display panels provided with the conductive (four) system is provided on the substrate, on the substrate having a plurality of trenches, and a first conductive layer filled in the trenches And covering the patterned second conductive layer of the first conductive layer. The first layer of the insulating layer is deleted. Therefore, the first insulating layer serves as the first layer of the softer material to fix the "wall of the layer", so as to avoid being scratched and moved. 曰1300240 Embodiments] Electric #, about - a system with conductive turns, the scales have - the first guide two 4 - the position of the conductive layer is - as the first - insulating layer of the retaining wall: Γ 4 to 5 Figure 4 is a block diagram of an electronic device connected to the display = inverse _5 本 provided by the present invention, and Fig. 5 is a schematic view of the panel 5 shown in Fig. 4. As shown in FIG. 4, the electronic device 1A includes a furnace device 102'w-LCD device' and the display device 102 includes a controller 104 and a display panel 50, wherein the controller 104 is integrated with the display panel and The controller 104 is operable to control the display panel 5 to provide images according to the input. The electronic device can be a laptop computer, a mobile phone, a digital camera, and a personal digital assistant. , PDA), : desktop computer, a TV set, Accordingly 'the user can control the electronic device to operate i 1〇〇 display panel 50 through the controller side 1〇4 portable DVD player - or a car display.
請參閱第5圖，顯示面板50包含有一第一基板52與一設置於 第一基板52下之第二基板54。第二基板54之尺寸係大於第一基 板52之尺寸，而未被第一基板52覆蓋之部分第二基板54係定義 為周圍電路區60 ,·被第一基板52覆蓋之部分第二基板54則定義 為覆蓋區域58。覆蓋區域58包含有一像素陣列區58a以及一控制 電路區58b。根據本發明之一較佳實施例，顯示面板50係為一 LCD 1300240 ^ 面板或一 OLED面板。 周圍電路區60包含有複數個導電墊56與導線乃設置於第二 基板54上。各導電墊56係分別透過一具有至少一内部電路之汇 曰曰片或可撓性印刷電路板(flexible print circuit，FPC board)以電性 連接至少一外部電路。請參閱第6圖至第7圖，其中第6圖係為 第5圖所不之導電墊兄與導線76之放大圖；而第7圖係為第6 φ 圖中導電墊56延A-A，切線之剖面圖。導電墊56包含有一基層62 覆蓋於第二基板54上與一圖案化之第三導電層64設置於基層62 上。基層62可包含絕緣材料，其亦可為一由氮化矽、氧化矽、或 其他非導電性材料形成之緩衝層。第三導電層64可包含有金屬材 料，更適包含鉬或鈦。 導電墊56更包含有一第一絕緣層66覆蓋於基層幻與部分第 三導電層64上。如第6圖所示，第一絕緣層的包含有複數個第 馨一溝槽72a、72b、72c以及一第二溝槽74於單一導電墊允内。 第-溝槽72a、72b、72c係延-第-方向，如又軸方向，彼此平 行，且皆連結於第二溝槽74。第二溝槽74係延一不平行於第一方 向之第二方向排列。於一較佳實施例中，該第二方向係垂直於該 第一方向。舉例來說，該第二方向係延一γ軸方向，因此第一溝 槽72a、72b、72c與第二溝槽74係呈一 Ε字形狀。一第一導電層 68係充填於第一溝槽72a、72b、72c與第二溝槽74内，且由於第 溝槽72a、72b、72c藉由第一溝槽74彼此連接，因此各溝槽内 1300240 之第-導電層68係可彼此傳導。 在第一導電層68之上設置有一圖案化之第二導電層7〇，其全 面性覆蓋第一導電層68,且覆蓋部分設置於第三導電層64上方之 第-絕緣層66。圖案化之第二導電層7〇之材質可包含有透明氧^ 銦錫(indium tin oxide，ITO)。 • 位於第-溝槽72a、72b、72c内之第一導電層68係呈平行排 列且互相連結。另外，第一溝槽72a、72b、72c係延第_絕緣層 66延伸，而位於第一溝槽仏、⑽❿内之第一導電層邰係曰電 f生連接至第二導電層64，故第一導電層68與第三導電層亦可 併聯操作。因此，即使位於第一溝槽72a、72b、72c與第二溝槽 Μ内之第一導電層68損壞，第三導電層64仍可提供導電墊允 之導電功能，以電性連接外部電路與顯示器面板5〇之内部電路。 另一方面，設置於第二基板54上且與導電墊56電性連接之導 線76係為一内部電路，且亦具有同於本發明所提供之導電墊允 之結構。由於各導線76係部分設置於周圍電路區6〇，且並未被第 一基板52所覆蓋，因此亦可根據本發明精神提供一較佳結構。請 參閱第6圖，未被覆蓋之導線76亦包含有一圖案化之第三導電層 64 (未示於第6圖）、一具有複數個互相平行之第三溝槽7如、7牝 之第一絕緣層66、一充填於第三溝槽78a、78b内之第一導電層 沾、以及一圖案化第二導電層70,而圖案化第二導電層7〇覆蓋了 11 1300240 弟二溝槽78a、78内之笛—it + β 因此、Μ 之弟一 V電層68與圖案化之第三導電層64。 =線76亦具有_堅固之結構叫抗外部應力。據此，暴露 介且:板54表面之顯不器面板5G之—周圍電路或—内部電路 亦具有如上所述之結構。 :得注意的是，第一絕緣層66之溝槽之上視形狀並不限於第6 雷丁之域。任何具有充填於第一絕緣層％之溝槽内之第一導 • 1、8之^電塾皆可含括於本發明精神内。第8圖至第10圖係 t別為本發觸提供之$二實施例、第三實施例、以及第四實施 ，中導電塾之放大圖。為簡單說明，第8圖至10圖中之標號係相 δ ;第6圖。如第8圖所示，第一絕緣層％之溝槽w係呈一格 狀排列。而第9圖中’多數溝槽75b係互相平行排列。另一方 面第10圖中之溝槽75c則呈一不一致之形狀。 鲁 乂下"兒明係為根據本發明所提供之導電墊56製作方法。請參 閱第11目至第14圖，第11 ®至第14 ®係為第7圖所示之導電 墊56之製作方法之示意圖。如第n圖所示，首先提供一第二基 板54。隨後’ 一第一絕緣層（標號62)與一第三導電層（標號64) 係依序形成於第二基板54上。第一絕緣層係定義為導電墊允之 後貫知一苐一顯影暨姓刻製程(photolithography-etching ΡΓ_8，以下簡稱為PEP)以圖案化第三導電層64，形成如第11 圖所示之圖案化之第三導電層64。之後，一第二絕緣層66，係沈積 於圖案化之第二導電層64與基層62上，第一導電層66,較佳為氧 12 1300240 化矽或氮化矽。 4參閱第12圖，隨後對第二絕緣層66，實施一第二PEP，以於 各導電墊56内形成複數個第一溝槽72a、72b、72c與一第二溝槽 74(未示於第12圖中），以便完成導電墊56之第一絕緣層66。另 方面’第6圖所示之導線76之第三溝槽78a、78b亦於第二PEP 中形成。 # ^ , 請參閱第13圖與第14圖，一第一導電層68,係全面性形成於 第二基板54上，並充填於第一溝槽72a、72b、72c、第二溝槽74 與第三溝槽78a、78b内。隨後對第一導電層68，係進行回蝕刻（或 藉由PEP)以移除位於第一絕緣層66上之部分第一導電層砧，， 而剩餘部分係僅充填於第一溝槽72a、72b、72c、第二溝槽74與 第三溝槽78a'78b内，如第14圖中標號68所示。第一導電層68 馨 較佳由具有低抗阻之金屬材料如鋁(A1)、鉬(Mo)、或鋁與鉬之合金 如Mo/Al/Mo或Ti/Al/Ti所構成。接下來，一第二導電層係形成於 第二基板54之上，並進行一第三PEP以圖案化該第二導電層，形 成一覆蓋第三導電層64與第一導電層68之圖案化第二導電層 70，以便完成如第7圖所示之導電墊56之製作。 導電墊56之製作係可與像素陣列區58内之元件如薄膜電晶體 (thin film transistor，以下簡稱TFT)、掃瞄線、或訊號線之製作並 行。像素陣列區58内元件之完整製程一般包含具有五至六次pEp 13 1300240 之非晶矽TFT製程與具有八至九次pep之低溫多晶矽薄膜電晶體 (low temperature polysilicon thin film transistor，LTPS TFT)製程，該 等製程係可含括製作導電墊56之第1至第3次PEP。舉例來說， 第—導電層64可與TFT之閘極或掃目苗線一同製作，且可具有相同 材質。第一絕緣層66可與TFT之閘極絕緣層一同製作，且可具有 相同材f ;第-導電層68可與源極、汲極、或訊號線具有相同材 質’而第二導電層70則可與像素電極如IT〇具有相同材質。因此， φ 多餘之光罩或製程係可省略。 於本發明所提供之另一實施例中，導電墊允僅包含有具有第 :溝槽72a、72b、72c與第二溝槽74之第一絕緣層66、充填於該 等溝槽之第|電層、以及第二導電層70，而不具有第三導電 、本毛月具有之優勢包含將具有較柔軟材質之第一導電層設置 於該等溝槽内，因此能受雜硬的第-絕緣層與第二導電層的保 文本t撕提供之導電墊之第-導電層不㈣外部應力或因 導電層移位’而導致與其他導電墊S位於第二基板上的元件 ^觸，造成短路。由於第—導電層係由較低抗阻之材質所構成， 其幸乂不易她’因此本發明係可提供—較佳之導電表現 由於第三盘筮 邱V電層係、為平行操作，即使第—導電層不幸於外 電:^於製程中產生其他缺陷，第三導電層仍可提供導 ’功能。因此製程良率更可於不需增加其他成本之情況 14 1300240 • 下有效提升。 . 以上所述僅為本發明之較佳實酬，凡依本發明申請專利範 圍所做之均等變化與修飾’皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1圖係為一習知之平面顯示器之上視圖。 春第2圖係為第1圖所示之平面顯示器之側視圖。 第3圖係為第1圖所示之導電墊之剖面圖。 第4圖係為根據本發明所提供之與一電子元件整合之顯示器面板 之方塊圖。 第5圖係為第4圖所示之顯示器面板之示意圖。 第6圖係為第5圖所示之導電墊與周圍電路之放大圖。 第7圖係為第6圖所示之導電墊延A_A，切線之剖面圖。 第8圖至第1〇圖係分別為本發明所提供之第二實施例、第三實施 例、以及第四實施例中導電墊之放大圖。 第11圖至第14圖係為第7圖所示之導電墊製程之示意圖。 【主要元件符號說明】 10 11 16 平面顯示器 像素陣列區 液晶分子 周圍電路區 12 Λ 14 玻璃基板 13 控制電路區 18 覆蓋區 22 導電墊 15 20 第一絕緣層 26 第一導電層 第二絕緣層 30 第二導電層 第三導電層 電子元件 102 顯不元件 控制器 顯示器面板 52 第一基板 第二基板 56 導電墊 覆蓋區 58a 像素陣列區 控制電路區 60 周圍電路區 基層 64 第三導電層 第一絕緣層 66， 第二絕緣層 第一導電層 68， 第一導電層 第二導電層 72a、72b、72c 第一溝槽 第二溝槽 75a、75b、75c 溝槽 導線 78a、78b 第三溝槽 16Referring to FIG. 5, the display panel 50 includes a first substrate 52 and a second substrate 54 disposed under the first substrate 52. The second substrate 54 is larger in size than the first substrate 52, and a portion of the second substrate 54 not covered by the first substrate 52 is defined as a peripheral circuit region 60, and a portion of the second substrate 54 covered by the first substrate 52. It is then defined as the coverage area 58. The coverage area 58 includes a pixel array area 58a and a control circuit area 58b. According to a preferred embodiment of the present invention, display panel 50 is an LCD 1300240^ panel or an OLED panel. The peripheral circuit region 60 includes a plurality of conductive pads 56 and wires disposed on the second substrate 54. Each of the conductive pads 56 is electrically connected to at least one external circuit through a flexible printed circuit (FPC board) having at least one internal circuit. Please refer to Fig. 6 to Fig. 7, wherein Fig. 6 is an enlarged view of the conductive pad brother and the wire 76 in Fig. 5; and Fig. 7 is the sixth φ figure in which the conductive pad 56 extends AA, tangent Sectional view. The conductive pad 56 includes a base layer 62 overlying the second substrate 54 and a patterned third conductive layer 64 disposed on the base layer 62. The base layer 62 may comprise an insulating material, which may also be a buffer layer formed of tantalum nitride, hafnium oxide, or other non-conductive material. The third conductive layer 64 may comprise a metal material, more preferably molybdenum or titanium. The conductive pad 56 further includes a first insulating layer 66 overlying the base layer and the third conductive layer 64. As shown in Fig. 6, the first insulating layer includes a plurality of first recesses 72a, 72b, 72c and a second trench 74 in a single conductive pad. The first grooves 72a, 72b, 72c are extended in the -first direction, such as the axial direction, are parallel to each other, and are connected to the second grooves 74. The second grooves 74 are arranged in a second direction that is not parallel to the first direction. In a preferred embodiment, the second direction is perpendicular to the first direction. For example, the second direction is extended by a γ-axis direction, so that the first grooves 72a, 72b, and 72c and the second groove 74 have a U-shape. A first conductive layer 68 is filled in the first trenches 72a, 72b, 72c and the second trench 74, and since the first trenches 72a, 72b, 72c are connected to each other by the first trench 74, each trench The first conductive layer 68 of the inner 1300240 is conductive to each other. A patterned second conductive layer 7 is disposed over the first conductive layer 68, which covers the first conductive layer 68 in a holographic manner and covers the first insulating layer 66 disposed over the third conductive layer 64. The material of the patterned second conductive layer 7〇 may include transparent indium tin oxide (ITO). • The first conductive layers 68 located in the first trenches 72a, 72b, 72c are arranged in parallel and connected to each other. In addition, the first trenches 72a, 72b, and 72c extend the first insulating layer 66, and the first conductive layer in the first trench 仏, (10) is electrically connected to the second conductive layer 64. The first conductive layer 68 and the third conductive layer may also operate in parallel. Therefore, even if the first conductive layer 68 located in the first trenches 72a, 72b, 72c and the second trench is damaged, the third conductive layer 64 can provide a conductive function of the conductive pad to electrically connect the external circuit with The internal circuit of the display panel 5〇. On the other hand, the wires 76 disposed on the second substrate 54 and electrically connected to the conductive pads 56 are an internal circuit and also have the same structure as the conductive pads provided by the present invention. Since each of the wires 76 is partially disposed in the peripheral circuit region 6 and is not covered by the first substrate 52, a preferred structure can be provided in accordance with the spirit of the present invention. Referring to FIG. 6, the uncovered conductor 76 also includes a patterned third conductive layer 64 (not shown in FIG. 6), and a plurality of third trenches 7 which are parallel to each other. An insulating layer 66, a first conductive layer filled in the third trenches 78a, 78b, and a patterned second conductive layer 70, and the patterned second conductive layer 7 covered 11 1300240 The flutes in 78a, 78 - it + β are thus, the V-electric layer 68 and the patterned third conductive layer 64. = Line 76 also has a sturdy structure called external stress resistance. Accordingly, the peripheral circuit or the internal circuit of the panel 5G of the surface of the panel 54 is also exposed as described above. It is to be noted that the top view of the trench of the first insulating layer 66 is not limited to the sixth redding domain. Any of the first electrodes 1 and 8 having a groove filled in the first insulating layer % may be included in the spirit of the present invention. 8 to 10 are enlarged views of the conductive ridges of the second embodiment, the third embodiment, and the fourth embodiment provided for the present invention. For the sake of simplicity, the numbers in Figures 8 through 10 are δ; Figure 6. As shown in Fig. 8, the grooves w of the first insulating layer are arranged in a lattice shape. On the other hand, in Fig. 9, the plurality of grooves 75b are arranged in parallel with each other. On the other hand, the groove 75c in Fig. 10 has an inconsistent shape.乂 & &" 儿明 is a method of making the conductive pad 56 provided in accordance with the present invention. Referring to Figures 11 through 14, the 11th through 14th are schematic views of the method of making the conductive pad 56 shown in Figure 7. As shown in Fig. n, a second substrate 54 is first provided. Subsequently, a first insulating layer (reference numeral 62) and a third conductive layer (reference numeral 64) are sequentially formed on the second substrate 54. The first insulating layer is defined as a conductive pad, and then a photolithography-etching ΡΓ8 (hereinafter referred to as PEP) is patterned to pattern the third conductive layer 64 to form a pattern as shown in FIG. The third conductive layer 64 is formed. Thereafter, a second insulating layer 66 is deposited on the patterned second conductive layer 64 and the base layer 62. The first conductive layer 66 is preferably oxygen 12 1300240 bismuth or tantalum nitride. 4, in FIG. 12, a second PEP is then applied to the second insulating layer 66 to form a plurality of first trenches 72a, 72b, 72c and a second trench 74 in each of the conductive pads 56 (not shown). In FIG. 12), the first insulating layer 66 of the conductive pad 56 is completed. The third trenches 78a, 78b of the conductor 76 shown in Fig. 6 are also formed in the second PEP. #^, Referring to FIG. 13 and FIG. 14, a first conductive layer 68 is integrally formed on the second substrate 54 and filled in the first trenches 72a, 72b, 72c, and the second trench 74. Inside the third grooves 78a, 78b. Subsequently, the first conductive layer 68 is etched back (or by PEP) to remove a portion of the first conductive layer anvil located on the first insulating layer 66, and the remaining portion is only filled in the first trench 72a, 72b, 72c, second trench 74 and third trench 78a'78b, as indicated by reference numeral 68 in Fig. 14. The first conductive layer 68 is preferably composed of a metal material having low resistance such as aluminum (A1), molybdenum (Mo), or an alloy of aluminum and molybdenum such as Mo/Al/Mo or Ti/Al/Ti. Next, a second conductive layer is formed on the second substrate 54 and a third PEP is patterned to pattern the second conductive layer to form a pattern covering the third conductive layer 64 and the first conductive layer 68. The second conductive layer 70 is formed to complete the fabrication of the conductive pad 56 as shown in FIG. The conductive pads 56 can be fabricated in parallel with components such as thin film transistors (TFTs), scan lines, or signal lines in the pixel array region 58. The complete process of the components in the pixel array region 58 generally includes an amorphous germanium TFT process having five to six pEp 13 1300240 and a low temperature polysilicon thin film transistor (LTPS TFT) process having eight to nine pep. The processes may include first to third PEPs for making conductive pads 56. For example, the first conductive layer 64 can be fabricated together with the gate of the TFT or the sweeping wire, and can have the same material. The first insulating layer 66 may be formed together with the gate insulating layer of the TFT, and may have the same material f; the first conductive layer 68 may have the same material as the source, the drain, or the signal line, and the second conductive layer 70 It can be the same material as the pixel electrode such as IT〇. Therefore, the φ excess mask or process system can be omitted. In another embodiment provided by the present invention, the conductive pad allows only the first insulating layer 66 having the first trenches 72a, 72b, 72c and the second trench 74 to be filled in the trenches| The electrical layer and the second conductive layer 70, without the third conductive, have the advantage that the first conductive layer having a softer material is disposed in the trenches, so that the first conductive layer can be subjected to The insulating layer and the second conductive layer provide the first conductive layer of the conductive pad without (four) external stress or displacement due to the conductive layer, resulting in contact with other conductive pads S on the second substrate, resulting in Short circuit. Since the first conductive layer is composed of a material having a lower resistance, it is not easy for her to be used. Therefore, the present invention can provide a preferred conductive performance due to the third disk, the Qi V layer, for parallel operation, even if - The conductive layer is unfortunately externally charged: ^ Other defects are generated in the process, and the third conductive layer can still provide a conducting function. Therefore, the process yield can be increased without additional cost. 14 1300240 • Effective improvement. The above is only the preferred embodiment of the present invention, and all changes and modifications made to the scope of the invention are intended to be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a top view of a conventional flat panel display. Figure 2 of the spring is a side view of the flat panel display shown in Fig. 1. Figure 3 is a cross-sectional view of the conductive pad shown in Figure 1. Figure 4 is a block diagram of a display panel integrated with an electronic component in accordance with the present invention. Figure 5 is a schematic view of the display panel shown in Figure 4. Figure 6 is an enlarged view of the conductive pad and surrounding circuitry shown in Figure 5. Figure 7 is a cross-sectional view of the conductive pad A_A shown in Figure 6 and a tangent line. Fig. 8 through Fig. 1 are enlarged views of the conductive pads of the second embodiment, the third embodiment, and the fourth embodiment, respectively, provided by the present invention. 11 to 14 are schematic views showing the process of the conductive pad shown in Fig. 7. [Main component symbol description] 10 11 16 Flat panel display pixel array area Liquid crystal molecule surrounding circuit area 12 Λ 14 Glass substrate 13 Control circuit area 18 Covering area 22 Conductive pad 15 20 First insulating layer 26 First conductive layer Second insulating layer 30 Second conductive layer third conductive layer electronic component 102 display component controller display panel 52 first substrate second substrate 56 conductive pad footprint 58a pixel array region control circuit region 60 surrounding circuit region base layer 64 third conductive layer first insulation Layer 66, second insulating layer first conductive layer 68, first conductive layer second conductive layer 72a, 72b, 72c first trench second trench 75a, 75b, 75c trench wire 78a, 78b third trench 16