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TWI398961B - Solar cell manufacturing method comprising at least two gettering steps - Google Patents

Solar cell manufacturing method comprising at least two gettering steps Download PDF

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TWI398961B
TWI398961B TW099100006A TW99100006A TWI398961B TW I398961 B TWI398961 B TW I398961B TW 099100006 A TW099100006 A TW 099100006A TW 99100006 A TW99100006 A TW 99100006A TW I398961 B TWI398961 B TW I398961B
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substrate
solar cell
twinned
etching
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TW099100006A
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TW201125147A (en
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Hsin Jung Feng
Cheng Han Su
Ming Chung Hsu
Tsung Fang Hsieh
Yu Chou Lee
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Tainergy Tech Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

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Description

包含至少二次去除有害雜質步驟之大陽能電池的製造方法Method for manufacturing a solar cell comprising at least two steps of removing harmful impurities

本發明係關於一種太陽能電池製造方法,尤其關於一種利用摻雜的雜質去除矽晶基板中有害顆粒的太陽能電池製造方法。The present invention relates to a solar cell manufacturing method, and more particularly to a solar cell manufacturing method for removing harmful particles in a twinned substrate by using doped impurities.

傳統的太陽能電池包含一具有P/N界面的矽晶基板,而矽晶基板的製造過程中,容易產生顆粒污染(particle contamination)現象,而對製造良率產生不好的影響。中華民國專利申請號第095139453號,揭露一種高吸雜能力及高平坦度之矽晶片及其製造方法。於此方法中,在矽晶基板的高溫製程中會產生一層均勻的錯位缺陷(stacking fault defects),該缺陷層會將製程中的金屬污染(有害顆粒)吸進其中,是為吸雜區域(gettering sites),藉此能夠減少矽晶基板中的有害金屬顆粒。於美國專利第5066359號中,是於鹹蝕刻時,未將研磨損傷層完全除去,而留一層薄的研磨損傷層用以作為吸雜(gettering)層。於中華民國專利申請第096127007號中,利用矽烷(silane)氣體在矽晶圓上沉積多晶矽區域作為雜質捕集區域,使矽晶圓包含一矽切片及一第一雜質捕集區域。A conventional solar cell includes a twinned substrate having a P/N interface, and during the manufacturing process of the twinned substrate, particle contamination is apt to occur, which adversely affects the manufacturing yield. The Republic of China Patent Application No. 095139453 discloses a silicon wafer having high gettering capability and high flatness and a method of manufacturing the same. In this method, a uniform stacking fault defects are generated in the high temperature process of the twinned substrate, and the defective layer absorbs metal contamination (harmful particles) in the process into the gettering region ( Gettering sites), thereby reducing harmful metal particles in the twinned substrate. In U.S. Patent No. 5,066,359, the abrasive damage layer is not completely removed during salty etching, leaving a thin layer of abrasive damage for use as a gettering layer. In the Republic of China Patent Application No. 096127007, a polycrystalline germanium region is deposited on a germanium wafer as an impurity trapping region by using a silane gas, so that the germanium wafer includes a germanium slice and a first impurity trapping region.

該些先前技術,雖已具有減少矽晶基板中有害顆粒的效果,但是用於製造太陽能電池時尚具有改善的空間。These prior art, although having the effect of reducing harmful particles in the twinned substrate, have an improved space for manufacturing solar cell fashion.

本發明一實施例之目的在於提供一種減少矽晶基板中有害雜質的太陽能電池製造方法。一實施例中,提供一種利用摻雜磷雜質的方式來減少矽晶基板中有害雜質的太陽能電池製造方法。It is an object of an embodiment of the present invention to provide a method of fabricating a solar cell that reduces harmful impurities in a twinned substrate. In one embodiment, a method of fabricating a solar cell that utilizes a method of doping phosphorus impurities to reduce harmful impurities in a twinned substrate is provided.

依據本發明一實施例,提供一種太陽能電池製造方法其包含以下步驟。提供一矽晶基板,且該矽晶基板為第一型並具有一第一表面及一第二表面。將第二型之多數的第一雜質,摻雜於矽晶基板的第一表面上。對矽晶基板的第一表面進行第一次蝕刻。將第二型之多數的第二雜質,摻雜於已被第一次蝕刻的矽晶基板的第一表面上,以形成一第一型區域及一第二型區域。對矽晶基板的第一表面進行第二次蝕刻。以及形成電連接第一型區域及第二型區域的一電極結構。According to an embodiment of the invention, a solar cell manufacturing method is provided which comprises the following steps. A twinned substrate is provided, and the twinned substrate is of a first type and has a first surface and a second surface. A plurality of first impurities of the second type are doped on the first surface of the twinned substrate. The first surface of the twinned substrate is etched for the first time. A plurality of second impurities of the second type are doped on the first surface of the twinned substrate that has been etched for the first time to form a first type region and a second type region. A second etch is performed on the first surface of the twinned substrate. And forming an electrode structure electrically connecting the first type region and the second type region.

於一實施例中,第一型為P型,而第二型為N型。且較佳的情況是第一雜質及第二雜質皆為磷雜質。In one embodiment, the first type is a P type and the second type is an N type. And preferably, the first impurity and the second impurity are all phosphorus impurities.

於一實施例中,對矽晶基板的第一表面進行第一次蝕刻的步驟,可以更對矽晶基板的第二表面進行第一次蝕刻。此外,對矽晶基板的第一表面進行第二次蝕刻的步驟,可以更對矽晶基板的第二表面進行第二次蝕刻。In one embodiment, the first etching of the first surface of the twinned substrate may be performed for the first etching of the second surface of the twinned substrate. In addition, the second etching of the first surface of the twinned substrate may be performed for the second etching of the second surface of the twinned substrate.

於一實施例中,將第二型之多數的第一雜質摻雜於矽晶基板的第一表面上的步驟,是在一第一預定溫度下進行,將第二型之多數的第二雜質摻雜於已被第一次蝕刻的矽晶基板的第一表面上的步驟,是在一第二預定溫度下進行,且第一預定溫度高於第二預定溫度。In one embodiment, the step of doping a plurality of first impurities of the second type on the first surface of the twin crystal substrate is performed at a first predetermined temperature, and the second impurity of the second type is The step of doping on the first surface of the twinned substrate that has been etched for the first time is performed at a second predetermined temperature, and the first predetermined temperature is higher than the second predetermined temperature.

於一實施例中,對矽晶基板的第一表面進行第一次蝕刻的步驟,進行一第一預定期間,對矽晶基板的第一表面進行第二次蝕刻的步驟,進行一第二預定期間,且第一預定期間長於第二預定期間。In one embodiment, the step of performing a first etching on the first surface of the twinned substrate, performing a first predetermined period of time, performing a second etching on the first surface of the twinned substrate, and performing a second predetermined step And the first predetermined period is longer than the second predetermined period.

依本發明一實施例的太陽能電池製造方法,對矽晶基板進行兩次摻雜磷雜質的步驟以及兩次蝕刻步驟(較佳的情況是一次過蝕刻步驟及一次標準蝕刻步驟),能夠有效減少矽晶基板中的有害雜質,進而提升矽晶基板內部少數載子的生命期。According to the solar cell manufacturing method of an embodiment of the present invention, the step of performing the doping of the phosphorus impurity twice on the twinned substrate and the two etching steps (preferably, the one-pass over-etching step and the one-time etching step) can effectively reduce Harmful impurities in the twinned substrate, thereby increasing the lifetime of minority carriers inside the twinned substrate.

本發明的其他目的和優點可以從本發明所揭露的技術特徵中得到進一步的了解。為讓本發明之上述和其他目的、特徵和優點能更明顯易懂,下文特舉實施例並配合所附圖式,作詳細說明如下。Other objects and advantages of the present invention will become apparent from the technical features disclosed herein. The above and other objects, features, and advantages of the invention will be apparent from

一般而言半導體元件能夠被分成P型及N型。以P型半導體元件為例,P型半導體元件會具有較多的電洞,因此P型半導體元件中多數載子(carrier)是指電洞,少數載子是指電子,而N型半導體元件則相反。In general, semiconductor components can be classified into P-type and N-type. Taking a P-type semiconductor device as an example, a P-type semiconductor device has a large number of holes. Therefore, a majority of a carrier in a P-type semiconductor device refers to a hole, a minority carrier refers to an electron, and an N-type semiconductor device refers to an electron. in contrast.

本案發明人進行實驗,對太陽能電池的原料矽晶圓(wafer)進行全檢測,並實際生產電池片,比對所產出之太陽能電池的光電轉換效率以及全檢測結果,發現矽晶圓中的少數載子(以P型多晶矽晶圓為例,少數載子為電子)的生命週期,會影響太陽能電池的光電轉換效率。於矽晶圓的製造過程中,受到顆粒污染而殘留的有害金屬粒子,會減少矽晶圓中的少數載子的生命週期。The inventor of the present invention conducted an experiment to fully test the raw material 矽 wafer of the solar cell, and actually produced the cell sheet, and compared the photoelectric conversion efficiency and the full detection result of the produced solar cell, and found that the wafer was in the wafer. The life cycle of a few carriers (for example, P-type polysilicon wafers, where a few carriers are electrons) affects the photoelectric conversion efficiency of solar cells. During the manufacturing process of the wafer, the harmful metal particles remaining by the particle contamination will reduce the life cycle of the minority carriers in the wafer.

為了提升太陽能電池之矽晶圓中少數載子的生命週期,在大致不影響太陽能電池品質及製程的情況下,本案發明人嘗試進行實驗,利用摻雜磷雜質的方式,驗證磷雜質吸附有害金屬粒子的效果。In order to improve the life cycle of a few carriers in the silicon wafer of the solar cell, the inventors of the present invention tried to conduct experiments using the method of doping phosphorus impurities to verify the adsorption of harmful metals by phosphorus impurities, without affecting the quality and process of the solar cell. The effect of particles.

本發明之實驗的設計方式如下說明。於一比較例中,僅對矽晶圓的一表面進行一次摻雜磷雜質的步驟。因為摻雜磷雜質的步驟中,會於表面處形成阻礙電子流動的陷阱(trap)層,因此更進一步在摻雜磷雜質的步驟後,對矽晶圓的該表面進行蝕刻以去除上述陷阱層。於本發明一實施例中,為了驗證磷雜質吸附有害金屬粒子的效果,進行了二次摻雜磷雜質的步驟以及二次蝕刻步驟。以下將詳述本發明一實施例之太陽能電池製造方法,以及上述二次摻雜磷雜質的步驟以及二次蝕刻步驟的目的及作用。The design of the experiment of the present invention is as follows. In a comparative example, only one surface of the germanium wafer is subjected to a step of doping phosphorus impurities. Since the step of doping the phosphorus impurity forms a trap layer at the surface that hinders the flow of electrons, the surface of the germanium wafer is etched to remove the trap layer after the step of doping the phosphorus impurity. . In an embodiment of the present invention, in order to verify the effect of the phosphorus impurities adsorbing harmful metal particles, a step of second-doping phosphorus impurities and a second etching step are performed. Hereinafter, a method of manufacturing a solar cell according to an embodiment of the present invention, and a step of the above-described secondary doping of phosphorus impurities and a purpose and a function of the second etching step will be described in detail.

圖1A至1B顯示依據本發明一實施例之太陽能電池製造方法的流程圖。圖2A至2H顯示依據本發明一實施例之太陽能電池製造方法之各步驟的剖面示意圖。如圖1A至1B及圖2A至2H所示,太陽能電池製造方法包含以下步驟。1A to 1B are flow charts showing a method of fabricating a solar cell according to an embodiment of the present invention. 2A to 2H are schematic cross-sectional views showing respective steps of a method of fabricating a solar cell according to an embodiment of the present invention. As shown in FIGS. 1A to 1B and FIGS. 2A to 2H, the solar cell manufacturing method includes the following steps.

如圖2A所示,步驟S02:提供一矽晶基板,且矽晶基板並具有一第一表面113及一第二表面114。於本實施例中,矽晶基板為一P型多晶矽基板110。As shown in FIG. 2A, step S02: providing a twinned substrate, and the twinned substrate has a first surface 113 and a second surface 114. In this embodiment, the twinned substrate is a P-type polycrystalline germanium substrate 110.

如圖2B所示,步驟S03:利用酸鹼溶液清洗或者蝕刻P型多晶矽基板110的第一表面113及第二表面114,使P型多晶矽基板110之表面113及114粗糙化,以降低太陽光的反射。As shown in FIG. 2B, step S03: cleaning or etching the first surface 113 and the second surface 114 of the P-type polycrystalline silicon substrate 110 with an acid-base solution to roughen the surfaces 113 and 114 of the P-type polycrystalline silicon substrate 110 to reduce sunlight. Reflection.

如圖2C所示,步驟S04:將N型之多數的第一雜質,摻雜於P型多晶矽基板110的第一表面113上。於一實施例中,可以利用爐管擴散法或者網印、旋塗或噴霧法,於第一表面113上摻雜N型雜質,N型雜質會擴散進入P型多晶矽基板110,形成一N型雜質擴散區,以使P型多晶矽基板110具有N型區域111及P型區域112。於一實施例中,第一雜質可以為磷雜質,並且是在溫度約800℃至約820℃下,利用三氯氧磷(POCl3 )來對P型多晶矽基板110進行磷雜質摻雜。為了使磷雜質能夠更深入P型多晶矽基板110內部,藉以吸附較多的有害雜質,最佳的情況是使步驟S04的製程溫度高於後述之步驟S08的製程溫度。As shown in FIG. 2C, step S04: a plurality of N-type first impurities are doped on the first surface 113 of the P-type polysilicon substrate 110. In an embodiment, the first surface 113 may be doped with an N-type impurity by a furnace tube diffusion method or a screen printing, a spin coating method or a spray method, and the N-type impurity may diffuse into the P-type polycrystalline germanium substrate 110 to form an N-type. The impurity diffusion region is such that the P-type polysilicon substrate 110 has an N-type region 111 and a P-type region 112. In one embodiment, the first impurity may be a phosphorus impurity, and the phosphorus impurity doping is performed on the P-type polycrystalline germanium substrate 110 by using phosphorus oxychloride (POCl 3 ) at a temperature of about 800 ° C to about 820 ° C. In order to allow the phosphorus impurities to penetrate deeper into the P-type polycrystalline silicon substrate 110, thereby adsorbing more harmful impurities, it is preferable to make the process temperature of the step S04 higher than the process temperature of the step S08 described later.

如圖2D所示,步驟S06:對P型多晶矽基板110的第一表面113進行第一次蝕刻。於一實施例中,步驟S06進行1.5小時(其為後述步驟S10之0.5小時的三倍)。步驟S06的蝕刻時間長於後述之步驟S10的蝕刻時間,除了能夠去除步驟S04所形成的陷阱層外,還能夠去除步驟S04所形成之N型區域111的至少一部分。因為於此部分中磷雜質已吸附有一部分之P型多晶矽基板110中的有害雜質(亦即摻雜磷雜質的步驟具有吸雜(gettering)的功能),所以去除N型區域111之該至少一部分後的P型多晶矽基板110,會具有較少的有害雜質。As shown in FIG. 2D, step S06: the first surface 113 of the P-type polysilicon substrate 110 is first etched. In one embodiment, step S06 is performed for 1.5 hours (which is three times 0.5 hours of step S10 described later). The etching time in step S06 is longer than the etching time in step S10 to be described later, and in addition to the trap layer formed in step S04, at least a part of the N-type region 111 formed in step S04 can be removed. Since the phosphorus impurity has adsorbed a part of the harmful impurities in the P-type polycrystalline germanium substrate 110 in this portion (that is, the step of doping the phosphorus impurity has a function of gettering), the at least a portion of the N-type region 111 is removed. The latter P-type polycrystalline germanium substrate 110 will have less harmful impurities.

如圖2E所示,步驟S08:將N型之多數的第二雜質,摻雜於已被第一次蝕刻的P型多晶矽基板110的第一表面113上,再一次地使P型多晶矽基板110具有N型區域111及P型區域112。於一實施例中,第二雜質可以為磷雜質,並且是在溫度約790℃至約810℃下,利用三氯氧磷(POCl3 ),對P型多晶矽基板110進行磷雜質摻雜。第二次磷摻雜步驟,除了能夠形成N型區域111外,亦具有吸附P型多晶矽基板110中的有害雜質的功能,達到第二次吸雜的效果。此外,於一實施例中,第二雜質亦可以不使用磷雜質,僅要是能形成N型雜質擴散區的N型雜質皆可。As shown in FIG. 2E, step S08: doping a majority of the second impurity of the N-type onto the first surface 113 of the P-type polysilicon substrate 110 that has been etched for the first time, and again making the P-type polysilicon substrate 110 There are an N-type region 111 and a P-type region 112. In one embodiment, the second impurity may be a phosphorus impurity, and the phosphorus impurity doping is performed on the P-type polycrystalline germanium substrate 110 by using phosphorus oxychloride (POCl 3 ) at a temperature of about 790 ° C to about 810 ° C. The second phosphorus doping step, in addition to being able to form the N-type region 111, also has the function of adsorbing harmful impurities in the P-type polycrystalline germanium substrate 110, achieving the effect of the second gettering. In addition, in an embodiment, the second impurity may not use phosphorus impurities, and only N-type impurities capable of forming an N-type impurity diffusion region may be used.

步驟S10:對P型多晶矽基板110的第一表面113進行第二次蝕刻,藉以去除步驟S08所形成的陷阱層。於一實施例中,由於步驟S10僅需達到去除步驟S08所形成的陷阱層的程度即可,因此依實驗的經驗,可以將步驟S10的蝕刻時間設為進行0.5小時。Step S10: performing a second etching on the first surface 113 of the P-type polysilicon substrate 110, thereby removing the trap layer formed in step S08. In an embodiment, since the step S10 only needs to remove the trap layer formed in step S08, the etching time of step S10 can be set to 0.5 hours according to experimental experience.

如圖2F所示,步驟S11:形成一抗反射層120於P型多晶矽基板110上。As shown in FIG. 2F, step S11: forming an anti-reflection layer 120 on the P-type polysilicon substrate 110.

如圖2G所示,步驟S12:形成電連接N型區域111及P型區域112的一電極結構130。As shown in FIG. 2G, step S12: forming an electrode structure 130 electrically connecting the N-type region 111 and the P-type region 112.

於一實施例中,上述的步驟S12可以包含以下步驟。步驟S32:將一第一導電膠形成於第一表面113上。步驟S34:將一第二導電膠形成於第二表面114上。步驟S36:對形成有第一導電膠及第二導電膠的P型多晶矽基板110,進行燒結處理,使第一導電膠被燒結後穿透抗反射層120形成第一電極131;使第二導電膠被燒結後形成第二電極132,且第一電極131及第二電極132互相電連接,形成一個電流迴路。In an embodiment, the foregoing step S12 may include the following steps. Step S32: forming a first conductive paste on the first surface 113. Step S34: forming a second conductive paste on the second surface 114. Step S36: performing a sintering treatment on the P-type polycrystalline germanium substrate 110 on which the first conductive paste and the second conductive paste are formed, so that the first conductive paste is sintered and penetrates the anti-reflective layer 120 to form the first electrode 131; After the glue is sintered, the second electrode 132 is formed, and the first electrode 131 and the second electrode 132 are electrically connected to each other to form a current loop.

請參照圖2H,於一實施例中,太陽能電池製造方法還可以包含步驟14:形成至少一分離溝140,用以分離相鄰的電池盒(cell)。依據上述步驟,即可製得依本發明一實施例之太陽能電池100。Referring to FIG. 2H, in an embodiment, the solar cell manufacturing method may further include the step 14 of forming at least one separation trench 140 for separating adjacent battery cells. According to the above steps, the solar cell 100 according to an embodiment of the present invention can be obtained.

下表一顯示比較例(進行一次吸雜步驟)及本發明一實施例(進行二次吸雜步驟)的實驗結果。Table 1 below shows the experimental results of the comparative example (the one-time gettering step) and the one embodiment of the present invention (the second gettering step).

如上表一所示,進行二次吸雜步驟之實施例的太陽能電池100的光電轉換效率16.132%,優於進行一次吸雜步驟之比較例之太陽能電池的光電轉換效率16.076%。進行二次吸雜步驟之實施例的太陽能電池100的電壓(Voc)值0.619及電流(Isc)值8.234,分別優於進行一次吸雜步驟之比較例之太陽能電池的電壓(Voc)值0.615及電流(Isc)值8.230。其中,電壓值的增加幅度較明顯,可以得知P型多晶矽基板110中少數載子的生命期已有增加,因此能夠得到較好的光電轉換效率。As shown in the above Table 1, the photoelectric conversion efficiency of the solar cell 100 of the embodiment in which the second gettering step was carried out was 16.132%, which was superior to the photoelectric conversion efficiency of the solar cell of the comparative example in which the gettering step was performed, which was 16.076%. The solar cell 100 of the embodiment in which the second gettering step is performed has a voltage (Voc) value of 0.619 and a current (Isc) value of 8.234, which are respectively superior to a voltage (Voc) value of 0.615 of the solar cell of the comparative example in which the gettering step is performed, respectively. The current (Isc) value is 8.230. Among them, the increase of the voltage value is more obvious, and it can be known that the lifetime of a few carriers in the P-type polycrystalline germanium substrate 110 has increased, so that a good photoelectric conversion efficiency can be obtained.

綜上所述,習知太陽能電池的製程中,是利用摻雜磷雜質的方式來形成具有P/N界面的矽晶基板。依上述實驗結果,能夠確定磷雜質具有吸雜(gettering)的功能。因此依本發明一實施例的太陽能電池製造方法,對矽晶基板進行兩次摻雜磷雜質的步驟以及兩次蝕刻步驟(較佳的情況是一次過蝕刻步驟及一次標準蝕刻步驟),能夠有效減少矽晶基板中的有害雜質,進而提升矽晶基板內部少數載子的生命期。結果,能夠提升太陽能電池的電壓(Voc)、電流(Isc)以及光電轉換效率(Ncell)。In summary, in the process of the conventional solar cell, a twinned substrate having a P/N interface is formed by doping phosphorus impurities. Based on the above experimental results, it was confirmed that the phosphorus impurity has a function of gettering. Therefore, in the solar cell manufacturing method according to an embodiment of the present invention, the step of performing the doping of the phosphorus impurity twice on the twinned substrate and the two etching steps (preferably, the one-pass over-etching step and the one-time etching step) can be effective. Reduces harmful impurities in the twinned substrate, thereby increasing the lifetime of minority carriers inside the twinned substrate. As a result, the voltage (Voc), current (Isc), and photoelectric conversion efficiency (Ncell) of the solar cell can be improved.

雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。另外,本發明的任一實施例或申請專利範圍不須達成本發明所揭露之全部目的或優點或特點。此外,摘要部分和標題僅是用來輔助專利文件搜尋之用,並非用來限制本發明之權利範圍。While the present invention has been described in its preferred embodiments, the present invention is not intended to limit the invention, and the present invention may be modified and modified without departing from the spirit and scope of the invention. The scope of protection is subject to the definition of the scope of the patent application. In addition, any of the objects or advantages or features of the present invention are not required to be achieved by any embodiment or application of the invention. In addition, the abstract sections and headings are only used to assist in the search of patent documents and are not intended to limit the scope of the invention.

100...太陽能電池100. . . Solar battery

110...矽晶基板110. . . Twin crystal substrate

111...N型區域111. . . N-type area

112...P型區域112. . . P-type area

113...第一表面113. . . First surface

114...第二表面114. . . Second surface

120...抗反射層120. . . Antireflection layer

130...電極結構130. . . Electrode structure

131...第一電極131. . . First electrode

132...第二電極132. . . Second electrode

140...分離溝140. . . Separation ditch

圖1A至1B顯示依據本發明一實施例之太陽能電池製造方法的流程圖。1A to 1B are flow charts showing a method of fabricating a solar cell according to an embodiment of the present invention.

圖2A至2H顯示依據本發明一實施例之太陽能電池製造方法之各步驟的剖面示意圖。2A to 2H are schematic cross-sectional views showing respective steps of a method of fabricating a solar cell according to an embodiment of the present invention.

Claims (10)

一種太陽能電池製造方法,包含:提供一矽晶基板,且該矽晶基板為第一型並具有一第一表面及一第二表面;將第二型之多數的第一雜質,摻雜於該矽晶基板的該第一表面上;對該矽晶基板的該第一表面進行第一次蝕刻;將第二型之多數的第二雜質,摻雜於已被第一次蝕刻的該矽晶基板的該第一表面上,以形成一第一型區域及一第二型區域;對該矽晶基板的該第一表面進行第二次蝕刻;形成電連接該第一型區域及該第二型區域的一電極結構。A solar cell manufacturing method comprising: providing a twinned substrate, wherein the twinned substrate is of a first type and having a first surface and a second surface; and doping a plurality of first impurities of the second type On the first surface of the twinned substrate; performing a first etching on the first surface of the twinned substrate; doping a second impurity of the second type into the twinned crystal that has been first etched Forming a first type region and a second type region on the first surface of the substrate; performing a second etching on the first surface of the twin crystal substrate; forming an electrical connection between the first type region and the second An electrode structure of the type region. 如申請專利範圍第1項所述之太陽能電池製造方法,其中該對該矽晶基板的該第一表面進行第一次蝕刻的步驟,更對該矽晶基板的該第二表面進行第一次蝕刻。The method for manufacturing a solar cell according to claim 1, wherein the step of performing the first etching on the first surface of the twinned substrate is performed for the first time on the second surface of the twinned substrate. Etching. 如申請專利範圍第2項所述之太陽能電池製造方法,其中該對該矽晶基板的該第一表面進行第二次蝕刻的步驟,更對該矽晶基板的該第二表面進行第二次蝕刻。The method for manufacturing a solar cell according to claim 2, wherein the step of performing the second etching on the first surface of the twinned substrate is performed a second time on the second surface of the twinned substrate. Etching. 如申請專利範圍第1項所述之太陽能電池製造方法,其中該第一雜質的種類相同於該第二雜質的種類。The method of manufacturing a solar cell according to claim 1, wherein the first impurity is of the same type as the second impurity. 如申請專利範圍第4項所述之太陽能電池製造方法,其中該將第二型之多數的第一雜質摻雜於該矽晶基板的該第一表面上的步驟,是在一第一預定溫度下進行,該將第二型之多數的第二雜質,摻雜於已被第一次蝕刻的該矽晶基板的該第一表面上的步驟,是在一第二預定溫度下進行,且該第一預定溫度高於該第二預定溫度。The method for manufacturing a solar cell according to claim 4, wherein the step of doping a plurality of first impurities of the second type on the first surface of the twin crystal substrate is at a first predetermined temperature Performing the step of doping a second impurity of the second type to the first surface of the twinned substrate that has been first etched, at a second predetermined temperature, and The first predetermined temperature is higher than the second predetermined temperature. 如申請專利範圍第5項所述之太陽能電池製造方法,其中該對該矽晶基板的該第一表面進行第一次蝕刻的步驟,進行一第一預定期間,該對該矽晶基板的該第一表面進行第二次蝕刻的步驟,進行一第二預定期間,且該第一預定期間長於該第二預定期間。The method for manufacturing a solar cell according to claim 5, wherein the step of performing the first etching on the first surface of the twinned substrate is performed for a first predetermined period of time, the The step of performing a second etching on the first surface is performed for a second predetermined period, and the first predetermined period is longer than the second predetermined period. 如申請專利範圍第6項所述之太陽能電池製造方法,其中該第一預定期間約三倍於該第二預定期間。The solar cell manufacturing method of claim 6, wherein the first predetermined period is about three times the second predetermined period. 如申請專利範圍第6項所述之太陽能電池製造方法,其中該第一型為P型,而該第二型為N型。The method of manufacturing a solar cell according to claim 6, wherein the first type is a P type and the second type is an N type. 如申請專利範圍第8項所述之太陽能電池製造方法,其中該將第二型之多數的第一雜質摻雜於該矽晶基板的該第一表面上的步驟,是在溫度約800℃至約820℃下,利用三氯氧磷對該矽晶基板進行磷雜質摻雜。The method for manufacturing a solar cell according to claim 8, wherein the step of doping a plurality of first impurities of the second type on the first surface of the twin crystal substrate is at a temperature of about 800 ° C to The twinned substrate was subjected to phosphorus impurity doping at about 820 ° C using phosphorus oxychloride. 如申請專利範圍第9項所述之太陽能電池製造方法,其中該將第二型之多數的第二雜質摻雜於已被第一次蝕刻的該矽晶基板的該第一表面上的步驟,是在溫度約790℃至約810℃下,利用三氯氧磷對該矽晶基板進行磷雜質摻雜。The method of manufacturing a solar cell according to claim 9, wherein the step of doping a second impurity of the second type onto the first surface of the twinned substrate that has been first etched, The twinned substrate is subjected to phosphorus impurity doping at a temperature of about 790 ° C to about 810 ° C using phosphorus oxychloride.
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Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004821A1 (en) * 2007-06-27 2009-01-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of soi substrate and manufacturing method of semiconductor device
TW201001508A (en) * 2008-03-25 2010-01-01 Applied Materials Inc Surface cleaning and texturing process for crystalline solar cells

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090004821A1 (en) * 2007-06-27 2009-01-01 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method of soi substrate and manufacturing method of semiconductor device
TW201001508A (en) * 2008-03-25 2010-01-01 Applied Materials Inc Surface cleaning and texturing process for crystalline solar cells

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