TWI398767B - Electronic system and alarm device thereof - Google Patents

Description

Electronic system and its warning device

The present invention relates to an electronic system and its warning device.

The functional requirements of electronic devices are getting higher and higher, and the number of accessory devices required by them is increasing to meet the requirements of multifunctional functions. An electronic device, usually controlled by a processor, is used as a control unit for driving, controlling, detecting, indicating, warning, and communicating. If the processor fails or is damaged due to external ambiguity, the electronic device cannot control the operation of the peripheral devices around it, such as the inability to control the operation of the heat sink. Heat dissipation, even in severe cases, can cause the electronic device to crash.

In order to improve the above situation, an alarm device is usually disposed in the electronic device to generate a warning signal when the processor generates an error as a reminder, so the warning device has become indispensable in the electronic device. One member.

Referring to FIG. 1 , the conventional electronic system 1 has a warning device 11 , a processor 12 , a client system terminal 13 and an electronic device 14 . The warning device 11 is electrically connected between the processor 12 and the client system 13 , and the processor 12 is electrically connected to the electronic device 14 (eg, a fan) and detects the electronic device 14 . State (for example, the speed of the fan).

Referring to FIG. 2 and FIG. 3 again, generally, the structure of the warning device 11 can be divided into an open drain or an open collector depending on the components used.

When the structure of the warning device 11 is an open-drain circuit, it has a first resistor 111, a second resistor 112, a MOS field-effect transistor 113, a third resistor 114, and a first Capacitor 115. The first resistor 111 and the second resistor 112 are electrically connected to one of the gates of the MOS transistor 113, and the second resistor 112 is further connected to the MOS field-effect transistor 113. A source and a ground are electrically connected. The third resistor 114 and the first capacitor 115 are electrically connected to one of the MOSFETs 113, respectively.

When the structure of the warning device 11 is an open collector circuit, it has a fourth resistor 116, a bipolar junction transistor 117, a fifth resistor 118 and a second capacitor 119. The bipolar junction transistor 117 is electrically connected to the fourth resistor 116, the second capacitor 119 and the fifth resistor 118, and the second capacitor 119 is electrically connected to the fifth resistor 119.

For example, the structure of the warning device 11 is an open-circuit circuit. Referring to FIG. 1 and FIG. 2 simultaneously, the processor 12 detects a sensing signal S01 of the electronic device 14 to generate a state. The signal S02 is caused to cause the warning device 11 to output a warning signal S03 to the client system terminal 13 according to the status signal S02.

The processor 12 detects the sensing signal S01 of the electronic device 14 to generate the status signal S02 of the high level when the electronic device 14 is in a normal state. The state signal S02 of the high level turns the first transistor 113 of the warning device 11 on, and outputs the warning signal S03 of the low level. The client system terminal 13 determines that the processor 12 and the electronic device 14 are in a normal state according to the warning signal S03 of the low level without generating any control on the electronic device 14.

Moreover, when the electronic device 14 is in an abnormal state, the processor 12 detects the sensing signal S01 of the electronic device 14 to generate the status signal S02 of the low level. The state signal S02 of the low level causes the first transistor 113 of the warning device 11 to turn off, and outputs the warning signal S03 of the high level. The client system 13 controls the electronic device 14 to stop operating according to the warning signal S03 of the high level to determine that the processor 12 and the electronic device 14 are in an abnormal state.

In addition, the processor 12 itself may also have an abnormal state, such as an open circuit, a short circuit or a floating connection, and the warning device 11 also generates a warning signal S03. When the processor 12 is in an abnormal state due to a short circuit or a floating connection, the status signal S02 is at a low level, so that the warning device 11 outputs the warning signal S03 of the high level. At this time, the client system Terminal 13 can be informed that the operation is abnormal.

However, when the processor 12 is in an abnormal state due to an open circuit or a high to Vdd state, the status signal S02 is at a high level, so that the warning device 11 outputs the low level warning signal. S03, causing the client system terminal 13 to judge that the processor 12 is still in a normal state, thereby causing misjudgment.

The above-mentioned erroneous determination occurs because the warning device 11 cannot clearly determine which device is in an abnormal state, and the processor 12 cannot effectively control the operation of the electronic device 14, and thus the electronic system 1 may be caused to crash.

Because of this, it has become one of the important topics to provide an electronic system and a warning device that can clearly determine whether the peripheral device is in an abnormal state and immediately issue a warning.

In view of the above problems, an object of the present invention is to provide an electronic system and a warning device capable of clearly determining whether or not a peripheral device is in an abnormal state and immediately issuing a warning.

Therefore, in order to achieve the above object, a warning device according to the present invention includes an isolation circuit, a first enable circuit, a second enable circuit, and an output circuit. In the present invention, the isolation circuit receives and correlates a status signal to generate an adjustment signal. The first enabling circuit is electrically connected to the isolation circuit and receives and according to the adjustment signal to generate a first enable signal. The second enabling circuit is electrically connected to the first enabling circuit and receives and according to the first enabling signal to generate a second enabling signal. The output circuit is electrically connected to the second enabling circuit and receives and outputs a warning signal according to the second enabling signal.

To achieve the above object, an electronic system in accordance with the present invention includes a processor, a warning device, and a system device. In the present invention, the warning device is electrically connected to the processor and receives and responds to a pulse signal or a continuous signal to generate a low level or high level warning signal. The system device is electrically connected to the warning device and the processor respectively to receive and generate a control signal to the processor according to the warning signal.

As described above, the electronic system of the present invention utilizes the warning device having the isolation circuit, the first enabling circuit, the second enabling circuit, and the output circuit, and receives and according to the first state The signal and/or the second status signal is the pulse signal or the DC signal to generate the warning signal. In this way, not only can the system device easily determine the current state of the peripheral device and the processor according to the warning signal, but also when the abnormal state occurs, whether in an open circuit, a short circuit or a floating state. The warning signal is correctly issued to immediately stop the operation of the processor or the peripheral device, so as to avoid damage or crash caused by the processor continuing to operate in an abnormal state due to misjudgment, thereby improving the overall quality.

An electronic system and its warning device in accordance with a preferred embodiment of the present invention will now be described with reference to the associated drawings.

Referring to FIG. 4, the electronic system 2 of the first preferred embodiment of the present invention includes a processor 21, a warning device 22, and a system device 23. In addition, the electronic system 2 further includes an electronic device 24.

In this embodiment, the processor 21 is electrically connected to the warning device 22, and generates a first state signal S11, and the first state signal S11 can be a pulse signal or a continuous signal. When the first state signal S11 is the pulse signal, the frequency is 200 Hz or more. The first status signal S11 is determined as the pulse signal or the DC signal according to the state of the processor 21 itself. When the state of the processor 21 is normal, the first state signal S11 is the pulse signal, and when the processor 21 is floating, short or open. In the state of (open), the first state signal S11 is the DC signal as an example. In addition, the processor 21 is implemented as a microcontroller or a microprocessor chip.

Please refer to FIG. 4 and FIG. 5 at the same time, wherein FIG. 5 shows another electronic system 2A of connection relationship. The electronic device 24 of the present embodiment is not limited to the connection between the processor 21 and the warning device 22, and the processor 21 can be electrically connected to the electronic device 24 and the warning device 22 in practice. The electronic device 24 and the processor 21 can be directly electrically connected to the warning device 22 (as shown in FIG. 5).

When the processor 21 is electrically connected between the electronic device 24 and the warning device 22, the processor 21 detects the state of the electronic device 24, for example, sensing the electronic device 24 to obtain a sensing. The signal SE is generated according to the sensing signal SE to generate a second state signal S12 (as shown in FIG. 4); when the electronic device 24 and the processor 21 are electrically connected to the warning device 22, respectively The warning device 22 receives the first status signal S11 output by the processor and the second status signal S12 outputted by the electronic device 24 (as shown in FIG. 5). Here, the processor 21 is electrically connected between the electronic device 24 and the warning device 22 as an example.

Referring to FIG. 4 and FIG. 5 simultaneously, the electronic device 24 of the embodiment may be a fan device, a sensing device, a power supply device, a communication device, and a flat display. A device, a pointing device or a pressure indicating device. Of course, the electronic system 2 can include the above-mentioned electronic devices 24 (not shown), and even the plurality of electronic devices 24 included in the electronic system 2 are the same device. For example, the electronic devices 24 are all The fan unit. The electronic device 24 is the fan device, and the processor 21 is configured to detect the rotation speed of the motor in the fan device to generate the second state signal S12 (as shown in FIG. 4). ).

Referring to FIG. 4 and FIG. 5 simultaneously, in the embodiment, the second state signal S12 generated by the electronic device 24 is sensed by the processor 21, or the electronic device 24 generates the first The second state signal S12 has the same features and functions as the first state signal S11, and therefore will not be described again. The second status signal S12 is different from the first status signal S11 in that the second status signal S12 is determined as the pulse signal or the direct current signal according to the state of the electronic device 24, so When the electronic device 24 is in a normal operating state, the second state signal S12 is the pulse wave signal; when the electronic device 24 is in an abnormal operating state, for example, when the circuit is open, shorted or floated, the second state signal S12 is the DC signal. The signal is an example.

Please refer to FIG. 4 and FIG. 6 at the same time. FIG. 6 is an equivalent circuit diagram of the warning device 22 of FIG. 4. The warning device 22 of the embodiment has an isolation circuit 221 and a first The matching circuit 222, a second enabling circuit 223 and an output circuit 224.

In the embodiment, the isolation circuit 221 has a capacitor C1. The one end of the capacitor C1 is electrically connected to the processor 21, and the other end is electrically connected to the warning device 22 to receive the first state signal S11 and the second state signal S12, respectively. The isolation circuit 221 generates an adjustment signal S13 according to the first state signal S11 and the second state signal S12.

The first enabling circuit 222 is electrically connected to the isolation circuit 221 and receives and according to the adjustment signal S13 to generate a first enabling signal S14. The first enable signal S14 of the embodiment has a low level or a high level.

In addition, as shown in FIG. 6, the first enabling circuit 222 has a first resistor R1, a second resistor R2, a first transistor Q1, and a second transistor Q2.

One end of the first resistor R1 is electrically connected to the other end of the capacitor C1 of the isolation circuit 221, and the other end of the first resistor R1 is grounded. One end of the second resistor R2 is electrically connected to a power source V, and the other end of the second resistor R2 is electrically connected to the first pole of the first transistor Q1. The gate of the first transistor Q1 is electrically connected to the terminal of the first resistor R1, and receives the adjustment signal S13, and the source of the first transistor Q1 is grounded. The base of the second transistor Q2 is electrically connected to the other end of the second resistor R2 and the first transistor Q1, and the emitter of the second transistor Q2 is grounded. The collector of the second transistor Q2 generates the first enable signal S14.

In the embodiment, the first transistor Q1 and the second transistor Q2 are respectively a metal oxide half field effect transistor (MOSFET) and a bipolar junction transistor (BJT).

Referring to FIG. 4 again, in the embodiment, the second enabling circuit 223 is electrically connected to the first enabling circuit 222, and receives and according to the first enabling signal S14 to generate a first The second signal is S15. The output circuit 224 receives and outputs the warning signal S16 according to the second enable signal S15. The second enabling circuit 223 of the embodiment may be a R-C adjustable integrator, and the second enabling signal S15 has a high level or a low level. Level.

Referring to FIG. 6 again, in the embodiment, the second enabling circuit 223 has a third resistor R3, a fourth resistor R4, a diode D1, and a first capacitor C2. One end of the third resistor R3 is electrically connected to the power source V, and the other end of the third resistor R3 is electrically connected to the first enabling circuit 222 and receives the first enabling signal S14. One end of the diode D1 is electrically connected to the other end of the third resistor R3. One end of the first capacitor C2 is electrically connected to the other end of the diode D1 and one end of the fourth resistor R4 to generate the second enable signal S15, and the other end of the first capacitor C2 And the other end of the fourth resistor R4 is grounded. The diode D1 of this embodiment is for preventing the current in the second enabling circuit 223 from flowing back to the third resistor R3.

The output circuit 224 has a fifth resistor R5, a third transistor Q3, and a second capacitor C3. One end of the fifth resistor R5 is electrically connected to the power source V. The gate of the third transistor Q3 is electrically connected to the second enabling circuit 223 to receive the second enabling signal S15. The drain of the third transistor Q3 is electrically connected to the other end of the fifth resistor R5, and the warning signal S16 is generated. The source of the third transistor Q3 is grounded. One end of the second capacitor C3 is electrically connected to the anode of the third transistor Q3, and the other end of the second capacitor C3 is grounded. The third transistor Q3 of the embodiment is implemented as a metal oxide half field effect transistor (MOSFET), and the warning signal S16 has a high level or a low level.

In addition, the isolation circuit 221, the first enabling circuit 222, the second enabling circuit 223, and the output circuit 224 of the warning device 22 of the embodiment may be disposed in a controller. That is, the internal components of the warning device 22 are fabricated in a modular manner, such as but not limited to a digital controller, a programmable controller, or a microprocessor.

The system device 23 of the embodiment is electrically connected to the warning device 22 and the processor 21 respectively to receive and generate a control signal S17 to the processor 21 according to the warning signal S16. The system device 23 is implemented in the client system.

Please refer to FIG. 4 and FIG. 6 at the same time, and the following will describe the operation of the electronic system 2. The operation is as follows: when the electronic system 2 is in a normal operating state, the processor 21 generates the first status signal S11, and detects the electronic device 24 to generate the second status signal S12. The status signal S11 and the second status signal S12 are respectively the pulse signal.

The isolation circuit 221 of the warning device 22 receives and adjusts the signal S1 according to the first state signal S11 to generate an adjustment signal S13. In the first enabling circuit 222, the gate of the first transistor Q1 receives and turns on the first transistor Q1 according to the adjusting signal S13, and the drain of the first transistor Q1 is low. The bit signal is to the second transistor, so that the second transistor Q2 is not turned on. At this time, the collector of the second transistor Q2 outputs the first enable signal S14 of the high level. The second enabling circuit 223 charges the first capacitor C2 through the third resistor R3 according to the first enabling signal S14, and outputs the second enabling signal of the high level. S15 to the output circuit 224. The third transistor Q3 of the output circuit 224 is turned on according to the second enable signal S15, so the drain signal of the third transistor Q3 outputs the low level of the warning signal S16.

At this time, since the warning signal S16 is at a low level, the system device 23 receives and according to the warning signal S16, the processor 21 and the electronic device 24 are all operating normally, and the system device 23 maintains the generation. The signal S17 is controlled to the processor 21, and the processor 21 and the electronic device 24 continue to operate.

Referring to FIG. 4 and FIG. 6 simultaneously, when the processor 21 and the electronic device 24 of the electronic system 2 or one of the electronic devices 24 are in an abnormal state, the electronic system 2 is activated as follows: In this case, the electronic device 24 is in an abnormal state, and the processor 21 is in a normal state. Since the processor 21 is in a normal state, the operation mode of the electronic system 2 has been discussed in the above embodiment. I will not repeat them.

When the electronic device 24 is in an abnormal state, the processor 21 detects the electronic device 24 to generate the second state signal S12 as the DC signal to the isolation circuit 221. At this time, the isolation circuit 221 isolates the second state signal S12 by the capacitor C1 to generate the low level adjustment signal S13. The first transistor Q1 of the first enabling circuit 222 is not turned on according to the adjustment signal S13 of the low level. At this time, the second transistor Q2 receives the power source V via the second resistor R2. Turning on, and outputting the first enable signal S14 of the low level to the drain of the second transistor Q2. The second enabling circuit 223 receives the first enabling signal S14, and at this time, the first capacitor C2 discharges the fourth resistor R4. The output circuit 224 cannot turn on the third transistor Q3 due to the second enable signal S15. Therefore, the fifth resistor R5 charges the second capacitor C3 to output the warning signal S16 of the high level.

At this time, the system device 23 receives and detects that the electronic device 24 is abnormal according to the warning signal S16, so the system device 23 generates the control signal S17 to the processor 21 to control the electronic device 24 to stop operating. In order to prevent the electronic device 24 from causing damage when the device continues to operate or to cause the electronic system 2 to crash. Of course, the system device 23 can also be electrically connected to the electronic device 24, so that the electronic device 24 stops operating according to the control signal S17.

In addition, the electronic system 2 can determine, according to the first state signal S11 and/or the second state signal S12, the warning device 22 to determine which device is in a normal or abnormal state, and in an abnormal state, the system The device 23 can immediately output the control signal S17 to stop the operation of the processor 21 or the electronic device 24.

In summary, the electronic system of the present invention is electrically connected to the warning device between the processor and the system device or between the electronic device and the system device, and the processor generates the first status signal. The warning device receives and generates the warning signal according to the first status signal and/or the second status signal obtained from the electronic device, and the system device generates the control signal according to the warning signal. To the processor.

In contrast to the prior art, the present invention utilizes the warning device having the isolation circuit, the first enabling circuit, the second enabling circuit, and the output circuit, and receives and according to the first state signal and / or the second status signal is the pulse signal or the DC signal to generate the warning signal. In this way, the system device can easily determine the current state of the processor and the electronic device according to the warning signal, and can be in an open state, a short circuit or a floating state when an abnormal state occurs. Correctly issue a warning signal to immediately stop the operation of the processor or the electronic device to avoid damage or downtime caused by the processor or the electronic device continuing to operate in an abnormal state due to misjudgment, thereby improving the overall Quality.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1, 2, 2A. . . electronic system

11, 22. . . Warning device

111, R1. . . First resistor

112, R2. . . Second resistor

113, Q1. . . First transistor

114, R3. . . Third resistor

115, C2. . . First capacitor

116, R4. . . Fourth resistor

117, Q2. . . Second transistor

118, R5. . . Fifth resistor

119, C3. . . Second capacitor

12, 21. . . processor

13. . . Client system side

14, 24. . . Electronic device

221. . . Isolation circuit

222. . . First uniform circuit

223. . . Second enabling circuit

224. . . Output circuit

twenty three. . . System device

C1. . . Capacitor

D1. . . Dipole

Q3. . . Third transistor

S01, SE. . . Sense signal

S03, S16. . . Warning signal

S02. . . Status signal

S11. . . First state signal

S12. . . Second status signal

S13. . . Adjustment signal

S14. . . First consistent signal

S15. . . Second enable signal

S17. . . Control signal

1 is a schematic diagram of an electronic system of the prior art; FIG. 2 is a schematic diagram of an equivalent circuit of the opening circuit of the warning device of the conventional electronic system; and FIG. 3 is an open collector circuit of the warning device of the conventional electronic system. FIG. 4 is a schematic diagram of an electronic system according to a preferred embodiment of the present invention; FIG. 5 is a schematic diagram of another electronic system according to a preferred embodiment of the present invention; and FIG. An equivalent circuit diagram of a warning device of an electronic system of the preferred embodiment of the invention.

2. . . electronic system

twenty one. . . processor

twenty two. . . Warning device

221. . . Isolation circuit

222. . . First uniform circuit

223. . . Second enabling circuit

224. . . Output circuit

twenty three. . . System device

twenty four. . . Electronic device

S11. . . First state signal

S12. . . Second status signal

S13. . . Adjustment signal

S14. . . First consistent signal

S15. . . Second enable signal

S16. . . Warning signal

S17. . . Control signal

SE. . . Sense signal

Claims (32)

A warning device for detecting a processor and an electronic device, comprising: an isolating circuit for receiving and adjusting a signal according to a status signal of the processor and the electronic device, wherein the status signal is a pulse signal Or a continuous signal; a first enabling circuit is electrically connected to the isolating circuit, and receives and according to the adjusting signal to generate a first enabling signal; a second enabling circuit is associated with the first The circuit is electrically connected, and receives and according to the first enable signal to generate a second enable signal; and an output circuit electrically connected to the second enable circuit, and receives and according to the second The signal can be output to output a warning signal. The warning device of claim 1, wherein the isolation circuit has a capacitor. The warning device of claim 1, wherein the pulse signal has a frequency of 200 Hz or more. The warning device of claim 1, wherein the first enable signal or the second enable signal has a low level or a high level. The warning device of claim 1, wherein the first enabling circuit further comprises: a first resistor electrically connected to the isolation circuit at one end and grounded at the other end; a second resistor One end of the device is electrically connected to a power source; a first transistor, wherein a gate is electrically connected to the end of the first resistor to receive the adjustment signal, and a drain is electrically connected to the other end of the second resistor, and a source thereof a pole is grounded; and a second transistor is electrically connected to the other end of the second resistor and the first pole of the first transistor, and an emitter is grounded, and an episode thereof The pole system generates the first enable signal. The warning device of claim 5, wherein the first electro-crystalline system is a metal oxide half field effect transistor. The warning device of claim 5, wherein the second electro-crystalline system is a bipolar junction transistor. The warning device of claim 1, wherein the second enabling circuit is a resistance-capacitor adjustable integrator. The warning device of claim 1, wherein the second enabling circuit comprises: a third resistor, one end of which is electrically connected to a power source, and the other end of which is coupled to the first enabling circuit. Electrically connected to receive the first enable signal; a diode having one end electrically connected to the other end of the third resistor; a fourth resistor having one end grounded; and a first capacitor One end of the second resistor is electrically connected to the other end of the diode and the other end of the fourth resistor to generate the second enable signal, and the other end is grounded. The warning device of claim 1, wherein the output circuit comprises: a fifth resistor, one end of which is electrically connected to a power source; a third transistor, a gate and the second The enabling circuit is electrically connected to receive the second enable signal, wherein a drain is electrically connected to the other end of the fifth resistor to generate the warning signal, a source is grounded, and a second capacitor is One end of the third transistor is electrically connected to one end of the third transistor, and the other end is grounded. The warning device of claim 10, wherein the third electro-crystalline system is a metal oxide half field effect transistor. The warning device of claim 1, wherein the warning signal has a high level or a low level. The warning device of claim 1, wherein the isolation circuit, the first enabling circuit, the second enabling circuit, and the output circuit are integrated in a controller. The warning device of claim 13, wherein the controller is a digital controller, a programmable controller or a microprocessor. An electronic system comprising: a processor for generating a pulse signal or a continuous stream signal; a warning device electrically connected to the processor and receiving and responding to the pulse signal or the DC signal to generate a low Warning signal at a high or high level; and A system device is electrically connected to the warning device and the processor to receive and generate a control signal to the processor according to the warning signal. The electronic system of claim 15, wherein the pulse signal has a frequency of 200 Hz or more. The electronic system of claim 15 further comprising an electronic device electrically connected to the warning device and the processor, or the processor is electrically connected to the electronic device and the warning device And generate the pulse signal or the DC signal. The electronic system of claim 17, wherein the electronic device is a fan device, a sensing device, a power supply device, a communication device, a flat display device, a pointing device or a pressure indicating device . The electronic system of claim 15, wherein the warning device has an isolation circuit, a first enabling circuit, a second enabling circuit, and an output circuit, wherein the isolating circuit receives and a pulse signal or the DC signal to generate an adjustment signal, the first enabling circuit is electrically connected to the isolation circuit, and receives and according to the adjustment signal to generate a first enable signal, the second enable circuit Electrically connecting with the first enabling circuit, and receiving and according to the first enabling signal to generate a second enabling signal, the output circuit is electrically connected to the second enabling circuit, and received and received The second enable signal outputs the warning signal. The electronic system of claim 19, wherein the isolating circuit has a capacitor. The electronic system of claim 20, wherein the first enable signal or the second enable signal has a low level or a high level. The electronic system of claim 20, wherein the first enabling circuit further comprises: a first resistor, one end of which is electrically connected to the isolation circuit, and the other end of which is grounded; a second resistor One end of the first transistor is electrically connected to a power source; a first transistor is electrically connected to the end of the first resistor to receive the adjustment signal, and one of the gates and the second The other end of the resistor is electrically connected, one of the sources is grounded; and a second transistor has a base respectively connected to the other end of the second resistor and the first polarity of the first transistor The connection is such that an emitter is grounded, and an collector system generates the first enable signal. The electronic system of claim 22, wherein the first electro-crystalline system is a gold-oxygen half field effect transistor. The electronic system of claim 22, wherein the second electro-crystalline system is a bipolar junction transistor. The electronic system of claim 20, wherein the second enabling circuit is a resistance-capacitor adjustable integrator. An electronic system as claimed in claim 20, wherein the The second enabling circuit includes: a third resistor, one end of which is electrically connected to a power source, and the other end of which is electrically connected to the first enabling circuit to receive the first enable signal; a body having one end electrically connected to the other end of the third resistor; a fourth resistor having the other end grounded; and a first capacitor having one end and the other end of the diode One end of the fourth resistor is electrically connected to generate the second enable signal, and the other end is grounded. The electronic system of claim 20, wherein the output circuit comprises: a fifth resistor, one end of which is electrically connected to a power source; a third transistor, a gate system and the second The enabling circuit is electrically connected to receive the second enable signal, and a drain is electrically connected to the other end of the fifth resistor to generate the warning signal, a source is grounded; and a second The capacitor has one end electrically connected to the drain of the third transistor and the other end of which is grounded. The electronic system of claim 27, wherein the third electro-crystalline system is a gold-oxygen half field effect transistor. The electronic system of claim 15, wherein the warning signal has a high level or a low level. An electronic system as claimed in claim 15 wherein the The processor is a microcontroller or a microprocessor chip. The electronic system of claim 20, wherein the isolation circuit, the first enabling circuit, the second enabling circuit, and the output circuit are integrated in a controller. The electronic system of claim 31, wherein the controller is a digital controller, a programmable controller or a microprocessor.