TWI394043B - Method of handling successive bitstream extraction and packing and related device - Google Patents

Description

Method for continuously capturing and packaging bits and related devices

The invention relates to a method and a related device for processing a bit data stream, in particular to a method and a related device for efficiently extracting and packaging a bit data stream.

Bitstreams can be applied to many different kinds of fields, such as multimedia file streaming or network streaming. Traditional operations of bitstreams include extraction and packing. For example, bitstream stream capture can be used to play a stream of sound files, and bitstream stream wrappers can be used to encode streaming sound files.

To continuously retrieve a bit from a bit stream in a memory, a series of operations/instructions need to be performed in accordance with the fetch conditions. The bits to be retrieved are stored in a bitstream storage register (BSR), and the retrieved bits are stored in a destination register (DR). Once all the bits in the bit stream storage buffer BSR have been retrieved, the memory will write the new bit (eg 32 bits) into the space vacated in the bit stream storage buffer BSR. . The position of the position register memory (starting position, SP) indicates the starting point of the bit extraction, and the length register of the length register (length of extraction, LE) Then the number of bits extracted from the BSR is indicated. For example, the value of the starting position SP may be between 1 and 32, and the value of the drawing length LE may be between 1 and 32. According to the relationship between the starting position SP and the capturing length LE, there are three different situations: "SP>LE", "SP=LE" and "SP<LE".

Figure 13 illustrates the manner in which the prior art retrieved bits in the first case "SP > LE". When the starting position SP is greater than the capturing length LE, the bit stream storage buffer BSR contains all the bits to be retrieved, and remains in the bit stream storage buffer BSR after the retrieval. There are untaken bits. In this case, the bit stream storage scratchpad BSR is translated (32-SP) bits to the left, and the in-process results are temporarily stored in the target register DR. Then, the result of the target scratchpad DR memory is shifted to the right (32-LE) bits, and the final captured result is written to the target register DR. Finally, the value of the location register is updated to the starting position SP minus the value of the retrieval length LE (SP-LE). The example instruction program 1300 shown in Fig. 13 illustrates the operation at "SP>LE".

Figure 14 illustrates the manner in which the prior art retrieved bits in the second case "SP = LE". When the starting position SP is equal to the capturing length LE, the bit stream storage buffer BSR contains all the bits to be retrieved, and there is no bit in the bit stream storage register BSR after the retrieval. Other untaken bit data. In this case, the bit stream storage scratchpad BSR is translated (32-SP) bits to the left, and the in-process results are temporarily stored in the target register DR. Then, the result of the target scratchpad DR memory is shifted to the right (32-SP) bits, and the final result is written to the target register DR. At the same time, the value of the location register will be updated to 32. Since all the bits in the bit stream storage buffer BSR have been retrieved, the memory will write the new 32 bits into the bit stream storage buffer BSR. The operation of the example instruction program 1400 shown in Fig. 14 at "SP = LE".

Figure 15 illustrates the manner in which the prior art retrieved bits in the third scenario "SP < LE". When the starting position SP is smaller than the capturing length LE, the bit stream storage buffer BSR does not include all the bits to be captured. This boundary condition is called "underflow". In this case, the bit stream storage scratchpad BSR is translated (32-SP) bits to the left, and the in-process results are temporarily stored in the target register DR. Next, the result of the target scratchpad DR memory is translated (32-LE) bits and the new in-process result is temporarily stored in the target register DR. At the same time, the value of the location register is updated to 32, and the value of the location register is updated to the length of the capture LE minus the value of the start position SP (LE-SP). Since the bits in the scratchpad BSR have all been fetched, the memory will write the new 32 bits into the bit stream storage scratchpad BSR. Then, the remaining bits are captured to a temporary register TR. After performing a logical OR (logic OR) operation on the data of the target scratchpad DR and the temporary scratchpad TR memory, the final captured result is written to the target register DR. The example indicating program 1500 shown in Fig. 15 illustrates the operation at "SP < LE".

To continuously wrap a bit into a bit stream in a memory, a series of operations/instructions need to be performed depending on the packaging conditions. The packaging data of a source register (SR) is recorded in a metadata stream storage register BSR. When the space of the bit stream storage buffer BSR is full, the bit stream is temporarily stored. The memory data of the BSR will be stored in the memory. The position register memory has a starting position SP, and the length register memory has a length of packing (LE). For example, the value of the starting position SP may be between 1 and 32, and the value of the package length LE may be between 1 and 32. According to the relationship between the starting position SP and the package length LE, there are three different situations: "SP>LE", "SP=LE" and "SP<LE".

Figure 16 illustrates the manner in which the prior art wraps the bit in the first case "SP > LE". When the starting position SP is greater than the package length LE, the bit stream storage buffer BSR may include all the bits to be packaged, and the packaged bit stream may still be packaged in the bit stream storage buffer BSR. More bits. In this case, the source register SR is shifted to the left (SP-LE) bits and the in-process results are temporarily stored in the source register SR. Then, after performing a logical OR operation on the data of the bit stream storage buffer BSR and the source register SR memory, the final package result is written into the bit stream storage register BSR. On the other hand, the value of the location register is updated to the starting position SP minus the value of the package length LE (SP-LE). The example instruction program 1600 shown in Fig. 16 illustrates the operation at "SP>LE".

Figure 17 illustrates the manner in which the prior art wraps the bit in the second case "SP = LE". When the starting position SP is equal to the package length LE, the bit stream storage buffer BSR may include all the bits to be packaged, and there is not much in the bit stream storage buffer BSR after packaging. The location can be repackaged. In this case, first perform a logical OR operation on the data of the bit stream storage buffer BSR and the source register SR memory, and then write the final package result into the bit stream storage register BSR. On the other hand, the value of the location register is updated to 32. After the data of the bit stream storage buffer BSR is stored in the memory, the value of the bit stream storage register BSR is updated to 0 to prepare for subsequent packaging. The example indicating program 1700 shown in Fig. 17 illustrates the operation at "SP=LE".

Figure 18 illustrates the manner in which the prior art wraps the bit in the third scenario "SP < LE". When the starting position SP is smaller than the package length LE, there is not enough space in the bit stream storage register BSR to contain all the bits to be packaged, so the packaging process needs to be carried out in two stages. The boundary condition is called "overflow". In this case, the source register SR is translated to the right (LE-SP) bits and the result of the process is temporarily stored in a temporary register (TR). Then, after performing a logical OR operation on the data of the bit stream storage buffer BSR and the temporary register TR memory, the final result is written into the bit stream storage buffer BSR. After the data of the bit stream storage buffer BSR is stored in the memory, the source register SR is translated to the right (32-LE+SP) bits, and the final result is written into the bit stream. Store the scratchpad BSR. On the other hand, the value of the location register is updated to (32-LE+SP). The example instruction program 1800 shown in Fig. 18 illustrates the operation of "SP<LE".

As shown in Figure 8, a MIPS DSP-specific application extension technique provides instructions for fetching 1 to 32 bits from a 64-bit scratchpad, but does not provide a bit number of more than 64 bits when the data is retrieved. The processing method of the bit time. On the other hand, U.S. Patent No. 7,334,116 B2 (hereinafter referred to as "previously referred to as 116") uses a 64-bit buffer and individual left/right translation operations to stream from one bit of a memory. Take a specific number of bits. However, the pre-116 case cannot effectively handle boundary conditions such as "data under-subscription" and "data overflow", and the bit length of the buffer needs to be larger than the position boundary length of the memory. The prior art cannot effectively handle boundary conditions such as "data underrun" and "data overflow" of the bit stream/capture, which reduces system efficiency.

The present invention provides a method for extracting a bit from a bit stream buffer, comprising: when the predetermined start position is greater than a predetermined draw length, the predetermined order from the bit stream register The starting position begins to capture a predetermined number of bits, wherein the predetermined number and the predetermined drawing length have the same value; the bits are stored in a lowest bit portion of a target register; when no data In the case of an under-position, setting a high-order portion of one of the un-stored bits in the target register to a predetermined value; clearing an empty flag and a data under-flag setting; and subtracting the predetermined starting position A predetermined number of values to update the predetermined starting position.

The present invention further provides a method for extracting a bit from a bit stream buffer, comprising: when a predetermined start position is equal to a predetermined draw length, from the bit stream register Determining a starting position to obtain a predetermined number of bits, wherein the predetermined number and the predetermined drawing length have the same value; storing the bits in a lowest bit portion of a target register; When the data is under-subscribed, the high-order part of one of the un-stored bits in the target register is set to a predetermined value; an empty flag is set to indicate that all the bit data in the bit stream register has been captured. And clearing a data underrun flag; and updating the predetermined starting location to a predetermined bit in the bit stream register to prepare for the next acquisition.

The present invention further provides a method for extracting a bit from a bit stream buffer, comprising: when a predetermined starting position is less than a predetermined draw length, from the bit stream register Determining a starting position to start capturing a predetermined number of bits, wherein the predetermined number and the predetermined starting position have the same value; adding one after the bits extracted from the bit stream register a predetermined number of buffer bits to increase the number of bits to the predetermined capture length; starting from a position that is the same as the predetermined capture length, storing the bits in a target temporary register a bit portion; when a data under-count flag is not set, setting a high-order portion of one of the un-stored bits in the target register to a predetermined value; updating the predetermined starting position to the bit data Predetermining a bit in the stream register to prepare for the next capture; updating the predetermined draw length by using the predetermined draw length minus the predetermined start position; and setting the data under flag and An empty flag.

The present invention further provides a method for extracting a bit from a bit stream buffer, which includes one of the most effective ones from the bit stream register when a data under flag has been set. The bit begins to retrieve a predetermined number of bits, wherein the predetermined number of values is equal to the previous value of the previous predetermined draw length minus a previous start position; storing the bits in a target temporary storage One of the lowest bit parts in the device; and the setting of clearing the data under-counter flag and an empty flag.

The present invention further provides a method for extracting a bit from a bit stream buffer, comprising: when a predetermined start position is greater than a predetermined draw length, from the bit stream register Determining a starting position to obtain a predetermined number of bits, wherein the predetermined number and the predetermined drawing length have the same value; storing the bits in a lowest bit portion of a target register; When the data is under-subscribed, the high-order portion of one of the un-stored bits in the target register is set to a predetermined value; the setting of an empty flag and a data under-flag is cleared; and the predetermined starting position is used to subtract the a predetermined number of values to update the predetermined starting position; when the predetermined starting position is equal to the predetermined drawn length, the predetermined number of bits is taken from the predetermined starting position in the bit stream register a unit, wherein the predetermined number and the predetermined draw length have the same value; the bits are stored in the lowest bit portion of the target register; when no data is under-ordered, the target register is The high-order portion of the unstored bit is set to the predetermined Setting an empty flag to indicate that all the bit data in the bit stream buffer has been retrieved, and clearing a data under flag; updating the predetermined starting position to the bit stream register One of the predetermined bits is prepared for the next capture; when the predetermined start position is less than the predetermined draw length, a predetermined number is taken from the predetermined start position in the bit stream register a bit, wherein the predetermined number and the predetermined starting position have the same value; adding a predetermined number of buffer bits after adding the bits from the bit stream register to increase a number of bits up to the predetermined length; starting from a position that is the same as the predetermined length, storing the bits in the lowest bit portion of the target register; when a data is under banner When the target is not set, the high-order portion of the unstored bit in the target register is set to the predetermined value; and the predetermined starting position is updated to the predetermined bit in the bit stream register In order to prepare for the next capture; use the predetermined draw length minus The predetermined starting position value is updated to update the predetermined drawing length; an empty flag and the data under-counting flag are set; when the data under-authing flag has been set, one of the bit stream registers is The most significant bit begins to retrieve the predetermined number of bits, wherein the predetermined number of values is equal to the previous value of the previous predetermined acquisition minus a previous starting position; the bits are stored in the target The lowest bit portion in the memory; and the setting of clearing the data under-flag and an empty flag.

The present invention further provides a method of packaging a bit into a one-bit data stream register, comprising: starting from a lowest bit portion of one of the source registers when a predetermined starting position is greater than a predetermined package length Packaging a predetermined number of bits, wherein the predetermined number and the predetermined package length have the same value; starting from the predetermined starting position, storing the bits in the bit stream register; clearing a full flag And a data overflow flag; and updating the predetermined starting position by using the predetermined starting position minus the value of the predetermined package length.

The present invention further provides a method of packaging a bit into a one-bit data stream register, comprising: starting from a lowest bit portion of one of the source registers when a predetermined starting position is equal to a predetermined package length Packaging a predetermined number of bits, wherein the predetermined number and the predetermined package length have the same value; from the predetermined starting position, the bits are stored in the bit stream register; setting a full flag And clearing a data overflow flag; and updating the predetermined starting position to one of the most significant bits of the bit stream register.

The present invention further provides a method of packaging a bit into a one-bit data stream register, comprising: starting from a lowest bit portion of one of the source registers when a predetermined starting position is less than a predetermined package length Packaging a predetermined number of bits, wherein the predetermined number and the predetermined starting position have the same value; starting from the predetermined starting position, storing the bits in the bit stream register; setting a full a flag and a data overflow flag; updating the predetermined starting position to one of the most significant bits of the bit stream register; and updating the value by using the predetermined package length minus the predetermined starting position The predetermined package length.

The present invention further provides a method of packaging a bit into a one-bit data stream register, comprising: starting from a lowest bit portion of one of the source registers when a predetermined starting position is greater than a predetermined package length Packaging a predetermined number of bits, wherein the predetermined number and the predetermined package length have the same value; starting from the predetermined starting position, storing the bits in the bit stream register; clearing a full flag And a data overflow flag; updating the predetermined starting position by subtracting the predetermined starting position from the predetermined starting position; and when the predetermined starting position is equal to the predetermined package length, from the source register One of the lowest bit portions begins to package the predetermined number of bits, wherein the predetermined number and the predetermined package length have the same value; from the predetermined starting position, the bits are stored in the bit stream temporary Setting the full flag and clearing the data overflow flag; updating the predetermined starting position to one of the most significant bits of the bit stream register; when the predetermined starting position is less than the predetermined package length Decapsulating the predetermined number of bits from the lowest bit portion of the source register, wherein the predetermined number and the predetermined starting position have the same value; starting from the predetermined starting position, storing the bits Entering the bit stream register; setting the full flag and the data overflow flag; updating the predetermined starting position to the most significant bit of the bit stream register; and using the The predetermined package length is updated by subtracting the predetermined package start value from the predetermined package length.

The invention further provides a bit data stream capture device, which comprises a one-bit data stream register for storing data; a shifter will temporarily stream from the bit data according to a difference result. The data retrieved by the memory is subjected to shift processing; a target register is used to store the data shifted by the shifter; a start position register is used to store a starting position; a memory for storing a length of the capture; an arithmetic logic unit for comparing the start position and the length of the capture to generate a comparison result, and for generating the basis according to the start position and the length of the capture a difference result; and a control logic for updating the starting position, updating the captured length, and controlling a left/right shifting direction of the shifter based on the comparison result.

The present invention further provides a bit data stream packaging device, comprising a source register for storing package data; a shifter for moving data packaged from the source register according to a difference result Bit processing; a meta data stream register for storing data shifted by the shifter; a start position register for storing a starting position; a package length register for storing a package length; an arithmetic logic unit for comparing the starting position and the length of the package to produce a comparison result, and for generating the difference result according to the starting position and the length of the package; and a control logic for The package length is updated according to the comparison result, the start position is updated, and the left/right shift direction of the shifter is controlled.

Figs. 1 to 4 and Fig. 9 illustrate a method of extracting bits from a bit stream stream register (BSR) Ra in the first embodiment of the present invention. As shown in FIGS. 1 to 4, the bit stream register scratcher Ra may include 32 bits, such as 0 to 31. The bit of the bit stream register scratcher Ra can be retrieved and stored to a target register (DR) Rt. A configuration register Rb can store a predetermined draw length (LE) in Rb (4, 0), a predetermined starting position (SP) into Rb (9, 5), and an empty flag. The empty flag is stored in Rb (13), and an underflow flag is stored in Rb (31). Of course, the predetermined retrieval length LE, the predetermined starting position SP, the empty flag and the data under-counting flag can be stored in other locations in the structure register Rb, and even stored in other registers. The flowchart of Fig. 9 illustrates a method of extracting bits from the one-bit data stream register Ra in the first embodiment of the present invention.

In FIG. 9, if the starting position SP is greater than the capturing length LE, LE bits are retrieved from the bit stream register scratcher Ra to the target register Rt. The process of extracting a bit when SP>LE is as shown in Fig. 1, and the LE bits (for example, BSR (SP-1, SP-LE)) extracted from the bit stream buffer Ra are stored. The lowest bit portion of the target register Rt (for example, DR(LE-1, 0)). Since the starting position SP is larger than the capturing length LE, some bits are still stored in the data stream buffer Ra after the retrieval, so that the "data under-bit" situation is not caused. At this time, the higher bit portion of the target register Rt (for example, DR (31, LE)) is written to a predetermined value (for example, 0) or remains unchanged according to the initial setting of the data under-counter flag, and then starts. The value of position SP is updated to (SP-LE). If the empty flag has an initial setting, the value of the empty flag will be cleared. If the data under-auversity flag has been initially set, the value of the retrieval length LE is returned to the value of the previous acquisition length LE, and then the value of the data under-counter flag is cleared.

Referring again to Fig. 9, if the starting position SP is equal to the drawing length LE, a depletion situation will occur at this time, so an empty flag is set and the DR (MSB, LE) of the target register Rt is set to zero. Next, LE bits are retrieved from the bit stream register scratcher Ra to the target register Rt. The process of extracting a bit when SP=LE is as shown in Fig. 2, and the LE bits (for example, BSR(LE-1, 0)) extracted from the bit stream buffer Ra are saved in the target. The lowest part of the register Rt (for example, DR(LE-1, 0)). Since the starting position SP is equal to the drawing length LE, it does not cause a "data under-bit" situation, in which case the higher-order portion of the target register Rt (for example, DR (31, LE)) is stored in a predetermined value. (for example, 0), and then clear the value of the understated flag. The value of the starting position SP is updated to the most significant bit (e.g., 32) of the bit stream buffer Ra to prepare for subsequent bit fetching.

If the starting position SP is smaller than the capturing length LE, an empty flag is set at this time due to a lack of space, and the DR (MSB, LE) of the target register Rt is set to zero. Then, SP bits (for example, BSR(SP-1, 0)) are extracted from the bit stream buffer Ra to the lowest bit portion (such as DR) from the position LE-1 in the target register Rt. (LE-1, LE-SP)). The process of extracting a bit when SP<LE is as shown in Fig. 3, at this time, a buffer bit corresponding to the start position SP and the length LE difference (SP-LE) is added to increase the length of the capture. The number of bits in LE. Since the starting position SP is smaller than the drawing length LE, this will cause a "data under-subscription" situation, so the data under-counting flag (for example, Rb(31)=1) in Rb(31) will be set and the target will be The upper portion of the register Rt is set to a predetermined value (for example, DR (32, LE) = 0). The value of the starting position SP is updated to the most significant bit of the bit stream register Ra (for example 32) in preparation for subsequent bit extraction, and the value of the length LE is updated to (LE- SP). The value of the original capture length LE is stored in a previous capture length register prev_LE before the update length LE is updated.

Please refer to FIG. 4, which illustrates the method of extracting bits from the bit stream buffer Ra after performing the bit drawing operation of FIG. 3, that is, setting the data of Rb (31). The method of extracting the bit from the bit stream buffer Ra after the under-flag is used. At this time, the number of bits to be retrieved is equal to the number of remaining bits after the previous capture, that is, equal to the captured length LE of the previous bit minus the starting position of the previous bit. value. In other words, after the bit of a complete capture length is extracted in the previous capture, the unfinished part is the bit to be retrieved. These bits to be fetched are stored in the lowest bit portion of the target register Rt (for example, DR(LE-SP-1, 0)), that is, the position of the buffer bit is added in the previous capture. Since the data under-count flag in Rb (31) has been set, the high-order portion of the target register Rt remains unchanged, so that the SP bits obtained from the previous capture can be retained. Therefore, when the starting position SP is smaller than the drawing length LE, the present invention can efficiently capture all LE bits by the data under-counting flag and the embodiments described in FIGS. 2 and 3.

5 to 7 and 10 illustrate a method of packaging a bit from a source register (SR) Ra to a bit stream stream register Rt in the second embodiment of the present invention. As shown in Figures 5-7, the bit stream register Rt can contain 32 bits, such as 0-31. The bits of the source register Ra can be packaged and stored in the bit stream register Rt. A structure register Rb can store a predetermined package length (LE) in Rb (4, 0), a predetermined starting position (SP) in Rb (9, 5), and a full flag (full flag) ) is stored in Rb (13), and a data overflow flag is stored in Rb (31). Of course, the predetermined package length LE, the predetermined starting position SP, the full flag and the data overflow flag can be stored in other locations in the structure register Rb, or even stored in other registers. The flowchart of Fig. 10 illustrates a method of packaging a bit from a source register Ra to a bit stream register Rt in the second embodiment of the present invention.

In Fig. 10, if the starting position SP is larger than the package length LE, the LE bits are packed from the source register Ra to the bit stream register Rt. The process of packing the bits in SP>LE is as shown in Fig. 5. The LE bits (such as SR(LE-1, 0)) packed from the source register Ra are stored in the bit stream. The lowest bit portion (for example, BSR (SP-1, SP-LE)) from the position (SP-1) in the Rt. The value of the starting position SP is updated to (SP-LE) and the value of the full flag is cleared. If the data overflow flag has been initially set (for example, Rb(31)=1), the value of the data overflow flag will be cleared and the value of the package length LE will be restored to the value of the previous package length prev_LE.

Referring again to FIG. 10, if the starting position SP is equal to the package length LE, the full flag value is set at this time, and the LE bits are packed from the source register Ra to the bit stream register Rt. The process of packing the bits in SP=LE is as shown in Fig. 6. The LE lowest bits in the source register Ra (for example, SR(LE-1, 0)) are packaged and start from the position (LE-1). It is stored in the bit stream register Rt (for example, BSR (LE-1, 0)). Since the starting position SP is equal to the package length LE, there is no "data overflow" condition, so the value of the data overflow flag is cleared and is not set. The value of the starting position SP is updated to the most significant bit (e.g., 32) of the bit stream register Rt to prepare for subsequent bit packing.

If the starting position SP is smaller than the package length LE, the values of the full flag and the data overflow flag are set at this time, and SP bits are packed from the source register Ra to the bit stream register Rt. The process of packing the bits in SP<LE is as shown in Fig. 7. The source SP is from the LE position to the next SP lowest bits (for example, SR(LE-1, LE-SP)) and is packaged. It is stored in the bit stream register Rt (for example, BSR(SP-1, 0)) from the position (SP-1). The scratchpad storing the package length LE is first stored in a previous package length register previous_LE, and then updated to (LE-SP), and the value of the start position SP is updated to the bit stream register Rt. The most significant bit (for example, 32). The previous package length register previous_LE can record the original package length LE before the update, and can be used to restore the value of the original package length LE after the second wrapping process in the data overflow.

It should be noted that the present invention can use the methods shown in FIGS. 1 to 4 to extract bits, or integrate some/all of the methods shown in FIGS. 1 to 4 into a bit to extract software or hardware. . Similarly, the present invention can also package the bits by using the methods shown in FIGS. 5-7, respectively, or integrate part/all of the methods shown in FIGS. 5-7 into the bit package software or hardware.

Please refer to FIG. 11 and FIG. 12 . FIG. 11 is a schematic diagram of a bit stream data stream capture (BSE) device according to an embodiment of the present invention, which can be used to implement the bit stream data capture method shown in FIG. 9; FIG. 12 is a schematic diagram of a bit stream data stream packaging (BSP) device according to an embodiment of the present invention, which can be used to implement the bit stream packaging method shown in FIG. First, the BSE device shown in FIG. 11 will be described. The BSE device includes a plurality of flip-flops (FFs, also referred to as registers) 11, 13, 15, 17, 19, 21, and 23, one for A control logic 41 for selecting a control signal is generated, and a plurality of multiplexers 31, 33, 35, 37, and 39 capable of selecting an input signal according to the selection control signal, an arithmetic logic unit (ALU)/comparison The device 43, and a mask generator 45. The plurality of flip-flops 11 to 23 include an empty flag (e_f) 11, a data under-count flag (u_f) 13, and a start position register (SP) 15 for storing the start position for storing the previous One of the lengths of the previous capture length register (Prev_LE) 17, a storage length register (LE) 19 for storing the length of the capture, one bit stream for storing the retrieved data stream temporary storage (BSR) 21, and a target register (DR) 23. In the plurality of multiplexers 31-39, the empty flag multiplexer 31 is coupled to the empty flag 11, the data under-flag multiplexer 33 is coupled to the data under-counter flag 13, and the starting position is multiplexed. The device 35 is coupled to the start location register 15 and the ALU/comparator 43, the previous capture length multiplexer 37 is coupled to the previous capture length register 17 and the capture length register 19, and is captured. The length flag multiplexer 39 is coupled to the pull length flip flop 19 and the ALU/comparator 43. The BSE apparatus further includes a left/right shifter 49 for shifting the data extracted from the bit stream register 21 in accordance with the difference result ∣AB∣ generated by the ALU/comparator 43. Bit processing. In Fig. 11, the signal values 51, 53 and 55 are only used to illustrate the embodiment, and do not limit the scope of the invention.

In operation, the ALU/comparator 43 receives the start position flip-flop 15 and the capture length flip-flop 19 and compares the results (eg, "SP>LE", "SP=LE" or "SP<LE") Transfer to control logic 41. The arithmetic logic unit 43 can also generate a difference result |A-B| depending on the start position and the draw length. According to the comparison result, the control logic 41 can output control signals to the multiplexers 31 and 33 to respectively set or clear the values of the empty flag and the data under-flag flag, and can also output the control signals to the multiplexers 35, 37 and 39 respectively. The values of the home position flip-flop 15, the previous length flip-flop 17 and the length-of-length flip-flop 19 are updated. After the shift direction is determined according to the control signal transmitted by the control logic 41, and the shift amount is determined according to |AB| generated by the ALU/comparator 43, the left/right shifter 49 can access the slave data. The data extracted from the stream register 21 is subjected to shift processing, and the shifted data is transferred to the target register 23. The mask generator 45 can generate a mask signal for setting the high-order portion of the target register 23 to a predetermined value, for example, setting DR (32, LE) to zero. The mask generator 45, the left/right shifter 49 and the target register 23 can be coupled to a first logic unit 63, so that the logic signal can be performed on the mask signal and the shifted data (logic AND ) Operation.

In summary, the control logic 41 of the BSE device shown in FIG. 11 can realize:

(1) update the length of the capture;

(2) update the starting position;

(3) controlling the shift direction of the left/right shifter 49;

(4) controlling the starting position multiplexer to select the starting position from the most significant bit and the difference result;

(5) Control the data under-auversity flag multiplexer to set or clear the value of the data under-auversity flag;

(6) controlling the previous capture length multiplexer to choose to maintain the previous capture length or update the value of the previous capture length;

(7) controlling the length multiplexer to select to maintain the length of the capture, or updating the value of the length of the capture to the value of the previously retrieved length register or the result of the difference;

(8) Control the empty flag multiplexer to set or clear the value of the empty flag according to the comparison result.

In the BSE apparatus shown in Fig. 12, the BSP apparatus includes a plurality of flip-flops (also referred to as registers) 11, 13, 15, 17, 19, 21, and 23, and a control logic for generating a selection control signal. 41. A plurality of multiplexers 31, 33, 35, 37, and 39 capable of selecting an input signal according to the selection control signal, an ALU/comparator 43, a mask generator 45, and a first left/right shift The bit 49, and a second left/right shifter 57. In the plurality of flip-flops 11 to 23, the full flag (f_f) 11 can store the value of the full flag, the data overflow flag (of) 13 can store the value of the data overflow flag, and the initial position is temporarily stored. The SP (SP) can store the value of the starting position, the previous package length register (Prev_LE) 17 can store the value of the previous package length, the package length register (LE) 19 can store the value of the package length, the source is temporarily stored. The (SR) 21 can store package information and a target bit stream register (BSR) 23. In the plurality of multiplexers 31-39, the full flag multiplexer 31 is coupled to the control logic 41 and the full flag 11, and the data overflow flag multiplexer 33 is coupled to the control logic 41 and the data overflow flag. The starting position multiplexer 35 is coupled to the home position register 15, the ALU/comparator 43 and the control logic 41. The previous package length multiplexer 37 is coupled to the control logic 41, and the previous package length is positive and negative. The package 17 and the package length flip-flop 19 are coupled to the ALU/comparator 43, the length-length flip-flop 19, the previous package length flip-flop 17 and the control logic 41. In Fig. 12, the signal values 51, 53 and 55 are only used to illustrate the embodiment, and do not limit the scope of the invention.

In operation, the ALU/comparator 43 receives the home position flip-flop 15 and the package length flip-flop 19 and transmits the comparison result (eg, "SP>LE", "SP=LE" or "SP<LE") To control logic 41. The arithmetic logic unit 43 can also generate a difference result |A-B| depending on the start position and the draw length. According to the comparison result, the control logic 41 can output control signals to the multiplexers 31 and 33 to respectively set or clear the values of the full flag and the data overflow flag, and can also output the control signals to the multiplexers 35, 37 and 39 respectively. The values of the home position flip-flop 15, the previous package length flip-flop 17, and the package length flip-flop 19 are updated. The left/right shifters 49 and 57 are available from the source after determining the shift direction based on the control signal transmitted by the control logic 41 and determining the shift amount based on |AB| generated by the ALU/comparator 43. The data extracted from the register 21 and the mask signal 53 generated by the mask generator 45 are shifted, and the shifted data is transferred to the target bit stream register 23, and the shift is shifted. The subsequent mask signal 53 is transmitted to a logic and gate unit 61. The mask generator 45 can generate a mask signal that maintains the original value of the high order portion of the target bit stream buffer 23 before and after the bit packing.

In summary, the control logic 41 of the BSP device shown in Fig. 12 can realize:

(1) update the package length;

(2) update the starting position;

(3) controlling the shift direction of the left/right shifters 49 and 57;

(4) controlling the starting position multiplexer to select the starting position from the most significant bit and the difference result;

(5) Control the data overflow flag multiplexer to set or clear the value of the data overflow flag;

(6) controlling the previous package length multiplexer to choose to maintain the previous package length or update the value of the previous package length;

(7) controlling the package length multiplexer to choose to maintain the package length, or to update the value of the package length to the value of the previous package length register or the difference result;

(8) Control the full flag multiplexer to set or clear the value of the full flag according to the comparison result.

In the foregoing embodiments of the method of capturing and packaging bits and the BSE/BSP device, the present invention uses an empty flag, a full flag, an under-status flag, and a data overflow flag when continuously capturing or packaging a bit. It is used to deal with boundary conditions such as "data under-subscription" and "data overflow". When the "data under-position" is captured, the present invention automatically adjusts the starting position of the bit stream source register and the read length in the configuration register, thereby continuously performing the capture operation twice. In the second acquisition, the high-order bits of the target register are not changed, so that the operation of the "data under-subscription" can be handled more efficiently. When the "data overflow" is packaged, the present invention automatically adjusts the starting position of the bit stream stream target register and the package length in the configuration register, thereby continuously performing the packaging operation twice, thereby enabling Efficiently handle packaging operations during "data overflow". In summary, the present invention automatically updates and retrieves the length of the capture/package using the automatic starting position, thereby increasing the parallelism of the work, thereby improving system efficiency.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

11~23. . . Positive and negative (storage)

31~39. . . Multiplexer

41. . . Control logic

43. . . ALU/comparator

45. . . Mask generator

49, 57. . . Shifter

1300~1800. . . Sample instruction program

Ra, Rb, Rt. . . Register

1 to 4 are schematic views showing a method of extracting a bit from a one-bit data stream register in the first embodiment of the present invention.

5 to 7 are schematic diagrams showing a method of packaging a bit from a source register to a bit stream buffer in the second embodiment of the present invention.

Figure 8 is a schematic diagram of a method of picking up bits in the prior art.

FIG. 9 is a flow chart of a method for extracting a bit from a one-bit data stream register in the first embodiment of the present invention.

FIG. 10 is a flow chart of a method for packaging a bit from a source register to a bit stream register in the second embodiment of the present invention.

FIG. 11 is a schematic diagram of a one-bit data stream capture device according to an embodiment of the present invention.

FIG. 12 is a schematic diagram of a one-bit data stream packaging apparatus according to an embodiment of the present invention.

Figures 13 to 15 are schematic views of a method of picking up bits in the prior art.

Figures 16-18 are schematic diagrams of a method of packaging a bit in the prior art.

11~23. . . Positive and negative (storage)

31~39. . . Multiplexer

41. . . Control logic

43. . . ALU/comparator

45. . . Mask generator

49. . . Shifter

Claims (31)

A method for extracting a bit from a bitstream register, comprising: temporarily storing a bit stream from a bit stream when a predetermined starting position is greater than a predetermined drawing length The predetermined starting position in the device begins to capture a predetermined number of bits, wherein the predetermined number and the predetermined drawing length have the same value; storing the bits in a lowest bit in a target register Part; when there is no underflow, the high-order portion of one of the unstored bits in the target register is set to a predetermined value; the setting of an empty flag and a data under-flag is cleared; The predetermined starting position is subtracted from the predetermined starting position to update the predetermined starting position. The method of claim 1, wherein the high-order portion of the un-stored bit in the target register is set to the predetermined value, and the high-order portion of the un-stored bit in the target register is set to zero. A method for extracting a bit from a bit stream buffer, comprising: when the predetermined start position is equal to a predetermined draw length, the predetermined start from the bit stream register The location begins to retrieve a predetermined number of bits, wherein the predetermined number and the predetermined retrieval length have the same value; The bits are stored in one of the lowest bit portions of a target register; when no data is under-subscribed, the high-order portion of one of the un-stored bits in the target register is set to a predetermined value; An empty flag to indicate that all the bit data in the bit stream buffer has been retrieved, and to clear a data under flag; and update the predetermined starting position to the bit stream One of the predetermined bits in the scratchpad is prepared for the next capture. The method of claim 3, wherein the high-order portion of the un-stored bit in the target register is set to the predetermined value, and the high-order portion of the un-stored bit in the target register is set to zero. The method of claim 3, wherein updating the predetermined starting location to the predetermined bit in the bitstream register to prepare for the next retrieval is to update the predetermined starting location to the bit One of the most signifi cant bits (MSB) in the metadata stream register is prepared for the next acquisition. A method for extracting a bit from a bit stream buffer, comprising: when the predetermined start position is less than a predetermined draw length, the predetermined start from the bit stream register The location begins to retrieve a predetermined number of bits, wherein the predetermined number and the predetermined starting location have a phase a same value; adding a predetermined number of buffer bits after the bits extracted from the bit stream buffer to increase the number of bits to the predetermined length; Start with one of the same lengths, store the bits in one of the lowest bits in a target register; when an underflow flag is not set, temporarily store the target One of the unstored bits in the device is set to a predetermined value; the predetermined starting position is updated to a predetermined bit in the bit stream register to prepare for the next acquisition; using the predetermined The predetermined length of the predetermined length is subtracted from the length of the predetermined starting position; and the data under-flag and an empty flag are set. The method of claim 6, wherein the predetermined number of buffer bits are added after the bits retrieved from the bit stream register to increase to the predetermined length The number of bytes is added to the plurality of zeros from the bits retrieved from the bit stream buffer to increase the number of bits to the predetermined length. The method of claim 6, wherein the high-order portion of the unstored bit in the target register is set to the predetermined value in the target register The high-order portion of the unstored bit is set to zero. The method of claim 6, wherein updating the predetermined starting location to the predetermined bit in the bitstream register to prepare for the next retrieval is to update the predetermined starting location to the bit One of the most significant bits in the metadata stream buffer is prepared for the next acquisition. A method for extracting a bit from a bit stream buffer includes: when a data under flag has been set, starting from one of the most significant bits in the bit stream register Extracting a predetermined number of bits, wherein the predetermined number of values is equal to a value obtained by subtracting a previous previous starting position from the previous previous reading; storing the bits in a target register One of the lowest bit parts; and the setting of the data under-flag and an empty flag. A method for extracting a bit from a one-bit data stream register, comprising: when the predetermined starting position is greater than a predetermined drawing length, from the predetermined starting point in the bit stream register The location begins to retrieve a predetermined number of bits, wherein the predetermined number and the predetermined capture length have the same value; the bits are stored in a lowest bit portion of a target register; when no data is under-subscribed When one of the unstored bits in the target register is high The bit portion is set to a predetermined value; the setting of an empty flag and a data under flag is cleared; the predetermined starting position is updated by subtracting the predetermined number of values from the predetermined starting position; when the predetermined starting position is When the predetermined length is equal to, the predetermined number of bits are extracted from the predetermined starting position in the bit stream register, wherein the predetermined number and the predetermined length have the same value; The bits are stored in the lowest bit portion of the target register; when no data is under-subscribed, the high-order portion of the un-stored bit in the target register is set to the predetermined value; setting an empty flag Marking that all the bit data in the bit stream register has been captured, and clearing a data under flag; updating the predetermined starting position to one of the bits in the bit stream register The bit is prepared for the next capture; when the predetermined start position is less than the predetermined draw length, a predetermined number of bits are extracted from the predetermined start position in the bit stream register. Wherein the predetermined number and the predetermined starting position have a phase Value; adding a predetermined number of bits in a plurality of buffer after the plurality of bits retrieved from the bit stream data registers to the predetermined number of bits is increased to retrieve length; Starting from a position that is the same as the predetermined capture length, the bits are stored in the lowest bit portion of the target register; when a data under-flag flag is not set, the target is temporarily stored The high-order portion of the unstored bit in the device is set to the predetermined value; the predetermined starting position is updated to the predetermined bit in the bit stream register to prepare for the next acquisition; using the predetermined Retrieving the length from the predetermined starting position to update the predetermined retrieval length; setting the data under-flag and an empty flag; when the data under-flag has been set, the data stream is from the bit One of the most significant bits in the register begins to retrieve the predetermined number of bits, wherein the predetermined number of values is equal to the previous predetermined length of the previous acquisition minus the previous starting position; The bits are stored in the lowest bit portion of the target register; and the setting of the data under-flag and an empty flag is cleared. The method of claim 11, wherein the high-order portion of the un-stored bit in the target register is set to the predetermined value, and the high-order portion of the un-stored bit in the target register is set to zero. The method of claim 11, wherein the predetermined starting location is updated to the predetermined bit in the bitstream register for the next acquisition. The backup unit updates the predetermined starting position to one of the most significant bits in the bit stream register to prepare for the next acquisition. The method of claim 11, wherein the predetermined number of buffer bits are added after the bits retrieved from the bit stream buffer to increase to the predetermined length The number of bytes is added to the plurality of zeros from the bits retrieved from the bit stream buffer to increase the number of bits to the predetermined length. A method of packing a bit into a meta-data stream register, comprising: when a predetermined starting position is greater than a predetermined package length, one of a source register is lowest The bit portion begins to package a predetermined number of bits, wherein the predetermined number and the predetermined package length have the same value; from the predetermined starting position, the bits are stored in the bit stream register Clearing a full flag and an overflow flag; and updating the predetermined starting position using the predetermined starting position minus the value of the predetermined package length. A method for packaging a bit into a bit stream buffer, the package thereof And: when a predetermined starting position is equal to a predetermined package length, packaging a predetermined number of bits from a lowest bit portion of a source register, wherein the predetermined number and the predetermined package length have the same value; Starting from the predetermined starting position, storing the bits in the bit stream register; setting a full flag and clearing a data overflow flag; and updating the predetermined starting position to the bit One of the most significant bits of the data stream register. A method of packaging a bit into a one-bit data stream register, comprising: packaging a predetermined order from a lowest bit portion of a source register when a predetermined starting position is less than a predetermined package length a number of bits, wherein the predetermined number and the predetermined starting position have the same value; from the predetermined starting position, the bits are stored in the bit stream register; setting a full flag and a data overflow flag; updating the predetermined starting position to one of the most significant bits of the bit stream register; and updating the predetermined package by subtracting the predetermined starting position from the predetermined package length length. A method of packaging a bit into a one-bit data stream register, comprising: packaging a predetermined order from a lowest bit portion of a source register when a predetermined starting position is greater than a predetermined package length a number of bits, wherein the predetermined number and the predetermined package length have the same value; from the predetermined starting position, the bits are stored in the bit stream register; clearing a full flag and a a data overflow flag; updating the predetermined starting position by subtracting the predetermined starting position from the predetermined starting position; and when the predetermined starting position is equal to the predetermined package length, one of the lowest from the source register The bit portion begins to package the predetermined number of bits, wherein the predetermined number and the predetermined package length have the same value; from the predetermined starting position, the bits are stored in the bit stream register; Setting the full flag and clearing the data overflow flag; updating the predetermined starting position to one of the most significant bits of the bit stream register; when the predetermined starting position is less than the predetermined package length, From here The lowest bit portion of the register begins to package the predetermined number of bits, wherein the predetermined number and the predetermined starting position have the same value; from the predetermined starting position, the bits are stored in the bit Data stream register; Setting the full flag and the data overflow flag; updating the predetermined starting position to the most significant bit of the bit stream register; and using the predetermined package length minus the predetermined starting position The value is used to update the predetermined package length. A bit data stream capture device, comprising: a one-dimensional data stream register for storing data; a shifter, according to a difference result, from the bit stream register 撷The taken data is subjected to shift processing; a target register is used for storing data shifted by the shifter; a start position register is used for storing a starting position; and a length register is used; And an arithmetic logic unit for comparing the starting position and the length of the drawing to generate a comparison result, and for using the starting position and the length of the drawing Generating the difference result; a control logic for updating the starting position according to the comparison result, updating the captured length, and controlling a left/right shifting direction of the shifter; a data underrun flag a register coupled to the control logic; and a data under-flag multiplexer coupled to the control logic and the data under-flag register, wherein the control logic further controls the data under-counter Standard multiplexer to select based on the comparison result Due to a data set Bit flag or clear the understated flag of the data. The bit stream extracting device of claim 19, further comprising: a mask generator for temporarily storing the target according to the length of the data when no data undershoot occurs One of the unregistered bits in the device is set to a predetermined value. The bit stream extracting device of claim 20, further comprising: a first logic unit for performing a logical AND on a mask signal and the data shifted by the shifter An operation to generate mask data, wherein the mask data is stored in the target register. The bit stream stream capture device of claim 19, further comprising: a start location multiplexer coupled to the start location register, the arithmetic logic unit, and the control logic, wherein the control logic The starting position multiplexer is further controlled to select the starting position from a maximum effective bit and the difference result according to the comparison result. The bitstream stream capture device of claim 19, further comprising: a previous capture length register for storing a previous capture length; and a previous capture length multiplexer coupled to The control logic, the previous 撷 And taking the length register and the capture length register, wherein the control logic further controls the previous capture length multiplexer, and further selecting to maintain the previous capture length or update the previous capture length according to the comparison result. The bit stream stream capture device of claim 23, further comprising: a read length multiplexer coupled to the operation logic unit, the capture length register, and the previous capture length temporary storage And the control logic, wherein the control logic further controls the capture length multiplexer, and further selecting to maintain the previous capture length according to the comparison result, or selecting to update the capture length to the previous capture length or Difference results. The bit stream stream capture device of claim 19, further comprising: an empty flag register for storing an empty flag; and an empty flag multiplexer coupled to the control logic and the empty The flag register, wherein the control logic further controls the empty flag multiplexer, and then selects the empty flag or clears the empty flag according to the comparison result. A bit data stream packaging device, comprising: a source register for storing package data; a first shifter, based on a difference result, from the source register The packaged data is subjected to shift processing; a target bit stream register is used for storing data shifted by the first shifter; and a start position register is used for storing a starting position; a package length register for storing a package length; an arithmetic logic unit for comparing the start position and the package length to generate a comparison result, and for using the start position and the The length of the package is used to generate the difference result; a control logic for updating the length of the package according to the comparison result, updating the starting position, and controlling the left/right direction of the shifter; a mask generation The device is configured to generate a mask signal to maintain a high-order portion of the target data stream buffer that does not store the existing package data at a previously packaged value; a second shifter coupled to the An arithmetic logic unit, the mask generator, and the control logic, configured to shift the mask signal according to the difference result to generate a shift mask signal; and a first logic unit for shift Mask signal and the data stored within the target bit register performs a logical data stream and (logical AND) operation, wherein the control logic further to control the shift direction of the second shifter. The bit stream packaging device of claim 26, further comprising: a start position multiplexer coupled to the start position register, the arithmetic logic unit, and the control logic, wherein the control logic further controls the start position multiplexer to be valid from a maximum according to the comparison result The starting position is selected from the bit and the difference result. The bit stream packaging device of claim 26, further comprising: a data overflow flag register coupled to the control logic for outputting a data overflow flag; and a data overflow a flag multiplexer coupled to the control logic and the data overflow flag register, wherein the control logic further controls the data overflow flag multiplexer to select the data overflow according to the comparison result Flag or clear the data overflow flag. The bit stream packaging device of claim 28, further comprising: a previous package length register for storing a previous package length; and a previous package length multiplexer coupled to the control logic, The previous package length register and the package length register, wherein the control logic further controls the previous package length multiplexer to select to maintain the previous package length or update the previous package length based on the comparison result. The bit stream packaging device of claim 29, further comprising: a package length multiplexer coupled to the operation logic unit, the package length register, the previous package length register, and the control logic, wherein the control logic further controls the package length multiplexer, and further The result of the comparison is selected to maintain the previous package length, or to update the package length to the previous package length or the difference result. The bit stream packaging device of claim 26, further comprising: a full flag register for storing a full flag; and a full flag multiplexer coupled to the control logic and The full flag register, wherein the control logic further controls the full flag multiplexer to select to set the full flag or clear the full flag according to the comparison result.