TWI392064B - Method of Making NOR - type Flash Memory - Google Patents

Description

NOR type flash memory manufacturing method

The invention relates to a method for fabricating a NOR-type flash memory, and more particularly to a method for fabricating a NOR-type flash memory with improved source ion implantation process.

With the advancement of semiconductor process technology, the size of Metal-Oxide-Semiconductor (MOS) has been gradually reduced, thereby greatly reducing manufacturing costs and increasing the component integration of integrated circuits. However, as the size of metal oxide semiconductors shrinks, the short channel effect (SCE) derived therefrom causes many problems, such as the shift of the threshold voltage and the roll-off of the threshold voltage. Therefore, it is very important to design a structure suitable for extremely short channel components.

The first picture is a top view of a NOR type flash memory array. The first figure shows a partial NOR-type flash memory array having a plurality of gate structures 102 as memory cells connected by control gates 102d deposited thereon. Vertically arranged word lines. Each gate structure 102 is adjacent to a drain region 104 and a gate region 106. As shown in the figure, the drain region 104 between the two gate structures 102 has a contact window 110 for enabling the gate structures 102 to be parallel to the bit lines perpendicular to the word lines (not shown). Show) make an electrical connection. In the NOR type flash memory array, there is a shallow trench isolation structure 112 (STI) which is perpendicular to the word line and separates the adjacent two gate structures 102.

Referring next to the second drawing, a cross-sectional view of a conventional NOR type flash memory is shown, which corresponds to the BB' transverse section line in the first figure. As shown in the figure, a gate structure 102 is disposed on a semiconductor substrate 100. The gate structure 102 includes a tunnel oxide layer 102a, a floating gate 102b, and a dielectric layer. 102c, a control gate 102d (contro1 gate) and a dioxide layer wall 202 on both sides of the gate structure 102. The semiconductor substrate 100 on one side of the gate structure 102 has a shallow doped drain region 104a and a deep doped drain region 104b forming a steep junction of the drain region 104, and the other side has a known source. A first source region 106a and a second source region 106b are formed by the ion implantation process. As the size of the memory is reduced, the first source region 106a formed by the conventional source ion implantation process is more convex, thereby increasing the probability of occurrence of a short channel effect between the shallow doped drain region 104a.

Referring to the third figure, a longitudinal cross-sectional view of a conventional NOR flash memory is shown, which corresponds to the AA' longitudinal section line in the first figure, and the area shown in the third figure corresponds to In the area 130 in the first figure. The figure shows a conventional source ion implantation process for self-alignment, preceded by the shallow doped drain region 104a and the deep doped drain region 104b with a mask 204 prior to the conventional source ion implantation process. The masking is performed, followed by the first source ion implantation process 206a with the dip angle, the second second source ion implantation process 208, and finally the third source ion implantation process 206b with the dip angle. . The first source region 106a formed by the conventional source ion implantation process is relatively close to the shallow doped drain region 104a (see the second figure), so that the short channel effect is more likely to occur when the device is miniature.

The main object of the present invention is to provide a method for fabricating a NOR-type flash memory, which can improve the implantation distribution of the source region by improving the source ion implantation process, and can be used in a NOR-type flash memory under a miniature size. Effectively reduce the chance of short channel effects.

To achieve the above object, the present invention provides a method for fabricating a NOR-type flash memory, the method comprising: forming a plurality of shallow trench isolation structures in a semiconductor substrate, the spacing between the shallow trench isolation structures being approximately 50 to 150 (nm); forming a plurality of gate structures on the semiconductor substrate, the gate structures are connected in a straight strip by a control gate, and the arrangement direction of the control gates on the semiconductor substrate is perpendicular to the a shallow trench isolation structure; performing a shallow doped drain ion implantation process, forming a plurality of shallow doped drain regions in the semiconductor substrate on one side of the gate structures; and two of the gate structures Forming an oxide layer wall on each side; performing a deep doped drain ion implantation process, forming a plurality of deep doped drain regions in the semiconductor substrate on one side of the gate structures, wherein the shallow doped germanium regions a polar region and the deep doped drain regions are located in the semiconductor substrate on the same side of the gate structures; performing an etching process on the semiconductor substrate having no drain regions on the other side of the gate structures The shallow trench isolation structure Etching to form a plurality of openings; and performing an oblique ion implantation process for forming an angle of inclination in the semiconductor substrate having no drain regions on the other side of the gate structures and the semiconductor substrate under the openings Planting the source area.

A method of fabricating a NOR-type flash memory according to an embodiment of the invention, wherein the semiconductor substrate is a P-type semiconductor substrate.

The method for fabricating a NOR-type flash memory according to an embodiment of the present invention, wherein the tilt ion implantation process comprises a first tilt ion implantation process and a second tilt ion implantation process, and is about 25 to 35 An angle of incidence of the cloth is implanted into the semiconductor substrate.

According to the method for fabricating a NOR-type flash memory according to an embodiment of the invention, the first dip ion implantation process and the second dip ion implantation process use N-type ions (eg, arsenic, phosphorus). The energy is about 20~60 (KeV), and the implantation dose is about 1×10 ¹⁴ to 1×10 ¹⁵ (atom/cm ² ).

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the accompanying drawings. In the various figures and embodiments, the same elements will be given the same symbols.

The method for fabricating the NOR type flash memory of the present invention mainly improves the method of implanting in the source ion implantation process. An embodiment of the invention is an N-channel memory structure and has an N-type source region and a drain region. 4 to 9 are longitudinal cross-sectional views showing the NOR-type flash memory production process of the present invention at different process steps, and the regions shown in the fourth to ninth drawings correspond to the first The area 130 and the AA' longitudinal section line in the figure.

Referring first to the fourth figure, boron ions (Boron) having a dose of about 1 × 10 ¹³ atoms/cm ² are implanted in a semiconductor substrate 100 to form a P-type semiconductor substrate, and then a pitch X of 50 is formed in the semiconductor substrate 100. A plurality of shallow trench isolation structures 302 of ~150 (nm). Only two shallow trench isolation structures 302 are shown in the fourth through tenth figures. The material of the semiconductor substrate 100 may be bismuth (Si), germanium (SiGe), silicon on insulator (SOI), silicon germanium on insulator (SGOI), and insulating layer. Germanium On Insulator (GOI). In the embodiment, the material of the semiconductor substrate 100 is germanium.

Referring to FIG. 5, a tunnel oxide layer 102a is formed on the semiconductor substrate 100 by thermal oxidation, and a floating gate 102b is deposited by Low Pressure Chemical Vapor Deposition (LPCVD). (floating gate). Finally, the dielectric layer 102c is deposited by thermal oxidation to form an ONO (Oxide-Nitride-Oxide) structure (see Figure 6).

Next, refer to the sixth figure, using a photoresist and etch process to separate each ONO structure to locate the gate structure that will be formed later. Next, referring to the seventh figure, a control gate 102d is formed by using a photoresist and an etching process. The control gate 102d is deposited on each ONO structure as shown in FIG. 7 to form a plurality of gate structures 102. The 102d has a long straight strip shape and connects the gate structures 102. The arrangement direction of the control gates 102d on the semiconductor substrate 100 is perpendicular to the shallow trench isolation structures 302. Each of the gate structures 102 includes a tunnel oxide layer 102a, a floating gate 102b, a dielectric layer 102c, and a control gate 102d. Then, a portion of the semiconductor substrate 100 on one side of the gate structure 102 is shielded by a photomask (not shown) to perform a shallow doping dopant ion implantation process on the side of the gate structures 102. A plurality of shallowly doped drain regions 104a are formed in the substrate 100. The ion used in the shallow doped bromide ion implantation process is arsenic, and the dose is about 1×10 ¹⁴ 5×10 ¹⁵ (atom/cm ² ), and the energy is about 10-30 (Kev).

Referring to FIG. 8 , an oxide layer is deposited and an oxide layer wall 304 is formed as a buffer layer on both sides of the gate structures 102 by etching (the gate structures 102 are used by the oxide layer wall 304 in the figure). It cannot be displayed because of the shading.) A portion of the semiconductor substrate 100 on one side of the gate structure 102 is shielded by a photomask (not shown), and a deep doped drain ion implantation process is performed to form a plurality of deep doped drain regions 104b. The shallow doped drain regions 104a and the deep doped drain regions 104b are located in the semiconductor substrate 100 on the same side of the gate structures 102, and form the drain regions 104 as shown in the first figure. The ions used in the deep doped bromide ion implantation process are arsenic, and the dose is about 1×10 ¹⁴ to 5×10 ¹⁵ (atom/cm ² ), and the energy is about 40-60 (Kev).

Referring to the ninth embodiment, one side of the gate structures 102 (ie, the shallow doped drain regions 104a and the sides of the deep doped drain regions 104b) are shielded by a mask 306. a self-aligned etching process (Self-Align Etch), etching the shallow trench isolation structures 302 in the semiconductor substrate 100 having the drain region 104 on the other side of the gate structure 102 to form a plurality Openings 307. Next, a dip ion implantation process is performed. The dip ion implantation process includes a first dip ion implantation process 308a and a second dip ion implantation process 308b, each of which has an incident angle of about 25 to 35 degrees. The θ cloth is implanted in the semiconductor substrate 100 for forming the connection in the semiconductor substrate 100 having no drain regions 104 on the other side of the gate structures 102, and in the semiconductor substrate 100 under the openings 307. The source region 106c is implanted at a dip angle. The first dip ion implantation process 308a and the second dip ion implantation process 308b use an ion implantation process to use N-type ions (eg, arsenic, phosphorus), and the energy is 20-60 (KeV). The implantation dose is about 1 x 10 ¹⁴ to 1 x 10 ¹⁵ (atom/cm ² ). The dip implant source region 106c corresponds to the source region 106 in the first figure.

Next, please refer to the tenth drawing, which is a transverse sectional view of the NOR type flash memory of the present invention, which corresponds to the BB' transverse section line in the first figure. The invention is characterized in that, compared with the conventional technique for performing the three-source source ion implantation process (see the second figure), the present invention discards the source ion implantation process in which the implantation angle is zero angle, and the inclination angle is made. The implant source region 106c is different from the first source region 106a of the prior art that is closer to the shallow doped drain region 104a. Therefore, the present invention can maintain a relatively long distance from the shallow doped drain region 104a as compared with the prior art, thereby effectively reducing the probability of occurrence of short channel effects.

In summary, the method for fabricating the NOR flash memory of the present invention utilizes two dip ion implantation processes to form a dip implant source region, and the implantation step is used to improve the source region of the cloth. The plant distribution allows the between the drain region and the source region in the NOR flash memory to increase the probability of short channel effects due to the short spacing.

The present invention has been disclosed in the above preferred embodiments, and it should be understood by those skilled in the art that this embodiment is only used to describe a part of the structure of the memory in the present invention, and should not be construed as limiting the scope of the present invention. . It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

100. . . Semiconductor substrate

102. . . Gate structure

102a. . . Tunneling oxide layer

102b. . . Floating gate

102c. . . Dielectric layer

102d. . . Control gate

104. . . Bungee area

104a. . . Shallow doped bungee zone

104b. . . Deep doped bungee zone

106. . . Source area

106a. . . First source region

106b. . . Second source region

106c. . . Inclination source area

110. . . Contact window

112. . . Shallow trench isolation structure

130. . . region

202. . . Oxide wall

204. . . Mask

206a. . . First ion implantation process

206b. . . Third ion implantation process

208. . . Second ion implantation process

302. . . Shallow trench isolation structure

304. . . Oxide wall

306. . . Mask

307. . . Opening

308a. . . First ion implantation process

308b. . . Second ion implantation process

AA’. . . Longitudinal section line

BB’. . . Transverse section line

X. . . spacing

θ. . . Incident angle

The first picture is a top view of a NOR type flash memory array.

The second figure is a transverse cross-sectional view of a conventional NOR type flash memory.

The third figure is a longitudinal perspective view of a conventional NOR type flash memory.

The fourth to ninth views are longitudinal cross-sectional views showing the NOR-type flash memory fabrication process of the present invention at different process steps.

The tenth figure is a transverse sectional view of the NOR type flash memory of the present invention.

100. . . Semiconductor substrate

102a. . . Tunneling oxide layer

102b. . . Floating gate

102c. . . Dielectric layer

102d. . . Control gate

104a. . . Shallow doped bungee zone

104b. . . Deep doped bungee zone

106c. . . Inclination source area

304. . . Oxide wall

306. . . Mask

307. . . Opening

308a. . . First ion implantation process

308b. . . Second ion implantation process

θ. . . Incident angle

Claims (4)

A method for fabricating a NOR flash memory, the method comprising: forming a plurality of shallow trench isolation structures in a semiconductor substrate, the spacing between the shallow trench isolation structures being about 50-150 (nm); forming a plurality a gate structure is disposed on the semiconductor substrate, the gate structures are connected in a straight strip shape by a control gate, and the arrangement direction of the control gate on the semiconductor substrate is perpendicular to the shallow trench isolation structures; a shallow doped dopant ion implantation process, forming a plurality of shallow doped drain regions in the semiconductor substrate on one side of the gate structures; forming an oxide layer on each side of the gate structures; a deep doped drain ion implantation process, forming a plurality of deep doped drain regions in the semiconductor substrate on one side of the gate structures, wherein the shallow doped drain regions and the deep doped germanium regions a polar region is located in the semiconductor substrate on the same side of the gate structures; an etching process is performed to etch the shallow trench isolation structures in the semiconductor substrate having no drain regions on the other side of the gate structures Removing to form a plurality of openings; and Forming a dip implant source region as a source region in the semiconductor substrate having no drain region on the other side of the gate structure and the semiconductor substrate under the openings by two tilt ion implantation processes The two-tilt ion implantation process is implanted into the semiconductor substrate at an incident angle of 25 to 35 degrees. The method of fabricating a NOR-type flash memory according to claim 1, wherein the semiconductor substrate is a P-type semiconductor substrate. The method for fabricating a NOR-type flash memory according to claim 1, wherein the two-tilt ion implantation process uses N-type ions. The method for fabricating a NOR-type flash memory according to claim 3, wherein the first dip ion implantation process and the ion implantation process used in the second dip ion implantation process are implanted For a dose of 20 to 60 (KeV), the implantation dose is about 1 x 10 ¹⁴ to 1 x 10 ¹⁵ (atom/cm ² ).