TWI390492B - A method for detecting resolution and a timing controller - Google Patents

Description

Method for detecting the resolution of an image data, and timing controller for automatically detecting the resolution of an image data

The present invention relates to a display related technique, and more particularly to a method for detecting the resolution of an image data and a timing controller for automatically detecting the resolution of an image data.

Generally, flat panel displays, such as liquid crystal displays, have superior features such as high image quality, space saving, low power consumption, and no radiation, and have gradually become the mainstream in the market. Among them, the timing controller is one of the important components of the liquid crystal display, and is used to control the peripheral circuits of the liquid crystal display (such as the gate level controller and the source level controller) according to the resolution of the image data transmitted by the scale control circuit (Scaler). Timing.

The general timing controller is designed according to the preset resolution of the display panel. In other words, if a timing controller is applied to a liquid crystal display panel of 800×600 resolution, the timing controller cannot be used in a display panel of other resolutions such as 1024×768 or 1280×1024. Therefore, manufacturers must design different timing controllers for the resolution specifications of different liquid crystal display panels.

In order to improve the convenience of the general timing controller application to the display panel, a manufacturer has introduced a timing controller that supports two resolution panels. This timing controller adds an additional pin (Pin), which is used to set the resolution. When the pin receives the high voltage level signal, the timing controller operates at the first resolution; and when the pin receives the low voltage level signal, the timing controller operates at the second resolution. . However, in order to increase the resolution of the timing controller, it is necessary to increase the number of pins, but this will make the layout of the printed circuit board difficult, and also increase the possibility of circuit interference.

In view of the above problems, an object of the present invention is to provide a method for detecting the resolution of an image data and a timing controller for automatically detecting the resolution of an image data, using the original without increasing the layout area of the circuit. Some signals automatically determine the resolution of the image data of the front-end circuit (such as the zoom control circuit). The problem of the conventional technology is solved, the convenience of the timing controller is improved, and the effect of reducing the production cost is achieved.

Another object of the present invention is to provide a method for detecting the resolution of an image data and a timing controller for automatically detecting the resolution of an image data for use in a wide range of flat display panels of different resolutions.

Another object of the present invention is to provide a method for detecting the resolution of an image data and a timing controller for automatically detecting the resolution of an image data to save development cost.

To achieve the above or other objects, an embodiment of the present invention provides a method for detecting resolution of an image data, the method comprising the steps of: first, receiving a set of image control signals. Then, the resolution of the image data is determined according to the set of image control signals, wherein the resolution includes a first dimensional resolution and a second dimensional resolution. When the group of image control signals includes a first reference signal, the first dimension resolution or the second dimension resolution may be determined according to the characteristics of the first reference signal.

Furthermore, an embodiment of the present invention provides a timing controller for automatically detecting an image data resolution, the timing controller receiving image data and a set of image control signals, and the timing controller includes a resolution detecting circuit With a timing control unit. The resolution detecting circuit determines the resolution of the image data according to the set of image control signals, wherein the resolution includes a first dimensional resolution and a second dimensional resolution. The timing control unit generates a timing control signal according to the first dimensional resolution and the second dimensional resolution. The resolution detecting circuit includes a first determining circuit and a second determining circuit. When the group of image control signals includes a first reference signal, the first determining circuit receives the first reference signal, and generates a first dimensional resolution according to the enabling period of the first reference signal. The second determining circuit also receives the first reference signal, and generates a second dimensional resolution according to the number of times the first reference signal is enabled within a preset time.

The method for detecting the resolution of an image data and the timing controller for automatically detecting the resolution of an image data use the characteristics of the reference signal in the input image control signal to determine the resolution of the input image data. The effect. Since the image data output by the front-end circuit needs to match the resolution of the panel, the technology of the present invention can realize the display panel supporting a plurality of resolutions by using a single timing controller, and reducing the production cost of the timing controller. efficacy.

BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a schematic view showing a display system in accordance with an embodiment of the present invention. The display system 1 includes a timing controller 10 that automatically detects the resolution of an image data, a front end circuit (such as a scale integrated circuit (Scaler)) 11, and a display panel 12. Generally, the display panel 12 has a predetermined resolution. The front end circuit 11 outputs the image data DV and a set of image control signals S to the timing controller 10. The image control signal S includes a plurality of reference signals Rf (not shown), and the reference signals may be a horizontal synchronization signal Hs, a vertical synchronization signal Vs, a data enable signal DE, or a baseband clock signal CK. . Then, the timing controller 10 receives the set of image control signals S and image data DV, and controls the timings of the source level, the gate level driver, and the peripheral circuits of the display panel according to the group of image control signals S to display images. It should be noted that in another embodiment, the image control signal S output by the front end circuit 11 may not include the horizontal synchronization signal Hs and the vertical synchronization signal Vs, and the horizontal synchronization signal Hs and the vertical synchronization signal Vs may be used by the timing controller. 10 is generated using its internal circuitry.

In one embodiment, the timing controller 10 includes a resolution detection circuit 101 and a timing control unit 102. The resolution detecting circuit 101 receives the set of image control signals S and image data DV, and determines the resolution of the image data DV according to the set of image control signals S, wherein the resolution of the image data DV includes a first dimensional resolution Rs1 Resolve Rs2 degrees with a second dimension.

The timing control unit 102 receives the set of image control signals S and image data DV, and generates a timing control signal C to the display panel 12 according to the first dimensional resolution Rs1 and the second dimensional resolution Rs2 to determine the display panel 12 Display timing.

2 is a schematic diagram showing a resolution detecting circuit 101 according to an embodiment of the present invention. In the figure, the resolution detecting circuit 101 includes a first determining circuit 201 and a second determining circuit 202. 3 is a timing diagram showing signals when the timing controller 10 and the resolution detecting circuit 101 operate in accordance with an embodiment of the present invention.

Please also refer to Figures 1, 2 and 3.

First, as shown in FIG. 2, the first determining circuit 201 receives the first reference signal Rf1 outputted by the front end circuit 11, and generates the first dimensional resolution Rs1 according to the enabling period of the first reference signal Rf1. The second determining circuit 202 also receives the first reference signal Rf1, and generates a second dimensional resolution Rs2 according to the number of times the first reference signal Rf1 is activated within a preset time. Of course, the second determining circuit 202 can also generate the second dimensional resolution Rs2 according to the first dimensional resolution Rs1.

In an embodiment, the first determining circuit 201 can be a horizontal resolution determining circuit; the second determining circuit 202 can be a vertical resolution determining circuit; and the first reference signal Rf1 can be the data enabling signal DE, Or horizontal sync signal Hs. It should be noted that the data enable signal DE and the horizontal sync signal Hs are synchronized with the image data DV of the image display screen.

Taking the data enable signal DE as an example, as shown in FIG. 3, since each data enable signal DE is in an enable state, it indicates that the front end circuit 11 transmits a scan line data to the timing controller 10 . Therefore, the second determining circuit 202 of FIG. 2 can determine the number of the image data DV according to the number of times the data enabling signal DE is within a preset time of the image data (for example, a frame time). Two-dimensional resolution Rs2 (ie vertical resolution).

In one embodiment, it is assumed that the set of image control signals S includes a vertical sync signal Vs, and the first reference signal Rf1 is a data enable signal DE. Then, the second determining circuit 202 receives the data enable signal DE and the vertical sync signal Vs, and determines the pre-required second dimensional resolution Rs2 (vertical resolution) according to the first reference signal Rf1 (data enable signal DE). The time is set: in FIG. 3, the time when the voltage value of the vertical synchronization signal Vs in one cycle is a first voltage level, for example, at the end of one frame of the image data DV and the beginning of the next frame.

In one embodiment, it is assumed that the set of image control signals S includes a fundamental frequency pulse signal CK, and the first reference signal Rf1 is a data enable signal DE. Please refer to the data enable signal DE at the dotted line in Figure 3 and the amplified DE and CK waveforms shown at the bottom of the figure. When each data enable signal DE is enabled, that is, when a scan line data is being transmitted to the timing controller 10, as long as the fundamental frequency clock signal CK is enabled once, the front end circuit 11 will Transfers a pixel of the scan line. Therefore, the operation of the first determining circuit 201 is to receive the fundamental frequency clock signal CK and the first reference signal Rf1 (the data enable signal DE), and the fundamental frequency clock signal CK according to the data enable signal DE is enabled. The number of enablements produces a first dimensional resolution (ie, horizontal resolution).

For example, if the input image data DV is a data having a resolution equal to 1280*1024, the second determining circuit 202 converts the vertical synchronization signal Vs above the third picture from a low voltage level 0 to a high voltage level. At 1 o'clock, the number of times of the first reference signal Rf1 (data enable signal DE) is counted, and the count is continued until the vertical sync signal Vs is switched from the high voltage level 1 to the low voltage level 0, and then one is obtained. The second dimensional resolution Rs2 (vertical resolution) is 1024; in contrast, the first determining circuit 201 counts the fundamental frequency clock signal CK when the first reference signal Rf1 (data enable signal DE) is in the same state. The number of times is obtained to obtain a first dimensional resolution Rs1 (horizontal resolution)=1280. Next, the resolution detecting unit 101 outputs the first dimensional resolution Rs1=1280 and the second dimensional resolution Rs2=1024 for the timing control unit 102 to refer to. Thereafter, the timing control unit 102 receives the first and second dimensional resolutions Rs1, Rs2, and selects a control parameter corresponding to the resolution 1280*1024 from among a plurality of built-in control parameters to generate a timing control signal C, The timing of the display panel 12 is accurately controlled according to the resolution of the image data DV, and the effect of correctly displaying the image is achieved.

It should be noted that the circuit and the design manner of the built-in parameters of the timing control unit 102 are known in the prior art, and are not repeatedly described. While the above embodiment determines the horizontal resolution by calculating the number of times the fundamental frequency clock signal CK is enabled, it should be understood by those skilled in the art that the above examples are merely one embodiment of the present invention, as long as the data is known. The relationship between the enable signal DE and the horizontal resolution can also be detected by other clock signals with different frequencies than the fundamental frequency clock signal. Furthermore, in another embodiment, the technique of the present invention only needs to calculate all possible information during the enabling period of the data enable signal DE, and can be determined according to the enabling period (for example, the length of the enabling period). The horizontal resolution of the image data DV.

Furthermore, the present invention can also use the other signals of the group of image control signals S to determine the resolution. For example, in FIG. 3, when the vertical synchronization signal Vs is at a high level, the number of times of the horizontal synchronization signal Hs is calculated, and the second dimensional resolution (vertical resolution) of the image data DV can also be determined. Furthermore, in another embodiment, the technique of the present invention only needs to calculate the number of times of the fundamental frequency clock signal CK during the period in which the horizontal synchronization signal Hs is enabled, and the image data DV can be determined according to the enabling period. The first dimensional resolution (horizontal resolution) is mainly due to different resolution liquid crystal display panels (for example, 800×600, 1024×768, or 1280×1024, etc.), and the resolution varies greatly, even if the horizontal synchronization signal The period during which Hs is enabled differs from the period during which the data enable signal DE is enabled, but this difference does not affect the resolution of the resolution. For example, the number of times the baseband clock signal CK is enabled during the period when the data enable signal DE is enabled. To obtain a first dimensional resolution (horizontal resolution) = 800, and the number of times the fundamental frequency clock signal CK is enabled during the period of Hs enable to obtain a judgment value of 890, and the Hs enable can still be utilized. During the period, the base frequency clock signal CK enable number is matched with the lookup table to obtain the first dimensional resolution (horizontal resolution)=800. Therefore, the present invention is not limited to the above embodiments.

In addition, the present invention can also obtain the first dimensional resolution (horizontal resolution) of the image data DV, and then the second dimensional resolution (vertical resolution) is obtained by using the built-in look-up table without calculation (and vice versa) However, since most of the horizontal resolution and the vertical resolution are paired, for example, a liquid crystal display panel of 800×600, 1024×768, or 1280×1024 resolution, when the horizontal resolution is 800, the inside is utilized. The table can be found to have a vertical resolution of 600.

4A is a flow chart showing a method of detecting the resolution of an image data according to an embodiment of the present invention. The method comprises the following steps: Step S402: Start.

Step S404: Receive a set of image control signals; and step S406: determine a resolution of the image data according to the set of image control signals, wherein the resolution includes a first dimensional resolution and a second dimensional resolution.

Step S408: End.

It should be noted that when the group of image control signals includes a first reference signal, the step S406 determines the first dimensional resolution according to the first reference signal. The first reference signal may be a data enable signal or a horizontal synchronization signal. And if the group of image control signals further includes a baseband clock signal, the step S406 generates the first dimensional resolution according to the number of times the first reference signal is enabled in the baseband clock signal. The first dimension resolution is a horizontal resolution.

Furthermore, the step S406 can further determine the second dimensional resolution according to the number of times the first reference signal is activated within a preset time, wherein the second dimensional resolution is a vertical resolution. The preset time may be a frame time or a time when the voltage value of the vertical synchronization signal in a cycle is a first voltage level.

In addition, the method for detecting the resolution of an image data according to another embodiment of the present invention may further generate a second dimensional resolution in a table lookup manner according to the first dimensional resolution of step S406.

In summary, the method for detecting the resolution of an image data and the timing controller for automatically detecting the resolution of an image data use the characteristics of the reference signal Rf in the input image control signal S to achieve the judgment. Enter the effect of the resolution of the image data. Since the image data output by the front-end circuit needs to match the resolution of the panel, the technology of the present invention can realize the display panel supporting a plurality of resolutions by using a single timing controller, and reducing the production cost of the timing controller. efficacy.

The present invention has been described above by way of examples, and the scope of the invention is not limited thereto, and various modifications and changes can be made by those skilled in the art without departing from the scope of the invention.

1. . . display system

10. . . Timing controller

11. . . Front end circuit

12. . . Display panel

101. . . Resolution detection circuit

102. . . Timing control unit

201. . . First judgment circuit

202. . . Second judgment circuit

Figure 1 shows a schematic diagram of a display system in accordance with an embodiment of the present invention.

2 is a schematic diagram showing a resolution detecting circuit according to an embodiment of the invention.

FIG. 3 is a timing diagram showing the timing of the operation of the timing controller and the resolution detecting circuit according to an embodiment of the invention.

FIG. 4 is a flow chart showing a resolution detecting method according to an embodiment of the present invention.

1. . . display system

10. . . Timing controller

11. . . Front end circuit

12. . . Display panel

101. . . Resolution detection circuit

102. . . Timing control unit

Claims (20)

A method for detecting the resolution of an image data, the method comprising: (a) receiving a set of image control signals; (b) determining a resolution of the image data according to the set of image control signals, wherein the resolution comprises a a first dimensional resolution and a second dimensional resolution; and (c) generating a timing control signal according to the first dimensional resolution and the second dimensional resolution. The method of claim 1, wherein the set of image control signals includes a first reference signal, and the step (b) determines the first dimensional resolution based on the first reference signal. For example, in the method of claim 2, the image control signal further includes a fundamental frequency pulse signal, and the step (b) is based on the fundamental frequency pulse signal when the first reference signal is in an enabled state. The first dimension resolution is generated by the number of times, wherein the first dimension resolution is a horizontal resolution. The method of claim 2, wherein the step (b) determines the second dimensional resolution according to the number of times the first reference signal is activated within a predetermined time, wherein the second dimensional resolution For a vertical resolution. The method of claim 4, wherein the preset time is a frame time of the image data. The method of claim 4, wherein the set of image control signals comprises a vertical sync signal, wherein the preset time is a time when the voltage value of the vertical sync signal in a period is a first voltage level. The method of claim 2, further comprising: generating the second dimensional resolution in a table lookup manner according to the first resolution. The method of claim 2, wherein the first reference signal is a data enable signal. The method of claim 2, wherein the first reference signal is a horizontal synchronization signal. A timing controller for automatically detecting an image data resolution, the timing controller receiving the image data and a set of image control signals, the timing controller includes: a resolution detection circuit, the resolution detection circuit is The set of image control signals determines the resolution of the image data, wherein the resolution includes a first dimensional resolution and a second dimensional resolution; and a timing control unit, according to the first dimensional resolution and the second Dimensional resolution to generate a timing control signal. The timing controller of claim 10, wherein the set of image control signals includes a first reference signal, the resolution detecting circuit includes: a first determining circuit receiving the first reference signal, the first a determining circuit generates the first dimensional resolution according to the enabling period of the first reference signal; and a second determining circuit receives the first reference signal and generates the first reference signal according to the first reference signal within a preset time period The number of times produces the second dimension resolution. The timing controller of claim 11, wherein the first determining circuit further receives a fundamental frequency clock signal, and the first determining circuit is configured to be based on the first reference signal when the first reference signal is in an enabled state. The number of times the signal is enabled produces the first dimensional resolution. For example, the timing controller described in claim 12, the first reference signal is a data enable signal. For example, the timing controller described in claim 12, the first reference signal is a horizontal synchronization signal. The timing controller of claim 11, wherein the preset time is a frame time of the image data and the first reference signal is a data enable signal. The timing controller of claim 11, wherein the group of image control signals comprises a vertical sync signal, wherein the preset time is a voltage value of the vertical sync signal in a period of a first voltage level. Time, and the first reference signal is a data enable signal. The timing controller of claim 10, wherein the set of image control signals includes a first reference signal, the resolution detecting circuit includes: a first determining circuit, receiving the first reference signal, and Generating the first dimensional resolution according to the first reference signal; and a second determining circuit, generating the second dimensional resolution according to the first dimensional resolution. The timing controller of claim 17, wherein the first determining circuit further receives a fundamental frequency clock signal, and the first determining circuit is configured to be based on the first reference signal when the first reference signal is in an enabled state. The number of times the signal is enabled produces the first dimensional resolution. The timing controller of claim 17, wherein the first determining circuit generates the first dimensional resolution according to the number of times the first reference signal is enabled in a frame time of the image data. The timing controller of claim 17, wherein the first reference signal is a data enable signal.