TWI387216B - Pulse width digitizing method and pulse width digitizer using thereof - Google Patents
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本發明是有關於一種脈寬(Pulse Width,PW)訊號數位器,且特別是有關於一種應用三角積分(Sigma-delta)調變演算法之PW訊號數位器。The invention relates to a Pulse Width (PW) signal digitizer, and in particular to a PW signal digitizer applying a Sigma-delta modulation algorithm.
在現有技術中,脈寬(Pulse Width,PW)訊號調變及偵測技術係已廣為人們所周知,並將其實現在許多應用場合中。一般來說,如何以精細之解析度來偵測PW之技術,是業界不斷致力的方向之一。傳統上,許多PW偵測方法,例如是低通濾波(Low Pass Filtering)處理方法及直接取樣(Direct-sampling)處理方法,係已經存在。低通濾波處理方法係對電壓域(Voltage Domain)之PW資訊進行操作。首先PW訊號經由低通濾波器進行平均操作,以找出直流(Direct Current,DC)電壓。接著應用電壓比較器來比較此直流電壓及臨界電壓。然而,低通濾波後之脈寬訊號的不平滑特性(Smoothness)會影響PW偵測的解析度。由於PW偵測的解析度可經由提高偵測週期來提升,使得使用者在應用低通濾波處理方法時,需在PW偵測的解析度及偵測速度間進行權衡考量。In the prior art, Pulse Width (PW) signal modulation and detection technology has been widely known and will be used in many applications. In general, how to detect PW technology with fine resolution is one of the direction that the industry is constantly striving for. Traditionally, many PW detection methods, such as Low Pass Filtering processing methods and Direct-sampling processing methods, have existed. The low pass filtering method operates on the PW information of the Voltage Domain. First, the PW signal is averaged through a low pass filter to find the Direct Current (DC) voltage. A voltage comparator is then applied to compare the DC voltage and the threshold voltage. However, the smoothness of the low-pass filtered pulse width signal affects the resolution of the PW detection. Since the resolution of the PW detection can be improved by increasing the detection period, the user needs to make a trade-off between the resolution and the detection speed of the PW detection when applying the low-pass filtering method.
另一方面,直接取樣處理方法在時間域(Time Domain)中對資料進行處理。PW訊號先經過硬限操作(Hard limited),之後直接以高頻參考時脈訊號來進行取樣,以對PW訊號進行PW偵測。然而,起因於不足的取樣頻率(即是量化抖動(Quantization Jitter)),使得PW偵測的解析度受限於時間域上的量化誤差(Quantization Noise),而對於直接取樣處理方法來說,起因於不足的取樣頻率之量化抖動仍然是影響PW偵測解析度的主要限制。On the other hand, the direct sampling processing method processes the data in the Time Domain. The PW signal is first subjected to hard limited operation (Hard limited), and then directly sampled by the high frequency reference clock signal to perform PW detection on the PW signal. However, due to insufficient sampling frequency (ie, quantization jitter), the resolution of PW detection is limited by the quantization error in the time domain, and for the direct sampling processing method, the cause Quantization jitter at insufficient sampling frequency is still the main limitation affecting the resolution of PW detection.
據此,如何設計出可有效地克服前述PW訊號調變及偵測方法的問題,並可有效地實現出高解析度之PW偵測方法為業界不斷致力的方向之一。Accordingly, how to design a method that can effectively overcome the above-mentioned PW signal modulation and detection method, and effectively realize a high-resolution PW detection method is one of the directions that the industry is constantly striving for.
本發明係有關於一種脈波寬度(Pulse Width,PW)數位化電路,其應用轉換器來將輸入PW訊號轉換為電流訊號,並應用數位器(Digitizer)來根據電流訊號產生數位訊號。本發明相關之PW數位化電路更應用迴授路徑來以負迴授控制之方式控制電流訊號收斂至一特定數值,並據以控制數位訊號切換於第一數位碼(Code)及第二數位碼之間。本發明相關之PW數位化電路更應用數位濾波器來計算數位訊號對應至第一數位碼及第二數位碼的次數,並據以得到PW訊號的PW資訊。換言之,本發明相關之PW數位化電路將三角積分(Delta-sigma)機制來實現輸入PW訊號之PW偵測。如此,相較於傳統PW偵測方法,本發明相關之PW數位化電路具有可有效地執行具有高解析度及良好偵測速度之PW偵測操作,及量化抖動(Quantization Jitter)較低之優點。The invention relates to a pulse width (PW) digitization circuit, which uses a converter to convert an input PW signal into a current signal, and uses a digitizer to generate a digital signal according to the current signal. The PW digitizing circuit of the present invention further applies a feedback path to control the current signal to converge to a specific value in a negative feedback control manner, and accordingly controls the digital signal to be switched between the first digital code (Code) and the second digital code. between. The PW digitizing circuit of the present invention further applies a digital filter to calculate the number of times the digital signal corresponds to the first digit code and the second digit code, and obtains PW information of the PW signal accordingly. In other words, the PW digitizing circuit of the present invention implements a delta-sigma mechanism to implement PW detection of the input PW signal. Therefore, compared with the conventional PW detection method, the PW digitization circuit of the present invention has the advantages of effectively performing PW detection operation with high resolution and good detection speed, and low quantization jitter (Quantization Jitter). .
根據本發明第一方面提出一種PW數位化系統,用以提供PW訊號之PW資訊。PW數位化系統包括感測器、電流泵(Current Pump)、第一電容、數位器(Digitizer)、第一迴授控制器及數位濾波器。感測器用以提供PW訊號。電流泵用以回應於PW訊號提供電流訊號。第一電容用以回應於電流訊號提供電壓訊號。數位器用以回應於電壓訊號提供數位訊號。第一迴授控制器用以回應於數位訊號提供迴授PW訊號,其中迴授PW訊號被選擇性地迴授至感測器及電流泵其中之一,以分別控制PW訊號收斂至特定PW值及控制電流訊號收斂至特定數值,並據以控制數位訊號切換於第一數位碼(Code)及第二數位碼之間。數位濾波器用以計算數位訊號對應至第一數位碼之次數及數位訊號對應至第二數位碼之次數,並據以得到PW資訊。According to a first aspect of the present invention, a PW digitization system is provided for providing PW information of a PW signal. The PW digitalization system includes a sensor, a current pump, a first capacitor, a digitizer, a first feedback controller, and a digital filter. The sensor is used to provide a PW signal. The current pump is used to provide a current signal in response to the PW signal. The first capacitor is configured to provide a voltage signal in response to the current signal. The digital device is configured to provide a digital signal in response to the voltage signal. The first feedback controller is configured to provide a feedback PW signal in response to the digital signal, wherein the feedback PW signal is selectively fed back to one of the sensor and the current pump to respectively control the PW signal to converge to a specific PW value and The control current signal converges to a specific value, and the digital signal is controlled to be switched between the first digital code (Code) and the second digital code. The digital filter is configured to calculate the number of times the digital signal corresponds to the first digital code and the number of times the digital signal corresponds to the second digital code, and obtain PW information accordingly.
根據本發明第二方面提出PW數位化方法,用以提供PW訊號之PW資訊。PW數位化方法包括下列之步驟。首先於感測器接收PW訊號。接著於電流泵根據PW訊號提供電流訊號。然後根據電流訊號提供電壓訊號。接著根據電壓訊號提供數位訊號。然後回應於數位訊號提供迴授PW訊號,其中迴授PW訊號被選擇性地迴授至感測器及電流泵其中之一,以分別控制PW訊號收斂至特定PW值及控制電流訊號收斂至特定數值,並據以控制數位訊號切換於第一及第二數位碼之間。之後計算數位訊號對應至第一數位碼之次數及數位訊號對應至第二數位碼之次數,並據以得到PW資訊。According to a second aspect of the present invention, a PW digitization method is provided for providing PW information of a PW signal. The PW digitization method includes the following steps. First, the PW signal is received at the sensor. The current pump then provides a current signal based on the PW signal. Then provide a voltage signal based on the current signal. Then provide a digital signal according to the voltage signal. Then, in response to the digital signal, a feedback PW signal is provided, wherein the feedback PW signal is selectively fed back to one of the sensor and the current pump to respectively control the convergence of the PW signal to a specific PW value and control the current signal to converge to a specific The value is controlled by the digital signal to be switched between the first and second digit codes. Then, the number of times the digital signal corresponds to the first digital code and the number of times the digital signal corresponds to the second digital code are calculated, and the PW information is obtained accordingly.
根據本發明第三方面提出一種PW數位化電路,用以提供PW訊號之PW資訊。PW數位電路包括電流泵、第一電容、數位器、第一迴授控制器、及數位濾波器。電流泵用以回應於PW訊號提供電流訊號。第一電容用以回應於電流訊號產生電壓訊號。數位器用以回應於電壓訊號提供數位訊號。第一迴授控制器用以回應於數位訊號提供迴授PW訊號,其中迴授PW訊號被迴授至電流泵,以控制電流訊號收斂至特定數值,並據以控制數位訊號切換於第一及第二數位碼之間。數位濾波器用以計算數位訊號對應至第一數位碼之次數及數位訊號對應至第二數位碼之次數,並據以得到PW資訊。According to a third aspect of the present invention, a PW digitizing circuit is provided for providing PW information of a PW signal. The PW digital circuit includes a current pump, a first capacitor, a digitizer, a first feedback controller, and a digital filter. The current pump is used to provide a current signal in response to the PW signal. The first capacitor is responsive to the current signal to generate a voltage signal. The digital device is configured to provide a digital signal in response to the voltage signal. The first feedback controller is configured to provide a feedback PW signal in response to the digital signal, wherein the feedback PW signal is fed back to the current pump to control the current signal to converge to a specific value, and accordingly, the digital signal is switched to the first and the third Between two digit codes. The digital filter is configured to calculate the number of times the digital signal corresponds to the first digital code and the number of times the digital signal corresponds to the second digital code, and obtain PW information accordingly.
為讓本發明之上述內容能更明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說明如下:In order to make the above-mentioned contents of the present invention more comprehensible, a preferred embodiment will be described below, and in conjunction with the drawings, a detailed description is as follows:
本發明實施例之脈波寬度(Pulse Width,PW)數位化電路應用三角積分(Delta-sigma)機制來進行PW偵測操作。The pulse width (PW) digitization circuit of the embodiment of the present invention applies a delta-sigma mechanism to perform a PW detection operation.
請參照第1圖,其繪示依照本發明第一實施例之脈波寬度數位化電路的方塊圖。PW數位化系統1包括感測器12、電流泵(Current Pump)14、電容C1、數位器(Quantizer)16、數位濾波器18及迴授控制器20。Referring to FIG. 1, a block diagram of a pulse width digitalization circuit in accordance with a first embodiment of the present invention is shown. The PW digitalization system 1 includes a sensor 12, a current pump 14, a capacitor C1, a Quantizer 16, a digital filter 18, and a feedback controller 20.
感測器12用以提供PW資訊待量測的PW訊號PWin 。請參照第2圖,其繪示乃第1圖之感測器12的詳細方塊圖。舉例來說,PW數位化系統1被應用於一通訊應用中,而感測器12係以超再生接收器(Super Regenerative Receiver)來實現,以接收射頻(Radio Frequency,RF)訊號,而PW訊號PWin 用以指示RF訊號的輸入功率值。舉例來說,感測器12包括天線12a、低雜訊放大器(Low Noise Amplifier)12b、振盪器12c、包絡偵測器(Envelope Detector)12d、限幅器(Limiter)12e及電流源12f。天線12a接收RF訊號RFin ,RF訊號RFin 接著經由低雜訊放大器12b之放大,並被提供至振盪器12c中。舉例來說,RF訊號RFin 為波幅調變(Amplitude-shift Keying,ASK)訊號。The sensor 12 is configured to provide a PW signal PW in to be measured by the PW information. Please refer to FIG. 2, which is a detailed block diagram of the sensor 12 of FIG. For example, the PW digitization system 1 is applied to a communication application, and the sensor 12 is implemented by a Super Regenerative Receiver to receive a Radio Frequency (RF) signal, and the PW signal is received. PW in is used to indicate the input power value of the RF signal. For example, the sensor 12 includes an antenna 12a, a Low Noise Amplifier 12b, an oscillator 12c, an Envelope Detector 12d, a Limiter 12e, and a current source 12f. The antenna 12a receives the RF signal RF in , and the RF signal RF in is then amplified by the low noise amplifier 12b and supplied to the oscillator 12c. For example, the RF signal RF in is an Amplitude-shift Keying (ASK) signal.
振盪器12c被電流源12f提供之驅動電流Idr 驅動,以回應於RF訊號RFin 產生振盪訊號OSC。振盪訊號OSC被提供至包絡偵測器12d及限幅器12e中,以經由找出振盪訊號OSC之包絡資訊的方式,找到PW訊號PWin 之PW資訊。舉例來說,在驅動電流Idr 被致能後,振盪器12c需要一段起始時間(Startup Time)始能開始產生振盪訊號OSC,而此段起始時間之長度實質上反比於RF訊號RFin 的功率,如第3圖所示。Drive current oscillator 12c is provided a current source 12f I dr driven in response to the RF signal RF in to generate the oscillation signal OSC. The oscillating signal OSC is provided to the envelope detector 12d and the limiter 12e to find the PW information of the PW signal PW in by finding the envelope information of the oscillating signal OSC. For example, after the drive current I dr is enabled, the oscillator 12c needs a start time (Startup Time) to start generating the oscillation signal OSC, and the length of the start time is substantially inversely proportional to the RF signal RF in The power is shown in Figure 3.
當RF訊號RFin 對應至低功率數值時,此段起始時間對應至期間Tstupl 。當RF訊號RFin 對應至高功率數值時,此段起始時間對應至期間Tstuph 。而對應至PW訊號PWin 產生之PW資訊PWh 及PWl 滿足下列條件:When the RF signal RF in corresponds to a low power value, the start time of this segment corresponds to the period T stupl . When the RF signal RF in corresponds to a high power value, the start time of this segment corresponds to the period T stuph . The PW information PW h and PW l corresponding to the PW signal PW in meet the following conditions:
PWl =TQ-Td-Tstupl PW l =TQ-Td-T stupl
PWh =TQ-Td-Tstuph PW h =TQ-Td-T stuph
其中Td為預設的重置時間(Reset Time);TQ為一段操作期間之長度,其之定義為兩個相鄰之重置時點RST間的固定時間長度。如此,經由指定PW訊號PWin 具有對應至此段起始時間之長度,則可有效地得到可用以指示RF訊號RFin 的輸入功率值的PW訊號PWin 。Where Td is the preset reset time (Reset Time); TQ is the length of a period of operation, which is defined as the fixed length of time between two adjacent reset time points RST. Thus, having a length corresponding to the starting point via the specified period of time in PW PW signal, it can be efficiently used to obtain the input power PW PW signal indicating the value of the RF signal RF in in.
請參照第4圖,其繪示乃第1圖之電流泵14的詳細方塊圖。電流泵14回應於PW訊號PWin 提供電流訊號Iin 。舉例來說,電流泵14包括電流源14a及14b,其係連接至節點ND。電流泵14經由節點ND連接至電容C1。電流源14a回應於致能位準之PW訊號PWin 為導通,以提供驅動電流Idr21 ,並回應於非致能位準之PW訊號PWin 為截止。Please refer to FIG. 4, which is a detailed block diagram of the current pump 14 of FIG. Current pump 14 provides a current signal I in response to the signal PW PW in. For example, current pump 14 includes current sources 14a and 14b that are coupled to node ND. Current pump 14 is connected to capacitor C1 via node ND. The current source 14a is turned on in response to the enable level PW signal PW in to provide the drive current I dr21 and is turned off in response to the non-enable level PW signal PW in .
電流源14b回應於參考PW訊號PWref 為導通,以提供驅動電流Idr3 ,其中參考PW訊號PWref 對應至一固定的PW值。驅動電流Idr2 及Idr3 之間之差值用以決定電流訊號Iin 。電容C1受到電流訊號Iin 之充電,以回應於電流訊號Iin 對應地產生電壓訊號Vin 。The current source 14b is turned on in response to the reference PW signal PW ref to provide a driving current I dr3 , wherein the reference PW signal PW ref corresponds to a fixed PW value. The difference between the drive currents I dr2 and I dr3 is used to determine the current signal I in . Capacitor C1 by the current signal I in charge, in response to a voltage signal corresponding to the current signal V in to I.
在各操作期間TQ中,數位器16回應於電壓訊號Vin 產生數位訊號VQT 。舉例來說,數位訊號VQT 為一位元(Bit)之數位訊號。當電壓訊號Vin 大於一臨界電壓時,數位訊號VQT 對應至數值1;當電壓訊號Vin 小於此臨界值時,數位訊號VQT 對應至數值0。During each operation period TQ, the digital device 16 generates a digital signal V QT in response to the voltage signal V in . For example, the digital signal V QT is a bit signal of a bit. When the voltage signal V in is greater than a threshold voltage, the digital signal V QT corresponds to the value 1; when the voltage signal V in is less than the threshold value, the digital signal V QT corresponds to the value 0.
迴授控制器20回應於數位訊號VQT 調變產生迴授PW訊號PWfb 。迴授PW訊號PWfb 例如被迴授至感測器12,以對PW訊號PWin 進行控制。在一個例子中,經由調變迴授PW訊號PWfb 的上升緣(Rising Edge)時間,迴授控制器20可以實現PW減法操作於PW訊號PWin 上,並據以實現對PW訊號PWin 之負迴授控制,藉此控制PW訊號PWin 、電流訊號Iin 及電壓訊號Vin 收斂至其對應之特定數值,及控制數位訊號VQT 切換於第一及第二數位碼之間。如此,經由PW三角積分之電路操作,數位濾波器18可回應於數位訊號VQT ,判斷PW訊號PWin 的PW資訊。接下來,將對前述PW減法操作、PW負迴授控制操作及PW三角積分操作做進一步的說明。The feedback controller 20 generates a feedback PW signal PW fb in response to the digital signal V QT modulation. The feedback PW signal PW fb is, for example, fed back to the sensor 12 to control the PW signal PW in . In an example, the feedback controller 20 can implement the PW subtraction operation on the PW signal PW in via the modulation Rising Edge time of the PW signal PW fb , and implement the PW signal PW in accordingly . Negative feedback control, thereby controlling the PW signal PW in , the current signal I in and the voltage signal V in to converge to their corresponding specific values, and controlling the digital signal V QT to be switched between the first and second digit codes. Thus, through the circuit operation of the PW delta integration, the digital filter 18 can determine the PW information of the PW signal PW in in response to the digital signal V QT . Next, the aforementioned PW subtraction operation, PW negative feedback control operation, and PW triangular integration operation will be further described.
請參照第5A及5B圖,其繪示乃第1圖之感測器12的相關訊號時序圖。在一個例子中,操作期間TQ可均等地分為子期間1st -Ts 、2nd -Ts 、3rd -Ts 及4th -Ts 。當數位訊號VQT 對應至數值0時,迴授PW訊號PWfb的上升緣被觸發於時點ST1,即是子期間1st -Ts 及2nd -Ts 間的邊界時點,如第5A圖所示。在這樣的條件下,PW訊號PWin 之PW值Dx 保持未進行相減操作之狀態。Please refer to FIGS. 5A and 5B , which are related timing diagrams of the sensor 12 of FIG. 1 . In one example, the operational period TQ can be equally divided into sub-periods 1 st -T s , 2 nd -T s , 3 rd -T s , and 4 th -T s . When the digital signal V QT corresponds to the value 0, the rising edge of the feedback PW signal PWfb is triggered at the time point ST1, that is, the boundary time between the sub-phases 1 st -T s and 2 nd -T s , as shown in FIG. 5A Show. Under such conditions, the PW value D x of the PW signal PW in remains in a state in which the subtraction operation is not performed.
當數位訊號VQT 對應至數值1時,迴授PW訊號PWfb 的上升緣被觸發於時點ST2,即是子期間2nd -Ts 及3rd -Ts 間的邊界時點,如第5B圖所示。換言之,相較於數位訊號VQT 對應至數值0時所執行操作,迴授PW訊號PWfb 上升緣被延遲一段子期間Ts (即是子期間2nd -Ts )。如此,(驅動電流源12f所執行之)提供驅動電流Idr1 之操作及(振盪器12c所執行之)產生振盪訊號OSC之操作被延遲一段子期間Ts ,而PW訊號PWin 的PWDx 將對應地被減去(即是縮減)一段子期間Ts 。這樣一來,感測器12可受控於迴授控制器20來調變PW訊號PWin ,使PW訊號PWin 對應至其之原始PW值Dx ,或對應至PW值Dx -Ts 。When the digital signal V QT corresponds to the value 1, the rising edge of the feedback PW signal PW fb is triggered at the time point ST2, that is, the boundary time between the sub-periods 2 nd -T s and 3 rd -T s , as shown in FIG. 5B Shown. In other words, the rising edge of the feedback PW signal PW fb is delayed by a sub-period T s (that is, the sub-period 2 nd -T s ) compared to the operation performed when the digital signal V QT corresponds to the value 0. Thus, the operation of supplying the drive current I dr1 (executed by the drive current source 12f) and the operation of generating the oscillation signal OSC (executed by the oscillator 12c) are delayed by a sub-period T s , and the PWD x of the PW signal PW in will be Correspondingly, the sub-period T s is subtracted (ie, reduced). In this way, the sensor 12 can be controlled by the feedback controller 20 to modulate the PW signal PW in such that the PW signal PW in corresponds to its original PW value D x or to the PW value D x -T s .
請參照第6圖,其繪示乃對應至第1至3圖的相關訊號時序圖。經由執行PW減法操作,可實現負迴授控制於PW訊號PWin 上,以控制PW訊號PWin 收斂至特定之PW值。舉例來說,此特定PW值為常數,而等於一倍的子期間Ts 。由於PW訊號PWin 收斂至此特定之PW值,根據PW訊號PWin 產生之電流訊號Iin 及電壓訊號Vin 亦將收斂至其對應之特定數值。在一個例子中,經由設定參考PW訊號PWref 對應至一倍的子期間Ts,電流源14a及14b將受到具有實質上相同PW值之PW訊號之控制,以對應地產生實質上相等的驅動電流Idr2 及Idr3 ;換言之,電流訊號Iin 及電壓訊號Vin 將分別收斂至零電流值及零電壓值。Please refer to FIG. 6 , which is a timing diagram of related signals corresponding to the first to third figures. By performing the PW subtraction operation, negative feedback control can be implemented on the PW signal PW in to control the PW signal PW in to converge to a specific PW value. For example, this particular PW value is a constant and is equal to a multiple of the sub-period T s . Since the signal PW PW in particular the convergence point value PW, PW signal PW in accordance with the current signal I in is generated and the voltage signal V in will also converges to a certain value of its corresponding. In one example, by setting the reference PW signal PW ref to a multiple of the sub-period Ts, the current sources 14a and 14b will be controlled by PW signals having substantially the same PW value to correspondingly generate substantially equal drive currents. I dr2 and I dr3 ; in other words, the current signal I in and the voltage signal V in will converge to a zero current value and a zero voltage value, respectively.
如前述段落所述,感測器12、電流泵14、數位器16及迴授控制器20可實現出一負迴授迴路。如此,數位訊號VQT 將持續地切換於數位碼1及0之間。數位濾波器18計算在一段取樣期間TDATA 中數位訊號VQT 對應至數位碼1之次數及數位訊號VQT 對應至數位碼0之次數,以對應地得到PW訊號PWin 的PW資訊。前述取樣期間TDATA 例如對應至8倍的操作期間TQ ,如第6圖所示。如此,可有效地執行三角積分調變操作,來找出PW訊號PWin 的PW資訊及RF訊號RFin 的輸入功率。As described in the preceding paragraphs, the sensor 12, the current pump 14, the digitizer 16, and the feedback controller 20 can implement a negative feedback loop. Thus, the digital signal V QT will be continuously switched between the digital code 1 and 0. The digital filter 18 calculates the number of times the digital signal V QT corresponds to the digital code 1 and the number of times the digital signal V QT corresponds to the digital code 0 during a sampling period T DATA to correspondingly obtain the PW information of the PW signal PW in . The aforementioned sampling period T DATA corresponds, for example, to an operation period T Q of 8 times as shown in FIG. In this way, the trigonometric integral modulation operation can be effectively performed to find the PW information of the PW signal PW in and the input power of the RF signal RF in .
在本實施例中雖僅以PW數位化系統1被應用於與超再生接收器配合之通訊應用場合的情形為例做說明,然,本發明實施例之PW數位化系統1並不侷限於此,而更可被應用於其他領域之操作中。In the embodiment, the case where the PW digitizing system 1 is applied to the communication application in cooperation with the super regenerative receiver is taken as an example. However, the PW digitizing system 1 of the embodiment of the present invention is not limited thereto. And can be applied to other areas of operation.
在本實施例中雖僅以PW數位化系統1中的感測器12為超再生接收器的情形為例做說明,然,本發明實施例之PW數位化系統1中的感測器12並不侷限於此,而更可以其他具有PW訊號輸出的感測器來實現。In the embodiment, the case where the sensor 12 in the PW digitizing system 1 is a super regenerative receiver is taken as an example. However, the sensor 12 in the PW digitizing system 1 of the embodiment of the present invention is It is not limited to this, but can be implemented by other sensors with PW signal output.
本發明實施例之PW數位化系統應用轉換器來將輸入PW訊號轉換為電流訊號;數位器來根據電流訊號產生數位訊號;迴授路徑來以負迴授控制之方式控制電流訊號收斂至一特定數值,並據以控制數位訊號切換於第一數位碼(Code)及第二數位碼之間;數位濾波器來計算數位訊號對應至第一數位碼及第二數位碼的次數,並據以得到PW訊號的PW資訊。換言之,本發明實施例之PW數位化電路將三角積分機制來實現輸入PW訊號之PW偵測。如此,相較於傳統PW偵測方法,本發明實施例之PW數位化電路具有可有效地執行具有高解析度及良好偵測速度之PW偵測操作,及量化抖動較低之優點。The PW digitization system of the embodiment of the invention applies a converter to convert the input PW signal into a current signal; the digitizer generates a digital signal according to the current signal; and the feedback path controls the current signal to converge to a specific manner in a negative feedback control manner. a value, and according to the control digital signal is switched between the first digital code (Code) and the second digital code; the digital filter calculates the number of times the digital signal corresponds to the first digital code and the second digital code, and accordingly PW information of PW signal. In other words, the PW digitization circuit of the embodiment of the present invention implements a triangular integration mechanism to implement PW detection of the input PW signal. Thus, the PW digitization circuit of the embodiment of the present invention has the advantages of effectively performing PW detection operation with high resolution and good detection speed, and lowering quantization jitter, compared to the conventional PW detection method.
本發明第二實施例之PW數位化系統應用另一種不同之迴授控制器迴路來執行迴授控制操作。請參照第7圖,其繪示依照本發明第二實施例之脈波寬度數位化系統的方塊圖。本發明實施例之PW數位化系統2與第一實施例之數位化系統不同之處在於迴授PW訊號PWfb 係被迴授至電流泵24,而非被迴授至感測器22。在本實施例中,電流泵24、數位器26、數位濾波器及迴授控制器30係形成PW數位化電路20,以執行PW轉數位之轉換操作。The PW digitization system of the second embodiment of the present invention applies another different feedback controller loop to perform the feedback control operation. Referring to FIG. 7, a block diagram of a pulse width digitalization system in accordance with a second embodiment of the present invention is shown. The PW digitization system 2 of the embodiment of the present invention is different from the digitization system of the first embodiment in that the feedback PW signal PW fb is fed back to the current pump 24 instead of being fed back to the sensor 22. In the present embodiment, the current pump 24, the digitizer 26, the digital filter, and the feedback controller 30 form a PW digitizing circuit 20 to perform a PW-to-digital conversion operation.
請參照第8圖,其繪示乃第7圖之感測器22的詳細方塊圖。在第二實施例中,PW訊號PWin並未被調變,且更應用一個額外的驅動控制器(Quench Controller)22g來提供電壓訊號VQ 驅動電流源22f。電壓訊號VQ 具有固定之上升緣,其係觸發於子期間1st -Ts 及2nd -Ts 的分界時點上。Please refer to FIG. 8 , which is a detailed block diagram of the sensor 22 of FIG. 7 . In the second embodiment, the PW signal PWin is not modulated, and an additional drive controller (Quench Controller) 22g is further applied to provide the voltage signal V Q drive current source 22f. The voltage signal V Q has a fixed rising edge which is triggered at the demarcation point of the sub-periods 1 st -T s and 2 nd -T s .
請參照第9圖,其繪示乃第7圖之電流泵24g的詳細方塊圖。第二實施例之PW數位化系統2係應用電流泵24,其中與第一實施例之電流泵14不同的是,電流泵24具有受控於迴授PW訊號PWfb 之電流源24b,而非如第一實施例之電流泵14具有受控於參考PW訊號PWref 之電流源14b。電流源24b係受到迴授PW訊號PWfb 之驅動以提供驅動電流Idr4 ,其中驅動電流Idr4 與電流源24a提供之驅動電流Idr2 對應至實質上相同的電流值。如此,如同第一實施例中受到PW數位化系統1所調變之電流訊號Iin一般地,由驅動電流Idr2 及Idr4 所決定之電流訊號Iin係收斂至零電流值。這樣一來,雖然具有不同的迴授路徑,仍可實現出相似於第一實施例中所描述之負迴授控制迴路,以執行相似的三角積分操作。Please refer to FIG. 9, which is a detailed block diagram of the current pump 24g of FIG. The PW digitizing system 2 of the second embodiment applies a current pump 24, wherein unlike the current pump 14 of the first embodiment, the current pump 24 has a current source 24b controlled by the feedback PW signal PW fb instead of The current pump 14 as in the first embodiment has a current source 14b controlled by a reference PW signal PW ref . Current source 24b by the feedback line drive signal PW PW FB to provide a drive current of I dr4, wherein the driving current and the current source I dr4 24a provided corresponding to the driving current I dr2 to substantially the same current value. Thus, as in the first embodiment, the current signal Iin by the PW digital modulation system of a general, the current signal Iin decided by the Department of the drive current I dr2 I dr4 converges to zero and the current value. In this way, although there are different feedback paths, a negative feedback control loop similar to that described in the first embodiment can be implemented to perform a similar triangular integration operation.
在本實施例中雖僅以PW數位化電路20具有如第7圖所述之電路結構的情形為例做說明,然而PW數位化電路20並不侷限於此,而更可以其他不同的電路結構來實現。In the present embodiment, the case where the PW digitizing circuit 20 has the circuit configuration as shown in FIG. 7 is taken as an example. However, the PW digitizing circuit 20 is not limited thereto, and other different circuit structures may be used. to realise.
在本實施例中,雖僅以PW數位化電路20應用於包括以超再生接收器實現之感測器22的PW數位化系統2中,以針對PW訊號PWin 執行PW轉數位之轉換操作的情形為例做說明,然而PW數位化電路20並不侷限於此,而更可應用於其他執行PW轉數位之轉換操作的應用場合中。In the present embodiment, although only the PW digitizing circuit 20 is applied to the PW digitizing system 2 including the sensor 22 implemented by the super regenerative receiver, the PW digit conversion operation is performed for the PW signal PW in The case is described as an example. However, the PW digitizing circuit 20 is not limited thereto, and is more applicable to other applications that perform a PW-to-digital conversion operation.
本發明實施例之PW數位化系統應用轉換器來將輸入PW訊號轉換為電流訊號;數位器來根據電流訊號產生數位訊號;迴授路徑來以負迴授控制之方式控制電流訊號收斂至一特定數值,並據以控制數位訊號切換於第一數位碼(Code)及第二數位碼之間;數位濾波器來計算數位訊號對應至第一數位碼及第二數位碼的次數,並據以得到PW訊號的PW資訊。換言之,本發明實施例之PW數位化電路將三角積分機制來實現輸入PW訊號之PW偵測。如此,相較於傳統PW偵測方法,本發明實施例之PW數位化電路具有可有效地執行具有高解析度及良好偵測速度之PW偵測操作,及量化抖動較低之優點。The PW digitization system of the embodiment of the invention applies a converter to convert the input PW signal into a current signal; the digitizer generates a digital signal according to the current signal; and the feedback path controls the current signal to converge to a specific manner in a negative feedback control manner. a value, and according to the control digital signal is switched between the first digital code (Code) and the second digital code; the digital filter calculates the number of times the digital signal corresponds to the first digital code and the second digital code, and accordingly PW information of PW signal. In other words, the PW digitization circuit of the embodiment of the present invention implements a triangular integration mechanism to implement PW detection of the input PW signal. Thus, the PW digitization circuit of the embodiment of the present invention has the advantages of effectively performing PW detection operation with high resolution and good detection speed, and lowering quantization jitter, compared to the conventional PW detection method.
本發明第二實施例之PW數位化系統係應用另一種不同之電路結構來實現。請參照第10圖,其繪示依照本發明第三實施例之脈波寬度數位化電路的方塊圖。PW數位化電路20'與前述實施例中之PW數位化電路不同之處在於其更應用積分器35及另一迴授控制器40來執行第二階(Second-order)迴授控制操作。The PW digitization system of the second embodiment of the present invention is implemented by applying another different circuit structure. Referring to FIG. 10, a block diagram of a pulse width digitizing circuit in accordance with a third embodiment of the present invention is shown. The PW digitizing circuit 20' is different from the PW digitizing circuit in the foregoing embodiment in that it further applies an integrator 35 and another feedback controller 40 to perform a second-order feedback control operation.
迴授控制器40用以回應於數位訊號VQT 對迴授電流訊號Ifb 進行調變。迴授控制器40將迴授電流訊號Ifb 迴授至積分器35。積分器35如第11圖所示,其中包括轉導器(Transconductor)35a、加法器35b、電容C3。轉導器35a根據電壓訊號Vin 經由轉到操作產生電流訊號Is 。加法器35b根據電流訊號Is 及迴授電流訊號Ifb 之差值產生差值Id 。電容C3用以對差值Id 進行積分,以產生濾波電壓訊號V'in 。濾波電壓訊號V'in 係被提供至數位器36,以對應地產生數位訊號VQT 。如此,PW數位化電路20'可被配置有針對量化雜訊移頻(Quantization Noise Shaping)之第二階高通濾波功能(即是積分器35),而非如前述實施例中僅具有一階高通濾波功能之PW數位化電路。The feedback controller 40 is configured to modulate the feedback current signal I fb in response to the digital signal V QT . The feedback controller 40 returns the feedback current signal I fb to the integrator 35. The integrator 35 is as shown in Fig. 11, and includes a transconductor 35a, an adder 35b, and a capacitor C3. Transducer 35a generates a current signal I s via the operation according to the voltage signal V in. The adder 35b generates a difference signal according to the difference current I s and the feedback current I fb of the signal I d. Capacitor C3 is used to integrate the difference I d to generate a filtered voltage signal V' in . The filtered voltage signal V' in is provided to the digital device 36 to correspondingly generate the digital signal V QT . As such, the PW digitizing circuit 20' can be configured with a second-order high-pass filtering function (ie, the integrator 35) for quantization noise shaping, instead of having only a first-order high-pass as in the foregoing embodiment. PW digitization circuit for filtering function.
本發明實施例之PW數位化系統應用轉換器來將輸入PW訊號轉換為電流訊號;數位器來根據電流訊號產生數位訊號;迴授路徑來以負迴授控制之方式控制電流訊號收斂至一特定數值,並據以控制數位訊號切換於第一數位碼(Code)及第二數位碼之間;數位濾波器來計算數位訊號對應至第一數位碼及第二數位碼的次數,並據以得到PW訊號的PW資訊。換言之,本發明實施例之PW數位化電路將三角積分機制來實現輸入PW訊號之PW偵測。如此,相較於傳統PW偵測方法,本發明實施例之PW數位化電路具有可有效地執行具有高解析度及良好偵測速度之PW偵測操作,及量化抖動較低之優點。The PW digitization system of the embodiment of the invention applies a converter to convert the input PW signal into a current signal; the digitizer generates a digital signal according to the current signal; and the feedback path controls the current signal to converge to a specific manner in a negative feedback control manner. a value, and according to the control digital signal is switched between the first digital code (Code) and the second digital code; the digital filter calculates the number of times the digital signal corresponds to the first digital code and the second digital code, and accordingly PW information of PW signal. In other words, the PW digitization circuit of the embodiment of the present invention implements a triangular integration mechanism to implement PW detection of the input PW signal. Thus, the PW digitization circuit of the embodiment of the present invention has the advantages of effectively performing PW detection operation with high resolution and good detection speed, and lowering quantization jitter, compared to the conventional PW detection method.
綜上所述,雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。In view of the above, the present invention has been disclosed in several preferred embodiments, and is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.
1、2...脈波寬度數位化系統1, 2. . . Pulse width digitalization system
12、22...感測器12, 22. . . Sensor
14、24、24'...電流泵14, 24, 24'. . . Current pump
16、26、26'...數位器16, 26, 26'. . . Digital device
18、28、28'...數位濾波器18, 28, 28'. . . Digital filter
20、30、30'、40...迴授控制器20, 30, 30', 40. . . Feedback controller
C1、C2、C2'...電容C1, C2, C2'. . . capacitance
12a、22a...天線12a, 22a. . . antenna
12b、22b...低雜訊放大器12b, 22b. . . Low noise amplifier
12c、22c...振盪器12c, 22c. . . Oscillator
12d、22d...包絡偵測器12d, 22d. . . Envelope detector
12e、22e...限幅器12e, 22e. . . Limiter
12f、14a、14b、22f、24a、24b...電流源12f, 14a, 14b, 22f, 24a, 24b. . . Battery
ND...節點ND. . . node
20、20'...脈波寬度數位化電路20, 20'. . . Pulse width digitalization circuit
22g...驅動控制器22g. . . Drive controller
35...積分器35. . . Integrator
35a...轉導器35a. . . Transducer
35b...加法器35b. . . Adder
第1圖繪示依照本發明第一實施例之脈波寬度數位化電路的方塊圖。1 is a block diagram of a pulse width digitalization circuit in accordance with a first embodiment of the present invention.
第2圖繪示乃第1圖之感測器12的詳細方塊圖。FIG. 2 is a detailed block diagram of the sensor 12 of FIG.
第3圖繪示乃第2圖的相關訊號時序圖。Figure 3 is a timing diagram of the related signals in Figure 2.
第4圖繪示乃第1圖之電流泵14的詳細方塊圖。Fig. 4 is a detailed block diagram of the current pump 14 of Fig. 1.
第5A及5B圖繪示乃第1圖之感測器12的相關訊號時序圖。5A and 5B are related timing diagrams of the sensor 12 of FIG. 1 .
第6圖繪示乃對應至第1至3圖的相關訊號時序圖。Figure 6 is a timing diagram of the correlation signal corresponding to the first to third figures.
第7圖繪示依照本發明第二實施例之脈波寬度數位化系統的方塊圖。Figure 7 is a block diagram showing a pulse width digitalization system in accordance with a second embodiment of the present invention.
第8圖繪示乃第7圖之感測器22的詳細方塊圖。FIG. 8 is a detailed block diagram of the sensor 22 of FIG. 7.
第9圖繪示乃第7圖之電流泵24g的詳細方塊圖。Fig. 9 is a detailed block diagram of the current pump 24g of Fig. 7.
第10圖繪示依照本發明第三實施例之脈波寬度數位化電路的方塊圖。Figure 10 is a block diagram showing a pulse width digitalization circuit in accordance with a third embodiment of the present invention.
第11圖繪示乃第10圖之積分器35的詳細方塊圖。Fig. 11 is a detailed block diagram of the integrator 35 of Fig. 10.
Claims (16)
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|---|---|---|---|
| TW98141938A TWI387216B (en) | 2009-12-08 | 2009-12-08 | Pulse width digitizing method and pulse width digitizer using thereof |
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| TW98141938A TWI387216B (en) | 2009-12-08 | 2009-12-08 | Pulse width digitizing method and pulse width digitizer using thereof |
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| TWI387216B true TWI387216B (en) | 2013-02-21 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7176819B1 (en) * | 2005-09-08 | 2007-02-13 | Agilent Technologies, Inc. | Precision low noise-delta-sigma ADC with AC feed forward and merged coarse and fine results |
| US20080272946A1 (en) * | 2007-05-02 | 2008-11-06 | Melanson John L | Signal processing system using delta-sigma modulation having an internal stabilizer path with direct output-to-integrator connection |
| US7519135B2 (en) * | 2001-08-15 | 2009-04-14 | Texas Instruments Incorporated | Direct radio frequency (RF) sampling with recursive filtering method |
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2009
- 2009-12-08 TW TW98141938A patent/TWI387216B/en active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7519135B2 (en) * | 2001-08-15 | 2009-04-14 | Texas Instruments Incorporated | Direct radio frequency (RF) sampling with recursive filtering method |
| US7176819B1 (en) * | 2005-09-08 | 2007-02-13 | Agilent Technologies, Inc. | Precision low noise-delta-sigma ADC with AC feed forward and merged coarse and fine results |
| US20080272946A1 (en) * | 2007-05-02 | 2008-11-06 | Melanson John L | Signal processing system using delta-sigma modulation having an internal stabilizer path with direct output-to-integrator connection |
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| TW201121253A (en) | 2011-06-16 |
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