TWI386942B - Non-volatile storage with source bias all bit line sensing and the related method therefor - Google Patents

Description

Non-volatile storage with source bias full bit line sensing and related methods

This invention relates to non-volatile memory.

Semiconductor memory has become increasingly popular in a variety of electronic devices. For example, non-volatile semiconductor memory is used in cellular phones, digital cameras, personal digital assistants, mobile computing devices, non-mobile computing devices, and other devices. Electrically erasable and programmable read only memory (EEPROM) and flash memory are the most popular non-volatile semiconductor memory. In the case of flash memory (also a type of EEPROM), the contents of one portion of the entire memory array or memory can be erased in one step as compared to conventional EEPROMs having all of the features.

Both conventional EEPROM and flash memory utilize floating gates that are positioned above and insulated from the channel regions in the semiconductor substrate. The floating gate is positioned between the source region and the drain region. The control gate is provided on and insulated from the floating gate. The threshold voltage (V _TH ) of the thus formed transistor is controlled by the amount of charge remaining on the floating gate. That is, the minimum amount of voltage that must be applied to the control gate before the transistor is turned on to allow conduction between the source and the drain of the transistor is controlled by the charge level on the floating gate.

Some EEPROM and flash memory devices have floating gates for storing two charge ranges, and thus, memory elements can be programmed between two states (eg, erased state and stylized state). Erase. Because each memory element can store a data bit, this flash memory device is sometimes referred to as a binary flash memory device.

A multi-state (also known as multi-level) flash memory device is implemented by identifying a plurality of different allowed/effectively programmed threshold voltage ranges. Each distinct threshold voltage range corresponds to a predetermined value of the encoded set of data bits in the memory device. For example, when each memory element can be placed in one of four discrete charge bands corresponding to four distinct threshold voltage ranges, the element can store two data bits.

Typically, the stylized voltage V _PGM applied to the control gate during the stylization operation is applied as a series of pulses whose magnitude increases over time. In one possible approach, the magnitude of the pulse is increased by a predetermined step size with each successive pulse, for example, 0.2-0.4 V. V _PGM can be applied to the control gate of the flash memory component. During the period between the stylized pulses, a verification operation is performed. That is, the programmed level of each of a group of components that are programmed in parallel is read between successive stylized pulses to determine whether the programmed level is equal to or greater than the verify bit to which the component is programmed. quasi. For a multi-state flash memory device array, a verification step can be performed for each state of the component to determine if the component has reached its verification level associated with the material. For example, a multi-state memory element capable of storing data in four states may need to perform a verify operation for three comparison points.

In addition, when programming an EEPROM or flash memory device (such as a NAND flash memory device in a NAND string), V _PGM is typically applied to the control gate and the bit line is grounded, thereby enabling the cell or memory. Electrons of the channels of the body elements (eg, storage elements) are injected into the floating gates. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the threshold voltage of the memory element rises, causing the memory element to be considered to be in a programmed state. This can be found in U.S. Patent No. 6,859,397, entitled "Source Side Self Boosting Technique For Non-Volatile Memory", and U.S. Patent Application Publication No. 2005/0024939, entitled "Detecting Over Programmed Memory", published on Feb. 3, 2005. More information on stylization; the full text of both cases is incorporated herein by reference.

The present invention provides a non-volatile storage device having the ability to sense stylized conditions of a non-volatile storage element using full bit line sensing.

In one embodiment, a non-volatile storage system includes a collection of non-volatile storage elements configured as NAND strings, wherein Each of the NAND strings is associated with a respective bit line, a respective sensing component, and a respective discharge path. One or more control circuits are in communication with the set of non-volatile storage elements. The or the control circuit: (1) during a first time period: (a) applying a source voltage to one of the sources of the NAND strings, and (b) preventing each individual bit a line coupled to the respective sensing component, and (c) coupling each bit line to the respective discharge path; and (2) during a second time period subsequent to the first time period, ( a) continuing to apply the source voltage to the source of each of the NAND strings, allowing each individual bit line to be coupled to the respective sensing component.

In another embodiment, a non-volatile storage system includes a set of non-volatile storage elements configured as NAND strings, wherein each of the NAND strings is associated with a respective bit line, a sense of individuality The test component is associated with a separate discharge path. One or more control circuits are in communication with the set of non-volatile storage elements. The control circuit: (a) applying a source voltage to one of the sources of the NAND strings, (b) coupling each bit line to the respective discharge path, and (c) After the coupling, one of the selected non-volatile storage elements in each of the NAND strings is programmed according to a potential of each of the individual bit lines.

In another embodiment, a non-volatile storage system includes: a first set of non-volatile storage elements associated with a first bit line and a respective discharge path; and a second bit line and a second set of one of the non-volatile storage elements associated with each of the respective discharge paths; and one or more control circuits in communication with the first set and the second set of non-volatile storage elements. The control circuit: (a) applying a source voltage to a source of the first set of storage elements, and (b) coupling the second bit line to the respective discharge paths to enable the application of the The source voltage is at least partially discharged from a potential of the first set of storage elements capacitively coupled to the second set of storage elements, and (c) after the potential is at least partially discharged, the second set is determined One of the storage elements selects one of the non-volatile storage elements to be stylized.

The present invention provides a non-volatile storage device having the ability to sense stylized conditions of one of the non-volatile storage elements using full bit line sensing.

One example of a memory system suitable for use in practicing the present invention uses a NAND flash memory structure that includes a plurality of transistors arranged in series between two select gates. The series connected transistors and the select gates are referred to as NAND strings. Figure 1 shows a NAND string Figure. Figure 2 shows the equivalent circuit of the NAND string. The NAND string depicted in FIGS. 1 and 2 includes four transistors 100, 102, 104, and 106 that are connected in series and sandwiched between a first select gate 120 and a second select gate 122. The gate 120 gate NAND string is connected to the bit line 126. The connection of the gate 122 gated NAND string to the source line 128 is selected. The selection gate 120 is controlled by applying an appropriate voltage to the control gate 120CG. The selection gate 122 is controlled by applying an appropriate voltage to the control gate 122CG. Each of the transistors 100, 102, 104, and 106 has a control gate and a floating gate. The transistor 100 has a control gate 100CG and a floating gate 100FG. The transistor 102 includes a control gate 102CG and a floating gate 102FG. The transistor 104 includes a control gate 104CG and a floating gate 104FG. The transistor 106 includes a control gate 106CG and a floating gate 106FG. The control gate 100CG is connected to the word line WL3, the control gate 102CG is connected to the word line WL2, the control gate 104CG is connected to the word line WL1, and the control gate 106CG is connected to the word line WL0. The control gates can also be provided as part of the word line. In one embodiment, transistors 100, 102, 104, and 106 are each a storage element (also referred to as a memory unit). In other embodiments, the storage element may comprise a plurality of transistors or may be different from the storage elements depicted in Figures 1 and 2. The selection gate 120 is connected to the selection line SGD (drain selection gate). Select gate 122 to connect to the selection line SGS (source selection gate).

Figure 3 is a circuit diagram depicting three NAND strings. A typical architecture of a flash memory system using a NAND structure would include several NAND strings. For example, three NAND strings 320, 340, and 360 are shown in a memory array with more NAND strings. Each of the NAND strings includes two select gates and four storage elements. Although four storage elements are illustrated for simplicity, modern NAND strings can have up to, for example, 32 or 64 storage elements.

For example, NAND string 320 includes select gates 322 and 327 and storage elements 323-326, NAND string 340 includes select gates 342 and 347 and storage elements 343-346, and NAND string 360 includes select gates 362 and 367 and storage element 363- 366. Each NAND string is connected to the source line by its select gate (eg, select gate 327, 347, or 367). The selection line SGS is used to control the source side selection gate. The various NAND strings 320, 340, and 360 are connected to the respective bit lines 321, 341, and 361 by selecting a selection transistor among the gates 322, 342, and 362. These selective transistors are controlled by the drain select line SGD. In other embodiments, it may not be necessary to use the select lines together between the NAND strings; that is, different select lines may be provided for different NAND strings. Word line WL3 is coupled to the control gates of storage elements 323, 343, and 363. Word line WL2 is coupled to the control gates of storage elements 324, 344, and 364. Word line WL1 is coupled to the control gates of storage elements 325, 345, and 365. Word line WL0 is coupled to the control gates of storage elements 326, 346, and 366. As can be seen, each bit line and each NAND string contains an array or set of storage elements. Word lines (WL3, WL2, WL1, and WL0) contain arrays or sets Combined column. Each word line connects the control gates of each of the storage elements in the column. Alternatively, the control gate can be provided by the word line itself. For example, word line WL2 provides control gates for storage elements 324, 344, and 364. In practice, there can be thousands of storage elements on a word line.

Each storage element can store data. For example, when storing a one-digit digital data, the range of possible threshold voltages (V _TH ) of the storage elements is divided into two ranges, which are assigned logical data "1" and "0". In one example of a NAND type flash memory, the _VTH is negative after erasing the storage element and is defined as a logic "1". The V _TH after the stylization operation is positive and is defined as a logic "0". When the _VTH is negative and an attempt is made to read, the storage element will turn "on" to indicate that the logic "1" is being stored. When the _VTH is positive and an attempt is made to perform a read operation, the storage element will not be turned on, indicating that the logic "0" is stored. The storage element can also store multiple information levels, for example, multiple digital data bits. In this case, the range of V _TH values is divided into the number of data levels. For example, if four information levels are stored, there will be four _VTH ranges assigned to the data values "11", "10", "01", and "00". In one example of a NAND type memory, the _VTH after the erase operation is negative and is defined as "11". Positive V _TH values are used for states "10", "01", and "00". The particular relationship between the data that is programmed into the storage element and the threshold voltage range of the component depends on the data encoding mechanism employed to store the component. For example, U.S. Patent No. 6,222,762 and U.S. Patent Application Publication No. 2004/0255090, the entireties of each of each of each of each of

U.S. Patent Nos. 5,386,422, 5,522,580, 5,570,315 Related examples of NAND-type flash memory and operations thereof are provided in U.S. Patent Nos. 5,774,397, 6, 046, 935, 6, 456, 528, and 6, 522, 580, each incorporated herein by reference.

When the flash storage component is programmed, a programmed voltage is applied to the control gate of the storage component and the bit line associated with the storage component is grounded. Electrons from the channel are injected into the floating gate. When electrons accumulate in the floating gate, the floating gate becomes negatively charged and the _{VTH of the} storage element rises. To apply a programmed voltage to the control gate of the memory element being programmed, the stylized voltage is applied to the appropriate word line. As discussed above, one of the storage elements in each of the NAND strings shares the same word line. For example, when the storage element 324 of FIG. 3 is programmed, a programmed voltage is also applied to the control gates of the storage elements 344 and 364.

4 depicts a cross-sectional view of a NAND string formed on a substrate. This view is simplified and not to scale. The NAND string 400 includes a source side select gate 406, a drain side select gate 424, and eight storage elements 408, 410, 412, 414, 416, 418, 420, and 422 formed on the substrate 490. A number of source/drain regions (one of which is source/drain region 430) are provided on either side of each storage element and select gates 406 and 424. In one method, substrate 490 employs a triple well technique that includes a p-well region 492 in n-well region 494, which in turn is within p-type substrate region 496. The NAND string and its non-volatile storage elements can be formed at least partially on the p-well region. In addition to the bit line 426 having the potential V _BL , a source supply line 404 having a potential V _SOURCE is provided. In one possible approach, a voltage can be applied to p-well region 492 via terminal 402. Voltage can also be applied to the n-well region 494 via terminal 403.

During a read or verify operation (including an erase-verify operation) (the condition of the storage element, such as its threshold voltage) is determined during this period, V is provided on the selected word line associated with the selected storage element _CGR . Additionally, it is recalled that the control gate of the storage element can be provided as part of the word line. For example, WL0, WL1, WL2, WL3, WL4, WL5, WL6, and WL7 may extend via control gates of storage elements 408, 410, 412, 414, 416, 418, 420, and 422, respectively. In a possible boosting mechanism, the read pass voltage V _READ can be applied to the unselected word lines associated with NAND string 400. Other boosting mechanisms apply V _READ to some word lines and lower voltages to other word lines. V _SGS and V _{SGD are} applied to select gates 406 and 424, respectively.

Figures 5a through 5d depict the stylization of non-volatile storage elements. In one possible stylization technique, the lower page, the middle page, and the upper page are programmed in the three steps depicted in Figures 5a, 5b, and 5c, respectively. Two _VTH distributions 510 and 512 are provided when the lower page of the data is programmed after the erase operation. The minimum distribution 510 represents the erased state and has a negative _VTH . Next, the first _VTH distribution 520 and the second _VTH distribution 522 of FIG. 5b are obtained from the first _VTH distribution 510 of FIG. 5a, respectively, and the third _VTH distribution 512 of FIG. 5a obtains the third of FIG. 5b, respectively. _VTH distribution 524 and fourth _VTH distribution 526. The first _VTH distribution and the second _VTH distribution of FIG. 5c representing the final erased state E and the first programmed state A, respectively, are obtained from the first _VTH distribution 520 of FIG. 5b. From the second _VTH distribution 522 of Figure 5b, the third _VTH distribution and the fourth _VTH distribution of Figure 5c representing the second programmed state B and the third programmed state C, respectively, are obtained. From the third _VTH distribution 524 of Figure 5b, the fifth _VTH distribution and the sixth _VTH distribution of Figure 5c representing the fourth programmed state D and the fifth programmed state E, respectively, are obtained. From the fourth _VTH distribution 526 of Figure 5b, the seventh _VTH distribution and the eighth _VTH distribution of Figure 5c representing the sixth programmed state F and the seventh programmed state G, respectively, are obtained. Additionally, code words 111, 011, 001, 101, 100, 000, 010, and 110 may be associated with states E, A, B, C, D, E, F, and G, respectively.

States E and A are examples of negative threshold voltage states. Depending on the implementation, one or more states may be a negative threshold voltage state.

Figure 5c also depicts a verify voltage for obtaining the indicated distribution. Specifically, the verify voltages V _VE , V _VA , V _VB , V _VC , V _VD , V _VE , V _{VF ,} and V _VG are associated with the distributions E, A, B, C, D, E, F, and G, respectively. During stylization, the threshold voltage to be programmed to a given distribution of storage elements is compared to the associated verify voltage. The storage element receives the stylized pulses via the associated word line until the threshold voltage of the elements is verified to have exceeded the associated verify voltage.

Figure 5d depicts a read voltage for reading a stylized state of a storage element. After the storage element has been programmed, it can be read using the read voltages V _RA , V _RB , V _RC , V _RD , V _RE , V _{RF ,} and V _RG . One or more storage elements and each read voltage are typically associated with a common word line to determine if the threshold voltage of the element exceeds the read voltage. The state of the storage element can then be determined by the highest read voltage that is exceeded. The read voltages are provided between adjacent states.

Note that the stylized process depicted is a possible example because other parties The legal system is possible.

Negative threshold voltage current sensing

In non-volatile storage devices, including non-volatile storage devices designed using NAND memory, there is no negative threshold voltage for sensing current sensing non-volatile storage elements during read or verify operations. A satisfactory method of state. Voltage sensing has been used, but it has been found that it takes a long time to complete. In addition, due to bit line to bit line capacitive coupling and other effects, voltage sensing is not yet suitable for full bit line sensing that simultaneously senses adjacent sets of storage elements. A possible solution includes adjusting the source voltage and the p-well pressure to a fixed positive DC level during sensing during current sensing; and via the associated word line of the sensed storage element The control gate of the storage element is connected to a potential lower than the source and p-well voltages. Component voltage and p-well voltage may also be different. By combining the bias of the source and p wells to a fixed potential, it is possible to sense one or more negative threshold voltage states using current sensing. In addition, because current sensing avoids many of the shortcomings of voltage sensing, it is compatible with full bit line sensing.

Figure 6a depicts a configuration of a NAND string and one of the components for sensing. In a simplified example, NAND string 612 includes four storage elements that are in communication with word lines WL0, WL1, WL2, and WL3, respectively. In practice, additional storage components and word lines can be used. In addition, the additional NAND strings are typically arranged adjacent to each other in blocks or other sets of non-volatile storage elements (see, for example, Figure 14). The storage element is coupled to the p-well region of the substrate. In addition to the sensing component 600, a bit line 610 having a voltage _{VBL is} depicted. In detail, a BLS (bit line sense) transistor 606 is coupled to bit line 610. BLS transistor 606 is a high voltage transistor and is turned on in response to control 608 during a sensing operation. The BLC (bit line control) transistor 604 is a low voltage transistor that is turned on in response to control 608 to allow the bit line to communicate with the current sensing module 602. During a sensing operation, such as a read or verify operation, a precharge operation occurs in which one of the capacitors in current sensing module 602 is charged. The BLC transistor 604 can be turned on to allow for pre-charging. Also, during the sensing operation, for a storage element having a negative threshold voltage state, a positive voltage is applied to the word line of one or more storage elements involved in the operation. Since a negative charge pump is not required to provide a negative word line voltage, it is advantageous to use a positive voltage for the selected word line in sensing operations that sense negative threshold voltages. Incorporating a negative charge pump into many non-volatile storage systems may require extensive process research and modification.

For example, suppose the selected word line is WL1. The voltage on WL1 is coupled to the control gate of the storage element on the word line as a control gate read voltage V _CGR . Additionally, a positive voltage V _SOURCE can be applied to the source side of the NAND string 630 and a positive voltage V _P-WELL can be applied to the p-well. In one implementation, V _SOURCE and V _{P-WELL are} greater than V _CGR . V _SOURCE and V _P-WELL may be different from each other, or they may be coupled to the same DC voltage V _DC . In addition, V _DC >V _CGR . As an example, the V _DC can be in the range of about 0.4 to 1.5 V, for example, 0.8 V. The higher V _DC causes a more negative threshold voltage state to be sensed. For example, the first negative threshold voltage state V _TH1 =−1.0 V and the second negative threshold voltage state V _TH2 =−0.5 V can be sensed using V _DC =1.5 V and V _DC =1.0 V, respectively. The V _DC can be set to a level such that V _DC -V _TH >0 V. Typically, to sense the negative threshold voltage, the word line and source voltages are set such that the gate to source voltage is less than zero, that is, V _GS <0 V. If the gate-to-source voltage is greater than the threshold voltage of the storage element (ie, V _GS >V _TH ), the selected storage element conducts. To sense the positive threshold voltage, the source and p wells can be held at the same voltage while the selected word line voltage is adjusted.

On the drain side of NAND string 630, BLS transistor 610 is turned on, for example, to conduct or turn it on. Additionally, a voltage V _{BLC is} applied to the BLC transistor 604 for conduction. The pre-charge capacitor in current sense module 602 is discharged into the source via a bit line such that the source acts as a current sink. The precharge capacitor at the drain of the NAND string can be precharged to a potential that exceeds the potential of the source such that when the selected storage element is in a conducting state, current flows through the selected non-volatile storage element and sinks into the source .

In particular, if a selected storage element is in a conducting state due to the application of V _CGR , a relatively high current will flow. If the selected storage element is in a non-conducting state, no current or relatively small current will flow. The current sensing module 602 can sense the unit/storage element current i _CELL . In one possible method, the current sensing module determines a voltage drop by the relationship ΔV=i. t/C is associated with a fixed current, where ΔV is the voltage drop, i is the fixed current, t is the predetermined discharge period and C is the capacitance of the pre-charge capacitor in the current sense module. See also Figure 6d, which depicts the voltage drop over time for different fixed current lines. A higher voltage drop indicates a higher current. At the end of a given discharge cycle, since i and C are fixed, ΔV of a given current can be determined. In one method, a p-mos transistor is used to determine the level of ΔV relative to a demarcation value. In another possible method, the cell current discriminator acts as a discriminator or comparator for the current level by determining whether the conduction current is above or below a given delimited current.

In contrast, voltage sensing does not include sensing the voltage drop associated with a fixed current. Alternatively, the voltage sensing includes determining whether charge sharing occurs between the capacitor in the voltage sensing module and the capacitance of the bit line. The current is not fixed or constant during sensing. When the selected storage element conducts, little or no charge sharing occurs, in which case the voltage of the capacitor in the voltage sensing module does not drop significantly. When the selected storage element is not conducting, charge sharing occurs, in which case the voltage of the capacitor in the voltage sensing module drops significantly.

The current sensing module 602 can therefore determine whether the selected storage element is in a conductive or non-conducting state by the level of the current. Typically, a higher current will flow when the selected storage element is in a conducting state, and a lower current will flow when the selected storage element is stored in a non-conducting state. When the selected storage element is in a non-conducting or conducting state, its threshold voltage is above or below a comparison level (such as verifying the level (see Figure 5c) or reading the level (see Figure 5d)).

Figure 6b depicts the waveform associated with Figure 6a. Waveform 620 depicts V _SOURCE and V _P-WELL , V _BL and V _BLC . V _SOURCE and V _{P-WELL are} set to an elevated level at t1 during the sensing operation. In one method, such as when the sensing operation includes a negative threshold voltage, V _SOURCE and V _P-WELL exceed V _CGR . However, for example, when the sensing operation includes a positive threshold voltage, V _SOURCE and V _P-WELL do not have to exceed V _CGR . V _BL increases with V _SOURCE between t1 and t2. At t2, the pre-charge capacitor is discharged, which in turn increases _VBL . Thus, the drain potential associated with the selected non-volatile storage element (e.g., _VBL ) is higher than the source potential (e.g., _VSOURCE ) associated with the selected non-volatile storage element. V _BLC tracks V _BL but is slightly higher due to the threshold voltage of the BLC transistor. In practice, after the rise, if current flows in the NAND string, V _BL will drop slightly (not shown). For example, when V _BLC = 2 V and the threshold voltage of the BLC transistor is 1 V, V _BL can rise to 1 V. When sensing, if current flows, V _BL can be reduced from 1 V to, for example, 0.9 V. Waveform 622 depicts a voltage applied to the BLS transistor indicating that the transistor is conducting between t0 and t5. Waveform 624 depicts a sense signal that is a control signal that indicates the time t after the capacitor begins to discharge in the current sense module.

Waveforms 626 and 628 depict the sense voltage of the selected bit line, which is associated with a fixed current. A determination can be made at t3 as to whether the voltage exceeds a certain level. It can be concluded that when the voltage drops below the delimiting level (eg, line 628), the selected storage element conducts. If the voltage does not fall below the demarcation level (eg, line 626), the selected storage element is not conducting.

Figure 6c depicts the sensing process associated with Figures 6a and 6b. Provide an overview of the sensing process. In this and other flow charts, the steps depicted are not necessarily taken as discrete steps and/or in the sequence described. A sensing operation such as a read or verify operation is initiated at step 640. Step 642 includes opening the BLS transistor and the BLC transistor to precharge the bit line. Step 644 includes setting the word line voltage. Step 646 includes setting V _SOURCE and V _P-WELL . Step 648 includes using current sensing to determine whether the storage element is conductive or non-conductive. If at decision step 650, another sensing operation is to be performed, then control flow continues at step 640. Otherwise, the process ends at step 652.

Multiple sensing operations can be performed continuously, for example, performing an operation for each verify or read level. In one method, the same source voltage and p-well voltage are applied in each sensing operation, but the selected word line voltage changes. Thus, in a first sensing operation, a first voltage can be applied to the control gate/word line of the selected storage element, the source voltage is applied to the source, and the p-well voltage is applied to the p-well. . Next, while applying the first voltage and the source voltage, current sensing is used to make a determination as to whether the storage element is in a conductive state or a non-conducting state. A second sensing operation includes applying a second voltage to the control gate while applying the same source voltage and p-well voltage. A determination is then made as to whether the storage element is in a conducting state or a non-conducting state. When the same source voltage and p-well voltage are used, successive sensing operations can similarly change the selected word line voltage.

Additionally, sensing can be performed simultaneously on a plurality of storage elements associated with a common word line and source. The plurality of storage elements can be in adjacent or non-adjacent NAND strings. The full bit line sensing previously discussed includes simultaneous sensing of storage elements in adjacent NAND strings. In this case, sensing includes determining whether each of the non-volatile storage elements is in a conductive state or a non-conducting state in a simultaneous sensing operation using current sensing.

Current sensing with source and P well bias

In non-volatile storage devices, including non-volatile storage devices designed using NAND memory, current sensing can be used to sense the threshold voltage state of a non-volatile storage element during a read or verify operation. However, this current sensing has caused a change in the source voltage or "bounce", especially at ground voltage. The degree of bounce depends on the level of current through the storage element. this In addition, bounce can cause sensing errors. A method of controlling cell source bounce during sensing is to sense using at least two gates. This minimizes the effect of cell source bounce. For example, in the case of current sensing, the current in the NAND string of the selected storage element can be sensed from each of the gates of the control. A relatively high or otherwise inaccurate bounce current may occur at the first gating, while a lower current occurs at the second gating, wherein the lower current more accurately represents the sensed state of the storage element. However, the use of additional gating to wait for current stability requires additional current and sensing time. See Figure 7a, which depicts changes in current and voltage as a function of time due to ground bounce during sensing operations.

Another technique is to couple the source to the gate and drain of the storage element. However, this technique is cumbersome, requires additional circuitry, and has an impact on the grain size and power consumption of the memory die. Moreover, this technique can not work well due to the RC delay from the source to the gate of the storage element.

A general approach to avoiding these shortcomings is to adjust the source and p wells to a fixed positive DC level during sensing, rather than ground. By keeping the source and p-wells at a fixed DC level and avoiding bouncing in the source voltage, we can use only one strobe to sense the data. As a result, the sensing time and power consumption are reduced. In addition, a large amount of additional circuitry is not required, so the grain size is not adversely affected. It is also possible to ground the p-well while adjusting the source voltage to a fixed positive DC level. Adjusting the source voltage to a fixed positive DC level is easier to achieve than adjusting the source voltage to ground because the regulation circuit only needs to sense a positive voltage. A voltage regulator typically adjusts its output by comparing its monitoring level based on (eg, source) to an internal reference voltage. Work. If the monitor level falls below the internal reference voltage, the voltage regulator can increase its output. Similarly, if the monitor level is increased above the internal reference voltage, the voltage regulator can reduce its output. For example, a voltage regulator can use an operational amplifier. However, if the reference voltage is grounded, the voltage regulator typically cannot reduce its output below 0 V if the monitor level becomes greater than 0 V. In addition, the voltage regulator may not be able to distinguish between monitoring levels below 0 V. Therefore, adjusting the source voltage to a fixed positive DC level avoids ground bounce and can reduce current consumption and sensing time. Referring to Figure 7b, there is depicted a decrease in current and voltage as the source voltage is adjusted to a fixed positive DC level during the sensing operation.

Figure 7c depicts another configuration of a NAND string and components for sensing. This configuration corresponds to the configuration provided in Figure 6a, except that the voltage regulator 720 is depicted. As mentioned, the source voltage and the p-well voltage can be adjusted to a fixed positive DC level during the sensing operation.

During a sensing operation of the storage element, such as a read or verify operation, a voltage is applied to the word line of one or more storage elements involved in the operation. For example, suppose the selected word line is WL1. This voltage is coupled to the control gate of the storage element on the word line as a control gate read voltage V _CGR . In addition, a fixed DC voltage can be applied to the source side of the NAND string 612 and the p-well as the source voltage V _SOURCE and the p-well voltage V _P-WELL , respectively. In one implementation, when the threshold voltage is negative, V _CGR may be positive ' and V _SOURCE and V _P-WELL may be greater than V _CGR . In one implementation, when the threshold voltage is positive, V _CGR may be greater than V _SOURCE and V _P-WELL . V _SOURCE and V _P-WELL may be different from each other, or they may be coupled to the same DC voltage V _DC . As an example, the V _DC can be adjusted by voltage regulator 720 to be in the range of about 0.4 to 1.2 V (eg, 0.8 V). As discussed previously, due to the constant voltage across the source and p-wells, accurate sensing can be achieved by using only one gate. Additionally, full bit line sensing (where the storage elements associated with all bit lines are sensed) can be performed (see Figure 14). In particular, voltage regulator 720 can receive a reference voltage V _{REF, SOURCE} (which is used to regulate V _SOURCE to a level greater than 0 V) and a reference voltage V _{REF, P-WELL} (which is used to p The well voltage is adjusted to a level greater than or equal to 0 V).

Figure 7d depicts the sensing process associated with Figures 7a-7c. A sensing operation such as a read or verify operation is initiated at step 700. Step 702 includes opening the BLS transistor and the BLC transistor and pre-charging the bit line. Step 704 includes setting a word line voltage. Step 706 includes adjusting V _SOURCE and V _P-WELL to a positive DC level. Step 708 includes using current sensing to determine whether the selected storage element is conductive or non-conductive. In decision step 710, if there is another sensing operation, the control flow continues at step 700. Otherwise, the process ends at step 712.

Additionally, as previously discussed, sensing can be performed simultaneously on a plurality of storage elements associated with a common word line and source. The plurality of storage elements can be in adjacent or non-adjacent NAND strings. In this case, sensing includes determining whether each of the non-volatile storage elements is in a conductive state or a non-conducting state in a simultaneous sensing operation using current sensing. For each sensing operation, the voltage is adjusted as discussed.

Source bias full bit line sensing

Full bit line sensing includes a sense of execution of storage elements in adjacent NAND strings Test operation (see Figure 14). A potential sensing method uses a DC storage element current to discharge a charge on a fixed capacitance in the sensing module for a fixed period of time to convert the threshold voltage value of the storage element into a digital data format. However, this requires a relatively large current sinking into the source side of the NAND string. Additionally, as previously discussed, to sense the negative threshold voltage value, a bias voltage can be applied to both the source and p-wells using analog voltage levels to avoid the need for negative word line voltages and negative charge pumps. . However, because full bit line sensing is very sensitive to source bias levels, maintaining a analog voltage level requires a relatively large voltage regulator and source voltage to be evenly distributed across the array. This can increase the required device area.

As discussed previously, another method of full bit line sensing uses voltage sensing. Since there is no DC current to the source side, this method does not require a large voltage regulator. However, due to the bit line-to-bit line coupling noise, this method has not been able to successfully sense each bit line at the same time. Alternatively, at a given time (eg, in parity sensing (see Figure 14)), only every other bit line is sensed. Therefore, from the time of sensing, performance is not optimal. In particular, due to the proximity of adjacent NAND strings, full bit sensing is problematic. Capacitive coupling can occur, particularly from the NAND string in which the selected storage element conducts to the NAND string in which the selected storage element is not conducting. The bit line voltage of the NAND string in which the selected storage element is not conducted is thereby increased, thereby interfering with the sensing operation. This capacitive coupling is depicted by a capacitance 813 to an adjacent bit line. Adjacent bit lines/NAND strings can be directly adjacent or non-contiguous. The capacitive coupling from adjacent bit lines/NAND strings is the strongest, but some electricity from non-adjacent bit lines/NAND strings can also occur. Capacitive coupling. A capacitor 811 to the ground terminal is also depicted.

To overcome these problems, sensing can be performed using the mechanism as depicted in Figure 8a. Figure 8a depicts the configuration of a NAND string and components, including a current discharge path. In a simplified example, NAND string 812 includes four storage elements that are in communication with word lines WL0, WL1, WL2, and WL3, respectively. In practice, additional storage elements and word lines can be used. Additionally, additional NAND strings are typically disposed adjacent to one another in blocks or other sets of non-volatile storage elements. The storage element is coupled to the p-well region of the substrate. In addition to the sensing component 800, a bit line 810 having a voltage _VBL is depicted. In particular, the initially opened or conductive BLS (bit line sense) transistor 806 is coupled to bit line 810 via sense node 814. BLS transistor 806 is a high voltage transistor and becomes conductive in response to control 808 during a sensing operation. The initially non-conducting BLC (bit line control) transistor 804 is a low voltage transistor that is turned on in response to control device 808 to allow the bit line to communicate with voltage sensing module/circuit 802. During a sensing operation, such as a read or verify operation, a pre-charge operation occurs in which one of the capacitors in voltage sensing module 802 is charged. The BLC transistor 804 can be turned on to allow for pre-charging.

In addition, a relatively weak current pull-down device is introduced. In particular, path 816, which is part of the current discharge path of NAND string 812, is coupled to sense node 814 (which is in turn coupled to bit line 810). A transistor in a conducting state (referred to as a GRS transistor 818) is provided such that path 816 is coupled to path 820 which is also part of the current discharge path. A current source 825 (eg, a current mirror) that provides current i _{REF is} provided parallel to paths 816, 820 to pull the current i _CELL on the paths down to ground. In one example, a relatively weak pulldown having an i _REF of about 150 nA is provided. However, the strength of current source 825 can vary depending on the particular implementation.

In a possible configuration, current source 825 is common to multiple bit lines and NAND strings. In this case, transistor 824 couples current source 825 to a different NAND string. Path 822 carries a control signal for GRS transistor 818 that is region-specific for a particular bit line and NAND string, while path 826 is a common ground path for a plurality of bit lines.

During sensing, the bit line will be charged to a level based on the threshold voltage and body effect of the selected storage element. In the case of negative Vti, the storage element will conduct even if V _GCR = 0 V. V _P-WELL can be set to 0 V.

The transistors 818 and 824 are made conductive to form a current discharge path and pull-down means for discharging any charge, the charge being coupled to the NAND from one or more adjacent NAND strings due to the capacitance 813 to the adjacent bit line String 812. Therefore, any extra charge generated by the coupling noise of adjacent bit lines will eventually disappear. After a certain amount of time, all of the bit lines reach their DC level, and BLC transistor 804 is turned "on" to allow charge sharing between voltage sensing module 802 and sense node 814, such that for selected storage elements Voltage sensing of the threshold voltage can occur. For example, voltage sensing module 802 can perform voltage sensing as part of a read or verify operation.

Figure 8b depicts the configuration of the NAND string and components of Figure 8a when voltage sensing occurs. Here, the BLC transistor 804 is turned on such that current flows from the voltage sensing module 802 to the discharge path in addition to the current discharged from the NAND string 812. Therefore, the GRS transistor remains in a conducting state such that the discharge continues during voltage sensing. Figure 8c depicts the waveforms associated with Figures 8a and 8b. V _SOURCE is depicted at waveform 830 and the voltages on three adjacent bit lines BL0, BL1, and BL2 are depicted at waveforms 832, 834, and 836, respectively. The voltage V _BLS on the BLS transistor is depicted at waveform 838 and the voltage V _BLC on the BLC transistor is depicted at waveform 840 and the voltage V _GRS on the GRS transistor is depicted at waveform 842. The sensed voltages on BL0 and BL2 are depicted at waveform 844. The sensed voltage on BL1 when the selected storage element on BL1 is conducting is depicted at waveform 846, and the sensed voltage on BL1 when the selected storage element on BL1 is not conducting is depicted at waveform 848. As mentioned, charge sharing between the voltage sensing module and the bit line occurs when the selected storage element is not conducting during voltage sensing. This charge sharing reduces the sensed voltage at the voltage sensing module. When the selected storage element conducts, little or no charge sharing between the voltage sensing module and the bit line occurs, so that the sensed voltage at the voltage sensing module remains high. Since the sensing did not occur, the sensed voltage at other times was not depicted.

At t0, V _{BLS is} increased, causing the BLS transistor to conduct. At t1, V _{SOURCE is} applied as the common source voltage of one of the NAND strings. In this example, we assume that the selected storage elements associated with BL1 are not conducting when the selected storage elements associated with BL0 and BL2 are conducting. BL0 is adjacent to BL1 on one side, and BL2 is adjacent to BL1 on the other side (see FIG. 14). As V _SOURCE increases at t1, V _BL0 and V _BL2 will rise as depicted by waveforms 832 and 836, respectively, resulting in capacitive coupling to BL1, as depicted by the transient increase in V _BL1 . By t2, this coupling will essentially disappear. As discussed, the GRS transistor of BL1 remains conductive during t1 and t5 to allow the bit line to discharge the coupled charge.

At t3, the BLC transistor is turned on by increasing the V _BLC as depicted by waveform 840, thereby allowing sensing for the selected storage element on BL1 to occur. Note that the corresponding components associated with BL0, BL2, and other bit lines can be similarly controlled to allow simultaneous sensing on their other bit lines. For BL1, if the selected storage element is not conducting, the sensed voltage at the voltage sensing module will drop as depicted by waveform 846. On the other hand, if the selected storage element conducts, the sense voltage will remain substantially high as depicted by waveform 844. The voltage sensing components can use voltage breakpoints at a specified sensing time t4 to determine whether the selected storage element is conductive or non-conductive. As mentioned, if the sensed voltage exceeds the breakpoint, this indicates that the storage element is open, and if the sensed voltage drops below the breakpoint, this indicates that the storage element is not conducting. V _SOURCE decreases at t5 and the BLS transistor does not conduct at t6, indicating the end of the sensing operation. In one possible approach, V _{P-WELL can be} set to 0 V during sensing. Depending on the particular sensing mechanism, the selected word line receives V _CGR while the unselected word line can receive the read pass voltage.

Therefore, after the source voltage is applied by t1, a predetermined delay of t3-t1 is set to allow sufficient time or at least partial discharge of the capacitive coupling from adjacent bit lines. The appropriate delay can be set as desired for a particular implementation based on theoretical and/or experimental testing. After the delay, voltage sensing occurs. At a specified time t4, a determination is made as to whether the storage element is in a conducting state or a non-conducting state and thus has a threshold voltage that is higher than the verify or read comparison level, respectively.

Figure 8d depicts the sensing process associated with Figures 8a-8c. At step 850, a sensing operation is initiated. At step 852, the BLS transistor is turned on while the BLC transistor remains non-conducting and the bit line is precharged. At step 854, the word line voltage is set. At step 856, V _SOURCE and V _P-WELL (V _P-WELL =0 V) are set. At step 858, the bit line is discharged. At step 860, the BLC transistor is conducted to allow sensing to occur. At step 862, voltage sensing is used to make a determination as to whether the selected storage element is conductive or non-conductive. In decision step 864, if there is another sensing operation, then control flow continues at step 850. Otherwise, the process ends at step 868.

Additionally, as previously discussed, sensing can be performed simultaneously on a plurality of storage elements associated with a common word line and source. The plurality of storage elements can be in adjacent or non-adjacent NAND strings. In this case, sensing includes determining whether each of the non-volatile storage elements is in a conductive state or a non-conducting state in a simultaneous sensing operation using current sensing. The delay before the BLC transistor is turned on can be set for each NAND string such that the NAND string can be discharged as needed before sensing occurs.

Temperature compensation bit line during sensing operation

In the non-volatile storage device of the present invention, such as a NAND flash memory device, temperature changes cause various problems in reading and writing data. The memory device is subject to varying temperatures based on the environment in which it is located. For example, some current memory devices are rated for use between -40 ° C and +85 ° C. Devices in industrial, military, and even consumer applications can experience significant temperature changes. Temperature affects many transistor parameters, the most important of which is the threshold voltage. In particular, temperature changes can cause read errors and widen the threshold voltage distribution of different states of the non-volatile storage element. Will be discussed below An improved technique for addressing the temperature effects in non-volatile storage devices.

Figure 9a depicts a NAND string and components for temperature compensated sensing. Components of the same number correspond to the components provided in Figure 8a. The current discharge path of Figure 8a is not depicted here. However, the configuration of Figure 8a may be combined with the configuration of some of Figure 9a or other figures provided herein. Additionally, a temperature dependent circuit 900 is provided as part of control 808 to provide a temperature compensated voltage to BLC transistor 804. BLC transistor 804 has a node coupled to voltage sensing module 802 and another node coupled to a NAND string 812 or a drain or bit line associated with other sets of non-volatile storage elements.

During a sensing operation, a voltage V _{BLC is} applied to the BLC transistor 804, which couples the bit line or drain side of the NAND string 812 to the voltage sensing module 802. According to the method herein, V _BLC is set based on the temperature to offset or compensate for the change in V _BL with temperature. Specifically, V _BLC = V _BL + V _TH (independent of temperature) + ΔV, where ΔV is a voltage change due to temperature. V _BL also changes ΔV due to temperature. Therefore, V _BLC can be controlled such that it changes with temperature according to the change of V _BL . In particular, by using the temperature dependent circuit 900, ΔV on the bit line can be matched to ΔV of V _BLC . Current i _CELL flows in NAND string 812. The dotted line indicates charge sharing.

Figure 9b illustrates the threshold voltage variation with temperature, for example, ΔV _TH / °C. Typically, the threshold voltage of a non-volatile storage element decreases with increasing temperature. The change in voltage with respect to temperature can be expressed by a temperature coefficient of typically about -2 mV/°C. The temperature coefficient depends on various characteristics of the memory device, such as doping, layout, and the like. In addition, it is desirable that the magnitude of the temperature coefficient increases as the size of the memory decreases.

In general, various techniques for providing temperature compensated signals are known. For example, one or more of these techniques can be used in temperature dependent circuit 900. Most of these technologies do not rely on obtaining actual temperature measurements, although this approach is also possible. For example, US Patent No. 6,801,454, entitled "Voltage Generation Circuitry Having Temperature Compensation", which is incorporated herein by reference, discloses a voltage generating circuit that outputs a read voltage to a non-volatile memory based on a temperature coefficient. The circuit uses a bandgap current comprising a temperature independent portion and a temperature dependent portion that increases with increasing temperature. U.S. Patent No. 6,560,152, entitled "Non-Volatile Memory With Temperature-Compensated Data Read," which is incorporated herein by reference, uses a bias generator circuit that applies a source or drain to a data storage element. The voltage is biased. U.S. Patent No. 5,172,338, the disclosure of which is incorporated herein by reference in its entirety in its entirety, in its entirety, in its entirety, in its entirety, in the same extent as the data storage unit. Reference storage unit on the bulk circuit die. The reference storage units provide reference levels and compare the measured current or voltage of the selected unit to the reference levels. Temperature compensation is provided because the reference level is affected by temperature in the same manner as the value read from the data storage unit. Any of these techniques, as well as any other known techniques, can be used to provide a temperature compensated voltage to the bit line control line, as described herein.

As discussed, V _BLC is the voltage of the control signal or the voltage provided to BLC transistor 804, which allows the sensing component to sense the _VTH of the selected storage element that is undergoing an erase-verify or other sensing operation. Sensing occurs via the bit line of the NAND string in which the selected storage element is located. In an example implementation, V _BLC = V _BL + V _TH (BLC transistor). Therefore, the control is configured to increase V _BLC with increasing temperature to track the increase in V _BL . For a given _{VTH of the} storage element, _VBL will increase with temperature.

Figure 9e illustrates the variation of V _BLC and V _BL with temperature. The figure depicts how V _BLC increases with temperature to track the increase in V _BL . A control curve that provides a specific change in temperature for V _BLC to temperature 808 can be programmed into control 808 based on theoretical and experimental results. Typically, the bit line voltage increases as the _{VTH of the} storage element decreases with higher temperatures. This means that the V _BLC should be higher to allow the voltage sensing module 802 to sense a higher V _BL . Note that the V _{TH of the} storage component dominates V _BL . However, the varying V _BLC changes the voltage sensed by the voltage sensing module such that the voltage is temperature compensated. Additionally, it is noted that variations in the _VTH of the BLC transistor 804 can be counteracted by providing a temperature dependent transistor similar to the BLC transistor 804 in the temperature dependent circuit 900.

Figure 9d depicts the waveforms associated with Figures 9a through 9c. Waveform 910 depicts V _SOURCE and V _P-WELL , which are set to an elevated level at t1 during the sensing operation. Waveforms 912 and 914 depict the increase in _VBL due to the application of _VSOURCE and Vp _-WELL . Waveform 912 depicts a higher level of _VBL at a higher temperature than waveform 914. In practice, after the rise, when the current flows in the NAND string, V _BL may drop slightly (not shown). Waveform 916 depicts the voltage applied to transistor BLS, which indicates that the transistor is turned "on" at t0. Waveforms 918 and 920 depict the voltage applied to transistor BLC at higher and lower temperatures, respectively. Note that the waveforms provided are for a temperature compensation mechanism combined with the mechanisms of Figures 8a through 8d, where the opening of the BLC transistor is delayed to allow the discharge to occur prior to sensing. However, the temperature compensation mechanism is not required to be used in this manner, and it can be used in other implementations that do not involve delays in the discharge path and/or sensing.

Waveform 922 depicts the sensed voltage in the voltage sensing module that selects the location line when the selected storage element is turned on, while waveform 924 depicts the sensed voltage when the selected storage element is not conducting. A determination is made at t2 as to whether the sensed voltage exceeds a breakpoint. It can be concluded that the selected storage element conducts when the sensed voltage exceeds the breakpoint, and the selected storage element does not conduct when the sensed voltage drops below the breakpoint.

Figure 9e depicts the sensing process associated with Figures 9a through 9d. A sensing operation, such as a read or verify operation, is initiated at step 930. Step 932 includes conducting the BLS transistor and the BLC transistor, precharging the bit line, and setting the temperature dependent V _BLC . Step 934 includes setting the word line voltage, which is temperature dependent as appropriate. In one method, only the selected word line voltage is temperature dependent, while in other methods, some or all of the word line voltage is temperature dependent. The word line voltage can be reduced as the temperature decreases as the _VTH decreases (see Figure 9b). Step 936 includes setting V _SOURCE and V _P-WELL . Step 938 includes using voltage sensing to determine whether the selected storage element is conductive or non-conductive. If it is determined at decision step 940 that another sensing operation will be performed, then control flow continues at step 930. Otherwise, the process ends at step 942.

Note that NAND is present because the storage elements on the drain side of the selected storage element are in a conducting state due to a sufficiently high voltage on the associated word line. The drain or bit line of the string is in communication with the drain of the selected storage element. Similarly, since the storage element on the source side of the selected storage element is in a conducting state due to a sufficiently high voltage on the associated word line, the source of the NAND string is in communication with the source of the selected storage element. Therefore, the voltage of the drain or bit line of the NAND string is also substantially the voltage of the drain of the selected storage element, and the voltage of the source of the NAND string is also substantially the voltage of the source of the selected storage element. Also, since the techniques described herein can be used with a single storage element, the sensed storage elements are not necessarily in other sets of NAND strings or storage elements.

Additionally, as previously discussed, sensing can be performed simultaneously on a plurality of storage elements associated with a common word line and source.

Moreover, from the perspective of control 808, the sensing process includes receiving information from the temperature dependent circuit 900 and providing a temperature compensated voltage to the control gate of the BLC transistor in response to the information, the BLC transistor NAND string or non-volatile storage element The other sets are coupled to the sensing circuit. Control may also set the word line, source and p-well voltages, and receive information from the voltage sensing module 802 regarding the sensed stylized conditions of the selected storage element.

Figure 9f depicts an erase-verify process. Step 950 includes erasing a collection of storage elements. Step 952 includes initiating the softening of one or more of the storage elements to, for example, an erased state. Soft programming typically involves applying a voltage pulse to the selected word line to raise the threshold voltage of one or more of the storage elements on the selected word line. The voltage pulse can be a soft stylized pulse that is less in amplitude than the pulse used to program to a higher state (step 954). For example, when the storage element is subjected to deep erase to ensure its full threshold voltage This type of stylization can be used when the part is below the threshold voltage of the state to be erased. Step 956 includes verifying the stylized condition of the storage element (e.g., relative to the state to be erased). For example, such verification can include performing steps 932-938 of Figure 9e as discussed above. At decision step 958, if the soft programming is to continue (e.g., when the storage element has not reached the desired erase state), then control flow continues at step 954. Otherwise, the process ends at step 960.

Additionally, an erase-verify operation can be performed simultaneously on a plurality of storage elements associated with a common word line and source.

Figure 10a illustrates the change in V _SOURCE with temperature. In another method, V _SOURCE is temperature compensated, for example, such that it increases with temperature. Typically, V _WL = V _SOURCE + V _TH (selected storage element), where V _WL is the voltage applied to the selected word line. As discussed, the _VTH decreases with temperature. Therefore, with V _WL fixed, V _SOURCE can be set to increase with temperature to avoid temperature bias during sensing. Additionally, in a possible implementation, constraints can be set such that V _SOURCE only increases to a positive value. For example, if V _SOURCE =0 V at baseline temperature and the temperature increases, V _SOURCE remains at 0 V. If the temperature is lowered, V _SOURCE increases according to the temperature coefficient. On the other hand, if V _SOURCE >0 V at baseline temperature and the temperature increases, V _SOURCE can be reduced to a value greater than or equal to 0 V (ie, non-negative). If the temperature is lowered, V _SOURCE increases according to the temperature coefficient.

Figure 10b depicts an example of a storage element array that includes different sets of NAND strings. Along the each row of the memory array 1000, the bit line 1006 is coupled to the drain terminal 1026 of the drain select gate of the NAND string 1050. Along the NAND string, the source line 1004 can be connected to the source selection gate of the NAND string. Active terminal 1028. Examples of NAND architecture arrays and their operation as part of a memory system are found in U.S. Patent Nos. 5,570,315, 5,774,397, and 6,046,935.

The array of storage elements is divided into a plurality of storage element blocks. As is common to flash EEPROM systems, the block is the unit of erasure. That is, each block contains a minimum number of storage elements that are erased together. Each block is usually divided into a number of pages. The page is a stylized unit. In an embodiment, individual pages may be divided into segments, and the segments may contain a minimum number of storage elements that are written once with a basic stylized operation. One or more data pages are typically stored in a storage element column. One page can store one or more sections. A section includes user data and additional item information. The additional item data usually includes an error correction code (ECC) that has been calculated from the user data of the segment. One portion of the controller (described below) calculates the ECC when the data is programmed into the array, and also checks the ECC when reading data from the array. Alternatively, the ECC and/or other additional items may be stored on a different page than the user profile to which they belong or even in different blocks.

One of the sections of user data is typically 512 bytes, which corresponds to the size of one of the segments in the drive. The additional item data is usually an additional 16-20 bytes. A large number of pages form a block from, for example, 8 pages up to any number between 32, 64, 128 or more pages. In some embodiments, a column of NAND strings constitutes a block.

In one embodiment, the p-well is raised to an erase voltage (eg, 20 V) for a sufficient period of time while the source line and the bit line are floated, and the word line of the selected block is grounded To erase the memory storage element. Attributable to capacitive coupling The unselected word line, bit line, select line, and common source (c-source) are also raised to a significant portion of the erase voltage. A strong electric field is thus applied to the tunnel oxide layer of the selected storage element, and the data of the selected storage element is erased as the electrons of the floating gate are emitted to the substrate side (usually by Fowler -Nordheim) tunneling mechanism). As the electron self-floating gate is transferred to the p-well region, the threshold voltage of the selected storage element is reduced. Erasing can be performed on the entire memory array, on a separate block, or on another element of the storage element.

Figure 11 is a block diagram of a non-volatile memory system using a single column/row decoder and a read/write circuit. The figure illustrates a memory device 1196 having read/write circuits for reading and programming a page of storage elements in parallel, in accordance with an embodiment of the present invention. Memory device 1196 can include one or more memory dies 1198. The memory die 1198 includes a two-dimensional storage element array 1000, a control circuit 1110, and a read/write circuit 1165. In some embodiments, the array of storage elements can be three dimensional. The memory array 1000 can be addressed by the column decoder via the word line and via the row decoder 1160 via the bit line. The read/write circuit 1165 includes a plurality of sensing blocks 1100 and allows a storage element page to be read or programmed in parallel. Typically, controller 1150 is included in the same memory device 1196 (e.g., a removable memory card) as the memory die 1198. Commands and data are transferred between the host and controller 1150 via line 1120 and transferred between the controller and the memory die 1198 via line 1118.

Control circuit 1110 cooperates with read/write circuit 1165 to perform a memory operation on memory array 1000. Control circuit 1110 includes state machine 1112 On-wafer address decoder 1114 and power control module 1116. State machine 1112 provides wafer level control of memory operations. The on-wafer address decoder 1114 provides an address interface between the address used by the host or memory controller to the hardware address used by the decoders 1130 and 1160. Power control module 1116 controls the power and voltage supplied to the word lines and bit lines during memory operation.

In some implementations, certain components of FIG. 11 can be combined. In various designs, one or more of these components (except storage element array 1000) may be considered as management or control circuitry. For example, one or more management or control circuits can include control circuit 1110, state machine 1112, decoder 1114/1160, power control 1116, sensing block 1100, read/write circuit 1165, controller 1150, and the like. Any one or a combination thereof.

Figure 12 is a block diagram of a non-volatile memory system using a dual column/row decoder and a read/write circuit. Here, another configuration of the memory device 1196 shown in FIG. 11 is provided. Access to the memory array 1000 by various peripheral circuits is performed symmetrically on the opposite side of the array such that the density of access lines and circuitry on each side is reduced by half. Therefore, the column decoder is divided into column decoders 1130A and 1130B, and the row decoder is divided into row decoders 1160A and 1160B. Similarly, the read/write circuit is divided into a read/write circuit 1165A connected from the bottom of the array 1000 to the bit line, and a read/write circuit 1165B connected from the top of the array 1000 to the bit line. . In this way, the density of the read/write modules is substantially reduced by half. The device of Figure 12 may also include a controller as described above for the device of Figure 11.

Figure 13 is a block diagram depicting one embodiment of a sensing block. Individual sensing The block 1100 is divided into a core portion (referred to as a sensing module 1180) and a common portion 1190. In one embodiment, there will be a separate sensing module 1180 for each bit line and a common portion 1190 for a collection of multiple sensing modules 1180. In one example, the sensing block will include a common portion 1190 and eight sensing modules 1180. Each of the sensing modules in the group will communicate with the associated common portion via the data bus 1172. For additional details, refer to U.S. Patent Application Publication No. 2006/0140007, entitled "Non-Volatile Memory and Method with Shared Processing for an Aggregate of Sense Amplifiers", published on Jun. 29, 2006, and the entire contents of which is hereby incorporated by reference. This is incorporated herein by reference.

The sensing module 1180 includes a sensing circuit 1170 that determines whether the conduction current in the connected bit line is above or below a predetermined threshold level. The sensing module 1180 also includes a bit line latch 1182 for setting voltage conditions on the connected bit lines. For example, a predetermined state latched in bit line latch 1182 will cause the connected bit line to be pulled to a state indicative of stylization suppression (eg, V _DD ).

The common portion 1190 includes a processor 1192, a set of data latches 1194, and an input/output (I/O) interface 1196 coupled between the data latch 1194 set and the data bus 1120. The processor 1192 performs calculations. For example, one of its functions is to determine the data stored in the sensed storage element and store the determined data in a set of data latches. The set of data latches 1194 is used to store the data bits determined by processor 1192 during the read operation. It is also used to store data bits imported from the data bus 1120 during the stylization operation. Data bit Represents written data that is intended to be stylized into memory. The I/O interface 1196 provides an interface between the data latch 1194 and the data bus 1120.

During reading or sensing, the operation of the system is controlled by state machine 1112, which controls the supply of different control gate voltages to the addressed storage elements. As it steps through various predefined control gate voltages corresponding to various memory states supported by the memory, the sensing module 1180 can trip at one of the voltages and the output will be via the bus The 1172 self-sensing module 1180 is provided to the processor 1192. At this time, the processor 1192 determines the obtained memory state by considering the tripping event of the sensing module and the information about the control gate voltage applied from the state machine via the input line 1193. The processor then calculates the binary encoding for the memory state and stores the resulting data bits into the data latch 1194. In another embodiment of the core portion, the bit line latch 1182 serves a dual purpose, both as a latch for latching the output of the sense module 1180 and as a bit line as described above. Latches.

Some implementations may include multiple processors 1192. In one embodiment, each processor 1192 will include an output line (not depicted) such that each of the output lines is hardwired together for a wired-OR. In some embodiments, the output line is inverted before being connected to the hardwired logic or line. This configuration enables a quick decision during the stylized verification process when the stylization process has completed, because the state machine receiving the hardwired logic OR can determine when all of the bits being programmed have reached the desired level. For example, when each bit has reached its desired level, the logical zero of that bit will be sent to the hardwired logic or line (or data 1 is inverted). When all bits output data 0 (or reversed data 1), the state machine knows to terminate the program. Process. Because each processor communicates with eight sensing modules, the state machine needs to read the hardwired logic or line eight times, or add logic to processor 1192 to accumulate the result of the associated bit line, making the state machine Only hardwired logic or lines need to be read once. Similarly, by properly selecting the logical level, the global state machine can detect when the first bit changes its state and change the algorithm accordingly.

During stylization or verification, the data to be programmed is stored in the collection of data latches 1194 from data bus 1120. The stylized operation controlled by the state machine includes a series of stylized voltage pulses applied to the control gates of the addressed storage elements. Each stylized pulse is followed by a readback (verification) to determine if the storage element has been programmed to the desired memory state. The processor 1192 monitors the read back memory state with respect to the desired memory state. When the two states coincide, the processor 1192 sets the bit line latch 1182 to cause the bit line to be pulled to indicate the state of stylization suppression. Even if a stylized pulse appears on the control gate of the storage element, this inhibits further storage of the storage element coupled to the bit line. In other embodiments, the processor initially loads the bit line latch 1182 and the sensing circuit sets it to a suppressed value during the verification process.

The data latch stack 1194 contains a data latch stack corresponding to the sense module. In one embodiment, there are three data latches per sensing module 1180. In some implementations (but not required), the data latch is implemented as a shift register such that parallel data stored therein is converted to serial data for data bus 1120, and vice versa . In the preferred embodiment, all data latches corresponding to the read/write blocks of the m storage elements The devices can be linked together to form a block shift register such that a data block can be input or output by serial transfer. In particular, a set of r read/write modules is used such that each data latch in its data latch set sequentially shifts data into or out of the data bus, As with the data latches being part of the shift register for the entire read/write block.

Additional information regarding the structure and/or operation of various embodiments of non-volatile storage devices can be found in (1) entitled "Non-Volatile Memory And Method With Reduced Source" dated March 27, 2007. U.S. Patent No. 7,196,931 to Line Bias Errors; (2) U.S. Patent No. 7,023,736 entitled "Non-Volatile Memory And Method with Improved Sensing", issued April 4, 2006; (3) May 2006 U.S. Patent No. 7,046,568 entitled "Memory Sensing Circuit And Method For Low Voltage Operation", entitled "Compensating for Coupling During Read Operations of Non-Volatile Memory", published on October 5, 2006. U.S. Patent Application Publication No. 2006/0221692; and (5) U.S. Patent Application Publication No. 2006/0158947, entitled "Reference Sense Amplifier For Non-Volatile Memory", issued July 20, 2006. All of the above five patent documents listed above are hereby incorporated by reference in their entirety.

Figure 14 illustrates an example of organizing memory arrays into blocks for a full bit line memory architecture or for a parity memory architecture. An illustrative structure of memory array 1400 is depicted. As an example, the description one is divided into 1,024 Block NAND flash EEPROM. The data stored in each block can be erased at the same time. In one embodiment, the block is the smallest unit of storage elements that are simultaneously erased. In this example, there are 8,512 rows corresponding to bit lines BL0, BL1, ..., BL8511 in each block. In an embodiment referred to as an All Bit Line (ABL) architecture (Architecture 1410), all of the bit lines of a block can be selected simultaneously during read and program operations. Storage elements along a common word line and connected to any bit line can be programmed simultaneously.

In the example provided, 64 storage elements and two dummy storage elements are connected in series to form a NAND string. There are 64 data word lines and two dummy word lines WL_d0 and WL_d1, wherein each NAND string includes 64 data storage elements and two dummy storage elements. In other embodiments, the NAND string can have more or less than 64 data storage elements and two dummy storage elements. The data memory unit stores user or system data. A dummy memory unit is usually not used to store user data or system data.

One terminal of the NAND string is connected to the corresponding bit line via a drain select gate (connected to the select gate drain line SGD), and the other terminal is connected to the other via a source select gate (connected to the select gate source line SGS) Common source.

In an embodiment referred to as an odd-even architecture (architecture 1400), the bit lines are divided into even bit lines (BLe) and odd bit lines (BLo). In this case, the storage elements along the common word line and connected to the odd bit lines are programmed at one time, while the storage elements along the common word line and connected to the even bit lines are stylized at another time. The data can be programmed into different blocks and read from different blocks at the same time. In this example, there are 8,512 rows in each block, which are divided into even rows and odd rows.

In one of the configuration of reading and stylizing operations, 4,256 storage elements are selected simultaneously. The selected storage elements have the same word line and the same type of bit line (eg, even or odd). Therefore, 532 data bytes of a logical page can be simultaneously read or programmed, and one block of memory can store at least eight logical pages (four word lines, each having odd pages and even numbers) page). For multi-state storage elements, when each storage element stores two data bits (where each of the two bits is stored in a different page), one block stores sixteen logical pages. Blocks and pages of other sizes can also be used.

For an ABL or parity architecture, the storage element can be erased by raising the p-well to an erase voltage (eg, 20 V) and grounding the word lines of the selected block. The source line and the bit line are floating. Erasing can be performed on the entire memory array, in a separate block, or on another cell of a storage element that is part of a memory device. The floating gate of the electron self-storage element is transferred to the p-well region such that the _{VTH of the} storage element becomes negative.

Figure 15 depicts an example set of threshold voltage distributions. An example _VTH distribution of the array of storage elements is provided for the condition that two data bits are stored for each storage element. A first threshold voltage distribution E is provided for the erase storage element. Three threshold voltage distributions A, B, and C for the stylized storage elements are also depicted. In one embodiment, the threshold voltage in the E distribution is negative and the threshold voltage in the A, B, and C distributions is positive.

Each distinct threshold voltage range corresponds to a predetermined value of the set of data bits. The particular relationship between the data that is programmed into the storage element and the threshold voltage level of the storage element depends on the data encoding mechanism employed for the storage element. For example, U.S. Patent No. 6,222,762, issued toK.S. mechanism. In one embodiment, the data value is assigned to the threshold voltage range using a Gray code assignment such that if the threshold voltage of the floating gate is erroneously shifted to its neighboring entity state, then only one bit Will be affected. An example assigns "11" to the threshold voltage range E (state E), "10" to the threshold voltage range A (state A), and "00" to the threshold voltage range B (state B), And assign "01" to the threshold voltage range C (state C). However, in other embodiments, the Gray code is not used. Although four states are shown, the invention is also applicable to other multi-state structures, including those that include more or less than four states.

Three read reference voltages Vra, Vrb, and Vrc are also provided for reading data from the storage element. By testing whether the threshold voltage of a given storage element is above or below Vra, Vrb, and Vrc, the system can determine the state in which the storage element is located (eg, stylized conditions).

In addition, three verification reference voltages Vva, Vvb, and Vvc are provided. Additional reading and reference values can be used when the storage element stores additional status. When the storage elements are programmed to state A, the system will test whether their storage elements have a threshold voltage greater than or equal to Vva. When the storage element is programmed to state B, the system will test whether the storage element has a threshold voltage greater than or equal to Vvb. When the storage element is programmed to state C, the system will determine if the storage element has a threshold voltage greater than or equal to Vvc.

In an embodiment referred to as full sequence stylization, the storage element can be self-erased The state E is directly programmed to any of the stylized states A, B, or C. For example, the population of storage elements to be programmed may be erased first such that all of the storage elements in the population are in an erased state E. A series of stylized pulses, such as those depicted by the control gate voltage sequence of Figure 19, are then used to program the storage elements directly to state A, B or C. When some storage elements are being programmed from state E to state A, the other storage elements are programmed from state E to state B and/or from state E to state C. When staging from state E to state C on selected word line WLi, the floating gate below WLi is compared to the voltage change from state E to state A or from state E to state B. The amount of charge changes the most, so the amount of parasitic coupling to the adjacent floating gate below WLi-1 is maximized. When staging from state E to state B, the amount of coupling to the adjacent floating gate is reduced, but still significant. When staging from state E to state A, the amount of coupling is even further reduced. Therefore, the amount of correction required to subsequently read each state of WLi-1 will vary depending on the state of the adjacent storage elements on WLn.

Figure 16 illustrates an example of a two-pass technique for a stylized multi-state storage element that stores data for two different pages: a lower page and an upper page. Four states are depicted: state E (11), state A (10), state B (00), and state C (01). For state E, both pages store "1". For state A, the lower page stores "0" and the upper page stores "1". For state B, both pages store "0". For state C, the lower page stores "1" and the upper page stores "0". Note that although a particular bit pattern has been assigned to each of these states, different bit patterns can also be assigned.

In the first pass of the stylization, the threshold voltage level of the storage element is set according to the bit to be programmed into the lower logical page. If the bit is a logic "1", the threshold voltage is not changed because it is in an appropriate state because it has been erased earlier. However, as indicated by arrow 1600, if the bit to be programmed is a logic "0", the threshold level of the storage element is increased to state A. This ends the first stylization.

In the second pass of the stylization, the threshold voltage level of the storage element is set according to the bit to be programmed into the upper logical page. If the upper logical page bit will store a logic "1", no stylization will occur, because depending on the stylization of the lower page bit, the storage element is in one of the states E or A, both of which carry the upper page. Bit "1". If the upper page bit will be a logic "0", the threshold voltage is shifted. If the first pass causes the storage element to remain in the erased state E, then as depicted by arrow 1620, the storage element is programmed in the second phase such that the threshold voltage is increased to state C. If the storage element has been programmed to state A due to the first pass stylization, as depicted by arrow 1610, the storage element is further programmed in the second pass such that the threshold voltage is increased to state B. The result of the second pass is to program the storage element to the indicated state to store the logical "0" of the upper page without changing the data of the lower page. In both Figures 15 and 16, the amount of coupling to the floating gate on the adjacent word line depends on the final state.

In an embodiment, the system can be configured to perform a full sequence of writes when sufficient data is written to fill the entire page. If the data written is less than one full page, the stylization process can be programmed to program the lower page with the received data. When the follow-up data is received, the system will then be programmed to the upper part. page. In yet another embodiment, the system can begin writing in the mode of the programmed lower page, and if it subsequently receives enough data to store the (or most) of the entire character line, the system can switch to full Sequence stylized mode. Further details of this embodiment are disclosed in U.S. Patent Application Publication No. 2006/0126390, the entire disclosure of which is hereby incorporated by reference. The manner is incorporated herein.

17a-17c illustrate another process for programming non-volatile memory that is written to a particular page after being written to a neighboring storage element of a previous page for any particular storage element. The components are stored to reduce the coupling effect of the floating gate to the floating gate. In an example implementation, the non-volatile storage element uses four data states to store two data bits in each storage element. For example, assume that state E is an erased state and states A, B, and C are programmed. State E stores data 11. State A stores data 01. State B stores data 10. State C stores data 00. This is an example of non-Gray coding because the two bits change between adjacent states A and B. You can also use the data to other codes of the entity data status. Each storage element stores two data pages. For the purposes of this reference, such material pages are referred to as upper and lower pages; however, such pages may be given other indicia. Referring to state A, the upper page stores bit 0 and the lower page stores bit 1. Referring to state B, the upper page stores bit 1 and the lower page stores bit 0. Referring to state C, both pages store bit data 0.

The stylization process is a two-step process. In the first step, the stylized lower part page. If the lower page holds data 1, the storage element state remains in state E. If the data is programmed to zero, the voltage threshold of the storage element rises, causing the storage element to be programmed to state B'. Figure 17a thus shows the stylization of the storage element from state E to state B'. State B' is transition state B; therefore, the verification point is depicted as Vvb', which is lower than Vvb.

In one embodiment, after the storage element is programmed from state E to state B', its neighboring storage elements (WLn+1) in the NAND string will then be programmed with respect to the lower page of the storage element. For example, referring back to FIG. 2, after the page below the stylized storage element 106, the page below the storage element 104 will be stylized. After staging the storage element 104, if the storage element 104 has a threshold voltage that rises from state E to state B', the coupling effect of the floating gate to the floating gate will cause the apparent threshold voltage of the storage element 106 to rise. high. This will have the effect of widening the threshold voltage distribution of state B' to the distribution described as the threshold voltage distribution 1750 of Figure 17b. This apparent broadening of the threshold voltage distribution will be corrected when the upper page is programmed.

Figure 17c depicts the process of stylizing the upper page. If the storage element is in the erased state E and the upper page remains at 1, the storage element will remain in state E. If the storage element is in state E and its upper page data is to be programmed to zero, the threshold voltage of the storage element will rise so that the storage element is in state A. If the storage element is at the intermediate threshold voltage distribution 1750 and the upper page data will remain at 1, the storage element will be programmed to final state B. If the storage element is at the intermediate threshold voltage distribution 1750 and the upper page data will become data 0, then the threshold voltage of the storage element will rise such that the storage element is in state C. The process depicted in Figures 17a through 17c reduces the floating gate to The coupling effect of the floating gates, because only page programming on top of adjacent storage elements will have an effect on the apparent threshold voltage of a given storage element. An example of an alternate status code is: when the upper page data is 1, move from distribution 1750 to state C, and when the upper page data is 0, move to state B.

Although FIGS. 17a-17c provide examples of four data states and two material pages, the concepts taught can be applied to other implementations having more or less than four states and different from two pages. For example, Figures 5a through 5d discuss embodiments having three pages: a lower page, an intermediate page, and an upper page.

18 is a flow chart depicting one embodiment of a method for staging non-volatile memory. In one implementation, the storage elements are erased (in blocks or other units) prior to programming. In step 1800, a "data load" command is issued by the controller and received by control circuit 1110. In step 1805, the address data representing the page address is input from the controller or host to the decoder 1114. In step 1810, a stylized data page of the addressed page is entered into a data buffer for stylization. The data is latched into the appropriate set of latches. In step 1815, the "stylized" command is issued by the controller to state machine 1112.

Triggered by a "stylized" command, the data latched in step 1810 is programmed to state machine 1112 using a stepwise stylized pulse of burst 1900 of FIG. 19 applied to the appropriate selected word line. Controlled in selected storage elements. In step 1820, the programmed voltage V _{PGM is} initialized to a start pulse (eg, 12 V or other value) and the programmed counter (PC) maintained by state machine 1112 is initialized to zero. In step 1830, a first V _PGM pulse is applied to the selected word line to begin programming the storage elements associated with the selected word line. If the logic "0" is stored in a specific data latch indicating that the corresponding storage element should be programmed, the corresponding bit line is grounded. On the other hand, if a logic "1" is stored in a particular latch indicating that the corresponding storage element should remain in its current data state, the corresponding bit line is connected to V _dd to suppress stylization.

In step 1835, the status of the selected storage element is verified. If it is detected that the target threshold voltage of the selected storage element has reached the appropriate level, the data stored in the corresponding data latch is changed to logic "1". If it is detected that the threshold voltage has not reached the appropriate level, the data stored in the corresponding data latch is not changed. In this way, there is no need to program a bit line having a logical "1" stored in the corresponding data latch of the bit line. When all data latches store a logic "1", the state machine (via the hardwired logic or type mechanism described above) knows that all selected storage elements have been programmed. In step 1840, a check is made as to whether all of the data latches store a logic "1". If all data latches store a logic "1", the stylization process is complete and successful because all selected storage elements are programmed and verified. The "pass" status is reported in step 1845.

If it is determined in step 1840 that not all of the data latches store a logic "1", then the stylization process continues. In step 1850, the stylized counter PC is checked against the stylized limit value PCmax. An example of one of the stylized limits is 20; however, other numbers can also be used. If the stylized counter PC is not less than PCmax, the stylization process fails and a "failed" status is reported in step 1855. If the stylized counter PC is less than PCmax, then in step 1860 V _{PGM is} incremented by a step size and the stylized counter PC is incremented. The process then returns to step 1830 to apply the next V _PGM pulse.

Figure 19 depicts an example pulse train 1900 applied to the control gate of the non-volatile storage element during stylization, and switching of the boost mode that occurs during the burst. Burst 1900 includes a series of stylized pulses 1905, 1910, 1915, 1920, 1925, 1930, 1935, 1940, 1945, 1950, etc. that are applied to the word lines selected for stylization. In one embodiment, the stylized pulses have a voltage V _PGM that begins at 12 V and increases in increments (eg, 0.5 V) for each successive stylized pulse until a maximum of 20 V is reached. Between the stylized pulses is a verify pulse. For example, the set of verification pulses 1906 includes three verification pulses. In some embodiments, there may be one of the verification pulses for each state (eg, states A, B, and C) to which the material is programmed. In other embodiments, there may be more or fewer verification pulses. The verify pulses in each set may have amplitudes of, for example, Vva, Vvb, and Vvc (Fig. 16) or Vvb' (Fig. 17a).

As mentioned, the voltage applied to the word line to implement the boost mode is applied when stylization occurs (eg, before the stylized pulse and during the stylized pulse). In practice, the boost voltage of the boost mode can be initiated slightly before each stylized pulse and removed after each stylized pulse. On the other hand, the boost voltage is not applied during the verification process that occurs, for example, between stylized pulses. Alternatively, a read voltage that is typically less than the boost voltage is applied to the unselected word line. When comparing the threshold voltage of the currently programmed storage element to the verify level, the read voltage has a sufficient amplitude to keep the previously programmed storage elements in the NAND string turned on. Width.

The foregoing detailed description of the invention has been presented for purposes of illustration It is not intended to be exhaustive or to limit the invention. Many modifications and variations are possible in light of the above teachings. The embodiments described are chosen to best explain the principles of the invention and the practice of the application in the The present invention is preferably utilized. The scope of the invention is intended to be defined by the scope of the appended claims.

100‧‧‧Optoelectronics

100CG‧‧‧Control gate

100FG‧‧‧ floating gate

102‧‧‧Optoelectronics

102CG‧‧‧Control gate

102FG‧‧‧ Floating Gate

104‧‧‧Optoelectronics

104CG‧‧‧Control gate

104FG‧‧‧Floating gate

106‧‧‧Optoelectronics

106CG‧‧‧Control gate

106FG‧‧‧ Floating Gate

120‧‧‧First choice gate

120CG‧‧‧Control gate

122‧‧‧Second selection gate

122CG‧‧‧Control gate

126 bit line

128‧‧‧ source line

320‧‧‧NAND strings

321‧‧‧ bit line

322‧‧‧Selection gate

323‧‧‧Storage components

324‧‧‧Storage components

325‧‧‧Storage components

326‧‧‧Storage components

327‧‧‧Selection gate

340‧‧‧NAND string

341‧‧‧ bit line

342‧‧‧Select gate

343‧‧‧Storage components

344‧‧‧Storage components

345‧‧‧Storage components

346‧‧‧Storage components

347‧‧‧Selection gate

360‧‧‧NAND string

361‧‧‧ bit line

362‧‧‧Select brake

363‧‧‧Storage components

364‧‧‧Storage components

365‧‧‧Storage components

366‧‧‧Storage components

367‧‧‧Select brake

400‧‧‧NAND strings

402‧‧‧terminal

403‧‧‧terminal

404‧‧‧Source supply line

406‧‧‧Source side selection gate

408‧‧‧Storage components

410‧‧‧Storage components

412‧‧‧Storage components

414‧‧‧Storage components

416‧‧‧Storage components

418‧‧‧Storage components

420‧‧‧Storage components

422‧‧‧Storage components

424‧‧‧汲polar selection gate

426‧‧‧ bit line

430‧‧‧Source/bungee area

490‧‧‧Substrate

492‧‧‧p well area

494‧‧‧n well area

496‧‧‧p-type substrate area

510‧‧‧V _TH distribution

512‧‧‧V _TH distribution

520‧‧‧First V _TH distribution

522‧‧‧Second V _TH distribution

524‧‧‧ Third V _TH distribution

526‧‧‧Four V _TH distribution

600‧‧‧Sensing components

602‧‧‧ Current Sensing Module

604‧‧‧BLC (bit line control) transistor

606‧‧‧BLS (bit line sensing) transistor

608‧‧‧Control device

610‧‧‧ bit line

612‧‧‧NAND string

620‧‧‧ waveform

622‧‧‧ waveform

624‧‧‧ waveform

626‧‧‧ waveform

628‧‧‧ waveform

720‧‧‧Voltage regulator

800‧‧‧Sensing components

802‧‧‧Voltage Sensing Module/Circuit

804‧‧‧BLC (bit line control) transistor

806‧‧‧BLS (bit line sensing) transistor

808‧‧‧Control device

810‧‧‧ bit line

811‧‧‧ to grounded capacitor

812‧‧‧NAND string

813‧‧‧ to the capacitance of the adjacent bit line

814‧‧‧Sensor node

816‧‧‧ Path

818‧‧‧GRS transistor

820‧‧‧ Path

822‧‧‧ Path

824‧‧‧Optoelectronics

825‧‧‧current source

826‧‧‧ Path

830‧‧‧ waveform

832‧‧‧ waveform

834‧‧‧ Waveform

836‧‧‧ waveform

838‧‧‧ waveform

840‧‧‧ waveform

842‧‧‧ waveform

844‧‧‧ waveform

846‧‧‧ waveform

900‧‧‧temperature dependent circuit

910‧‧‧ waveform

912‧‧‧ waveform

914‧‧‧ waveform

916‧‧‧ waveform

918‧‧‧ waveform

922‧‧‧ waveform

924‧‧‧ waveform

1000‧‧‧ memory array

1004‧‧‧ source line

1006‧‧‧ bit line

1026‧‧‧汲 Extreme

1028‧‧‧ source terminal

1050‧‧‧NAND string

1100‧‧‧Sensing block

1110‧‧‧Control circuit

1112‧‧‧ state machine

1114‧‧‧ on-chip address decoder

1116‧‧‧Power Control Module

Line 1118‧‧

1120‧‧‧Line/data bus

1130‧‧‧ column decoder

1130A‧‧‧ column decoder

1130B‧‧‧ column decoder

1150‧‧‧ Controller

1160‧‧ ‧ row decoder

1160A‧‧ ‧ decoder

1160B‧‧ line decoder

1165‧‧‧Read/Write Circuit

1165A‧‧‧Read/Write Circuit

1165B‧‧‧Read/Write Circuit

1170‧‧‧Sensor circuit

1172‧‧‧ data bus

1180‧‧‧Sense Module

1182‧‧‧ bit line latch

1190‧‧‧Common part

1192‧‧‧ processor

1193‧‧‧Input line

1194‧‧‧ Data Latches

1196‧‧‧Memory device/I/O interface

1198‧‧‧ memory grain

1400‧‧‧ parity structure

1410‧‧‧ Full Bit Line (ABL) Architecture

1750‧‧‧ threshold voltage distribution

1900‧‧‧pulse

1905‧‧‧Stylized Pulse

1910‧‧‧Stylized Pulse

1915‧‧‧Stylized Pulse

1920‧‧‧Stylized Pulse

1925‧‧‧Stylized Pulse

1930‧‧‧Stylized Pulse

1935‧‧‧Stylized Pulse

1940‧‧‧ Stylized Pulse

1945‧‧‧Stylized Pulse

1950‧‧‧Stylized Pulse

1906‧‧‧Verification pulse set

BL0, BL1, BL2, BL3, BL4, BL5, BL8511‧‧ Bit line

BLe0, BLe1, BLe2, BLe4255‧‧ Even bit line

BLo0, BLo1, BLo2, BLo4255‧‧ Odd bit line

SGD‧‧‧Bungee selection line

SGS‧‧‧Source selection line

Vra, Vrb, Vrc‧‧ ‧ read reference voltage

Vva, Vvb, Vvc‧‧‧Verification reference voltage

WL_d0, WL_d1‧‧‧Dummy word line

WL0‧‧‧ character line

WL1‧‧‧ character line

WL2‧‧‧ character line

WL3‧‧‧ character line

Figure 1 is a top plan view of a NAND string.

2 is an equivalent circuit diagram of the NAND string of FIG. 1.

3 is a block diagram of an array of NAND flash memory elements.

4 depicts a cross-sectional view of a NAND string formed on a substrate.

Figures 5a through 5d depict the stylization of non-volatile storage elements.

Figure 6a depicts a configuration of a NAND string and one of the components for sensing.

Figure 6b depicts the waveform associated with Figure 6a.

Figure 6c depicts the sensing process associated with Figures 6a and 6b.

Figure 6d depicts current sensing based on voltage changes.

Figure 7a depicts the current and voltage as a function of time due to ground bounce during a sensing operation.

Figure 7b depicts the change in current and voltage as the source voltage is adjusted to a fixed positive DC level during the sensing operation.

Figure 7c depicts another configuration of a NAND string and components for sensing.

Figure 7d depicts the sensing process associated with Figures 7a-7c.

Figure 8a depicts one configuration of a NAND string and components, including a current discharge path.

Figure 8b depicts the configuration of the NAND string and components of Figure 8a when voltage sensing occurs.

Figure 8c depicts the waveforms associated with Figures 8a and 8b.

Figure 8d depicts the sensing process associated with Figures 8a-8c.

Figure 9a depicts a NAND string and components for temperature compensated sensing.

Figure 9b illustrates the variation of the threshold voltage with temperature.

Figure 9c illustrates the variation of V _BLC and V _BL with temperature.

Figure 9d depicts the waveform associated with Figures 9a through 9c

Figure 9e depicts the sensing process associated with Figures 9a through 9d.

Figure 9f depicts an erase-verify process.

Figure 10a illustrates the change in V _SOURCE with temperature.

Figure 10b depicts an example of a storage element array that includes different sets of NAND strings.

11 is a block diagram of a non-volatile memory system using a single column decoder/row decoder and read/write circuits.

Figure 12 is a block diagram of a non-volatile memory system using a dual column decoder/row decoder and a read/write circuit.

Figure 13 is a block diagram depicting one embodiment of a sensing block.

Figure 14 depicts an example of organizing memory arrays into blocks for parity and full bit line memory architecture.

Figure 15 depicts a collection of examples of a single pass stylized threshold voltage distribution.

Figure 16 depicts a collection of examples of a multi-pass stylized threshold voltage distribution.

Figures 17a through 17c show various threshold voltage distributions and describe the process for programming non-volatile memory.

18 is a flow chart depicting one embodiment of a process for programming non-volatile memory.

Figure 19 depicts an example pulse train applied to a control gate of a non-volatile storage element during stylization.

800‧‧‧Sensing components

802‧‧‧Voltage Sensing Module/Circuit

804‧‧‧BLC (bit line control) transistor

806‧‧‧BLS (bit line sensing) transistor

808‧‧‧Control device

810‧‧‧ bit line

811‧‧‧ to grounded capacitor

812‧‧‧NAND string

813‧‧‧ to the capacitance of the adjacent bit line

814‧‧‧Sensor node

816‧‧‧ Path

818‧‧‧GRS transistor

820‧‧‧ Path

822‧‧‧ Path

824‧‧‧Optoelectronics

825‧‧‧current source

826‧‧‧ Path

SGD‧‧‧Bungee selection line

SGS‧‧‧Source selection line

WL0‧‧‧ character line

WL1‧‧‧ character line

WL2‧‧‧ character line

WL3‧‧‧ character line

Claims (16)

A method for operating a non-volatile storage system, comprising: (a) applying a source voltage to a source of each of a plurality of NAND strings during a first time period, the plurality of Each of the NAND strings is associated with a respective bit line, (b) preventing each individual bit line from being coupled to a respective sensing component, and (c) coupling each bit line to a respective one of the discharge paths; and continuing to apply the source voltage to the source of each of the plurality of NAND strings during a second time period subsequent to the first time period, and for each The other bit line is coupled to the respective sensing component. The method of claim 1, wherein the respective sensing components perform voltage sensing to determine whether charge sharing occurs between the respective bit lines and the respective sensing components. The method of claim 1, wherein a respective transistor is coupled between each of the individual bit lines and the respective sensing component, and the coupling of the step (c) includes providing a control gate voltage to the The respective transistors are placed such that the respective transistors are in a conducting state. The method of claim 1, further comprising continuing to couple each bit line to its respective discharge path during the second time period. The method of claim 1, further comprising adjusting the discharge of each bit line via the respective discharge path. The method of claim 1, further comprising adjusting a discharge of each bit line via the respective discharge path using a current mirror. The method of claim 1, wherein the first time period has a predetermined duration Time, which is selected such that bit line noise due to capacitive coupling from one or more adjacent bit lines is discharged. The method of claim 7, wherein the bit line noise is coupled to an association by one or more associated non-volatile storage elements in one or more adjacent bit lines in a conductive state. The non-volatile storage element is in a bit line of one of the NAND strings in a non-conducting state. A non-volatile storage system includes: a set of non-volatile storage elements configured as a plurality of NAND strings, each of the plurality of NAND strings and a respective bit line, a respective sensing component And one or more respective control circuits associated with the set of non-volatile storage elements, the one or more control circuits: (1) during a first time period: (a) Applying a source voltage to one of the plurality of NAND strings, (b) preventing each individual bit line from being coupled to the respective sensing component, and (c) coupling each Each of the bit lines to the respective one of the plurality of NAND strings; and (2) during a second period of time subsequent to the first period of time, (a) continuing to apply the source voltage to each of the plurality of NAND strings One of the sources, and each of the individual bit lines is coupled to the respective sensing component. The non-volatile storage system of claim 9, wherein the respective sensing components perform voltage sensing to determine whether charge sharing occurs between the respective bit lines and the respective sensing components. The non-volatile storage system of claim 9, further comprising a respective electro-crystal coupled between each of the individual bit lines and the respective sensing components The one or more control circuits are coupled to each of the respective bit lines to the respective ones by providing a control gate voltage to the respective transistors such that the respective transistors are in a conducting state Sensing component. The non-volatile storage system of claim 9, wherein the one or more control circuits continue to couple each bit line to its respective discharge path during the second time period. The non-volatile storage system of claim 9, wherein the one or more control circuits adjust the discharge of each bit line via the respective one of the respective discharge paths. The non-volatile storage system of claim 9, wherein the one or more control circuits adjust the discharge of each bit line via the respective discharge path using a current mirror. The non-volatile storage system of claim 9, wherein the first time period has a predetermined duration selected to cause bit line noise due to capacitive coupling from one or more adjacent bit lines Is discharged. The non-volatile storage system of claim 15, wherein the bit line noise is coupled to the one or more adjacent bit lines in a conductive state by one or more associated selected non-volatile storage elements An associated non-volatile storage element is in a bit line of one of the NAND strings in a non-conducting state.