TWI385765B - Method for manufacturing structure with embedded circuit - Google Patents

Description

Buried circuit structure and manufacturing method thereof

The present invention relates to a method of fabricating a buried wiring structure, and more particularly to a method of fabricating a buried wiring structure without an electroplating line.

In recent years, with the rapid development of electronic technology and the advent of high-tech electronics industry, electronic products with more humanization and better functions have been continuously introduced, and they are moving towards a trend of light, thin, short and small. Under this trend, since the circuit board has the advantages of fine wiring, compact assembly, and good performance, the circuit board becomes one of the main media for carrying a plurality of electronic components and electrically connecting the electronic components to each other.

In the prior art, when a circuit board is fabricated, a plurality of bonding pads formed on the circuit layer are usually formed after the outer circuit layer and the patterned solder mask layer are completed. The surface is plated with an anti-oxidation layer, such as a Ni/Au layer, to prevent oxidation of the surfaces of the pads made of copper and to increase the bonding strength of the pads during soldering. Moreover, the formation of the oxidation resistant layer by electroplating has the advantage of a fast formation speed.

In order to perform electroplating processes on the surfaces of the pads, the pads may be respectively connected to a plating bar to be electrically connected to an external power source. Moreover, after the plating layer completes the oxidation resistant layer, the plating line is cut off or the connection of the plating line to the pads is cut off to electrically insulate the pads from each other. However, the plating line takes up a limited line layout on the board. Space (layout space) and reduce the freedom of line layout of the circuit layer.

The invention provides a method for fabricating a buried circuit structure, which forms an anti-oxidation layer by covering the conductive layer of the circuit layer in a comprehensive manner, so that it has a large degree of freedom in line layout.

The invention provides a method for fabricating a buried circuit structure as follows. First, a circuit board having a first buried line, a core layer and a second buried line is provided, and the first buried line and the second buried line are respectively buried in opposite surfaces of the core layer. And forming a first conductive layer and a second conductive layer extending through the circuit board, the first conductive layer covering and electrically connecting the first buried circuit, and the second conductive layer Covering and electrically connecting the second buried circuit.

Then, a first plating resist is formed on the first conductive layer, and the first resistive layer has at least one first opening to expose a first surface of the first conductive layer. And forming a second plating resist on the second conductive layer, the second plating resist having at least one second opening to expose a second surface of the second conductive layer. Thereafter, a first anti-oxidation layer is formed on the first surface, and a second anti-oxidation layer is formed on the second surface.

Next, the first plating resist, the second plating resist, the first conductive layer, and the second conductive layer are removed to expose the first buried wiring and the second buried wiring. Then, a first solder resist layer is formed to cover the first buried wiring, and the first solder resist layer has at least one third opening, and the third opening exposes the first anti-oxidation layer. Thereafter, a second solder mask is formed to cover the second buried wiring, and the second solder resist layer has at least one fourth opening, and the fourth opening exposes the second anti-oxidation Layer.

In an embodiment of the invention, before forming the first plating resist layer, further including thinning the first conductive layer and the second conductive layer.

In an embodiment of the present invention, before thinning the first conductive layer and the second conductive layer, further comprising forming a first protective layer on the portions of the first conductive layer and the second conductive layer on the conductive path respectively a second protective layer, and after thinning the first conductive layer and the second conductive layer, removing the first protective layer and the second protective layer.

In an embodiment of the invention, the method of forming the first anti-oxidation layer and the second anti-oxidation layer comprises electroplating or electroless plating.

In an embodiment of the invention, the electroless plating method comprises a chemical deposition method or a physical deposition method.

In an embodiment of the invention, the first anti-oxidation layer and the second anti-oxidation layer are made of nickel and gold.

In one embodiment of the invention, the method of removing the first conductive layer and the second conductive layer includes etching.

The invention provides a method for fabricating a buried circuit structure as follows. First, a circuit board having at least one buried line and a core layer is provided, and the buried line is buried in a surface of the core layer. Then, at least one conductive channel penetrating through the core layer and the buried circuit and a conductive layer electrically connected to the conductive channel are formed, and the conductive layer covers and electrically connects the buried circuit. Then, a plating resist is formed on the conductive layer, and the plating resist exposes a surface of the conductive layer. Thereafter, an oxidation resistant layer is formed on the first surface. Then, removing the plating resist and the conductive layer not covered by the first anti-oxidation layer to reveal the buried line. Then, a solder resist layer is formed to cover the buried wiring, and the solder resist layer exposes the oxidation resistant layer.

In an embodiment of the invention, the thin conductive layer is further included before the formation of the plating resist.

In an embodiment of the invention, before the thinning of the conductive layer, a portion of the conductive layer on the conductive path is respectively formed with a protective layer, and after the conductive layer is thinned, the protective layer is removed.

In an embodiment of the invention, the material of the oxidation resistant layer comprises nickel and gold.

In one embodiment of the invention, the method of removing the conductive layer includes etching.

The present invention provides a buried circuit structure including a core layer, a first buried circuit, a first conductive path, a first conductive layer, a first oxidation resistant layer and a first solder resist layer. The first buried circuit is buried in a surface of the core layer. The first conductive path penetrates the core layer and a first pad of the first buried circuit. The first conductive layer covers the first pad and the first conductive channel. The first oxidation resistant layer is formed on the first conductive layer. The first solder resist layer covers the first buried wiring and exposes the first anti-oxidation layer.

In an embodiment of the invention, the material of the first oxidation resistant layer comprises nickel and gold.

In an embodiment of the invention, the buried circuit structure further includes a second buried circuit, a second conductive path, a second conductive layer, a second oxidation resistant layer and a second solder resist layer. The second buried circuit is buried in the other surface of the core layer. a second conductive path penetrating the core layer and one of the second buried lines Second pad. The second conductive layer covers the second pad and the second conductive path. The second anti-oxidation layer is formed on the second conductive layer. The second solder resist layer covers the second buried wiring and exposes the second anti-oxidation layer.

In an embodiment of the invention, the material of the second oxidation resistant layer comprises nickel and gold.

In summary, since the present invention forms the oxidation resistant layer by the conductive layer, it is not necessary to form a conventional plating line in the wiring layer. Therefore, the present invention has a large degree of freedom in line layout, and more signal lines (i.e., lines of non-plated lines) can be disposed on the circuit board.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

1A-1F are cross-sectional views showing a process of a buried circuit structure according to an embodiment of the present invention. 2A-2D are cross-sectional views showing processes of a buried circuit structure according to another embodiment of the present invention.

First, referring to FIG. 1A, a circuit board 110 is provided. The circuit board 110 is, for example, a buried circuit board, and the buried circuit board can be a single-layer or double-layer buried circuit board. In this embodiment, a double-layer buried circuit board is taken as an example, but not It is used to define the invention.

The circuit board 110 has a first buried line 112, a core layer 114 and a second buried line 116. The core layer 114 has an upper surface 114a and a lower surface 114b, and the first buried line 112 and the second inner portion The buried lines 116 are buried in the upper surface 114a and the lower surface of the core layer 114, respectively. 114b. The first buried line 112 has a plurality of first pads P1, and the second buried line 116 has a plurality of second pads P2.

Next, referring to FIG. 1B, a second conductive path C is formed through the circuit board 110, and a first conductive layer 120 and a second conductive layer 130 electrically connected to the conductive path C. The conductive channels C penetrate through the first pad P1. The second pad P2. Specifically, the first conductive layer 120 is disposed on the upper surface 114 a and covers the first buried circuit 112 , and the first conductive layer 120 is electrically connected to the first buried circuit 112 . The second conductive layer 130 is disposed on the lower surface 114b and covers the second buried line 116, and the second conductive layer 130 is electrically connected to the second buried line 116. It should be noted that the present invention does not limit the number of conductive channels C. For example, the number of conductive channels C may be one or more. Since the circuit board 110 has a flat upper surface 114a and a lower surface 114b, the first conductive layer 120 and the second conductive layer 130 can be formed on the upper surface 114a and the lower surface 114b by electroplating, and can also have a flat surface to avoid Conventionally, the surface of the wiring board has an excessively large surface unevenness, so that the conductive material cannot be uniformly deposited or drained. In addition, the first conductive layer 120 and the second conductive layer 130 are formed together when the conductive via C is plated, and the process of the circuit board can be further simplified without separately preparing or adding a process.

Then, referring to FIG. 1C, in the embodiment, the first conductive layer 120 and the second conductive layer 130 are thinned, and the thinning method includes etching to make the thickness of the first conductive layer 120 and the second conductive layer 130 remain. Below 1~6 microns. Next, referring to FIG. 1D , a first plating resist 140 is formed on the first conductive layer 120 , and the first plating resist 140 has a first opening OP1 to expose a first surface 122 of the first conductive layer 120 . And in the second conductive layer A second plating resist 150 is formed on the second resistive layer 150, and the second barrier layer 150 has a second opening OP2 to expose a second surface 132 of the second conductive layer 130. In detail, the first opening OP1 exposes a portion of the first conductive layer 120 on the first pad P1, and the second opening OP2 exposes a portion of the second conductive layer 130 on the second pad P2.

Then, referring to FIG. 1D again, a first anti-oxidation layer 160 is formed on the first surface 122, and a second anti-oxidation layer 170 is formed on the second surface 132, wherein the first anti-oxidation layer 160 and the second anti-oxidation layer The material of the oxide layer 170 is, for example, nickel and gold. In the present embodiment, the method of forming the first anti-oxidation layer 160 and the second anti-oxidation layer 170 is, for example, electroplating, that is, the present embodiment can be applied to the first conductive layer 120 and the second conductive layer 130. The first anti-oxidation layer 160 and the second anti-oxidation layer 170 are formed on the first surface 122 and the second surface 132, respectively, in a current or voltage manner.

It should be noted that, in the prior art, an electroplating line is first formed in the circuit layer to form an anti-oxidation layer by electroplating. In this embodiment, the first and second conductive layers 120 and 130 form the first and the first The second antioxidant layer 160, 170. As a result, the first and second anti-oxidation layers 160, 170 formed by the electroplating method in this embodiment do not affect the circuit layout of the first and second buried lines 112, 116, and do not occupy the lines on the circuit board 110. Layout space. Therefore, the present embodiment has a large degree of freedom in the layout of the circuit, and more signal lines (ie, lines of the non-plating line) can be disposed on the circuit board 110. In addition, the method of forming the first anti-oxidation layer 160 and the second anti-oxidation layer 170 may also be electroless plating, and the electroless plating may be a chemical deposition method or a physical deposition method, wherein the chemical deposition method is, for example, chemical vapor deposition, physical Deposition method For physical vapor deposition (such as sputtering or evaporation).

Next, referring to FIG. 1E , the first plating resist 140 , the second plating resist 150 , the first conductive layer 120 , and the second conductive layer 130 are removed to expose the first buried wiring 112 and the second buried wiring 116 . In detail, this embodiment removes only the first and second conductive layers 120, 130 that are not covered by the first and second oxidation resistant layers 160, 170, while remaining by the first and second oxidation resistant layers 160, 170 The first and second conductive layers 120, 130 are covered. In addition, in the embodiment, the method of removing the first conductive layer 120 and the second conductive layer 130 includes etching, and the upper surface 114a and the lower surface 114b of the circuit board 110 are flat surfaces, which also contributes to cleaning residual etching. Chemicals such as liquids and photoresists to improve the quality of products.

Then, referring to FIG. 1F, a first solder resist layer 180 and a second solder resist layer 190 are formed to cover the first buried line 112 and the second buried line 116, respectively. The first solder resist layer 180 has a third opening OP3, and the third opening OP3 exposes the first anti-oxidation layer 160. The second solder resist layer 190 has a fourth opening OP4, and the fourth opening OP4 exposes the second anti-oxidation layer 170.

In addition, referring to FIG. 2A , in other embodiments, before the first conductive layer 120 and the second conductive layer 130 are thinned, the first conductive layer 120 and the second conductive layer 130 may be located on the first pad P1. A first protective layer 210 and a second protective layer 220 are respectively formed on portions of the second pads P2.

Next, referring to FIG. 2B, the first conductive layer 120 and the second conductive layer 130 are thinned. In detail, since the first protective layer 210 and the second protective layer 220 respectively cover portions of the first conductive layer 120 and the second conductive layer 130 on the conductive path C, only the first conductive layer 120 and the first conductive layer 120 can be thinned. two A portion of the conductive layer 130 that is not covered by the first protective layer 210 and the second protective layer 220. As a result, the portions of the first conductive layer 120 and the second conductive layer 130 on the first pads P1 and the second pads P2 are thicker.

Then, referring to FIG. 2C, the first protective layer 210 and the second protective layer 220 are removed. Thereafter, the buried circuit structure 200 of FIG. 2D can be obtained by following the process of FIG. 1D to FIG. 1F. It is noted that since the portions of the first conductive layer 120 and the second conductive layer 130 on the first pad P1 and the second pad P2 are thick, the first anti-oxidation is formed thereon by electroplating. When the layer 160 and the second anti-oxidation layer 170 are used, the resistance is small and the plating is less likely to occur.

In summary, the present invention forms an oxidation resistant layer by a conductive layer, so that it is not necessary to form a conventional plating line in the wiring layer. In this way, the formation of the anti-oxidation layer by the electroplating method of the present invention does not affect the layout of the buried circuit, and does not occupy the layout space of the circuit board. Therefore, the present invention has a large degree of freedom in line layout, and more signal lines (ie, lines of non-plated lines) can be disposed on the circuit board. In addition, the present invention can also form a protective layer before thinning the conductive layer to thicken the portions of the conductive layer on the first pad and the second pad, thereby reducing the resistance when forming the anti-oxidation layer and avoiding the plating. The situation arises.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

110‧‧‧PCB

112‧‧‧First buried line

114‧‧‧ core layer

114a‧‧‧Upper surface

114b‧‧‧lower surface

116‧‧‧Second buried line

120‧‧‧First conductive layer

122‧‧‧ first surface

130‧‧‧Second conductive layer

132‧‧‧ second surface

140‧‧‧First barrier coating

150‧‧‧second barrier coating

160‧‧‧First anti-oxidation layer

170‧‧‧Second antioxidant layer

180‧‧‧First solder mask

190‧‧‧Second solder mask

200‧‧‧ buried circuit structure

210‧‧‧First protective layer

220‧‧‧Second protective layer

C‧‧‧ conductive channel

OP1‧‧‧ first opening

OP2‧‧‧ second opening

OP3‧‧‧ third opening

OP4‧‧‧ fourth opening

P1‧‧‧first mat

P2‧‧‧second mat

1A-1F are diagrams of an internal buried circuit structure according to an embodiment of the present invention; Process profile.

2A-2D are cross-sectional views showing processes of a buried circuit structure according to another embodiment of the present invention.

112‧‧‧First buried line

114‧‧‧ core layer

116‧‧‧Second buried line

160‧‧‧First anti-oxidation layer

170‧‧‧Second antioxidant layer

180‧‧‧First solder mask

190‧‧‧Second solder mask

OP3‧‧‧ third opening

OP4‧‧‧ fourth opening

P1‧‧‧first mat

P2‧‧‧second mat

Claims (16)

A method for fabricating a buried circuit structure includes: providing a circuit board having a first buried line, a core layer, and a second buried line, and the first buried line and the second buried line Separating the two opposite surfaces of the core layer respectively; forming at least one conductive channel penetrating the circuit board and a first conductive layer and a second conductive layer electrically connected to the conductive channel, the first conductive layer covering and electrically The first conductive layer is connected to the first buried circuit, and the second conductive layer is electrically connected to the second buried circuit. A first plating resist is formed on the first conductive layer, and the first resistive layer has at least one An opening to expose a first surface of the first conductive layer; a second plating resist layer formed on the second conductive layer, the second plating resist having at least one second opening to expose the second conductive layer a second surface; forming a first anti-oxidation layer on the first surface; forming a second anti-oxidation layer on the second surface; removing the first anti-plating layer, the second anti-plating layer, the first a conductive layer and the second conductive layer to reveal a first buried line and the second buried line and a first solder resist layer to cover the first buried line, and the first solder resist layer has at least one third opening, the third opening exposing the a first anti-oxidation layer; forming a second solder resist layer to cover the second buried line, and the second The solder resist layer has at least one fourth opening that exposes the second oxidation resistant layer. The method for fabricating a buried wiring structure according to claim 1, further comprising thinning the first conductive layer and the second conductive layer before forming the first plating resist. The method for fabricating a buried wiring structure according to claim 2, wherein before the thinning the first conductive layer and the second conductive layer, the first conductive layer and the second conductive layer are further included The portions on the conductive path respectively form a first protective layer and a second protective layer, and after thinning the first conductive layer and the second conductive layer, removing the first protective layer and the second The protective layer. The method for fabricating a buried wiring structure according to claim 1, wherein the method of forming the first oxidation resistant layer and the second oxidation resistant layer comprises electroplating or electroless plating. The method for fabricating a buried wiring structure according to claim 4, wherein the electroless plating method comprises a chemical deposition method or a physical deposition method. The method for fabricating a buried circuit structure according to claim 1, wherein the material of the first oxidation resistant layer and the second oxidation resistant layer comprises nickel and gold. The method of fabricating a buried wiring structure according to claim 1, wherein the method of removing the first conductive layer and the second conductive layer comprises etching. A method for fabricating a buried circuit structure includes: providing a line having at least one buried line and a core layer a buried circuit in a surface of the core layer; forming at least one conductive path penetrating the core layer and the buried line and a conductive layer electrically connected to the conductive path, the conductive layer covering and electrically Connecting the buried line; forming a resist layer on the conductive layer, the resist layer exposing a surface of the conductive layer; forming an anti-oxidation layer on the surface of the conductive layer; removing the resist layer and The conductive layer covered by the anti-oxidation layer to expose the buried wiring; and a solder resist layer to cover the buried wiring, and the solder resist layer exposes the anti-oxidation layer. The method for fabricating the buried wiring structure according to Item 8 of the patent application, further comprising thinning the conductive layer before forming the plating resist. The method for fabricating a buried circuit structure according to claim 9, wherein before the thinning the conductive layer, a portion of the conductive layer on the conductive path respectively forms a protective layer, and After the conductive layer is thinned, the protective layer is removed. The method for fabricating a buried circuit structure according to claim 8, wherein the material of the oxidation resistant layer comprises nickel and gold. The method of fabricating a buried wiring structure according to claim 8, wherein the method of removing the conductive layer comprises etching. An embedded circuit structure includes: a core layer; a first buried circuit buried in a surface of the core layer; a first conductive channel penetrating the core layer and a first pad of the first buried circuit; a first conductive layer covering the first pad and the first conductive channel; a first anti-oxidation layer, Formed on the first conductive layer; and a first solder resist layer covering the first buried line and exposing the first anti-oxidation layer. The buried circuit structure of claim 13, wherein the material of the first oxidation resistant layer comprises nickel and gold. The embedded circuit structure of claim 13, further comprising: a second buried circuit buried in another surface of the core layer; a second conductive path extending through the core layer and the first a second pad of the buried circuit; a second conductive layer covering the second pad and the second conductive path; a second anti-oxidation layer formed on the second conductive layer; and a second a solder resist layer covering the second buried wiring and exposing the second anti-oxidation layer. The buried circuit structure of claim 15, wherein the material of the second oxidation resistant layer comprises nickel and gold.