TWI384759B - One-bit phase-discriminating device and method - Google Patents

Description

One-bit phase identification device and method

The present invention relates to a phase discriminating apparatus and method, and more particularly to a one-bit phase discriminating apparatus and method applied to a radio frequency receiving system.

Please refer to the first figure, which is a schematic diagram of a conventional arctangent phase-discriminating (APD) device 10. As shown, the inverse tangent phase discrimination (APD) device 10 includes a local oscillator 11, two multiplying circuits 121 and 122, two integrating circuits 131 and 132, and a phase estimating unit 14. The inverse tangent phase discriminating device 10 receives an input signal S ₁ and produces an estimated phase of the input signal S ₁ Wherein the input signal S ₁ has a carrier frequency f _C and a phase θ ₁ . For example, the input signal S ₁ can be expressed as {E ₁ cos(2pf _C t+θ ₁ )+n ₁ (t)}, where E ₁ is the signal amplitude, the n ₁ (t) is the added Gaussian noise, t is time.

The local oscillator 11 generates an in-phase reference wave R1 _I and a quadrature reference wave R1 _Q . The in-phase reference wave R1 _I can be expressed as cos(2pf _C t), and the quadrature reference wave R1 _Q has a phase difference of 90° (p/2 radians) and can be expressed as sin (2pf) compared to the in-phase reference wave R1 _{I C} t). The multiplication circuit 121 receives the input signal S ₁ and the in-phase reference wave R1 _I and multiplies the input signal S ₁ by the in-phase reference wave R1 _I to generate a signal SR _I . The multiplication circuit 122 receives the input signal S ₁ and the quadrature reference wave R1 _Q and multiplies the input signal S ₁ by the quadrature reference wave R1 _Q to generate a signal SR _Q .

The integrating circuit 131 receives the signal SR _I and integrates the signal SR _I for a specific period of time to produce an in-phase component I _{A of the} input signal S ₁ , wherein the in-phase component I _A can be an estimate of (E ₁ cos θ ₁ ). Integrating circuit 132 receives signal SR _Q and integrates signal SR _Q for a particular period of time to produce a quadrature component Q _{A of} input signal S ₁ , where quadrature component Q _A can be an estimate of (E ₁ sin θ ₁ ). In a conventional scheme, the integrating circuits 131 and 132 operate by a multi-bit analog/digital conversion operation, and the signals SR _I and SR _Q are processed to generate an in-phase component I _A and a quadrature component Q _{A , respectively} .

The phase estimating unit 14 receives the in-phase component I _A and the quadrature component Q _A and performs an arctangent operation tan ^-1 (Q _A /I _A ) to generate an estimated phase .

In any case, due to the nonlinear form, the arctangent operation tan ^-1 (Q _A /I _A ) is complex, so that performing the arctangent operation tan ^-1 (Q _A /I _A ) requires a large amount of computational storage, extra power. Consumption and automatic gain control, therefore, there is a need to improve the described disadvantages of the arc tangent phase discrimination device 10.

In view of the above-mentioned needs, the inventor of this case, through careful research and a perseverance spirit, finally invented the "one-yuan phase identification device and method".

It is an object of the present invention to provide a one-bit phase discrimination apparatus and method that is developed based on the digital viewpoint of a receiver used in a one-bit meta analog/digital conversion process. In an environment without noise or high signal-to-noise ratio (SNR), the Quantization loss is limited to the accuracy of the arctangent phase discriminating device, so that the phase discriminating device provided in the present case is under enough samples. Typical arctangent phase discrimination devices achieve high accuracy in several levels. The phase discriminating device of the present invention is also robust to noise and has high accuracy in an environment without noise (or high signal-to-noise ratio). The complexity and computational load of the phase discriminating device of this case is much smaller than the conventional arc tangent phase discriminating device; furthermore, due to the automatic gain control (AGC) exemption, effective bit-oriented processing and cost reduction (such as in the field The planned logic gate array (FPGA) and special application integrated circuit (ASIC) aspects, the reduction in the number of logic gates and the design of a simple one-bit operation), the feasibility of a one-bit processing receiver is compelling. The phase discrimination device of the present invention is widely implemented in the fields of communication, digital signal processing, software-defined receivers, sensor networks, positioning and navigation.

The first concept of the present invention is to provide a one-bit phase discrimination device including a phase discrimination unit. The phase discriminating unit converts an input signal and a reference signal into an input sequence and a reference sequence by a one-bit analog/digital conversion operation, and determines a first value and the input in response to the input sequence and the reference sequence. An in-phase component of the signal and a quadrature component, and generating an estimated phase of the input signal based on the first value, a relationship between the in-phase component and a positive or negative of the quadrature component, wherein the first value is A first integer and a specific integer in a second integer. The first integer is a sample number of the one-bit analog/digital conversion operation for generating the input sequence; and the second integer is the sum of the absolute value of the in-phase component and the absolute value of the orthogonal component.

A second concept of the present invention is to provide a one-bit phase discrimination device including a phase discrimination unit. The phase discriminating unit processes an input signal to determine a first value and an in-phase component and an orthogonal component of the input signal by a one-bit analog/digital conversion operation, and according to the first value, the in-phase component and An estimated phase between the positive and negative of the quadrature component produces an estimated phase of the input signal.

The third concept of the present invention is to provide a one-bit phase discrimination method comprising the steps of: processing a input signal to determine a first value and an in-phase component of the input signal by a one-bit meta analog/digital conversion operation And a quadrature component; and generating an estimated phase of the input signal based on the first value, a relationship between the in-phase component and a positive or negative of the quadrature component.

Please refer to the second figure, which is a schematic diagram of the phase discriminating device 30 proposed in the present invention. As shown, phase discrimination device 30 includes a phase discrimination unit 31. Phase discrimination unit 31 receives an input signal S ₂ and produces an estimated phase of input signal S ₂ (or in another embodiment Wherein the input signal S ₂ has a carrier frequency f _C and a phase θ ₂ . For example, the input signal S ₂ can be expressed as S(t)=E ₂ cos(2pf _C t+θ ₂ )+n ₂ (t), where E ₂ is the signal amplitude, and the n ₂ (t) is the added Gaussian Noise, the t is time, and the E ₂ and the θ ₂ may be a function of time t.

In one embodiment, the phase discriminating unit 31 receives the input signal S ₂ and processes the input signal S ₂ by a one-bit analog/digital conversion operation to determine an in-phase component I _{P of the} value A _P and the input signal S ₂ . a quadrature component Q _P , and generating an estimated phase of the input signal S ₂ according to a relationship between the value A _P , the in-phase component I _P and a positive and negative of the quadrature component Q _P .

In the above embodiment, the phase discriminating unit 31 determines a reference signal R2 according to the input signal S ₂ , and converts the input signal S ₂ and the reference signal R2 into an input sequence US and a respectively by the one-bit analog/digital conversion operation. Referring to the sequence UR, and in response to the input sequence US and the reference sequence UR, the value A _P , the in-phase component I _P and the quadrature component Q _{P are determined} , wherein the relationship is a formula (sgn[Q _P ]‧(1-I _P /A _P )/2), and the sgn[Q _P ] represents a positive and negative function; for example, if x=0, then sgn[x]=1; and if x<0, then sgn[x]=-1. The value A _P can be a specific integer of a first integer and a second integer. The first integer is a sample number N of the one-bit analog/digital conversion operation for generating an input sequence US, and the second integer is an absolute value of the in-phase component I _{P and} an absolute value of the quadrature component Q _P sum.

The reference signal R2 includes an in-phase reference wave R2 _I and a quadrature reference wave R2 _Q . When the input signal S _{2 is} expressed in the form of S(t)=E ₂ cos(2pf _C t+θ ₂ )+n ₂ (t), the in-phase reference wave R2 _I can be expressed as a cosine wave cos(2pf _C t), and The reference wave R2 _Q can be expressed as a sine wave sin(2pf _C t); when the input signal S _{2 is} expressed as W(t)=E ₃ sin(2pf _C t+θ ₃ )+n ₃ (t), the in-phase reference The wave R2 _I can be expressed as a sine wave sin(2pf _C t), and the orthogonal reference wave R2 _Q can be expressed as a cosine wave cos(2pf _C t), where E ₃ is a signal amplitude, and the n ₃ (t) is added Gaussian noise, the θ ₃ is the phase. In the following description of the example, the input signal S _{2 is} expressed in the form of S(t) = E ₂ cos(2pf _C t + θ ₂ ) + n ₂ (t).

The value A _P can be related to a signal to noise ratio (SNR) of the input signal S ₂ . In an embodiment, the formula (sgn[Q _P ]‧(1-I _P /A _P )/2) is suitable for the first case "the signal-to-noise ratio is high", in the first case, the value A _P Is an integer which is a sample number N of the one-bit meta analog/digital conversion operation for generating the input sequence US, and the phase discrimination unit 31 forms a digital phase-discrimination (DPD) configuration 311. In an embodiment, the formula (sgn[Q _P ]‧(1-I _P /A _P )/2) is applicable to the second case "the signal-to-noise ratio is low (eg, SNR is less than 10 dB)", in the second In the case, the value A _P is an integer which is the sum of the absolute value of the in-phase component I _{P and} the absolute value of the orthogonal component Q _P , and the phase discriminating unit 31 forms a noise-balanced digital phase discrimination (Noise-balanced digital phase) -discriminating, NB-DPD) configuration 312.

The digital phase discrimination (DPD) configuration 311 includes a decision unit 33 and a phase estimation unit 34. The determining unit 33 converts the input signal S ₂ (such as S(t)) and the reference signal R2 into an input sequence US (such as sgn[S(kT _S )], k=0, respectively, by the one-bit analog/digital conversion operation. 1, ..., N-1, where k is the sample number and T _S is the sampling period) and the reference sequence UR, and the value A _P (i.e., the number of samples N) is determined in response to the input sequence US and the reference sequence UR, The in-phase component I _P and the quadrature component Q _P .

The reference sequence UR comprises an in-phase reference sequence UR _I (such as sgn[cos(2pf _C kT _S )]) and an orthogonal reference sequence UR _Q (such as sgn[sin(2pf _C kT _S )]). Each of the input sequence US, the in-phase reference sequence UR _I and the orthogonal reference sequence UR _Q has a high bit value and a low bit value, the high bit value and the low bit value being 1 and -1, respectively. The decision unit 33 of the digital phase discrimination configuration 311 includes an analog/digital converter 331, two multiplying circuits 332 and 333, and two counting devices 334 and 335.

The analog/digital converter 331 of the digital phase discrimination configuration 311 receives the input signal S ₂ , determines the reference signal R2 based on the input signal S ₂ , and samples the input signal S _{2 by the} number N of samples of the one-bit analog/digital conversion operation. The in-phase reference wave R2 _I and the orthogonal reference wave R2 _Q respectively generate an input sequence US, an in-phase reference sequence UR _I and an orthogonal reference sequence UR _Q . A value A _P equal to the number N of samples is supplied to the phase estimating unit 34 by the analog/digital converter 331 for calculating the estimated phase . The analog/digital converter 331 includes a numerically controlled oscillator 3311. The numerically controlled oscillator 3311 receives the input signal S ₂ , determines the reference signal R2, and generates a reference sequence UR. In one embodiment, the numerically controlled oscillator 3311 pre-converts the reference signal R2 into a reference sequence UR, stores the reference sequence UR in a table, and provides a reference sequence UR from the table when the phase θ ₂ is identified.

The multiplication circuit 332 receives the input sequence US and the in-phase reference sequence UR _I and multiplies the input sequence US by the in-phase reference sequence UR _I to produce a sequence USR _I having a complex corresponding bit value. A multiplication circuit 332 may comprise exclusive OR (XOR) gate 3321, XOR gate 3321 in response to the input sequence and in phase with the reference US UR _I sequence generated sequence USR _I. The multiplication circuit 333 receives the input sequence US and the orthogonal reference sequence UR _Q and multiplies the input sequence US by the orthogonal reference sequence UR _Q to produce a sequence USR _Q having a complex corresponding bit value. A multiplication circuit 333 may comprise exclusive OR (XOR) gate 3331, and US the input sequence to a reference sequence UR _Q orthogonal sequences generated USR _Q XOR gate 3331 in response.

Counting device 334 receives sequence USR _I and accumulates the complex corresponding bit values of sequence USR _I to produce an in-phase component I _P , for example, an in-phase component I _P is an estimate of E ₂ cos(θ ₂ ). The counting means 335 receives the sequence USR _Q and accumulates the complex corresponding bit values of the sequence USR _Q to produce an orthogonal component Q _P , for example, the orthogonal component Q _P is an estimate of E ₂ sin(θ ₂ ).

The phase estimating unit 34 of the digital phase discrimination configuration 311 is electrically connected to the decision unit 33, and receives the value A _P , the in-phase component I _P and the quadrature component Q _P , and calculates the formula (sgn[Q _P ]‧(1-I _P /A _P a value of /2), and multiplying the value by p to produce an estimated phase in radians =sgn[Q _P ]‧(1-I _P /A _P )p/2).

The formula for the digital phase discrimination configuration 311 (sgn[Q _P ]‧(1-I _P /A _P )/2) can be equivalent to a formula (sgn[Q _P ]‧(B _P /A _P )), Wherein the value B _P can be the total number of low-order values in the sequence USR _I. Counting device 334 can also generate a value B _P which is an integer. The phase estimating unit 34 receives the value A _P , the value B _P and the orthogonal component Q _P , calculates a value of the formula (sgn[Q _P ]‧(B _P /A _P )), and multiplies the value by p to generate Estimated phase of the input signal S ₂ in radians =(sgn[Q _P ]‧(B _P /A _P )p).

The Noise Balance Digital Phase Identification (NB-DPD) configuration 312 includes a decision unit 33 and a phase estimation unit 34. The determining unit 33 converts the input signal S ₂ and the reference signal R2 into the input sequence US and the reference sequence UR by the one-bit analog/digital conversion operation, and determines the in-phase component I _P and the positive response in response to the input sequence US and the reference sequence UR. The component Q _P . The decision unit 33 of the noise balanced digital phase discrimination configuration 312 includes an analog/digital converter 331, two multiplying circuits 332 and 333, and two counting devices 334 and 335.

The analog/digital converter 331 of the noise balanced digital phase discrimination configuration 312 receives the input signal S ₂ , determines the reference signal R2 according to the input signal S ₂ , and samples the input signal by using the number N of samples of the one-bit analog/digital conversion operation. S ₂ , the in-phase reference wave R 2 _I and the orthogonal reference wave R2 _Q respectively generate an input sequence US, an in-phase reference sequence UR _I and an orthogonal reference sequence UR _Q . In an embodiment, the analog/digital converter 331 receives the input signal S ₂ , the in-phase reference wave R2 _I and the orthogonal reference wave R2 _Q , and uses the number N of samples of the one-bit analog/digital conversion operation as the number of times, The input signal S ₂ , the in-phase reference wave R2 _I and the quadrature reference wave R2 _Q are sampled to generate an input sequence US, an in-phase reference sequence UR _I and an orthogonal reference sequence UR _{Q , respectively} . The multiplying circuits 332 and 333 of the noise balanced digital phase discrimination configuration 312 are identical to the multiplying circuits 332 and 333 of the digital phase discrimination configuration 311.

The counting means 334 of the noise balanced digital phase discrimination configuration 312 receives the sequence USR _I and accumulates the complex corresponding bit values of the sequence USR _I to produce an in-phase component I _P , for example, the in-phase component I _P is E ₂ cos(θ ₂ ) An estimate. The counting means 335 receives the sequence USR _Q and accumulates the complex corresponding bit values of the sequence USR _Q to produce an orthogonal component Q _P , for example, the orthogonal component Q _P is an estimate of E ₂ sin(θ ₂ ). The phase estimation unit 34 of the noise balance digital phase discrimination configuration 312 is electrically coupled to the decision unit 33, and receives the in-phase component I _P and the quadrature component Q _P , and calculates the value A _P (A _P = ∣I _P ∣ + ∣ Q _P ∣) and formula _{(sgn [Q P] ‧ (} 1-I P / a P) / 2) is a value, and the formula _{(sgn [Q P] ‧ (} 1-I P / a P) / 2) of this value multiplied by Producing the estimated phase of the input signal S ₂ in radians in p .

Please refer to the third figure, which is a schematic diagram of the phase estimation unit 50 displayed according to the digital phase discrimination configuration 311 in the second figure. As shown, a phase estimation unit 50, which is a detailed circuit of the phase estimation unit 34 of the digital phase discrimination configuration 311, includes an addition circuit 51, a division circuit 53, a positive and negative decision circuit 54, and a three-multiplication circuit 52, 55 and 56.

The adding circuit 51 receives the in-phase component I _P and the number N of samples (i.e., the value A _P ) from the decision unit 33, and subtracts the in-phase component I _P from the number of samples N to generate a value G3. The multiplication circuit 52 receives the number N of samples and multiplies the number of samples N by 2 to produce a value G4. The dividing circuit 53 receives the value G3 and the value G4, and divides the value G3 by the value G4 to generate a value G5. The positive and negative decision circuit 54 receives the quadrature component Q _P and produces a value G6 of the sgn [Q _P ]. The multiplication circuit 55 receives the value G5 and the value G6, and multiplies the value G5 by the value G6 to generate a value G2 of the formula (sgn[Q _P ]‧(1-I _P /A _P )/2). Multiplying circuit 56 receives value G2 and multiplies value G2 by p to produce an estimated phase . Because the value G2 is proportional to the estimated phase with a constant p From the application point of view, the value G2 can represent the estimated phase Therefore, the multiplication circuit 56 can be omitted.

Please refer to the fourth diagram, which is a schematic diagram of phase estimation unit 60 shown in accordance with noise balance digital phase discrimination configuration 312 in the second diagram. As shown, phase estimation unit 60, which is a detailed circuit of phase estimation unit 34 of noise balanced digital phase discrimination configuration 312, includes two operational circuits 61 and 62, and a multiplying circuit 63. The operation circuit 61 generates a value H3 and a value H4 in response to the in-phase component I _P . The operation circuit 62 generates a value H2 of the formula (sgn[Q _P ]‧(1-I _P /A _P )/2) in response to the orthogonal component Q _P , the value H3 and the value H4. The multiplication circuit 63 receives the value H2 and multiplies the value H2 by p to produce an estimated phase . Because the value H2 is proportional to the estimated phase with a constant p From the application point of view, the value H2 can represent the estimated phase Therefore, the multiplication circuit 63 can be omitted.

The operation circuit 61 includes a positive/negative decision circuit 611, a reverse gate 612, an absolute value decision circuit 613, and a multiplication circuit 614. The positive and negative decision circuit 611 receives the in-phase component I _P and generates a value H15 of the sgn [I _P ]. The reverse gate 612 receives the value H15 and produces a value H16 (equal to (-1)‧H15). The absolute value decision circuit 613 receives the in-phase component I _P and calculates an absolute value of the in-phase component I _P to generate a value H3. Multiplication circuit 614 receives value H3 and value H16 and multiplies value H3 by value H16 to produce value H4.

The operation circuit 62 includes an absolute value decision circuit 621, two adder circuits 622 and 623, two multiplying circuits 624 and 627, a dividing circuit 625, and a positive/negative decision circuit 626. The absolute value decision circuit 621 receives the orthogonal component Q _P and calculates an absolute value of the orthogonal component Q _P to generate a value H25. Addition circuit 622 receives value H3 and value H25, and adds value H3 to value H25 to produce value H1 (equal to value A _P = ∣I _P ∣ + ∣Q _P ∣). The addition circuit 623 receives the value H4 and the value H1, and adds the value H4 to the value H1 to generate a value H26. Multiplication circuit 624 receives value H1 and multiplies value H1 by 2 to produce a value H27. The dividing circuit 625 receives the value H26 and the value H27, and divides the value H26 by the value H27 to generate a value H28. The positive and negative decision circuit 626 receives the quadrature component Q _P and produces a value H29 of the sgn [Q _P ]. The multiplication circuit 627 receives the value H28 and the value H29, and multiplies the value H28 by the value H29 to generate a value H2 of the formula (sgn[Q _P ]‧(1-I _P /A _P )/2).

Please refer to the fifth figure, which is a schematic diagram of the standard deviation of the estimated phase expressed in degrees from the arc tangent phase discriminating device 10 and the digital phase discrimination configuration 311 as a function of the number N of samples. As shown, the standard deviation curve APD1 is obtained from the arc tangent phase discrimination device 10, and the standard deviation curve DPD1 is obtained from the digital phase discrimination configuration 311. When the number of samples N = 512, the standard deviation of the estimated phase of the arc tangent phase discriminating means 10 is almost irrelevant to the number N of samples. In contrast, as the number of samples N increases, the standard deviation of the estimated phase of the digital phase discrimination configuration 311 continues to decrease. This means that the accuracy of the arc tangent phase discriminating device 10 is limited, and when the number of samples N continues to increase, the accuracy of the digital phase discriminating configuration 311 can be improved several levels better than the arc tangent phase discriminating device 10.

See Sixth view (a) of FIG sixth (b), the sixth figure (a) as a phase estimation error in degrees from the arctangent of the phase discriminating means 10 is obtained with the phase of the input signals S ₁ is a schematic view changed And FIG. 6(b) is a diagram showing the phase estimation error expressed in degrees from the digital phase discrimination configuration 311 as a function of the phase of the input signal S ₂ . The sixth graph (a) and the sixth graph (b) are plotted under the following conditions: the observation time is 1 millisecond (equal to NT _S , where N is the number of samples and T _s is the sampling period), and the carrier frequency f _C is 15.42. MHz, and the number of samples N is 8192. As shown, in general, the phase estimation error of the digital phase discrimination configuration 311 is much smaller than the phase estimation error of the arc tangent phase discrimination device 10. In addition, the phase estimation errors of the arc tangent phase discriminating device 10 and the digital phase discrimination configuration 311 both exhibit periodic characteristics, and as the number of samples N increases, the transient variation of the phase estimation error as the phase changes decreases.

Please refer to the seventh (a), (b), (c), (d), (e), (f), (g) and (h), which are 30dB, 20dB in each of the eight signal to noise ratios. , 10dB, 5dB, 0dB, -5dB, -10dB and -20dB, from the inverse tangent phase discrimination (APD) device 10, the digital phase discrimination (DPD) configuration 311 and the noise balance digital phase discrimination (NB-DPD) configuration 312 A schematic diagram is obtained in which the standard deviation of the estimated phase expressed in degrees varies with the number N of samples. The seventh diagrams (a), (b), (c), (d), (e), (f), (g), and (h) are drawn under the following conditions: the carrier frequency f _C is 15.42 MHz, And the number of samples (the total number of samples) N includes 128, 512, ... and 65536. As shown, the standard deviation curves A1, A2, ... and A8 are obtained from the inverse tangent phase discrimination (APD) device 10, and the standard deviation curves D1, D2, ... and D8 are from the digital phase discrimination (DPD) configuration 311. The standard deviation curves B1, B2, ..., and B8 obtained are obtained from the Noise Balance Digital Phase Identification (NB-DPD) configuration 312. In one-bit quantization, the Noise Balance Digital Phase Identification (NB-DPD) configuration 312 avoids significant quantization loss; when the signal-to-noise ratio (SNR) is high or no noise, the noise balance digital phase discrimination (NB- The phase error of the DPD) configuration 312 is much smaller than the phase error of the arctangent phase discrimination (APD) device 10; the higher the signal to noise ratio, the greater the improvement. Moreover, in the case of noisy, the implementation of the noise balance digital phase discrimination (NB-DPD) configuration 312 is generally better than the digital phase discrimination (DPD) configuration 311; and the lower the signal to noise ratio, the greater the improvement; That is, the noise balanced digital phase discrimination (NB-DPD) configuration 312 is equivalent to digital phase discrimination (DPD) configuration 311 in the absence of noise, but is far more robust to digital phase discrimination (DPD) in noisy environments. Configuration 311.

The phase discriminating device 30 has the following features as compared to the arc tangent phase discrimination (APD) device 10. When the signal-to-noise ratio is greater than 2.6 dB, the accuracy of the phase discriminating device 30 is high. Unlike the calculation of the nonlinear tan ^-1 (Q _A /I _A ) of the inverse tangent phase discrimination (APD) device 10, the calculation of the digital phase discrimination (DPD) configuration 311 and the noise balance digital phase discrimination (NB-DPD) configuration 312 It is linear. Since one-bit signal processing reduces complexity, power consumption, and memory storage, its adoption reduces the processing load. A phase discriminating device for obtaining an estimated phase, which currently employs a multi-bit scheme, can be simply updated by taking the sign bit. In addition, the phase discrimination device 30 can also omit automatic gain control (AGC). When the signal-to-noise ratio is less than 2.6 dB, the accuracy of the noise-balanced digital phase discrimination (NB-DPD) configuration 312 is equivalent to the inverse tangent phase discrimination (APD) device 10, but the noise-balanced digital phase discrimination (NB-DPD) configuration The calculation of 312 is much less than that of the inverse tangent phase discrimination (APD) device 10.

In summary, the one-bit phase identification device and method of the present invention can achieve the effects set by the invention. The above descriptions are only the preferred embodiments of the present invention. Any equivalent modifications or variations made by those skilled in the art of the present invention should be included in the scope of the following patent application.

10. . . Anti-tangential phase discrimination device

11. . . Local oscillator

121, 122, 332, 333, 52, 55, 56, 614, 624, 627, 63. . . Multiplication circuit

131, 132. . . Integral circuit

14, 34, 50, 60. . . Phase estimation unit

30. . . Phase discrimination device

31. . . Phase identification unit

311. . . Digital phase discrimination configuration

312. . . Noise balance digital phase discrimination configuration

33. . . Decision unit

331. . . Analog/digital converter

3311. . . Numerically controlled oscillator

3321, 3331. . . Mutual exclusion or gate

334, 335. . . Counting device

51, 622, 623. . . Addition circuit

53,625. . . Division circuit

54, 611, 626. . . Positive and negative decision circuit

61, 62. . . Operating circuit

612. . . Reverse gate

613, 621. . . Absolute value determining circuit

S ₁ , S ₂ . . . input signal

, , . . . Estimated phase

f _C . . . Carrier frequency

θ ₁ , θ ₂ . . . Phase

E ₁ , E ₂ , E ₃ . . . Signal amplitude

R1 _I , R2 _I . . . In-phase reference wave

R1 _Q , R2 _Q . . . Orthogonal reference wave

SR _I , SR _Q . . . signal

I _A , I _P . . . In-phase component

Q _A , Q _P . . . Quadrature component

A _P , B _P , G2, G3, G4, G5, G6, H1, H2, H3, H4, H15, H16, H25, H26, H27, H28, H29. . . value

N. . . Number of samples

T _S . . . Sampling period

k. . . Sample number

R2. . . Reference signal

US. . . Input sequence

UR. . . Reference sequence

UR _I . . . In-phase reference sequence

UR _Q . . . Orthogonal reference sequence

USR _I , USR _Q. . . sequence

This case can be further explained by the detailed description of the following drawings:

The first figure: a schematic diagram of a conventional arc tangent phase discriminating device;

Figure 2: Schematic diagram of the phase discriminating device proposed in this case;

Third diagram: a schematic diagram of a phase estimation unit displayed in accordance with the digital phase discrimination configuration in the second figure;

Fourth: a schematic diagram of a phase estimation unit displayed in accordance with the noise balance digital phase discrimination configuration in the second figure;

Figure 5: Schematic diagram of the standard deviation of the estimated phase expressed in degrees from the inverse tangent phase discriminating device and the digital phase discrimination configuration of the present case as a function of the number of samples;

Figure 6 (a) is a diagram showing the phase estimation error expressed in degrees from the arctangent phase discriminating means as a function of the phase of the input signal;

Figure 6 (b) is a schematic diagram showing the phase estimation error expressed in degrees from the phase identification configuration of the present case as a function of the phase of the input signal;

Figure 7 (a), (b), (c), (d), (e), (f), (g) and (h): The case has eight signal-to-noise ratios of 30 dB, 20 dB, 10 dB, 5dB, 0dB, -5dB, -10dB and -20dB, the standard deviation of the estimated phase expressed in degrees from the arctangent phase discrimination device, the digital phase discrimination configuration and the noise balance digital phase discrimination configuration is changed with the number of samples. .

30. . . Phase discrimination device

31. . . Phase identification unit

311. . . Digital phase discrimination configuration

312. . . Noise balance digital phase discrimination configuration

34. . . Phase estimation unit

33. . . Decision unit

331. . . Analog/digital converter

3311. . . Numerically controlled oscillator

332, 333. . . Multiplication circuit

3321, 3331. . . Mutual exclusion or gate

334, 335. . . Counting device

S ₂ . . . input signal

. . . Estimated phase

f _C . . . Carrier frequency

R2. . . Reference signal

R2 _I . . . In-phase reference wave

R2 _Q . . . Orthogonal reference wave

I _P . . . In-phase component

Q _P . . . Quadrature component

A _P , B _P . . . value

N. . . Number of samples

T _S . . . Sampling period

k. . . Sample number

US. . . Input sequence

UR. . . Reference sequence

UR _I . . . In-phase reference sequence

UR _Q . . . Orthogonal reference sequence

USR _I , USR _Q. . . sequence

Claims (20)

A one-bit phase discriminating device comprising: a phase discriminating unit for converting an input signal and a reference signal into an input sequence and a reference sequence by a one-bit analog/digital conversion operation, in response to the input sequence and the Determining a first value A _P and an in-phase component I _{P of} the input signal and a quadrature component Q _P according to the reference sequence, and according to the first value A _P , the in-phase component I _P and the orthogonal component Q _P An estimated phase of the input signal is generated by a relationship between positive and negative, wherein the first value A _P is a specific integer of the following integer: a first integer, which is one of the one-bit analog/digital conversion operations The number of samples used to generate the input sequence; and a second integer is the sum of the absolute value of the in-phase component I _{P and} the absolute value of the quadrature component Q _P . A one-bit phase discriminating device according to claim 1, wherein: the input signal has a carrier frequency; the reference signal includes an in-phase reference wave and an orthogonal reference wave, and the in-phase reference wave and the orthogonal reference wave Having the carrier frequency; the relationship is a formula (sgn[Q _P ]‧(1-I _P /A _P )/2); and the sgn[Q _P ] represents a positive and negative function. The one-bit phase discriminating device of claim 2, wherein the first value A _P is the first integer, and the phase discriminating unit comprises: a determining unit, by the one-bit analog/digital conversion operation, Converting the input signal and the reference signal into the input sequence and the reference sequence respectively, and determining the first value A _P , the in-phase component I _P and the orthogonal component Q _{P in} response to the input sequence and the reference sequence; a phase estimating unit electrically connected to the determining unit, calculating a second value of the formula (sgn[Q _P ]‧(1-I _P /A _P )/2), and multiplying the second value by π This estimated phase is generated. The one-bit phase discriminating device of claim 2, wherein the first value A _P is the second integer, and the phase discriminating unit comprises: a determining unit, by the one-bit analog/digital conversion operation, Converting the input signal and the reference signal into the input sequence and the reference sequence respectively, and determining the in-phase component I _P and the orthogonal component Q _{P in} response to the input sequence and the reference sequence; and a phase estimation unit, electrically connected In the determining unit, calculating a second integer and a second value of the formula (sgn[Q _P ]‧(1-I _P /A _P )/2), and multiplying the second value by π to generate the second value Estimate the phase. A one-bit phase discriminating device comprising: a phase discriminating unit for processing an input signal to determine a first value A _P and an in-phase component I _{P of} the input signal by a one-bit analog/digital conversion operation Orthogonal component Q _P , and generating an estimated phase of the input signal based on a relationship between the first value A _P , the in-phase component I _{P ,} and a positive or negative of the quadrature component Q _P . The one-bit phase discriminating device of claim 5, wherein: the phase discriminating unit determines a reference signal according to the input signal, and converts the input signal and the reference signal by the one-bit analog/digital conversion operation respectively. Forming an input sequence and a reference sequence, and determining the first value A _P , the in-phase component I _P and the orthogonal component Q _{P in} response to the input sequence and the reference sequence; the input signal has a carrier frequency; the reference The signal includes an in-phase reference wave and an orthogonal reference wave, the in-phase reference wave and the orthogonal reference wave having the carrier frequency; the reference sequence includes an in-phase reference sequence and an orthogonal reference sequence; the input sequence, the in-phase reference Each of the sequence and the orthogonal reference sequence has a high bit value and a low bit value, the high bit value and the low bit value being 1 and -1, respectively; the relationship is a formula (sgn[Q _P ]‧ (1-I _P /A _P )/2); the sgn[Q _P ] represents a positive and negative function; and the first value A _P is related to a signal-to-noise ratio of the input signal. The one-bit phase discriminating device of claim 6, wherein the signal-to-noise ratio is greater than 10 dB, the first value A _P is an integer, and the integer is a number of samples of the one-bit analog/digital conversion operation. For generating the input sequence, and the phase discriminating unit comprises: a determining unit, respectively converting the input signal and the reference signal into the input sequence and the reference sequence by the one-bit analog/digital conversion operation, and responding to the The input sequence and the reference sequence determine the first value A _P , the in-phase component I _P and the orthogonal component Q _P ; and a phase estimating unit electrically connected to the determining unit to calculate the formula (sgn[Q _P ] A second value of ‧ (1-I _P /A _P )/2), and multiplying the second value by π to generate the estimated phase. The one-bit phase discriminating device of claim 7, wherein the determining unit comprises: an analog/digital converter that receives the input signal, determines the reference signal according to the input signal, and uses the one-bit analog/digital And sampling the input signal, the in-phase reference wave and the orthogonal reference wave to generate the input sequence, the in-phase reference sequence and the orthogonal reference sequence, respectively; a first mutual exclusion or gate, Generating a first sequence having a plurality of corresponding bit values in response to the input sequence and the in-phase reference sequence; a second mutex or gate, generating a complex corresponding bit value in response to the input sequence and the orthogonal reference sequence a second sequence; a first counting means for accumulating the complex corresponding bit value of the first sequence to generate the in-phase component I _P ; and a second counting means for accumulating the complex corresponding bit value of the second sequence To generate the quadrature component Q _P . A one-bit phase discriminating device according to claim 7, wherein the phase estimating unit comprises: an adding circuit, receiving the in-phase component I _P and the number of samples from the determining unit, and subtracting the in-phase from the number of samples The component I _{P is} used to generate a third value; a first multiplication circuit receives the number of samples, and multiplies the number of samples by 2 to generate a fourth value; a dividing circuit receives the third value and the fourth value And dividing the third value by the fourth value to generate a fifth value; a positive/negative decision circuit receiving the quadrature component Q _P and generating a sixth value of the sgn[Q _P ]; a second a multiplying circuit receiving the fifth value and the sixth value, and multiplying the fifth value by the sixth value to generate the second value; and a third multiplying circuit receiving the second value and The binary value is multiplied by π to produce the estimated phase. A one-bit phase discriminating device as claimed in claim 6, wherein the first value A _P is an integer which is a sum of an absolute value of the in-phase component I _{P and} an absolute value of the quadrature component Q _P , And the phase discriminating unit comprises: a determining unit, respectively converting the input signal and the reference signal into the input sequence and the reference sequence by the one-bit analog/digital conversion operation, and responding to the input sequence and the reference sequence Determining the in-phase component I _P and the orthogonal component Q _P ; and a phase estimating unit electrically connected to the determining unit, calculating the first value A _P and the formula (sgn[Q _P ]‧(1-I _P / A second value of A _P )/2), and multiplying the second value by π to generate the estimated phase. The one-bit phase discriminating device of claim 10, wherein the determining unit comprises: an analog/digital converter, receiving the input signal, the in-phase reference wave and the orthogonal reference wave, and using the one-bit element The number of samples of the analog/digital conversion operation is a number of times, and the input signal, the in-phase reference wave and the orthogonal reference wave are sampled to generate the input sequence, the in-phase reference sequence and the orthogonal reference sequence, respectively; Or a gate, in response to the input sequence and the in-phase reference sequence, generating a first sequence having a plurality of corresponding bit values; a second mutex or gate, generating a complex corresponding bit in response to the input sequence and the orthogonal reference sequence a second sequence of the plurality of values; a first counting means for accumulating the complex corresponding bit values of the first sequence to generate the in-phase component _Ip ; and a second counting means for accumulating the complex number of the second sequence The bit value is used to generate the quadrature component Q _P . The scope of the patent application of one yuan phase discriminating means 10, wherein the phase estimating unit comprises: a first operation circuit, responsive to the same phase component I _P and generate a third value and a fourth value; a second operation a circuit that generates the second value in response to the quadrature component Q _P , the third value and the fourth value; and a first multiplication circuit that receives the second value and multiplies the second value by π to generate The estimated phase. The one-bit phase discriminating device of claim 12, wherein the first operating circuit comprises: a positive/negative determining circuit, receiving the in-phase component I _P , and generating a fifth value of the sgn[I _P ]; Reversing, receiving the fifth value, and generating a sixth value; an absolute value determining circuit receiving the in-phase component I _P and calculating an absolute value of the in-phase component I _P to generate the third value; The second multiplication circuit receives the third value and the sixth value, and multiplies the third value by the sixth value to generate the fourth value. The one-bit phase discriminating device of claim 12, wherein the second operating circuit comprises: an absolute value determining circuit that receives the quadrature component Q _P and calculates an absolute value of the quadrature component Q _P Generating a fifth value; a first adding circuit receiving the third value and the fifth value, and adding the third value to the fifth value to generate the first value A _P ; a second adding circuit, Receiving the fourth value and the first value A _P , and adding the fourth value to the first value A _P to generate a sixth value; a second multiplication circuit receiving the first value A _P and The first value A _{P is} multiplied by 2 to generate a seventh value; a dividing circuit receives the sixth value and the seventh value, and divides the sixth value by the seventh value to generate an eighth value; a positive/negative decision circuit receiving the quadrature component Q _P and generating a ninth value of the sgn[Q _P ]; and a third multiplying circuit receiving the eighth value and the ninth value, and the eighth The value is multiplied by the ninth value to produce the second value. A one-bit phase discrimination method comprising the steps of: (a) processing an input signal by a one-bit meta analog/digital conversion operation to determine a first value A _P and an in-phase component I _{P of} the input signal and a The quadrature component Q _P ; and (b) generate an estimated phase of the input signal based on a relationship between the first value A _P , the in-phase component I _P and a positive or negative of the quadrature component Q _P . A one-bit phase identification method according to claim 15 wherein the step (a) further comprises the steps of: (c) determining a reference signal according to the input signal; and (d) converting by the one-bit analog/digital conversion. Operation, respectively converting the input signal and the reference signal into an input sequence and a reference sequence; (e) determining the first value A _P , the in-phase component I _P and the orthogonal component in response to the input sequence and the reference sequence Q _P , wherein: the input signal has a carrier frequency; the reference signal includes an in-phase reference wave and a quadrature reference wave, the in-phase reference wave and the orthogonal reference wave have the carrier frequency; the reference sequence includes an in-phase reference a sequence and an orthogonal reference sequence; each of the input sequence, the in-phase reference sequence, and the orthogonal reference sequence has a high bit value and a low bit value, the high bit value and the low bit value being 1 and -1; the relationship is a first formula (sgn[Q _P ]‧(1-I _P /A _P )/2); the sgn[Q _P ] represents a positive and negative function; and the first value A _P and the A signal to noise ratio of the input signal is related. A one-bit phase discrimination method according to claim 16, wherein the signal-to-noise ratio is greater than 10 dB, and the first value A _P is an integer, and the integer is a number of samples of the one-bit analog/digital conversion operation. For generating the input sequence, and the step (d) further comprises the step of sampling the input signal, the in-phase reference wave and the orthogonal reference wave by using the number of samples of the one-bit analog/digital conversion operation as a number of times Generating the input sequence, the in-phase reference sequence and the orthogonal reference sequence, respectively; and the step (e) further comprises the step of multiplying the input sequence by the in-phase reference sequence to generate a first bit having a complex corresponding bit value a sequence; multiplying the input sequence by the orthogonal reference sequence to generate a second sequence having a plurality of corresponding bit values; accumulating the complex corresponding bit values of the first sequence to generate the in-phase component I _P ; and accumulating The complex number of the second sequence corresponds to a bit value to produce the quadrature component Q _P . A one-bit phase identification method according to claim 17, wherein the step (b) further comprises the step of: calculating the first formula (sgn[Q _P ]‧(1-I _P /A _P )/2) a second value; and multiplying the second value by π to generate the estimated phase. For example, a one-bit phase discrimination method of claim 17 wherein: the first formula (sgn[Q _P ]‧(1-I _P /A _P )/2) is equivalent to a second formula (sgn[ Q _P ]‧(B _P /A _P )); and the B _P is the total number of low-order values in the first sequence. A one-bit phase discrimination method according to claim 16, wherein the first value A _P is an integer, and the integer is a sum of an absolute value of the in-phase component I _{P and} an absolute value of the orthogonal component Q _P , And step (b) further comprises the steps of: calculating a second value of the first formula (sgn[Q _P ]‧(1-I _P /A _P )/2); and multiplying the second value by π To generate the estimated phase.