TWI383308B - Method of designing semiconductor integrated circuit, apparatus for designing semiconductor integrated circuit, recording medium, and mask manufacturing method - Google Patents

Description

Semiconductor integrated circuit design method, semiconductor integrated circuit design device, recording medium, and photomask manufacturing method

The present invention relates to a method of designing a semiconductor integrated circuit in which the design method is simplified, a design apparatus of a semiconductor integrated circuit, a recording medium, and a mask manufacturing method.

In recent years, advances in the manufacturing technology of semiconductor devices have been very rapid, and semiconductor devices having a minimum processing size of 0.1 μm or less have been mass-produced. Such miniaturization is realized by a leap in the fine pattern forming technique and various EDA (Electronic Design Automation) tools for generating a circuit pattern. In the era when the pattern size is very large, the planar shape of a large-scale integrated circuit (LSI) pattern to be formed on a wafer is directly drawn as a design pattern, and a reticle pattern faithful to the design pattern is created. The reticle pattern is transferred to the wafer by a projection optical system, and the substrate is etched to form a pattern on the wafer that is substantially identical to the design pattern.

However, as the pattern is refined, it is becoming more and more difficult to form a pattern faithfully in each process, resulting in the problem that the final pattern cannot meet the design pattern requirements.

In particular, in the most important photolithography and etching processes required for microfabrication, other pattern layout environments disposed around the pattern to be formed have a great influence on the accuracy of the pattern.

Therefore, in order to reduce these effects, the processed inch method can be formed. The pattern is expected, and there is an optical proximity effect correction (OPC: Process Proximity Correction) or a process proximity correction (PPC) method (hereinafter referred to as PPC method) in which an auxiliary pattern is added to the design pattern (for example, PPC method). Refer to Patent Document 1.).

On the other hand, in the design flow of the layout performed by the upper stream of the mask data processing, the timing driving design is performed. That is, it is difficult to converge the components of the driving force in the margin by using the operating speed of the transistor, or the buffer is inserted too frequently, and it is necessary to perform timing verification on the layout of the result, and this design method has to be adopted. The state is gone.

The complication of the optical proximity effect correction (OPC) and the process proximity effect correction (PPC) technique in the foregoing technology makes the pattern formed by the designer greatly different from the mask pattern used in the exposure. There is a problem that it is not easy to predict the shape of the finished pattern on the wafer.

Moreover, in the layout design, a buffer is inserted in order to converge the timing, and as a result, in addition to causing an increase in the area of the wafer, it is usually performed in a transistor written by the worst condition method. Timing converges, so the problem of burdening the interphase required to converge timing is becoming more serious.

Because of this layout design, and in the reticle data processing (OPC, OPC verification processing) after the completion of the design data, the burden becomes double, so the process simulator must be used for verification before the design pattern is shipped. .

However, because the process verification of the design pattern is at the end of the design process In the stage, the feedback of the verification result is returned after the design project, and the TAT (turn around time) imposes a great burden, and there is such a problem.

In order to solve the problem of TAT, it is proposed to prioritize the design pattern of the problem in OPC, and solve the problem by design data, OPC, or optical lithography rule check (for example, refer to the patent literature). 2.). Further, there has been proposed a method of detecting a pattern which causes a problem in OPC with a apex density of a pattern at a high speed, and a pattern for reducing the yield (for example, refer to Patent Document 2). In addition, there is a design method of arranging components in which OPC has been previously performed (for example, refer to Patent Document 3).

For example, in the arrangement wiring method of the conventional method, pre-filtering of the layout (extraction of a small margin pattern) is performed in the arrangement of the functional elements of the semiconductor integrated circuit and the outline wiring. In the pre-filtering, the process verification is performed on the layout, and is mainly used to extract and remove the pattern that does not satisfy the pre-defined process margin, that is, the reason that the yield is lowered. Next, the reticle pattern formed by the proximity effect correction (OPC) is applied to the extracted pattern, and the transfer simulation is performed. If there is a problem with the result of the simulation, the pattern is corrected. The pattern in which the process margin is not reached is a process verification in which the layout is performed in advance on the entire wafer level before the wiring is arranged, and based on the result, the layout of the process margin is small, and a database or a library is created. Also, when process conditions, or processing of OPC, OPC verification, etc. are changed, verification must be performed again. Therefore, it takes a large burden to prepare the wiring processing.

At the same time, however, with the miniaturization and complication of the pattern, problems that cannot be handled by the aforementioned methods occur. That is, in the technique disclosed in Patent Document 2, if the correction is performed at the stage of the original drawing, the problem of an increase in TAT occurs.

On the other hand, in the technique disclosed in Patent Document 3, the pre-implementation of OPC itself has a problem of burden, and in the technique disclosed in Patent Document 2, it is impossible to obtain screening only by the apex density information of the pattern. The problem of (screening) precision exists.

In addition, in order to shorten the TAT pattern comparison or databaseization, the result of the process verification will cause too much change in the problem of the under-process margin pattern, and the time-consuming problem arises in the construction of the library or the database. It will become more and more difficult to use in the future.

Moreover, once the pattern is refined and progressed, the pattern that is not satisfied with the process margin will be more sharply increased, and there may be flaws in the classification itself.

[Patent Document 1] Japanese Patent Laid-Open Publication No. Hei 9-319067 [Patent Document 2] Japanese Patent Laid-Open Publication No. 2006-126745 [Patent Document 3] US Patent No. 6425117

The problem to be solved is that as the pattern is refined and complicated, if the correction is made in the original artwork stage, the TAT will increase; while the proximity effect correction itself is costly and cannot be selected. Degree and other issues.

An object of the present invention is to simplify or eliminate verification of a pattern having a margin in a process margin, and to simplify the design of a semiconductor integrated circuit without lowering the screening accuracy.

The design method of the semiconductor integrated circuit of the present invention described in the application item 1 is a method for designing a semiconductor integrated circuit when the physical layout of the semiconductor integrated circuit is generated by the semiconductor integrated circuit design data. , has: component configuration wiring project, which is to configure and wire the components required for the layout of the pre-recorded entity; and the design rule inspection project, which refers to the rule library for design rule checking, which will contain the components of the pre-recorded entity layout. The shape of the second entity layout is verified; and the reticle data is created into a project, and the current design rule is used to check the pre-recording design rule, and the second entity layout is used to create the reticle data corresponding to the layout of the pre-recorded entity; The hood data processing project is the reticle data processing of the second entity layout as the verification object when the design rule is not satisfied in the current design rule inspection project; and the reticle data creation project is the use of the reticle data processing project The second entity layout in which the mask data processing has been performed, corresponding to the pre-record Body mask layout data.

In the method of designing a semiconductor integrated circuit of the present invention described in the application item 1, the design rule inspection process after component placement wiring engineering is performed on a full wafer scale, and a marginal pattern is excluded from the verification object. Outside, so make good use of the pattern comparison library and database so far. The work of the proximity effect correction and the process margin verification performed before the event is performed, and on the other hand, the person who does not need the verifier is excluded from the processing flow, thereby achieving high efficiency of processing. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

The design method of the semiconductor integrated circuit of the present invention described in the third aspect of the invention is a method for designing a semiconductor integrated circuit when the physical layout of the semiconductor integrated circuit is generated by the semiconductor integrated circuit design data, and is characterized in that , with: component configuration wiring project, the components required to generate the pre-recorded entity layout are configured and wired; and the design rule inspection project refers to the rule library for design rule checking, which will contain the components of the pre-recorded entity layout. The shape of the second entity layout is verified; and the correction decision engineering is to determine whether to check the second entity layout before the pre-record design rule is satisfied in the pre-design rule checking project, and to perform the proximity effect correction; and the reticle data creation project is the current record In the correction determination project, when it is determined that the correction is not necessary, the second entity layout that is determined to be unnecessary to be corrected is used to create the mask data corresponding to the layout of the predecessor entity; and the proximity effect correction engineering is determined in the current compensation positive determination project. When correction is required, the second entity layout is performed before the object of judgment Near-effect correction; and reticle data creation project, using the second entity layout corrected in the proximity effect correction project to create the reticle data corresponding to the layout of the pre-recorded entity; and the adjacent effect correction project, the current design rule When the pre-requisite design rules are not met in the inspection project, the second entity layout as the verification object is used to perform the proximity effect correction; and the process margin verification project is in the vicinity of the pre-recording In the effect correction project, the second entity layout with the proximity effect correction is verified to verify whether there is a certain process margin; and the rule addition project is determined as the process margin when the current record process margin verification project determines that there is a process margin. The second entity layout is extracted, and the rules of the second entity layout are added to the pre-reporting rule library, and the mask data corresponding to the pre-recorded entity layout of the second entity layout is prepared; and the correction, correction, and verification engineering are performed. When it is determined that there is no process margin in the current verification process, the pattern correction, the artwork, the proximity effect correction, the proximity effect correction verification, and the reticle data creation project are performed on the second entity layout. The reticle data corresponding to the layout of the predecessor entity is created using the second physical layout of the pre-recording correction, correction, and verification project.

In the design method of the semiconductor integrated circuit of the present invention described in the application item 3, the design rule inspection process after the component layout wiring engineering is performed on the full wafer scale, and the marginal pattern is used to correct the proximity effect or the proximity effect. The conditions for the verification verification are alleviated, or are excluded from the verification object. Therefore, the use of the proximity effect correction and the process margin verification performed before the pattern comparison library and the database are used. In the case where the verifier is not required, it is excluded from the processing flow, whereby the efficiency of the processing can be improved. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

The design method of the semiconductor integrated circuit of the present invention described in claim 9 belongs to the semiconductor integrated circuit design data to generate a semiconductor integrated body. A method of designing a semiconductor integrated circuit for physical layout of a circuit, comprising: component arrangement wiring engineering, configuring and wiring components required for generating a physical layout of a pre-recorded; and relating to an image on a semiconductor substrate Comparison and coverage rate, the setting of the project; and the comparison inspection project, is to calculate the comparison of the pre-recorded layout, and refer to the pre-recording of the pre-recorded components of the layout of the pre-recorded comparison with the pre-record The calculation results are compared; and the correction project is the case where the calculation result of the comparison in the comparison check project is less than or equal to the pre-recorded threshold value, and the transfer information of the field less than or equal to the threshold value is compared. Acquiring, correcting the physical layout of the field, processing the original image; and correcting the verification project, the pre-recorded entity layout of the pre-revision correction project, performing the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, using Pre-reviewed. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check project, the calculation result of the comparison of the pre-record layout is larger than the pre-recorded threshold value, then refer to the pre-recorded entity layout. The threshold of the coverage rate is compared with the information about the coverage rate of the layout extracted from the previous note; and the layout extraction project is the current coverage coverage inspection project, and the information about the coverage rate satisfies the pre-recorded coverage rate. When the limit value is used, the physical layout of the object to be determined is extracted, and the physical layout obtained by the pre-recording extraction project is corrected. After verifying the project after the project; in the current coverage rate check project, if the information about the coverage rate does not satisfy the pre-recorded threshold value of the coverage rate, the pre-recorded entity layout is corrected. Correction. Verify the project after the project.

In the method of designing a semiconductor integrated circuit of the present invention described in claim 9, the comparative inspection process after component placement wiring engineering is performed on a full wafer scale, and a marginal pattern is used to alleviate the condition of the proximity effect correction. Or, it is excluded from the verification object, so the use of the proximity effect correction and the process margin verification performed before the pattern comparison library and the database are used, and on the other hand, the verification is not required. It is excluded from the processing flow, whereby the efficiency of processing can be improved. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

The design method of the semiconductor integrated circuit of the present invention described in claim 13 is a method for designing a semiconductor integrated circuit when the physical layout of the semiconductor integrated circuit is generated by the semiconductor integrated circuit design data. , with: component configuration wiring project, the components required to generate the pre-recorded entity layout are configured and wired; and the design rule inspection project refers to the rule function library for design rule checking to verify the components containing the pre-recorded entity layout. Whether part of the second entity layout has a defined process margin; and the correction decision project is to determine whether there will be a marginal second entity layout with margins in the current design rule check project; The hood data creation project is a reticle data corresponding to the layout of the predecessor entity; and the correction is made when the current stipulation is judged to be unnecessary to be corrected, and the second entity layout that is determined to be unnecessary to be corrected is used. When the verification project is determined to be required to be corrected in the current correction determination project, the second entity layout is recorded as the determination target. Proximity effect correction, proximity effect correction verification; and reticle data creation engineering, the use of pre-recording correction. In the verification project, the second entity layout of the proximity effect correction and the proximity effect correction verification is performed to create the mask material corresponding to the layout of the predecessor entity; and the correction. Verification project, when there is no process margin in the current design rule checking project, the second entity layout will be verified, and the proximity effect correction and proximity effect correction will be performed; and the second entity layout will be about the yield. The project for setting the limit value; and the yield evaluation project are based on the pre-requisite threshold, and compared with the information on the yield of the second entity layout; and the rule addition project, which is the current record of the good rate evaluation project. When the information on the yield meets the precautionary threshold of the yield, the layout of the second entity that is the object of judgment is extracted, and the rule of the layout of the second entity is added to the pre-reporting library; Engineering, in the current record of the rate of evaluation project, the pre-recorded information about the yield does not meet the pre-requisites of the yield limit, the transfer information obtained in the field of the pre-recorded yield less than or equal to the threshold, the field Correction of the second entity layout, original image processing; and correction. Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the second physical layout of the project to create the reticle data.

In the design method of the semiconductor integrated circuit of the present invention described in the application item 13, the design rule inspection process after component placement wiring engineering is performed on a full wafer scale, and a marginal pattern is used to correct the proximity effect or the proximity effect. The conditions for correcting the verification are alleviated or are sorted from the verification object In addition, the use of the proximity effect correction and the process margin verification performed before the pattern comparison library and the database are used, and on the other hand, the non-verifier is excluded from the processing flow. Thereby, the efficiency of the processing can be improved. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

The design method of the semiconductor integrated circuit of the present invention described in the application item 21 is a method for designing a semiconductor integrated circuit when the physical layout of the semiconductor integrated circuit is generated by the semiconductor integrated circuit design data. , with: component configuration wiring project, which is to configure and wire the components required to generate the pre-recorded physical layout; and the yield evaluation project refers to the second entity layout with the component of the pre-recorded entity layout. The threshold value is compared with the information about the yield of the second entity layout; and the layout extraction project is the current record of the yield evaluation project, and the information about the yield before the satisfaction meets the pre-requisites for the yield. At the time, the physical layout of the object to be judged will be extracted; and corrected. Verification project, for the physical layout obtained in the pre-record layout extraction project, the proximity effect correction, the proximity effect correction verification; and the correction project, in the current record rate evaluation project, the information about the yield is not satisfied with the pre-record When the rate is limited, the transfer information obtained in the field where the yield is less than or equal to the threshold value, the correction of the second entity layout in the field, and the original image processing; and the correction and verification work are performed. Pre-revision of the second entity layout of the revision project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verification project The second physical layout is used to make the reticle data.

According to the method for designing a semiconductor integrated circuit of the present invention described in the application 21, the yield evaluation project is based on the threshold of the second entity layout regarding the yield, and the layout of the second entity Since the information on the yield is compared, the design time of the semiconductor integrated circuit can be shortened.

The design apparatus of the present invention described in the application item 22 is a design apparatus for implementing a method of designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, and is characterized in that The design method of the pre-recorded semiconductor integrated circuit has: a component configuration wiring project, which is to configure and wire the components required for generating the pre-recorded physical layout; and a design rule inspection project, which refers to a rule library for design rule checking, The shape of the second entity layout containing the components of the pre-recorded entity layout is verified; and the reticle data is created into a project, and the current design rule is used to check the design rules in the project, and the second entity layout is used to create a corresponding The reticle data of the physical layout of the pre-recording; and the data processing of the reticle data processing, the reticle data processing of the second entity layout as the verification object is performed when the pre-recording design rule is not satisfied in the current design rule checking project; and the reticle data creation project , using the mask data processing in the pre-recorded mask data processing project The second physical layout to creating mask data corresponding to the physical layout of the front mind.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in the application 22, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the design rule after the component arrangement wiring works Then, the inspection process is performed on the full wafer scale, and the marginal pattern is excluded from the verification target, so that the processing can be improved.

The recording medium of the present invention described in claim 23 is a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by semiconductor integrated circuit design data is recorded. The design method of the pre-recorded semiconductor integrated circuit includes: component configuration wiring engineering, which is to configure and wire the components required for generating the physical layout of the pre-record; and design rule inspection engineering, refer to the rules for design rule inspection. The library will verify the shape of the second entity layout of the component with the pre-recorded entity layout; and the reticle data creation project, when the design rule is checked in the current design rule, the second entity layout is used. The reticle data corresponding to the layout of the pre-recorded entity; and the reticle data processing project are the reticle data processing of the second entity layout as the verification object when the current design rule checking project does not satisfy the pre-design rule; The cover data is made into a project, which was carried out using the pre-recorded reticle data processing project. The second cover physical layout of data processing, made to correspond to the mask layout data entity referred to before.

According to the recording medium of the present invention described in the application item 23, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the design rule inspection after the component arrangement wiring engineering is based on the full wafer scale. Since the remaining pattern is excluded from the verification target, it is possible to improve the efficiency of the processing.

The method for manufacturing a reticle of a semiconductor integrated circuit according to claim 24 is to use a semiconductor integrated circuit design data to generate a semiconductor product. A method of manufacturing a photomask produced by a method of designing a semiconductor integrated circuit in a physical layout of a bulk circuit, characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: component arrangement wiring engineering, which generates a pre-recorded physical layout The required components are configured and wired; and the design rule inspection project refers to the rule library for design rule checking, and the shape of the second entity layout containing the components of the pre-recorded entity layout is verified; and the mask data is created. The project is the current design rule checking system to meet the pre-recording design rules, using the second entity layout to create the reticle data corresponding to the layout of the pre-recorded entity; and the reticle data processing project, which is not in the current design rule inspection project. When the pre-script design rule is satisfied, the reticle data processing of the second entity layout as the verification object is performed; and the reticle data creation project is performed, and the second entity layout in which the reticle data processing is performed in the reticle data processing project is used to create Correspondence data corresponding to the layout of the predecessor entity.

According to the reticle manufacturing method of the semiconductor integrated circuit of the present invention described in the application item 24, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the design rule check after the component arrangement wiring work is performed. The engineering is performed on a full wafer scale, and the remaining patterns are excluded from the verification target, so that the processing can be improved.

The design apparatus of the present invention described in the application item 25 is a design apparatus for implementing a method of designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data. The pre-recorded semiconductor integrated circuit design method includes: component configuration wiring engineering, which is configured to generate components required for the pre-recorded physical layout. And wiring; and design rule inspection project, refer to the rule library for design rule check, verify the shape of the second entity layout containing the pre-recorded entity layout before the component; and correct the judgment project, determine whether to pre-record In the design rule inspection project, the second entity layout is recorded before the pre-requisite design rule is satisfied, and the proximity effect correction is performed; and the reticle data creation project is judged as the second correction without negation when the current record is determined in the judgment project. The physical layout is used to create the reticle data corresponding to the layout of the predecessor entity; and the proximity effect correction project is determined by the neighboring effect before the judgment object is determined to be required to be corrected; And the reticle data creation project, which uses the second entity layout that has been corrected in the proximity effect correction project to create the reticle data corresponding to the layout of the predecessor entity; and the adjacent effect correction project, which is not in the current design rule inspection project. When the prescriptive design rule is met, the second entity that is the object of verification will be Bureau, the correction of the proximity effect; and the process of the margin verification project, the second entity layout of the proximity effect correction in the pre-recording proximity effect correction project, to verify whether there is a certain process margin; and the rule addition project, the current record process When it is determined that there is a process margin in the margin verification project, the second entity layout to be determined is extracted, and the rule of the second entity layout is added to the pre-report rule library, and is created corresponding to the pre-recorded second entity layout. The reticle data of the pre-recorded entity layout; and the correction, correction, and verification project are the pattern corrections and original drawings of the second entity layout as the object of judgment when it is determined that there is no process margin in the current verification process. Artwork), proximity effect correction, proximity effect correction verification; and reticle data creation engineering, use The second entity layout of the project is corrected, corrected, and verified beforehand to create a mask material corresponding to the layout of the predecessor entity.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in the application 25, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the design rule inspection after the component layout wiring project is Performing on a full-wafer scale with a marginal pattern that mitigates the conditions for proximity effect correction or proximity effect correction verification, or excludes from verification objects, so make good use of the pattern comparison library and When the database is created, the proximity effect correction and the process margin verification are performed beforehand. On the other hand, if the certificate is not required, the process is excluded from the processing flow, thereby improving the efficiency of the processing.

The recording medium of the present invention described in claim 26 is a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by semiconductor integrated circuit design data is recorded. It is characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: component arrangement wiring engineering, which is to arrange and wire the components required for generating the layout of the pre-recorded entity; and the design rule inspection engineering refers to the rules for design rule inspection. The library will verify the shape of the second entity layout of the component before the layout of the pre-recorded entity; and correct the decision-making project, and determine whether to check the layout of the second entity before the pre-requisite design rule is met in the pre-design rule. Proximity effect correction; and reticle data creation project, when it is determined that the correction is not necessary in the current correction and determination project, the second entity layout that is determined to be unnecessary to be corrected is used to create the reticle data corresponding to the layout of the predecessor entity; Effect correction project, current record In the correction determination project, when it is determined that correction is necessary, the second entity layout is corrected for the proximity effect before the object is determined; and the reticle data creation project is based on the layout of the second entity that has been corrected in the proximity effect correction project. The reticle data corresponding to the layout of the pre-recorded entity; and the adjacent effect correction project are the second physical layout of the verification object when the current design rule inspection project does not satisfy the pre-design rule, and the proximity effect is corrected; The Yu Yu verification project is a second entity layout that has been corrected for the proximity effect in the previous neighbor correction effect correction project to verify whether there is a certain process margin; and the rule addition project is determined to have a process margin in the current record process margin verification project. When the second entity layout is determined as the object to be determined, the rule of the second entity layout is added to the pre-reporting rule library, and the mask data corresponding to the layout of the pre-recorded entity of the second entity layout is created; And the correction, correction, and verification project are judged as no in the current record process In the case of the process margin, the pattern correction, artwork, proximity effect correction, and proximity effect correction of the second entity layout as the object of judgment are performed; and the reticle data creation project is used, and the pre-record correction, correction, and verification are performed. The second physical layout of the project is to create a mask material corresponding to the layout of the predecessor entity.

According to the recording medium of the present invention described in claim 26, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the design rule inspection after component placement wiring works is on a full wafer scale. The pattern that is carried out and has a marginal pattern is to alleviate the conditions of the proximity effect correction or the proximity effect correction verification, or is excluded from the verification object, so the use of the pattern comparison library and the database so far is utilized. The work of the proximity effect correction and the process margin verification performed before the event is performed, and on the other hand, if the verifier is not required, it is excluded from the processing flow, thereby improving the efficiency of the processing.

The mask manufacturing method of the present invention described in the application item 27 is a mask manufacturing method which is produced by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data. The method is characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: a component arrangement wiring project, which is configured to arrange and wire components required for generating a pre-recorded physical layout; and a design rule inspection project, which is referred to the design rule inspection. The rule library will verify the shape of the second entity layout of the component before the layout of the pre-recorded entity; and correct the decision-making project, and determine whether to check the second entity layout before the pre-requisite design rule is checked in the pre-design rule. For the correction of the proximity effect; and the reticle data creation project, when it is determined that the correction is not necessary in the current correction and determination project, the second entity layout that is determined to be unnecessary to be corrected is used to create the reticle data corresponding to the layout of the pre-recorded entity; And the adjacent effect correction project, which is determined by the current record When correcting, correct the proximity effect of the second entity layout before the object of judgment; and the reticle data creation project, using the second entity layout corrected in the proximity effect correction project to create the layout corresponding to the pre-recorded entity. The reticle data; and the adjacent effect correction project are the second entity layout of the verification object when the design rule is not satisfied in the current design rule inspection project, and the proximity effect correction is performed; and the process margin verification project is The second entity layout of the proximity effect correction in the proximity effect correction project is verified. If there is a certain process margin, and if the rule addition project is determined to have a process margin in the current verification process, the second entity layout to be determined is extracted, and the rule of the second entity layout is added. Go to the rule library and make the mask data corresponding to the layout of the pre-recorded entity in the layout of the second entity; and correct, correct, and verify the project. Pattern modification, artwork, proximity effect correction, proximity effect correction verification of the second entity layout as the object of judgment; and the reticle data creation project, using the second entity layout of the pre-recording correction, correction, and verification project , to create a mask material corresponding to the layout of the predecessor entity.

According to the reticle manufacturing method of the present invention described in the application item 27, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the design rule inspection after the component arrangement wiring engineering is a full wafer. The scale is carried out, and the marginal pattern is to alleviate the conditions of the proximity effect correction or the proximity effect correction verification, or is excluded from the verification object, so the use of the pattern comparison library and the database is now utilized. On the other hand, the work of the proximity effect correction and the process margin verification performed before the event is excluded from the processing flow, and the efficiency of the processing can be improved.

The design apparatus of the present invention described in the application 28 is a design apparatus for implementing a method of designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, and is characterized in that The pre-recorded semiconductor integrated circuit design method includes: component configuration wiring engineering, which is configured to generate components required for the pre-recorded physical layout. And the wiring inspection; and the comparison inspection project, the comparison of the layout of the predecessor is calculated, and the comparison value of the comparison on the image on the semiconductor substrate of the layout obtained by arranging the pre-recorded components is compared with the calculation result of the comparison with the previous note. And the correction project, the current calculation of the contrast in the comparison check in the project, the calculation result is less than or equal to the pre-recorded limit value of the comparison, the pre-recording comparison of the transfer information of the field less than or equal to the threshold value, the field of Correction of the physical layout, original image processing; and correction. Verification project, the pre-recorded entity layout of the pre-revision correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check project, the calculation result of the comparison of the pre-record layout is greater than the pre-recorded threshold value, then refer to the pre-recorded entity layout. Regarding the threshold of the coverage rate, the information on the coverage ratio of the layout extracted from the previous record is compared; and the layout extraction project is the current coverage coverage inspection project, and the information about the coverage rate satisfies the pre-recorded coverage rate. When the threshold is reached, the physical layout of the object to be determined is extracted, and the physical layout obtained by the pre-recording extraction project is corrected. After verifying the project after the project; in the current record of the coverage rate inspection project, if the information about the coverage rate does not satisfy the pre-recorded threshold of the coverage rate, the pre-recording correction is made. Verify the project after the project.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in the application 28, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the comparative inspection project after the component layout wiring project is Full wafer scale, and there are marginal patterns that will be adjacent The conditions for effect correction are alleviated or excluded from the verification object. Therefore, the use of the proximity effect correction and photolithography verification performed before the pattern comparison library and the database are used. On the one hand, if the verifier is not required, it is excluded from the processing flow, whereby the efficiency of the processing can be improved.

According to the recording medium of the semiconductor integrated circuit of the present invention described in the application 29, the design method of the semiconductor integrated circuit for generating the physical layout of the semiconductor integrated circuit by the semiconductor integrated circuit design data is The recorded recording medium is characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: a component arrangement wiring project, which is to arrange and wire the components required for generating the layout of the pre-recorded entity; and a comparison inspection project, which is calculated The comparison of the layout of the pre-recording refers to the comparison of the calculation results of the comparison on the image on the semiconductor substrate with the layout of the components arranged in the pre-recording, and compares the calculation results with the previous comparison; and the correction engineering is the current comparison check. In the case where the calculation result of the pre-comparison in the project is less than or equal to the pre-recorded threshold value, the acquisition of the transfer information of the field less than or equal to the threshold value, the correction of the physical layout of the field, and the original image processing are performed; Correction. Verification project, the pre-recorded entity layout of the pre-revision correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check project, the calculation result of the comparison of the pre-record layout is larger than the pre-recorded threshold value, then refer to the pre-recorded entity layout. The threshold of the coverage rate, and the coverage of the layout drawn by the pre-record News, comparison; and layout extraction project, in the current record coverage rate inspection project, the pre-recorded information about the coverage rate meets the pre-recorded threshold of the coverage rate, the physical layout of the object to be determined, to extract; for the pre-record The layout of the physical structure obtained by the project is extracted and corrected. After verifying the project after the project; in the current record of the coverage rate inspection project, if the information about the coverage rate does not satisfy the pre-recorded threshold of the coverage rate, the pre-recording correction is made. Verify the project after the project.

According to the recording medium of the present invention described in claim 29, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the comparative inspection process after the component arrangement wiring work is performed on a full wafer scale. And the pattern with the margin is to alleviate the conditions for the correction of the proximity effect, or to be excluded from the verification object, so make good use of the proximity effect correction performed beforehand in the pattern comparison library and the database. The operation of the photolithography verification, on the other hand, is not excluded from the processing flow, and the efficiency of the processing can be improved.

The reticle manufacturing method of the present invention described in the application item 30 is a mask manufacturing method which is produced by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data. The method is characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: a component configuration wiring project, which is configured to arrange and wire components required for generating a pre-recorded physical layout; and a comparison inspection project, which calculates a comparison of the pre-recorded layout, Referring to the comparison of the results of the comparison of the images on the semiconductor substrate in the layout of the components of the pre-recorded components, the comparison results with the previous comparison are compared; and the correction engineering is the current comparison checker. In the case where the calculation result of the comparison before the process is less than or equal to the case of the threshold value of the comparison, the acquisition of the transfer information in the field of the comparison value less than or equal to the threshold value, the correction of the physical layout of the field, and the original image processing; Correction. Verification project, the pre-recorded entity layout of the pre-revision correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check project, the calculation result of the comparison of the pre-record layout is larger than the pre-recorded threshold value, then refer to the pre-recorded entity layout. The threshold of the coverage rate is compared with the information about the coverage rate of the layout extracted from the previous note; and the layout extraction project is the current coverage coverage inspection project, and the information about the coverage rate satisfies the pre-recorded coverage rate. When the limit value is used, the physical layout of the object to be determined is extracted, and the physical layout obtained by the pre-recording extraction project is corrected. After verifying the project after the project; in the current record of the coverage rate inspection project, if the information about the coverage rate does not satisfy the pre-recorded threshold of the coverage rate, the pre-recording correction is made. Verify the project after the project.

According to the reticle manufacturing method of the present invention described in claim 30, since the design method of the semiconductor integrated circuit of the present invention is used, as described above, the comparative inspection project after component placement wiring engineering is on a full wafer scale. To carry out, and the marginal pattern is to alleviate the conditions of the proximity effect correction, or to be excluded from the verification object, so make good use of the proximity of the pattern comparison library and the database beforehand. Effect correction, photolithography verification, and no verification on the other hand The person is excluded from the processing flow, whereby the efficiency of the processing can be improved.

The design apparatus of the semiconductor integrated circuit of the present invention described in claim 31 is a design apparatus for designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data. It is characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: a component arrangement wiring project, which is configured to arrange and wire components required for generating a pre-recorded physical layout; and a design rule inspection project, which is referred to the design rule inspection. The rule function library verifies whether the second entity layout including the part of the pre-recorded entity layout has a predetermined process margin; and the correction determination project is to determine whether there is a process margin in the current design rule inspection project, and whether it will have Yu Yu's pre-recorded second entity layout, for correction; and the reticle data creation project, which is determined to be unnecessary for correction in the current record correction judgment project, and is determined to be the second entity layout that is determined not to be corrected before use, to create a layout corresponding to the pre-recorded entity Photomask information; and corrections. In the verification project, when it is determined that the correction is necessary in the current judgment and judgment project, the second entity layout is recorded before the judgment object, and the proximity effect correction and the proximity effect correction verification are performed; and the reticle data creation project is used to correct the correction. In the verification project, the second entity layout of the proximity effect correction and the proximity effect correction verification is performed to create the mask material corresponding to the layout of the predecessor entity; and the correction. Verification project, when there is no process margin in the current design rule check project, it will be the second entity layout of the verification object, and the proximity effect correction and proximity effect correction verification; and the yield evaluation project refer to the layout of the second entity. Regarding the threshold of yield, and the second note The information on the yield of the physical layout is compared; and the rule addition project is in the current rate evaluation project. If the information about the yield meets the pre-requisite threshold of the yield, it will be the object of judgment. The second entity layout is extracted, and the rules of the second entity layout are added to the pre-reporting rule library; and the revision project is in the current rate evaluation project, and the information about the yield is not satisfied with the pre-recording rate. In the case of the threshold, the acquisition of the transfer information in the field where the pre-recording yield is less than or equal to the threshold value, the correction of the second entity layout in the field, and the original image processing; Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the second physical layout of the project to create the reticle data.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in the application item 31, the design rule inspection process after the component layout wiring engineering is performed on the full wafer scale, and the marginal pattern is used to correct the proximity effect or the proximity effect. The conditions for the verification verification are alleviated or excluded from the verification object. Therefore, the use of the proximity effect correction and the photolithography verification performed before the pattern comparison library and the database are used. On the one hand, if the verifier is not required, it is excluded from the processing flow, whereby the efficiency of the processing can be improved. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

The recording medium of the present invention described in claim 32 belongs to a solid cloth for generating a semiconductor integrated circuit by using semiconductor integrated circuit design data. A recording medium in which a design method of a semiconductor integrated circuit is recorded, and a method of designing a semiconductor integrated circuit is provided with a component layout wiring project, which is a component required to generate a physical layout of a predecessor. For configuration and wiring; and the design rule inspection project, refer to the rule library for design rule checking to verify whether the second entity layout containing the part of the component before the layout of the pre-recorded entity has the specified process margin; and the correction decision engineering When there is a process margin in the current design rule check project, it is determined whether or not the second entity layout with margins is corrected, and the reticle data creation project is used when the current record correction judgment project is determined not to be corrected. It is judged that the second entity layout is not necessary to be corrected, and the reticle data corresponding to the layout of the predecessor entity is created; and the correction is made. In the verification project, when it is determined that the correction is necessary in the current judgment and judgment project, the second entity layout is recorded before the judgment object, and the proximity effect correction and the proximity effect correction verification are performed; and the reticle data creation project is used to correct the correction. In the verification project, the second entity layout of the proximity effect correction and the proximity effect correction verification is performed to create the mask material corresponding to the layout of the predecessor entity; and the correction. Verification project, when there is no process margin in the current design rule check project, it will be the second entity layout of the verification object, and the proximity effect correction and proximity effect correction verification; and the yield evaluation project refer to the layout of the second entity. Regarding the threshold of the yield, and comparing with the information on the yield of the second entity layout, and the rule addition project, in the current record rate evaluation project, the information about the yield before the satisfaction meets the pre-record on the yield. When the threshold is exceeded, the second entity layout that is the object of judgment is extracted, and the rule of the second entity layout is added to the pre-report rule function. The library; and the revision project, in the current record of the rate evaluation project, the information on the yield of the pre-recording does not meet the pre-recorded threshold of the yield, then the transfer information in the field where the yield is less than or equal to the threshold Acquire, correct the layout of the second entity in the field, original image processing; and correction. Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the second physical layout of the project to create the reticle data.

According to the recording medium of the present invention described in claim 32, the design rule inspection process after component placement wiring engineering is performed on a full wafer scale, and a marginal pattern is used to verify the conditions of proximity effect correction or proximity effect correction. Relieve, or be excluded from the verification object, so use the proximity effect correction and photolithography verification work done before the pattern comparison library and database creation, and on the other hand, no verification is needed. The person is excluded from the processing flow, whereby the efficiency of the processing can be improved. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

The reticle manufacturing method of the present invention described in the application item 33 is a reticle manufacturing method which is produced by using a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data. The method is characterized in that the design method of the pre-recorded semiconductor integrated circuit includes: a component configuration wiring project, which is configured to arrange and wire components required for generating a pre-recorded physical layout; and a design rule inspection project, which is referred to The rule function library for the rule check verifies whether the second entity layout including the part of the component before the layout of the pre-recorded entity has a predetermined process margin; and the correction determination project is the current design rule check process when there is a process margin It is determined whether or not the layout of the second entity having the margin is corrected, and the reticle data creation project is determined by the second entity layout that is determined to be unnecessary to be corrected when the current record is determined to be unnecessary. Correspondence information corresponding to the layout of the predecessor entity; and correction. In the verification project, when it is determined that the correction is necessary in the current judgment and judgment project, the second entity layout is recorded before the judgment object, and the proximity effect correction and the proximity effect correction verification are performed; and the reticle data creation project is used to correct the correction. In the verification project, the second entity layout of the proximity effect correction and the proximity effect correction verification is performed to create the mask material corresponding to the layout of the predecessor entity; and the correction. Verification project, when there is no process margin in the current design rule check project, it will be the second entity layout of the verification object, and the proximity effect correction and proximity effect correction verification; and the yield evaluation project refer to the layout of the second entity. Regarding the threshold of the yield, and comparing with the information on the yield of the second entity layout, and the rule addition project, in the current record rate evaluation project, the information about the yield before the satisfaction meets the pre-record on the yield. When the threshold is reached, the second entity layout that is the object of judgment is extracted, and the rule of the second entity layout is added to the pre-reporting rule library; and the correction project is in the current rate evaluation project. If the information about the yield does not satisfy the pre-requisites for the yield, the acquisition of the transfer information in the field where the yield is less than or equal to the threshold, the correction of the second entity layout in the field, and the original image. Processing; and correction. Verification project, The second entity layout of the pre-recording correction project was carried out, and the proximity effect correction and the proximity effect correction verification were performed; and the reticle data creation project was used to make corrections. Verify the second physical layout of the project to create the reticle data.

In the photomask manufacturing method of the present invention described in the application item 33, the design rule inspection process after the component placement wiring engineering is performed on a full wafer scale, and the marginal pattern is verified by the proximity effect correction or the proximity effect correction. Conditions are alleviated, or excluded from the verification object, so the use of the proximity effect correction and photolithography verification performed before the pattern matching library and database is used. If the verifier is required, it is excluded from the processing flow, whereby the efficiency of the processing can be improved. Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

According to the design method of the semiconductor integrated circuit of the present invention described in the application 1, the burden of the pattern matching library can be reduced, and the data of the full wafer processing can be deleted, and the verification of the pattern with the margin can be eliminated. In addition, the overall processing load can be reduced, and the advantage of simplifying the design of the semiconductor integrated circuit can be achieved without lowering the screening accuracy.

According to the design method of the semiconductor integrated circuit of the present invention described in the application item 3, the burden of the pattern matching library can be reduced, and the data of the entire wafer processing can be deleted, and the verification of the pattern with the margin can be alleviated. Or in In addition, the overall processing load can be reduced, and the advantage of simplifying the design of the semiconductor integrated circuit can be achieved without lowering the screening accuracy.

According to the design method of the semiconductor integrated circuit of the present invention described in the application 9, the design of the semiconductor integrated circuit can be simplified without lowering the screening accuracy. Further, compared with the method of designing the semiconductor integrated circuit of the present invention described in the third aspect of the invention, since the creation of the library is not performed, there is an advantage that the burden of the library creation can be reduced.

According to the method for designing a semiconductor integrated circuit of the present invention described in claim 13, since the layout is screened using the yield evaluation value, all the processing is judged from the viewpoint of the yield, even if the process margin is small. However, as long as the yield can be obtained, since it can be judged in this way, it is possible to achieve high efficiency and simplification of the entire design process without lowering the screening accuracy from a different viewpoint.

According to the design method of the semiconductor integrated circuit of the present invention described in the application 21, since the layout is screened using the yield evaluation value, all the processing is judged from the viewpoint of the yield, even if the process margin is small. However, as long as the yield can be obtained, since it can be judged in this way, it is possible to achieve high efficiency and simplification of the entire design process without lowering the screening accuracy from a different viewpoint.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in the application item 22, since the design method of the semiconductor integrated circuit of the present invention described in the application 1 is used, it is advantageous to obtain the same effect as the above. .

According to the recording medium of the present invention described in claim 23, According to the design method of the semiconductor integrated circuit of the present invention described in the application item 1, there is an advantage that the same effect as described above can be obtained.

According to the reticle manufacturing method of the present invention described in the application item 24, since the design method of the semiconductor integrated circuit of the present invention described in the application item 1 is used, there is an advantage that the same effect as described above can be obtained.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in claim 25, since the design method of the semiconductor integrated circuit of the present invention described in claim 3 is used, there is an advantage that the same effect as described above can be obtained. .

According to the recording medium of the present invention described in claim 26, since the design method of the semiconductor integrated circuit of the present invention described in the application 3 is used, there is an advantage that the same effect as described above can be obtained.

According to the reticle manufacturing method of the present invention described in the application item 27, since the design method of the semiconductor integrated circuit of the present invention described in the application 3 is used, there is an advantage that the same effect as described above can be obtained.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in the application item 28, since the design method of the semiconductor integrated circuit of the present invention described in the application 9 is used, there is an advantage that the same effect as the above can be obtained. .

According to the recording medium of the present invention described in claim 29, since the design method of the semiconductor integrated circuit of the present invention described in the application 9 is used, there is an advantage that the same effect as described above can be obtained.

According to the reticle manufacturing method of the present invention described in claim 30, the design of the semiconductor integrated circuit of the present invention described in claim 9 is used. The method has the advantage that the same effect as above can be obtained.

According to the design apparatus of the semiconductor integrated circuit of the present invention described in claim 31, since the design method of the semiconductor integrated circuit of the present invention described in claim 13 is used, it is possible to obtain the same effect as the above-described effect. .

According to the recording medium of the present invention described in claim 32, since the design method of the semiconductor integrated circuit of the present invention described in claim 13 is used, there is an advantage that the same effect as described above can be obtained.

According to the reticle manufacturing method of the present invention described in the application item 33, since the design method of the semiconductor integrated circuit of the present invention described in the application item 13 is used, there is an advantage that the same effect as described above can be obtained.

An embodiment (first embodiment) of the method of designing a semiconductor integrated circuit of the present invention described in the first aspect of the present invention will be described with reference to the flowchart of FIG. 1.

As shown in FIG. 1, in the method of designing a semiconductor integrated circuit for generating a physical layout of a semiconductor integrated circuit by using a semiconductor integrated circuit design data, a semiconductor integrated body is disposed in the "element arrangement wiring project" S11. The functional elements (cells) and wiring of the circuit form a physical layout.

Then, by using the "rule library" 21, referring to the rule for design rule checking, in the "design rule checking project" S12, it is verified whether the second entity layout including the part of the component above the layout of the entity has the predetermined Process margin. For example, refer to the "Rules Library" 21 and design by Rule checking (DRC) to extract the pattern with a very large process margin among the above physical layouts.

In the present embodiment, a pattern having a sufficient process margin is, for example, a line arrangement of the short line pattern shown in Fig. 2 (1), a pattern of a part of the parallel line pattern shown in (2), and (3) The arrangement rule of the long line segment pattern shown, the long line segment pattern shown in (4), and the pattern in which the short line pattern is mixed is designed.

Since all the patterns shown in Figs. 2(1) to (4) are patterns having a very large process margin, for example, proximity effect correction and proximity effect correction are not performed.

As a result, if there is a process margin in the "Design Rule Checking Project" S12 (Yes), it is extracted as a very large pattern. Therefore, after the "Design Rule Checking Project" S12 is performed, the follow-up is not performed. In the "mask data creation project" S14, the second entity layout is used to create a mask material corresponding to the layout of the predecessor entity.

On the other hand, if there is no process margin (No) in the "Design Rule Checking Project" S12, the "mask data processing project" S13 is performed.

In the "mask data processing project" S13, for example, in the "proximity effect correction project" S13-1, the second entity that is the object of verification is laid out, and the proximity effect is corrected.

Next, in the "proximity effect correction verification project" S13-2, the proximity effect of the pattern of the second entity layout subjected to the proximity effect correction is corrected and verified.

Moreover, the optical conditions of the proximity effect correction, the proximity effect correction verification, and the relaxation condition of the proximity effect correction can be changed according to the layout to be processed.

Next, in the "mask data creation project" S14, the second entity layout in which the "proximity effect correction verification project" S13-2 has been performed is used to create the mask data corresponding to the layout of the predecessor entity.

In the above-mentioned "mask data processing project" S13, when it is not necessary to correct the proximity effect of the data of the second entity layout, for example, when the processing flow after the mask data is created includes the proximity effect correction processing, the above is not performed. Proximity Effect Correction Project S13-1, "Proximity Effect Correction Verification Project" S13-2.

Further, the design rules used in the present embodiment are set to various types depending on the product and the process.

Further, FIG. 1 is only an example of the present embodiment. If the pattern having a sufficient processing margin can be extracted and the mask data is tape-out, the flow of FIG. 1 is not necessarily limited. For example, design rules can be replaced by design rules, contrasts using design data, or MEEF (Mask Error Enhancement Factor), and combinations of these.

An embodiment (second embodiment) of the method of designing a semiconductor integrated circuit of the present invention described in the third aspect of the present invention will be described with reference to the flowchart of FIG.

As shown in FIG. 3, the design of the semiconductor integrated circuit at the time of generating the physical layout of the semiconductor integrated circuit by using the semiconductor integrated circuit design data In the method, in the "element arrangement wiring work" S11, the functional elements (cells) and wirings of the semiconductor integrated circuit are arranged to form a physical layout.

Then, by using the "rule library" 21, referring to the rule for design rule checking, in the "design rule checking project" S12, it is verified whether the second entity layout including the part of the component above the layout of the entity has the predetermined Process margin. For example, a design rule check (DRC) is referred to the "rule library" 21 to pre-filter a pattern having a very large process margin of the above-described physical layout.

First, as shown in Table 1, the design rule (DR) for the preparation of the product (if it is informal) can be added to the design rule by adding a predetermined bias (bias) to make the comparison design. rule. Table 1 is a rule for the pattern Lnm and the interval Snm of a pattern indicated by the pattern 1 and the pattern 2. When the pattern of the verification object layout is a condition that satisfies the L and S method, the remaining margin is judged to be large. In this embodiment, the deviation is set to 30 nm. The design rule check (DRC) of the layout is then performed based on the DR for comparison.

Then, if there is a system in the "Design Rule Checking Project" S12 In the case of Cheng Yuyu (Yes), in the "correction determination project" S13, it is compared with a predetermined process margin specification, and it is determined whether or not the second entity layout having the margin is corrected.

When it is determined that the correction is not necessary (No), the "mask data creation project" S14 is used to create a second physical layout that is determined to be uncorrected. The reticle data of the physical layout is written.

When it is determined that the correction is necessary (Yes) in the "correction determination project" S13, the second entity layout is corrected and corrected in the "correction project" S16. For example, perform proximity effect correction (eg OPC), proximity effect correction verification.

Next, in the "mask data creation project" S14, the second entity layout corrected in the "correction project" S16 described above is used to create the mask material corresponding to the layout of the pre-recorded entity.

On the other hand, if there is no process margin in the "Design Rule Checking Project" S12 (No), in the "Proximity Effect Correction Project" S17, the second entity that is the verification target is laid out, and the proximity effect correction is performed. .

Next, in the "process margin verification project" S18, it is verified whether or not there is a certain process margin for the layout of the second entity in which the proximity effect correction is performed in the neighboring effect correction project.

When it is determined that there is a process margin in the "process margin verification project" S18 (Yes), in the "proximity effect correction project" S19, the second entity layout to be determined is extracted, and the second entity is extracted. entity The rules of the layout are added to the "rule library" 21 above.

On the other hand, when it is determined that there is no process margin in the "process margin verification project" S18 (No), the "correction, correction, verification project" S20 performs the second entity layout as the determination target. Pattern correction, original image, proximity effect correction, proximity effect correction verification.

Next, in the "mask data creation project" S14, the second entity layout in which the "correction, correction, verification project" S20 has been performed is used to create the mask data corresponding to the layout of the pre-recorded entity.

When the pattern comparison is performed again in the "design rule check" S12, the "addition of the small margin pattern", the "proximity effect correction", and the "transfer simulation" which were previously performed are omitted for the added pattern. ", layout correction."

Also, the rule library is obtained as follows.

For example, as shown in the flowchart of FIG. 4, first, in the "layout creation project", the first physical layout in which the components constituting the physical layout are arranged and wired is created.

Next, in the "transfer information creation project", a simulation for applying the proximity effect correction to the first physical layout to transfer the first physical layout onto the semiconductor substrate is performed, and then transfer information is created.

Next, in the "pattern extraction project", based on the above-described transfer information, a pattern larger than the process margin of the first physical layout is extracted.

Next, in the "rule creation project", a rule for checking the design rule including the pattern information of the extracted first entity layout is created, and the created rule is stored in the above "rule function library".

In this way, the second entity layout is extracted, and then the rule of the second entity layout is added to the rule function library, thereby relaxing the condition of the optical proximity effect correction, or alleviating the condition of the photolithography verification, or easing the light. The condition of the proximity effect correction is excluded from the object of photolithography verification, or the optical proximity effect correction is eliminated, and the condition of photolithography verification is alleviated, or excluded from the object of optical proximity effect correction and photolithography verification. Any of the above matters is possible, whereby the design time of the semiconductor integrated circuit can be shortened.

In the second embodiment, in order to set the deviation for the comparison to be large, all the layouts written by the rule larger than the design rule shown in Table 1 above are excluded from the verification target field. In other words, it is the processing when "Design Rule Check" is "Yes". Whether or not to be judged as the field of verification object can be adjusted by adding a deviation to the design rule. Alternatively, it is also possible to perform screening only with design rules, and then redo the transfer simulation with the relaxed conditions.

When the layout is cut out, the attributes of the layout are changed to distinguish them from others. If the verification is finished, the attributes are changed back and then tape-out is performed.

Further, in the "correction determination project" S13, whether or not the correction is made is made when the deviation of the design rule is large and there is a significant process margin, and the process proceeds directly to the "mask data creation project" S14; when the design rule deviation is small, Before proceeding to the "correction project" S16, the "correction project" S16 performs proximity effect correction and proximity effect correction verification. Here, full wafer verification is possible.

In the second embodiment, for example, when the design rule deviation is 10 nm or more, the "mask data creation project" S14 is directly entered; if it is less than 10 nm, the process proceeds to "correction project" S16. . Further, the value of the design rule deviation is not limited to this.

The design rule shown in Table 1 used in the second embodiment is an excerpt from the rules of a certain pattern. As long as the design rules can be used, it is not limited to this form.

Further, in the second embodiment, the variation required for the design rule for comparison is set to 30 nm, but the value of the design rule deviation is not limited to 30 nm, and can be freely set.

In addition, if the result of the verification by the "Design Rule Checking Project" S12 is to perform the "proximity effect correction" S17 and the "process margin verification project" S18, the processing conditions can be set according to the purpose. For example, the optical conditions of the transfer simulation of the proximity effect correction and the process margin inspection are set to an exposure wavelength of 193 nm, NA = 0.75, σ = 0.85, and 2/3 of the wheel. On the other hand, the amount of exposure was 13.5 mJ, and the center portion was changed stepwise every 0.5 mJ, and the defocus amount was calculated in the range of ±0.2 μm in steps of 0.05 μm. Further, the setting values of the doping amount and the focusing condition are regarded as the target value by the line segment and the interval of 100 nm. Further, the process flow "correction process" S16 after the tape-out process includes the proximity effect correction (OPC) process, but the proximity effect correction process may or may not be applied. Further, in the above-mentioned "correction, correction, verification project" S20, although not shown, a tape-out is included between the original image and the adjacent effect correction, and the adjacent effect correction (OPC) processing after the offline is applied. Or not Apply.

Further, the optical condition of the proximity effect correction, the process margin check, and the proximity effect correction verification, and the relaxation condition of the proximity effect correction are not limited to the method of the present embodiment, and may be changed depending on the layout to be processed.

In addition, the above conditions are based on the period of product planning, and until the process conditions are mature, they can be adapted to various conditions. Even when the processing of the present embodiment is performed, the processing priority can be given in consideration of electrical characteristics. That is to say, the part of the circuit corresponding to the critical path must be subjected to transfer simulation, and the other areas are subjected to usual verification processing.

In the design method of the semiconductor integrated circuit of the second embodiment, the design rule inspection process after the component placement wiring process is performed on the full wafer scale, and the marginal pattern is the condition for verifying the proximity effect correction or the proximity effect correction. It is moderated or excluded from the verification object. Therefore, it is not necessary to use the proximity effect correction and photolithography verification work performed before the pattern comparison library and database creation. The verifier is excluded from the processing flow, whereby the efficiency of the processing can be improved.

Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

Therefore, the burden of the pattern matching library can be reduced, and the data of the whole wafer processing can be deleted, and the verification of the pattern with the margin can be alleviated or excluded, and the overall processing load can be reduced, and the filtering precision can be reduced. The advantages of the design of the semiconductor integrated circuit can be simplified.

An embodiment (third embodiment) of the method of designing a semiconductor integrated circuit of the present invention described in claim 9 will be described with reference to the flowchart of FIG.

As shown in FIG. 5, in the semiconductor integrated circuit design method for generating the physical layout of the semiconductor integrated circuit by the semiconductor integrated circuit design data, the semiconductor integrated body is disposed in the "element arrangement wiring project" S31. The functional elements (cells) and wiring of the circuit form a physical layout.

Next, in the "Comparative Inspection Project" s32, the comparison of the above-mentioned layouts is calculated, and the "pre-measurement threshold value" 41 of the image on the semiconductor substrate obtained by arranging the wirings of the respective components is compared with the above. Calculate the results for comparison. For example, in the above-mentioned "contrast inspection project" S32, the slope of the optical image is calculated for the edge of each pattern, and a pattern surrounded by a predetermined comparison specification, for example, a slope value greater than 55, is extracted.

In the above-mentioned "Comparative Inspection Project" S32, when the calculation result of the comparison above is less than or equal to the threshold value of the comparison (No), in the "correction engineering" S33, the comparison is performed with the upper limit being less than or equal to the threshold value. The acquisition of transfer information in the field, the correction of the physical layout of the field, and the processing of the original image.

Then, in the "correction and verification project" S34, the layout of the upper body of the above-mentioned correction project is performed, and the proximity effect correction and the proximity effect correction are performed.

Then in the "Mask data creation project" S35, the use was carried out Record the physical layout of the "Remediation. Verification Project" S34 to create a mask material.

In the above-mentioned "contrast inspection project" S32, when the calculation result of the comparison above is greater than the threshold value for the comparison (Yes), the "coverage inspection project" S36 refers to the "relationship of the layout of the upper entity". The rate limit "42" is compared with the information on the coverage rate of the layout extracted by the above. For example, the slope value is a layout location that is larger than a predetermined value and the coverage ratio is larger than a predetermined coverage specification value (for example, 45%), and is extracted.

In the above-mentioned "coverage rate inspection project" S36, when the information on the coverage ratio satisfies the above-mentioned threshold value of the coverage rate (Yes), the "layout extraction project" S37 is used as the determination target. The physical layout is extracted.

Then, for the physical layout obtained in the above-mentioned layout extraction project, the above-mentioned "correction and verification project" S34 is performed. At this time, for the pattern extracted by the combination of the slope value and the coverage ratio, the conditions of the proximity effect correction (for example, OPC) and the proximity effect correction (for example, OPC) verification can be alleviated for processing.

In the above-mentioned "coverage rate inspection project" S36, when the information on the coverage rate does not satisfy the above-mentioned threshold value of the coverage rate (No), the above-mentioned "correction project" S33 is performed.

In the third embodiment above, although the processing time is not consumed because the proximity effect correction (OPC) processing is omitted, the physical layout is extracted because the mask data after the adjacent effect correction (OPC) is used. For the transfer simulation, the Proximity Effect Correction (OPC) and Proximity Effect Correction (OPC) verification in the "Revision and Verification Project" S34 are performed without being omitted. Based on the "Contrast Inspection Project" S32 and the "Coverage Rate Inspection Project" The verification result of S36 determines the processing conditions of "correction. verification project" S34.

On the other hand, in the process of "Contrast Inspection Project" S32 or "Coverage Rate Inspection Project" s36, the pattern that does not satisfy the specifications is again in the "correction project" s33, and the above comparison is equal to or less than the threshold. The acquisition of transfer information in the field, the correction of physical layout in the field, and the processing of original drawings.

In this way, by performing the contrast check and the coverage rate check, the condition for mitigating the light proximity effect, or the condition for mitigating the photolithography verification, or the condition for mitigating the light proximity effect can be made and excluded from the object of photolithography verification. It is possible to eliminate or exempt the pre-recording optical proximity effect from the condition of photolithographic verification, or to exclude any of the above-mentioned matters other than the object of optical proximity effect correction and photolithography verification, thereby realizing semiconductor integration The design time of the circuit is shortened.

Here, an example of a pattern extracted based on the slope and the coverage ratio is shown in FIG. 6. As an example, the arrangement of the short line pattern shown in Fig. 6 (1), the pattern in which a part of the parallel line pattern shown in (2) is connected, and the arrangement of the long line pattern shown in (3) are extracted. (4) The arrangement of the long line segment pattern and the short line segment pattern shown, and the like.

All the patterns shown in Fig. 6 (1) to (4), because the result of the transfer simulation is a pattern with a very large process margin, the proximity effect is corrected, The proximity effect correction verification can be performed by using conditions such as mitigating the verified trans, the number of interphases corrected by the proximity effect, and the like.

Further, as an example, the optical conditions of the transfer simulation of the proximity effect correction and the process margin inspection are set to an exposure wavelength of 193 nm, NA = 0.75, σ = 0.85, and 2/3 of the wheel. On the other hand, the amount of exposure was 13.5 mJ, and the center portion was changed stepwise every 0.5 mJ, and the defocus amount was calculated in the range of ±0.2 μm in steps of 0.05 μm.

Further, the setting values of the doping amount and the focusing condition are, for example, a line segment and an interval of 100 nm as a target value.

Moreover, although the process flow after the offline process includes the proximity effect correction process, the proximity effect correction engineering system may or may not be applied.

Moreover, the optical conditions of the proximity effect correction, the process margin check and the proximity effect correction verification, and the relaxation condition of the proximity effect correction are not limited to the pre-recording conditions, and may be changed according to the layout to be processed.

In the third embodiment, the extraction condition is such that the slope value is 55 or more and the coverage ratio is 45% or more. However, the extraction conditions are not limited thereto, and can be appropriately set. Further, it is not limited to the slope and the coverage ratio, and for example, it may be extracted by a combination with a CD (critical dimension) value. Moreover, the optical conditions of the proximity effect correction, the proximity effect correction verification, and the relaxation condition of the proximity effect correction can be changed according to the layout to be processed.

Moreover, these conditions are related to the period of product planning, and until the process conditions are mature, they can be adapted to various conditions. Even when the processing of the present embodiment is performed, the processing priority can be given in consideration of electrical characteristics. That is, the circuit is equivalent to a critical path. Part of the transfer must be carried out simulation, and other areas use the usual verification process.

In the design method of the semiconductor integrated circuit of the third embodiment, the comparison inspection process after the component placement wiring process is performed on the full wafer scale, and the marginal pattern is used to alleviate the condition of the proximity effect correction, or to verify Objects are excluded, so the use of the proximity effect correction and photolithography verification performed before the pattern comparison library and database are used. On the other hand, the verifier is excluded. In addition to the processing flow, the efficiency of the processing can be improved.

Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

Therefore, the design of the semiconductor integrated circuit can be simplified without lowering the screening accuracy. Further, compared with the design method of the semiconductor integrated circuit of the present invention described in the second aspect of the invention, since the library is not created, there is an advantage that the burden of the library creation can be reduced.

Next, an embodiment (fourth embodiment) of the method of designing a semiconductor integrated circuit of the present invention described in the application 13 will be described with reference to the flowchart of FIG.

As shown in FIG. 7, in the method of designing a semiconductor integrated circuit for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, a semiconductor integrated circuit is disposed in the "element arrangement wiring project". The functional elements (cells) and wiring form a physical layout.

Then, with the "rule library" 21, refer to the design rule check In the "Design Rule Checking Project" S12, it is verified whether or not the second physical layout including the portion of the component above the physical layout has a predetermined process margin. For example, a design rule check (DRC) is referred to by referring to the "rule library" to pre-filter a pattern having a very large process margin of the above-described physical layout.

First, as shown in Table 1 above, the design rule (DR) for the preparation of the product (if it is informal) can be added to the design rule by adding a predetermined bias (bias) for comparison. Design rules. Table 1 is a rule for the pattern Lnm and the interval Snm of a pattern indicated by the pattern 1 and the pattern 2. When the pattern of the verification object layout is a condition that satisfies the L and S method, the remaining margin is judged to be large. In this embodiment, the deviation is set to 30 nm. The design rule check (DRC) of the layout is then performed based on the DR for comparison.

Then, if there is a process margin in the "design rule check project" S12 (Yes), the "correction determination project" S13 compares with a predetermined process margin specification to determine whether or not there is a margin. The second entity layout is reviewed and corrected.

When it is determined that the correction is not necessary (No), the "mask data creation project" S14 is used to create a second physical layout that is determined to be uncorrected. The reticle data of the physical layout is written.

When it is determined that the correction is necessary (Yes) in the "correction determination project" S13, the second entity layout is corrected and corrected in the "correction and verification project" S16. For example, proceeding proximity Effect correction (eg OPC), proximity effect correction verification.

Next, in the "mask data creation project" S14, the second entity layout corrected in the above-mentioned "correction and verification project" S16 is used to create the mask data corresponding to the layout of the pre-recorded entity.

On the other hand, if there is no process margin in the "Design Rule Checking Project" S12 (No), in the "Revision and Verification Project" S16, the second entity to be verified is laid out, and the proximity effect is corrected. , proximity effect correction verification.

Next, in the "benefit evaluation project" S51, the information on the yield of the second entity layout is compared with the information on the yield of the second entity layout.

In the above-mentioned "Benefit Evaluation Project" S51, if the information on the yield is satisfied with the threshold value of the above-mentioned yield (Yes), the "Proximity Effect Correction Project" S19 will be the object of judgment. The second entity layout is extracted, and the rule of the second entity layout is added to the above-mentioned "rule library" 21.

On the other hand, in the above-mentioned "benefit evaluation project" S51, when the information on the yield is not satisfied with the margin of the above-mentioned yield (No), the "correction project" S52 is performed. Acquisition of transfer information in areas where the yield is less than or equal to the threshold, correction of the layout of the second entity in the field, and processing of the original image.

Next, in the "correction and verification project" S53, the second entity layout of the above-mentioned "correction project" S52 is performed, and the proximity effect correction and the proximity effect correction are performed.

Next, in the "mask data creation project" S14, the second entity layout in which the "correction. verification project" S53 has been performed is used to create the mask data corresponding to the layout of the predecessor entity.

The yield evaluation value in the above-mentioned "benefit evaluation project" S51 is as shown in Table 2, and the probability density calculated based on the value of the dew amount of the exposure device and the defocus amount is as shown in FIG. The function of the measured number of errors can be obtained by performing the cyclotron integral.

The results are shown in Table 3.

As shown in Table 3, the left column indicates the probability that the pattern of the pattern formed on the wafer is exposed when the pattern is exposed by the exposure conditions in the range of the amount of dew and the amount of defocus set. Density; the right column corresponds to the probability density of the left column, and the result of the convolution integral of the function of the number of errors shown in Fig. 8 is expressed in %. Since it is a defect probability equivalent to the yield, the judgment of the processing can be performed by the value of the defect probability.

Generally, the probability density is as shown in equation (3).

When the P system of the above formula (3) is such that X is continuous and X is a probability between the intervals a and b, it is assumed that f(x) given by the above equation (3) is a probability density function, and some The double variable function f(x, y) is as in (4).

In the case of the above formula (4), f(x, y) is a simultaneous density variable of a two-dimensional probability variable (X, Y), and can be expressed as equation (5).

That is, if the probability density function of a certain amount of exposure is f(x), the probability density of the probability density function f(y) of a certain defocus amount will be the product of f(x) and f(y). Come to give. Here, it is assumed that the amount of exposure of the light-emitting device for processing a product is, for example, 1.5%, and the defocus parameter is, for example, 0.18%. Then, the probability density is obtained, the product of each probability density is obtained, and then a certain amount of light and dispersion are obtained. The probability density at the time of the amount of focus. Then, an example of the result of calculating the probability density by considering the processing unevenness and the assembly unevenness is shown in Table 2 above. The function shown in Fig. 8 is a function indicating the yield of the product, the horizontal axis indicates the pattern after the transfer of a certain pattern (for example, the line width), and the vertical axis indicates the yield by the number of errors.

On the other hand, as shown in the foregoing Table 3, the line width of the pattern when the exposure is performed by the combination of the amount of each of the exposure amount and the defocus amount is calculated, and the yield evaluation value corresponding to the line width and the predetermined yield are determined. The threshold value of the evaluation value is compared to extract the pattern.

In the fourth embodiment, the pattern having a defect probability of less than 0.1% is used. , take it out. Then, the proximity effect correction and the proximity effect correction after the offline of the extracted pattern are performed under the condition of mitigation, or the processing of the proximity effect correction and the proximity effect correction verification has been completed.

The optical conditions of the transfer simulation of the proximity effect correction and the design rule check and the process margin check are set as an exposure wavelength of 193 nm, NA = 0.75, σ = 0.85, and 2/3 of the wheel. On the other hand, the amount of exposure was 13.5 mJ, and the center portion was changed stepwise every 0.5 mJ, and the defocus amount was calculated in the range of ±0.2 μm in steps of 0.05 μm. Further, the setting values of the doping amount and the focusing condition are regarded as the target value by the line segment and the interval of 100 nm.

Moreover, although the process flow after the offline process includes the proximity effect correction process, the proximity effect correction engineering system may or may not be applied. Moreover, the proximity condition correction, the process margin check at the time of design rule check, and the optical condition of the proximity effect correction and the mitigation condition of the proximity effect correction can be changed according to the layout to be processed.

Further, in the fourth embodiment, the variation of the exposure device is assumed, and the difference function is assumed to calculate the probability density, and the yield evaluation value is calculated using the convolution integral with the actual measurement value, but it is also possible to simply calculate the respective values. The probability density is stepwise to the function. If the yield is 100%, the multiplication is 1. If the yield is 0%, the multiplication is 0, which is used as the yield evaluation value. The function of stending, staggered, and measured values can be used to make various settings.

Moreover, the range of variation of the amount of dew and the amount of defocus shown in Table 3 is not limited to the range described.

Proximity effect correction, process margin check and proximity effect of the fourth embodiment The gradual conditions for the correction of the optical conditions and the correction of the proximity effect should be corrected at the beginning of the product planning period, and until the process conditions are mature, it can be adapted to various conditions. Even when the processing of the fourth embodiment is performed, the processing priority can be given in consideration of electrical characteristics.

That is to say, the part of the circuit corresponding to the critical path must be subjected to transfer simulation, and the other areas are usually verified.

Further, the rule library can be obtained in the same manner as in the second embodiment.

As described above, in the fourth embodiment, the second entity layout is extracted, and the rule of the second entity layout is added to the rule library, whereby the condition of the light proximity effect correction can be alleviated, or the light micro-mode can be alleviated. The condition of the shadow verification, or the condition for correcting the optical proximity effect, and excluding the object of photolithographic verification, or eliminating the correction of the optical proximity effect, and alleviating the condition of photolithography verification, or eliminating the correction of the optical proximity effect and Any of the above matters other than the object of photolithography verification is possible, whereby the design time of the semiconductor integrated circuit can be shortened.

In the design method of the semiconductor integrated circuit of the fourth embodiment, the design rule inspection process after the component placement wiring process is performed on the full wafer scale, and the marginal pattern is the condition for verifying the proximity effect correction or the proximity effect correction. It is moderated or excluded from the verification object. Therefore, it is not necessary to use the proximity effect correction and photolithography verification work performed before the pattern comparison library and database creation. The verifier is excluded from the processing flow, whereby the efficiency of the processing can be improved.

Moreover, if the verification object is omitted from the database or the library, the pattern with the margin will be extracted, so the pattern is only regarded as the usual processing object.

Therefore, since the layout is screened using the yield evaluation value, all the processing is judged from the viewpoint of yield, even if the process margin is small, as long as the yield can be obtained, since it can be judged as such, it is different. In view of the above, it is possible to improve the efficiency and simplification of the entire design process without reducing the deterioration of the screening accuracy.

Further, in the fourth embodiment, the rule for layout extraction is created based on the result of the transfer simulation, and the rule is used to select the layout of the object, and then the judgment of the yield evaluation value is performed, but the rule of the rule is The screening is not necessary, and the yield evaluation value can be directly used for screening. This point is explained as follows in the fifth embodiment corresponding to the embodiment of the application 21.

In the method of designing a semiconductor integrated circuit for realizing the physical layout of the semiconductor integrated circuit by using the semiconductor integrated circuit design data, the above-mentioned "component arrangement wiring project" is performed, and the design is not performed as described above. "Rules inspection project", but refer to "the threshold for yield" of the layout of the second entity containing the part of the physical layout component, and directly compare the information about the yield of the second entity layout to perform such good Rate evaluation project. In the "benefit evaluation project", when the information about the yield is the threshold value for the yield, the "layout extraction project" is used to extract the physical layout of the object to be determined. Then, for the physical layout obtained in the "Layout Extraction Project", in "Revision. Verification Project" , the proximity effect correction, the proximity effect correction verification.

On the other hand, in the "Benefit Evaluation Project", when the information on the yield is not satisfied with the threshold value of the yield, in the "correction project", the field in which the yield is less than or equal to the threshold is performed. The acquisition of the transfer information, the correction of the second entity layout in the field, and the original image processing. Then, in the "Revision and Verification Project", the second entity layout of the "correction project" is verified by the proximity effect correction and the proximity effect correction. Then, in the "Photomask data creation project", the second entity layout in which the "correction and verification project" was performed was used to create the mask material.

Further, the rule library can be obtained in the same manner as in the second embodiment.

According to the design method of the semiconductor integrated circuit of the present invention according to the fifth embodiment, the yield evaluation project is referred to the threshold of the second entity layout regarding the yield, and the layout of the second entity The information on the yield is also referred to as "the threshold for the yield", so that the design time of the semiconductor integrated circuit can be shortened.

Moreover, although the previous pattern alignment is basically a comparison process of the two-dimensional graphics, the processing load is less likely to occur, but the design rule check in each of the embodiments described above is the same graphical calculation as the mask data processing. The processing is therefore less effective in processing compared to the previous pattern alignment, and therefore has the advantage of increasing the processing speed.

The design method of each of the semiconductor integrated circuits of the first embodiment, the second embodiment, the third embodiment, the fourth embodiment, and the fifth embodiment is applicable to the design of the semiconductor integrated circuit design data. Design method of semiconductor integrated circuit for generating physical layout of semiconductor integrated circuit Design device.

Moreover, it is applicable to a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by semiconductor integrated circuit design data is recorded.

It is also applicable to a reticle manufacturing method produced by a method of designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit.

S11‧‧‧ Component Configuration Wiring Engineering

S12‧‧‧Design rule inspection project

S13‧‧‧Revision and determination project

S14‧‧‧Mask making project

S16‧‧‧ Correction Project

S17‧‧‧ Proximity Effect Correction Project

S18‧‧‧Process margin verification project

S19‧‧‧Additional Engineering

S20‧‧‧ Amendment. Correction. Verification project

21‧‧‧Russary Library

1 is a flow chart showing an embodiment (first embodiment) of a method of designing a semiconductor integrated circuit of the present invention described in claim 1.

[Fig. 2] A layout layout of an example of the extracted pattern.

[Fig. 3] A flowchart of an embodiment (second embodiment) of a method of designing a semiconductor integrated circuit of the present invention described in claim 3.

[Fig. 4] A flow chart showing an example of design rule checking.

[Fig. 5] A flowchart of an embodiment (third embodiment) of a method of designing a semiconductor integrated circuit of the present invention described in claim 9.

Fig. 6 is a layout diagram of an example of a pattern extracted based on a slope and a coverage ratio.

[Fig. 7] A flowchart of an embodiment (fourth embodiment) of a method of designing a semiconductor integrated circuit of the present invention described in claim 13.

[Fig. 8] A graph showing the yield of a product, which is a graph showing the relationship between the pattern after the pattern transfer and the number of errors.

21‧‧‧Russary Library

Claims (29)

A method for designing a semiconductor integrated circuit is a method for designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit, and has a component layout wiring project. The components required to generate the pre-recorded entity layout are configured and wired; and the design rule inspection project refers to the rule library for design rule checking, and the shape of the second entity layout containing the components of the pre-recorded entity layout is added. Verification; and the first reticle data creation project, when the design rules are met in the current design rule inspection project, the second entity layout is used to create the reticle data corresponding to the layout of the predecessor entity; and the reticle data processing project In the current design rule inspection project, when the pre-requisite design rule is not satisfied, the reticle data processing of the second entity layout as the verification object is performed; and the second reticle data creation project is performed in the pre-record reticle data processing project. The second physical layout of the mask data processing to create a mask corresponding to the layout of the predecessor entity ; Note before engineering design rule checking, whether the braking system according to Cheng Yuyu design rules is determined whether the process has a range of patterns to be extracted. The semiconductor integrated circuit as recited in claim 1 The design method, wherein the pre-recorded reticle data processing engineering department has: a proximity effect correction project, which is a neighboring effect correction of the second entity layout; and a proximity effect correction verification project, which is the second to be corrected by the proximity effect. Physical layout, verified. A method for designing a semiconductor integrated circuit is a method for designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit, and is characterized in that: a component layout wiring project is provided. The components required to generate the pre-recorded entity layout are configured and wired; and the design rule inspection project refers to the rule library for design rule checking, and the shape of the second entity layout containing the components of the pre-recorded entity layout is added. Verification to determine whether the layout of the second entity before the process meets the process margin; and the correction decision project is to compare the layout of the second entity with the predetermined process margin specification before the design rule is met in the pre-design rule inspection project to determine whether The second entity layout with the margin is used to perform the proximity effect correction; and the first mask data creation project is used to determine the second entity layout that is determined to be unnecessary to be corrected when the current record is determined to be unnecessary. Corresponding to the layout of the pre-recorded entity; and correction works, Hutchison correction determination works judged to be supplemented, as before judgment target in mind for the second layout entity proximity effect up The second reticle data creation project is to use the second entity layout that has been corrected in the pre-remediation project to create the reticle data corresponding to the layout of the pre-recorded entity; and the proximity effect correction project, which is the current design rule check. When the pre-requisite design rules are not met in the project, the second entity layout, which is the verification object, is used to correct the proximity effect; and the process margin verification project is the second entity layout that has been corrected for the proximity effect in the predecessor proximity effect correction project. , to verify whether there is a certain process margin; and the rule addition project, when it is determined that there is a process margin in the current verification process, the second entity layout is determined as the object to be determined, and the second entity is laid out. The rule is added to the pre-reporting rule library, and the reticle data corresponding to the pre-recorded entity layout of the second entity layout is prepared; and the correction, correction, and verification engineering are determined when there is no process margin in the current recording process Then, pattern correction, artwork, proximity effect correction, and the second entity layout of the object to be determined are performed. Near-effect correction verification; and the third reticle data creation project, using the second entity layout of the pre-recording correction, correction, and verification project to create the reticle data corresponding to the layout of the pre-recorded entity; According to whether there is process margin to determine whether the design rules are met, the pattern of the process range will be drawn. Out. The method for designing a semiconductor integrated circuit according to the third aspect of the invention, wherein the layout creation project is configured as a first physical layout, wherein each component constituting the layout of the physical entity is arranged and wired; The printing information creation project is a simulation of applying the proximity effect correction to the first physical layout of the pre-recording to transfer the layout of the first physical entity to the semiconductor substrate, and then making the transfer information; and the pattern extraction project is based on the pre-recording transfer. The information is extracted from the pattern of the customized process margin as described in item 1 of the patent application scope of the first entity layout; and the rule creation project is applied for the patent application containing the pattern information of the first entity layout extracted from the previous record. The rules for the design rule inspection described in item 1 of the scope, and in the pre-report rule library, the rules that have been created are stored. The method for designing a semiconductor integrated circuit according to the fourth aspect of the patent application, wherein the pre-recording rule is a design rule relating to the pattern and the interval of the pattern included in the layout of the first entity, and the design rule for the pre-recording Add or subtract the rules of bias. The design method of the semiconductor integrated circuit according to the third aspect of the patent application, wherein the pre-correction determination project is used as a subsequent correction engineering system to determine whether to verify the proximity effect correction and the proximity effect correction. The design method of the semiconductor integrated circuit according to the fourth aspect of the invention, wherein the pre-recording extraction engineering system has a project for selecting a threshold value of a process margin in a second physical layout; and The limit value and the pre-recording transfer information and the pre-recording rule are used to extract the pattern of the pattern with the larger margin of the first entity layout; and the layout of the first entity extracted by the pre-recording to verify the layout of the second entity. A method for designing a semiconductor integrated circuit is a method for designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit, and is characterized in that: a component layout wiring project is provided. It is to configure and wire the components required to generate the layout of the pre-recorded entity; and to set the comparison of the image on the semiconductor substrate and the threshold of the coverage rate; and compare the inspection project to calculate the layout of the pre-recorded entity. And refer to the calculation result of the pre-recorded comparison of the pre-recording of the pre-recorded components, and compare the calculation results with the pre-comparison; and the correction project, the current calculation of the pre-comparison in the comparison inspection project is less than or equal to the pre-record For the case of the threshold value of the comparison, the acquisition of the transfer information in the field of less than or equal to the threshold value, the correction of the physical layout of the field, the original image processing, and the correction are performed. Verification project, the pre-record of the pre-revision project Body layout, correction of proximity effect, verification of proximity effect correction; and reticle data creation engineering, which is used before the correction. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check engineering, the calculation result of the comparison of the pre-recorded entity layout is larger than the pre-recorded comparison threshold, then refer to the pre-recorded entity layout. Regarding the threshold of the coverage rate, the information about the coverage rate of the previous entity layout is compared; and the layout extraction project is the current coverage coverage inspection project, and the information about the coverage rate satisfies the precaution of the coverage rate. When the value is used, the physical layout of the object to be determined is extracted, and the physical layout obtained by the pre-recording extraction project is corrected. After verifying the project after the project; in the current coverage rate check project, if the information about the coverage rate does not satisfy the pre-recorded threshold value of the coverage rate, the pre-recorded entity layout is corrected. Correction. Verify the project after the project; the information about the comparison is the first use of the light intensity of the optical image; in the pre-comparison inspection project, calculate the slope of the optical image for each edge of the pattern and calculate the pre-comparison. The pattern surrounded by the slope greater than the threshold value for the comparison of the previous note is extracted. The method for designing a semiconductor integrated circuit according to the eighth aspect of the invention, wherein the threshold value of the comparison is obtained by preliminarily evaluating the layout of the target generation or using an empirical value. A method for designing a semiconductor integrated circuit is a method for designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit, and is characterized in that: a component layout wiring project is provided. The components required to generate the pre-recorded entity layout are configured and wired; and the design rule checking project refers to the rule library for design rule checking to verify whether the second entity layout of the component containing the pre-recorded entity layout is With the predetermined process margin; and the correction judgment project, when there is a process margin in the current design rule inspection project, the second entity layout with margin is compared with the predetermined process margin specification to determine whether the predecessor has a margin. The second entity layout is corrected for the proximity effect; and the first mask data creation project is determined to be a second entity layout that is determined to be unnecessary to be corrected, and is created in accordance with the pre-record The reticle data of the physical layout; and the correction project, the current record is positively determined When it is judged that the correction is necessary, the second entity layout is recorded before the judgment object, and the proximity effect correction and the proximity effect correction verification are performed; and the second mask data creation project is performed, and the proximity effect correction is performed in the pre-remediation correction project. The second entity layout of the proximity effect correction verification is made to form the mask material corresponding to the layout of the predecessor entity; and the first correction. Verification project, when there is no process margin in the current design rule checking project, the second entity layout will be verified, and the proximity effect correction and proximity effect correction verification will be performed; The yield evaluation project is based on the pre-recorded second entity layout with respect to the yield threshold, and compares with the pre-recorded second entity layout on the yield information; and the rule addition project is the current record rate evaluation project. In the above, when the information about the yield meets the precautionary threshold of the yield, the layout of the second entity that is the object of judgment is extracted, and the rule of the layout of the second entity is added to the pre-reporting library. And the revision project, in the current record of the rate evaluation project, the information on the yield of the pre-recording does not meet the pre-recorded threshold of the yield, then the transfer information obtained in the field where the yield is less than or equal to the threshold , the correction of the second entity layout in the field, the original image processing; and the second correction. Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the third mask data creation project, the use of the previous record second correction. Verify the second entity layout of the project to create a reticle data; the pre-design rule check project is based on whether there is a process margin to determine whether the design rules are met, and the pattern with the process range is extracted. The method for designing a semiconductor integrated circuit according to claim 10, wherein the layout creation process is a first physical layout in which each component constituting the layout of the physical entity is arranged and wired; Printed information into a project, the Department of the first entity to the layout of the first entity The proximity effect is corrected to transfer the texture of the first entity layout onto the semiconductor substrate, and then the transfer information is created; and the pattern extraction process is based on the pre-recorded transfer information, which is larger than the pattern of the first physical layout of the previous physical layout. And the rule-making project is a rule for checking the pre-design rule that contains the pattern information of the layout of the first entity that has been extracted, and stores the created rule in the pre-report library. The method for designing a semiconductor integrated circuit according to claim 10, wherein the verification of the information on the yield of the second entity layout in the pre-recording rate evaluation project determines in advance the threshold of the yield. The value is then referred to the pre-recorded threshold for yield. For example, the design method of the semiconductor integrated circuit described in claim 10, wherein the information about the yield is given by considering the results of the following four: When P is a probability that X is continuous and X is in the interval a, b, it is assumed that f(x) given by the formula (1) is a probability density function, and a double variable function f(x, y) By The given probability density function given by the simultaneous density variable of the two-dimensional probability variable (X, Y); and the machining parameters, assembly variations, and experimental results. The method for designing a semiconductor integrated circuit according to claim 13, wherein the pre-recorded probability density function is a product of the exposure density and the probability density of the defocus amount of the exposure device of the second physical layout. Given. The method of designing a semiconductor integrated circuit according to claim 13, wherein the result of the preliminary test is the number of defects of the pattern after transfer on the semiconductor substrate. The design method of the semiconductor integrated circuit according to claim 11, wherein the pre-recording extraction engineering system has a project for selecting a threshold value of a process margin in a second physical layout; and 2 The physical layout of the process margin and the pre-recording transfer information and the pre-reporting rule library, extracting the pattern of the layout of the first entity layout with a large margin; refer to the layout of the first entity extracted by the pre-record, To verify the layout of the second entity. A method for designing a semiconductor integrated circuit is a method for designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit, and is characterized in that: The component configuration wiring project is to configure and wire the components required to generate the layout of the pre-recorded entity; and the yield evaluation project refers to the threshold of the second entity layout of the component containing the pre-recorded entity layout. To compare with the information on the yield of the second entity layout; and the layout extraction project, in the current record of the yield evaluation project, the information on the yield before the satisfaction meets the precautions on the yield threshold The physical layout of the object of judgment is extracted; and the first correction is made. Verification project, for the physical layout obtained in the pre-record layout extraction project, the proximity effect correction, the proximity effect correction verification; and the correction project, in the current record rate evaluation project, the information about the yield is not satisfied with the pre-record When the rate is limited, the transfer information obtained in the field where the yield is less than or equal to the threshold value, the correction of the second entity layout in the field, and the original image processing; and the second correction are performed. Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recorded second correction. Verify the second physical layout of the project to create the reticle data. A design device is a design device for designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, and is characterized by: The component configuration wiring means is used to configure and wire the components required for generating the layout of the pre-recorded entity; and the design rule checking means is used to refer to the rule function library for design rule checking, and the component is included before the layout of the pre-recorded entity The shape of the second physical layout is verified; and the first reticle data creation means is used to prepare the pre-recorded design rule in the design rule checking means, and to use the pre-recorded second physical layout to create a layout corresponding to the pre-recorded entity. The reticle data processing method and the reticle data processing means are used for processing the reticle data of the second entity layout as the verification object when the current design rule checking means does not satisfy the pre-recording design rule; and the second reticle data is created The method is configured to use the second physical layout of the reticle data processing method in the pre-recording reticle data processing method to create the reticle data corresponding to the layout of the pre-recorded entity; the pre-recording design rule checking means is used according to whether there is a manufacturing process Yu Yu came to determine whether the design rules were met and the pattern with the range of the process was extracted. A recording medium is a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data is recorded, and is characterized by a semiconductor product The design method of the body circuit has: a component configuration wiring project, which is configured and wired to generate components required for the layout of the pre-recorded entity; The design rule inspection project refers to the rule function library for design rule check, and verifies the shape of the second entity layout including the pre-recorded entity layout component; and the first mask data creation project, which is the current design rule When the pre-recording design rules are met in the inspection project, the second entity layout is used to create the reticle data corresponding to the layout of the pre-recorded entity; and the reticle data processing project is performed when the design rule inspection project does not satisfy the pre-design rules. The reticle data processing for verifying the second entity layout of the object; and the second reticle data creation project is performed by using the second physical layout of the reticle data processing in the reticle data processing project to correspond to the pre-recording entity The reticle data of the layout; the pre-requisite design rule inspection project determines whether the design rule is satisfied according to whether there is a process margin, and the pattern with the process range is extracted. A method of manufacturing a mask for a semiconductor integrated circuit is a mask manufacturing method produced by using a method of designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit. The feature is that the design method of the pre-recorded semiconductor integrated circuit includes: component configuration wiring engineering, which is to configure and wire the components required to generate the pre-recorded physical layout; and design rule inspection engineering, which refers to the rule letter for design rule inspection. Library, which will contain the second entity layout of the pre-recorded entity layout component Shape, verification; and the first reticle data creation project, when the design rules are met in the current design rule inspection project, the second entity layout is used to create the reticle data corresponding to the layout of the predecessor entity; and the reticle data processing In the current project design rule inspection project, when the pre-script design rule is not satisfied, the reticle data processing of the second entity layout as the verification object is performed; and the second reticle data creation project is used, and the reticle data processing project is used. The second physical layout of the reticle data processing is performed to create a reticle data corresponding to the layout of the pre-recorded entity; the pre-design rule checking engineering determines whether the design rule is satisfied according to whether there is a process margin, and there is a pattern of the process range. Take it out. A design device is a design device for designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, and is characterized in that: The component used to generate the pre-recorded entity layout is configured and wired; and the design rule checking means is used to refer to the rule library for design rule checking, and the second entity layout including the pre-recorded entity layout component The shape is verified to determine whether the layout of the second entity of the predecessor satisfies the process margin; and the means for correcting the judgment is used to check the pre-record design rule Before the design rule, the second entity layout is compared with the predetermined process margin specification to determine whether the second entity layout with the margin has a margin for the proximity effect correction; and the first mask data creation means is used for the current record. When it is determined that the correction determination means does not need to be corrected, the second entity layout that is determined to be unnecessary to be corrected is used to create the mask data corresponding to the layout of the pre-recorded entity; and the correction means is used to determine that the current compensation positive determination means is When correction is required, the proximity effect correction is performed on the layout of the second entity before the determination object; and the second mask data creation means is used to create the second entity layout corrected by the pre-correction means. The reticle data of the pre-recorded entity layout; and the neighboring effect correction means are used to check the second entity layout as the verification object when the pre-reporting design rule is not met in the current design rule checking means, and to perform the proximity effect correction; and the process margin The verification means is used to apply the second entity cloth to the neighboring effect correction method in the pre-recording proximity effect correction means. And verifying whether there is a certain process margin; and the rule appending means is used to determine that there is a process margin in the current process margin verification means, and then extracting the second entity layout as the object to be determined, the second entity The rules of the layout are added to the pre-reported rule library, and the reticle data corresponding to the pre-recorded entity layout of the second entity layout is prepared; and the correction, correction, and verification means are used to verify the current process margin. When it is determined that there is no process margin in the means, the pattern correction, the artwork, the proximity effect correction, the proximity effect correction verification of the second entity layout as the determination target, and the third mask data creation means are used. The second entity layout processed by the pre-recording correction, correction, and verification means is used to create the mask material corresponding to the layout of the pre-recorded entity; the pre-design rule checking means is used to determine whether the design is satisfied according to whether there is a process margin. The rules will be drawn out of the pattern of the process range. A recording medium is a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data is recorded, and is characterized by a semiconductor product The design method of the body circuit is: a component configuration wiring project, which is to configure and wire the components required to generate the pre-recorded physical layout; and the design rule inspection project refers to the rule function library for design rule checking, which will contain the pre-record Before the physical layout, the shape of the second entity layout of the component is verified to determine whether the layout of the second entity of the predecessor satisfies the process margin; and the correction determination project is to check the layout of the second entity before the design rule is met in the pre-design rule. Performing a comparison with a predetermined process margin specification to determine whether to adjust the proximity of the second entity layout having the margin; and In the first reticle data creation project, when it is determined that the correction is not necessary in the current correction and determination process, the second entity layout that is determined to be unnecessary to be corrected is used to create the reticle data corresponding to the layout of the predecessor entity; When it is determined that the correction is necessary in the current correction positive judgment project, the proximity effect correction is performed on the second physical layout before the judgment object; and the second mask data creation project is the second correction in the correction history project. The physical layout is used to create the mask data corresponding to the layout of the predecessor entity; and the proximity effect correction project is the second entity layout of the verification object when the current design rule inspection project does not satisfy the prescript design rule, and the proximity effect is performed. Correction; and the process of the margin verification project, the second entity layout of the proximity effect correction in the pre-recorded proximity effect correction project, to verify whether there is a fixed process margin; and the rule addition project, which is determined in the current record process When there is a process margin, the second entity layout that is the object of judgment is extracted, and the 2 The rule of the physical layout is added to the pre-reporting rule library, and the reticle data corresponding to the pre-recorded entity layout of the second entity layout is prepared; and the correction, correction, and verification engineering are determined in the current recording process. When the process margin is exceeded, the pattern correction, the artwork, the proximity effect correction, and the proximity effect correction of the second entity layout as the determination target are performed; The third reticle data creation project uses the second entity layout of the pre-recording correction, correction, and verification project to create the reticle data corresponding to the layout of the pre-recorded entity; the pre-record design rule inspection project is based on whether there is a process margin. Determine whether the design rules are met, and the pattern with the process range will be extracted. A method of manufacturing a mask for a semiconductor integrated circuit is a mask manufacturing method produced by using a method of designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit. The design method of the pre-recorded semiconductor integrated circuit includes: component placement wiring engineering, which configures and wires the components required to generate the pre-recorded physical layout; and design rule inspection engineering, which refers to the rule letter for design rule inspection. The library will verify the shape of the second entity layout of the component with the pre-recorded entity layout to determine whether the second entity layout satisfies the process margin; and the correction decision engineering, which satisfies the pre-design rule in the design rule inspection project. The second entity layout is compared with the predetermined process margin specification to determine whether the second entity layout with the margin has a margin for the proximity effect correction; and the first mask data creation project is determined by the current record positive determination project. In order to avoid having to make corrections, the second record that is judged as not having to be corrected is used. Layout, made to correspond to the physical layout of the mask before the record information; and The correction project is the correction of the neighboring effect before the judgment object is determined to be required to be corrected in the current correction and judgment project; and the second mask data creation project is corrected in the pre-remediation project. The second entity layout is used to create a mask material corresponding to the layout of the predecessor entity; and the proximity effect correction project is the second entity layout of the verification object when the current design rule inspection project does not satisfy the prescript design rule. For the proximity effect correction; and the process margin verification project, the second entity layout for the proximity effect correction in the pre-recorded proximity effect correction project is verified to verify whether there is a certain process margin; and the rule addition project is the current record process margin verification. When it is determined that there is a process margin in the project, the second entity layout to be determined is extracted, and the rule of the second entity layout is added to the pre-reporting rule library, and a pre-record corresponding to the layout of the second entity is prepared. The reticle data of the physical layout; and the correction, correction, verification project, the current record process When it is determined that there is no process margin, the pattern correction, the artwork, the proximity effect correction, the proximity effect correction verification of the second entity layout as the determination target, and the third mask data creation project are used. Correction, correction, and verification of the second entity layout of the project to create a mask material corresponding to the layout of the predecessor entity; The pre-requisite design rule inspection project is based on whether there is a process margin to determine whether the design rules are met, and the pattern with the process range is extracted. A design device is a design device for designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, and is characterized in that: A means for configuring and wiring the components required to generate the layout of the pre-recorded entity; and means for setting the contrast of the image on the semiconductor substrate and the threshold of the coverage ratio; and comparing the inspection means for calculating the layout of the pre-recorded entity The comparison, and refer to the pre-comparison threshold value of the layout of the pre-recorded components, and compare with the calculation results of the previous comparison; and the correction means are used to compare the pre-records in the current comparison check method. When the calculated result is less than or equal to the pre-recorded threshold value, the acquisition of the transfer information in the field of less than or equal to the threshold value, the correction of the physical layout of the field, the original image processing, and the correction are performed. The verification means is used for the layout of the pre-recorded entity that has been processed by the pre-recognition means, and the proximity effect correction and the proximity effect correction verification; and the reticle data creation means are used to correct the use of the pre-record. The physical layout of the processing means to be processed into a mask material; and the coverage rate checking means are used in the current comparison check means, before When the calculation result of the comparison of the physical layout is greater than the pre-requisite threshold, the reference to the coverage ratio of the pre-existing entity layout is compared with the information about the coverage ratio of the physical layout extracted by the pre-record; The layout extraction means is used in the current coverage rate checking means. When the information about the coverage ratio satisfies the pre-requisites of the coverage rate, the physical layout of the determination target is extracted, and the pre-recording extraction means is used. The physical layout obtained, previously recorded. The means of verification is to be processed later; in the current coverage rate checking means, if the information about the coverage rate does not satisfy the pre-requisites of the coverage rate, the previous record is corrected. The verification means is used to process the layout of the pre-recorded entity; the information about the comparison is a one-time differentiation of the light intensity of the optical image; in the pre-comparison check method, the slope of the optical image is calculated for the edge of each pattern (slope) And the pre-comparison is calculated, and the pattern surrounded by the slope larger than the threshold value of the previous comparison is extracted. A recording medium is a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data is recorded, and is characterized by a semiconductor product The design method of the body circuit is provided with: component arrangement wiring engineering, which is to configure and wire the components required for generating the physical layout of the pre-recorded; and to add the threshold of the comparison and coverage of the image on the semiconductor substrate. For the set project; and the comparison check project, the comparison of the layout of the predecessor entity is calculated, and the calculation result of the pre-comparison comparison is compared with the layout of the pre-recorded components of the pre-recorded components, and compared with the calculation result of the previous comparison; The correction project is the case where the calculation result of the comparison in the comparison check inspection project is less than or equal to the pre-recorded threshold value, and the transfer information obtained in the field of the comparison value less than or equal to the threshold value is obtained, and the physical layout of the field is performed. Correction, original image processing; and correction. Verification project, the pre-recorded entity layout of the pre-revision correction project, the proximity effect correction, the proximity effect correction verification; and the reticle data creation project, the use of the pre-recording correction. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check engineering, the calculation result of the comparison of the pre-recorded entity layout is larger than the pre-recorded comparison threshold, then refer to the pre-recorded entity layout. Regarding the threshold of the coverage rate, compare with the information on the coverage rate of the physical layout of the pre-recorded entity; and the layout extraction project, which is the current coverage coverage inspection project, the information about the coverage rate meets the pre-recorded coverage rate. When the limit value is used, the physical layout of the object to be determined is extracted, and the physical layout obtained by the pre-recording extraction project is corrected. After verifying the project after the project; in the current record of the coverage rate inspection project, if the information about the coverage rate does not satisfy the pre-recorded threshold of the coverage rate, the pre-recording correction is made. Verify the project after the project; The information about the comparison is a one-time differentiation of the light intensity of the optical image. In the pre-comparison inspection project, the slope of the optical image is calculated for the edge of each pattern to calculate the pre-comparison, which will be greater than the comparison with the previous note. The pattern enclosed by the slope of the critical value is extracted. A method of manufacturing a mask for a semiconductor integrated circuit is a mask manufacturing method produced by using a method of designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit. The feature is that the design method of the pre-recorded semiconductor integrated circuit includes: component arrangement wiring engineering, which configures and wires the components required for generating the physical layout of the pre-recorded; and the comparison and coverage of the image on the semiconductor substrate The project for setting the limit value; and the comparison check project, which is to compare the layout of the pre-recorded entity, and refer to the threshold value of the comparison of the image on the semiconductor substrate in the layout of the pre-recorded components, and compare with the pre-record The calculation results are compared; and the correction project is the case where the calculation result of the comparison in the comparison check project is less than or equal to the pre-recorded threshold value, and the transfer information of the field less than or equal to the threshold value is compared. Acquire, correct the physical layout of the field, original image processing; and correction. Verification project, which is the pre-recorded entity layout of the pre-revision correction project, and the proximity effect correction and proximity effect correction verification; The reticle data is made into a project, which is used before the correction. Verify the physical layout of the project to create the reticle data; and the coverage rate inspection project, in the current comparison check engineering, the calculation result of the comparison of the pre-recorded entity layout is larger than the pre-recorded comparison threshold, then refer to the pre-recorded entity layout. Regarding the threshold of the coverage rate, the information about the coverage rate of the previous entity layout is compared; and the layout extraction project is the current coverage coverage inspection project, and the information about the coverage rate satisfies the precaution of the coverage rate. When the value is used, the physical layout of the object to be determined is extracted, and the physical layout obtained by the pre-recording extraction project is corrected. After verifying the project after the project; in the current record of the coverage rate inspection project, if the information about the coverage rate does not satisfy the pre-recorded threshold of the coverage rate, the pre-recording correction is made. Verify the project after the project; the information about the comparison is the first use of the light intensity of the optical image; in the pre-comparison inspection project, calculate the slope of the optical image for each edge of the pattern and calculate the pre-comparison. The pattern surrounded by the slope greater than the threshold value for the comparison of the previous note is extracted. A design device is a design device for designing a semiconductor integrated circuit for realizing a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data, and is characterized in that: Used to generate the pre-recorded entity layout The component is configured and wired; and the design rule checking means is used to refer to the rule library for checking the design rule to verify whether the second entity layout containing the part of the component before the layout of the pre-recorded entity has a predetermined process margin; And the correction determination means is used to compare the layout of the second physical entity having the margin with the predetermined process margin specification when there is a process margin in the current design rule checking means, to determine whether the second entity having the margin is provided. The layout is corrected by the proximity effect; and the first mask data creation means is used to determine the layout of the second entity that is determined to be unnecessary to be corrected, and is used to prepare the layout corresponding to the pre-recorded entity when the current compensation correction means determines that the correction is not necessary. The reticle data and the correction means are used to determine the need for correction in the current compensation positive determination means, and the second entity layout is recorded before the determination object, and the proximity effect correction and the proximity effect correction verification are performed; and the second light is performed; The method of making cover data is used to correct the proximity effect and the proximity effect in the method of using the pre-remediation method. Correct the second entity layout of the verification to create a mask material corresponding to the layout of the predecessor entity; and the first correction. The verification method is used to check the second entity layout of the object to be verified, and to verify the proximity effect and the proximity effect correction; and the yield evaluation method is used to refer to the pre-record 2 The physical layout of the threshold for the yield, and compared with the information on the yield of the second entity layout, and the rule addition means, used in the current record of the rate of evaluation, pre-record When the information on the yield meets the precautionary threshold of the yield, the layout of the second entity that is the object of judgment is extracted, and the rule of the layout of the second entity is added to the pre-reporting library; The means is used in the current rate evaluation means. If the information about the yield does not satisfy the prevailing margin of the yield, the transfer information of the field in which the yield is less than or equal to the threshold is obtained. Correction of the second entity layout in the field, original image processing; and second correction. The verification means is used to perform the proximity effect correction and the proximity effect correction verification on the second entity layout of the pre-recording correction means; and the third mask data creation means is used to use the second correction of the pre-record. The second entity layout processed by the verification means is used to create the mask data; the pre-design rule checking means is for determining whether the design rule is satisfied according to whether there is a process margin, and extracting the pattern having the process range. A recording medium is a recording medium in which a semiconductor integrated circuit design method for generating a physical layout of a semiconductor integrated circuit by using semiconductor integrated circuit design data is recorded, and is characterized by a semiconductor product The design method of the body circuit is: a component configuration wiring project, which is to configure and wire the components required to generate the pre-recorded physical layout; and the design rule inspection project refers to the rule letter for design rule inspection. The library, verifying whether the second entity layout containing the part of the component before the layout of the pre-recorded entity has a predetermined process margin; and correcting the judgment project, which is the pre-record of the margin when there is a process margin in the current design rule inspection project. 2 The physical layout is compared with the predetermined process margin specification to determine whether the second entity layout with the margin has a margin for the proximity effect correction; and the first mask data creation project is determined to be unnecessary in the current compensation positive determination project. When the pre-recording is judged as the second physical layout that is not necessary to be corrected, the reticle data corresponding to the layout of the pre-recorded entity is created; and the correction engineering is determined as the object to be judged when it is determined that the correction is necessary in the current punctuality determination project. Preface 2nd entity layout, verification of proximity effect correction, proximity effect correction; and 2nd reticle data creation project, using the second entity layout in which the proximity effect correction and the proximity effect correction are performed in the pre-remediation correction project to make a correspondence The mask material in the layout of the physical record; and the first correction. Verification project, when there is no process margin in the current design rule check project, it will be the second entity layout of the verification object, and the proximity effect correction and proximity effect correction verification; and the yield evaluation project refer to the layout of the second entity. Regarding the threshold of the yield, and comparing with the information on the yield of the second entity layout, and the rule addition project, in the current record rate evaluation project, the information about the yield before the satisfaction meets the pre-record on the yield. When the threshold is reached, the layout of the second entity that is the object of judgment is extracted, and the layout of the second entity is laid. Then, add to the pre-reporting rule library; and the revision project, in the current record of the rate evaluation project, if the information about the yield does not satisfy the pre-recorded threshold of the yield, then the pre-recording yield is less than or equal to the threshold. The acquisition of transfer information in the field of value, the revision of the second entity layout in the field, the original image processing; and the second correction. Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the third mask data creation project, the use of the previous record second correction. Verify the second entity layout of the project to create a reticle data; the pre-design rule check project is based on whether there is a process margin to determine whether the design rules are met, and the pattern with the process range is extracted. A method of manufacturing a mask for a semiconductor integrated circuit is a mask manufacturing method produced by using a method of designing a semiconductor integrated circuit when a semiconductor integrated circuit design data is used to generate a physical layout of a semiconductor integrated circuit. The design method of the pre-recorded semiconductor integrated circuit includes: component placement wiring engineering, which configures and wires the components required to generate the pre-recorded physical layout; and design rule inspection engineering, which refers to the rule letter for design rule inspection. a library that verifies whether the second entity layout containing the part of the component before the layout of the pre-recorded entity has a predetermined process margin; and the correction determination project is a process in the current design rule inspection project. In the case of Yu Yu, the second entity layout with margins is compared with the predetermined process margin specification to determine whether to adjust the proximity of the second entity layout with the margin; and the first mask data creation project is currently When it is determined that the correction is not necessary, the second entity layout that is determined to be unnecessary to be corrected is used to create the mask data corresponding to the layout of the predecessor entity; and the correction project is determined to be necessary in the current correction determination project. In the case of correction, the second entity layout is recorded before the judgment object, and the proximity effect correction and the proximity effect correction verification are performed; and the second mask data creation project is performed, and the proximity effect correction and the proximity effect correction are performed in the pre-remediation correction project. The second entity layout, to create a mask material corresponding to the layout of the predecessor entity; and the first correction. Verification project, when there is no process margin in the current design rule check project, it will be the second entity layout of the verification object, and the proximity effect correction and proximity effect correction verification; and the yield evaluation project refer to the layout of the second entity. Regarding the threshold of the yield, and comparing with the information on the yield of the second entity layout, and the rule addition project, in the current record rate evaluation project, the information about the yield before the satisfaction meets the pre-record on the yield. When the threshold is reached, the second entity layout that is the object of judgment is extracted, and the rule of the second entity layout is added to the pre-reporting rule library; and the correction project is in the current rate evaluation project. If the information about the yield does not satisfy the pre-requisites of the yield, the pre-recording rate is Acquisition of transfer information in the field of less than or equal to the threshold, correction of the layout of the second entity in the field, processing of the original image; and second correction. Verification project, the second entity layout of the pre-recording correction project, the proximity effect correction, the proximity effect correction verification; and the third mask data creation project, the use of the previous record second correction. Verify the second entity layout of the project to create a reticle data; the pre-design rule check project is based on whether there is a process margin to determine whether the design rules are met, and the pattern with the process range is extracted.