TWI383227B - Liquid crystal display panel and pixel structure thereof - Google Patents

Description

Liquid crystal display panel and its pixel structure

The present invention relates to a display panel and a pixel structure thereof, and more particularly to a liquid crystal display panel and a pixel structure thereof.

The liquid crystal display panel is one of the currently common display panels, and has become more and more popular because of its high resolution, light weight, thin thickness, and low power consumption. At present, the common liquid crystal display panel has a twisted nematic (TN) type liquid crystal display panel, a multi-Domain Vertically Aligned (MVA) type liquid crystal display panel, and an In-Plane Switching (IPS) switch. Liquid crystal display panel and Fringe-Field Switching (FFS) type liquid crystal display panel.

Please refer to FIG. 1 and FIG. 2 simultaneously, which is a schematic cross-sectional view of a Twisted Nematic (TN) type liquid crystal display panel, and FIG. 2 is a top view of the pixel structure of FIG. The liquid crystal display panel 1 includes a thin film transistor substrate 11, a color filter substrate 12, and a liquid crystal layer 13. The thin film transistor substrate 11 is provided to face the color filter substrate 12, and the liquid crystal layer 13 is provided between the thin film transistor substrate 11 and the color filter substrate 12. The thin film transistor substrate 11 includes a substrate 111 and a pixel electrode 112. The color filter substrate 12 includes a substrate 121, a color filter 122, and a common electrode 123. The pixel structure 10 is located between two adjacent scan lines SL _n , SL _{n + 1} and two adjacent data lines DL _n , DL _{n + 1} , and the pixel structure 10 includes a thin film transistor T and a pixel. The electrode 112 and a storage electrode 14. The thin film transistor T is used to control the rotation of the liquid crystal molecules of the pixel structure 10.

Please refer to FIG. 2 and FIG. 3 at the same time. FIG. 3 is an equivalent circuit diagram of the pixel structure 10 of FIG. Herein, the liquid crystal capacitor C _{L C} is defined by the corresponding arrangement of the pixel electrode 112 and the common electrode 123; the storage capacitor C _{s t} is defined by the corresponding arrangement of the storage electrode 14 and the pixel electrode 112. The pixel electrode 112 is electrically connected to the corresponding one of the data lines DL _n and the scan lines SL _{n + 1} through the thin film transistor T.

Referring to FIG. 2 to FIG. 4 again, FIG. 4 is a timing diagram of the scan line SL _{n + 1} and the node V _P in FIG. First, when the scan line SL _{n + 1} inputs a signal to the pixel electrode 112, the thin film transistor T is turned on, and a positive pixel data is input via the data line DL _n such that the potential of the node V _P is V ₁ . When the scan line SL _{n + 1} stops inputting the signal to the pixel electrode 112, the thin film transistor T is momentarily turned off, at which time the parasitic capacitance effect is generated by the gate and the drain of the thin film transistor T, so that the node V _{P is} subjected to the feedthrough ( The effect of the feed through) effect is V ₂ . Then, when the next picture time comes, the scan line SL _{n + 1} inputs the signal again to turn on the thin film transistor T, and inputs a negative pixel data through the data line DL _n , so that the potential of the node V _P becomes V _{3 .} . When the scanning line SL _{n + 1} stops inputting the signal, the thin film transistor T is momentarily turned off, and similarly, the potential of the node V _P is affected by the feedthrough effect, and its potential is V ₄ . It is to be noted that the level of the common voltage V _{c o m} of the common electrode 123 also changes with respect to the change in the potential of the V _P .

According to the above, when the brightness and color of the liquid crystal display panel 1 are adjusted, the voltage of the common electrode 123 is usually set to a fixed voltage, and then the pixel structure 10 of a specific position is used as a reference to control the pixel structure. The voltage of the 10 middle pixel 112 (ie, the voltage value of the node V _P ) causes the liquid crystal molecules to be deflected by the influence of the voltage difference between the pixel electrode 112 and the common electrode 123, thereby causing the brightness of the liquid crystal display panel 1 to change. .

However, when the above method is used, both the pixel electrode 112 and the common electrode 123 are attenuated by signals, so that the common voltage V _{c o m} level in the pixel structure 10 at different positions may vary. As a result, the brightness and color of each pixel structure 10 in the liquid crystal display panel 1 cannot achieve the desired effect, and the liquid crystal display panel 1 is liable to cause flickering problems, and the liquid crystal molecules are more polarized for a long time. The generation of the image sticking phenomenon in the liquid crystal display panel 1 affects the quality and reliability of the liquid crystal display panel 1.

Therefore, how to provide a liquid crystal display panel and its pixel structure which can separately adjust the common voltage level of each pixel structure is one of the current important topics.

In view of the above problems, an object of the present invention is to provide a liquid crystal display panel and a pixel structure thereof which can individually control the common voltage level of each pixel structure.

In order to achieve the above object, a pixel structure according to the present invention is disposed on a first substrate and a second substrate, and a liquid crystal layer is disposed between the first substrate and the second substrate, and the first substrate is Opposite to the second substrate, the pixel structure comprises a first data line, a second data line, a scan line, a first electrode and a common electrode pattern, wherein the first data line and the second data line are substantially Parallelly disposed, the scan line intersects the first data line and the second data line, the first electrode is located between the first data line and the second data line, and the first electrode has at least a first pattern and at least a second The first pattern is electrically connected to the first data line and the scan line, and the second pattern is electrically connected to the second data line and the scan line respectively. The common electrode pattern is corresponding to the first electrode and located at the first data line. The first data line, the second data line, the scan line, and the first electrode are disposed on the first substrate, and the common electrode pattern is disposed on the second substrate.

In addition, in order to achieve the above object, a pixel structure according to the present invention is disposed on a first substrate and a second substrate, and a liquid crystal layer is disposed between the first substrate and the second substrate, and the first substrate is coupled to The second substrate is oppositely disposed. The pixel structure comprises a first data line, a second data line, a scan line and a first electrode. The first data line and the second data line are substantially parallel, and the scan line is And intersecting the first data line and the second data line, the first electrode is located between the first data line and the second data line, the first electrode has at least a first pattern and at least one second pattern, the first pattern and The second patterns are respectively comb-shaped and interlaced, and the first patterns are electrically connected to the first data lines and the scan lines, respectively, and the second patterns are electrically connected to the second data lines and the scan lines, respectively, wherein The data line, the second data line, the scan line and the first electrode are disposed on the first substrate.

Furthermore, in order to achieve the above object, a liquid crystal display panel according to the present invention comprises a first substrate, a second substrate, a plurality of pixel structures, and a liquid crystal layer, and the first substrate is disposed opposite to the second substrate, and the liquid crystal layer The pixel structure is disposed between the first substrate and the second substrate, and each of the pixel structures includes a first data line, a second data line, a scan line, a first electrode, and a common electrode pattern, and the first data line and the first data line The first electrode and the common electrode pattern are disposed between the first data line and the second data line, the first electrode is disposed corresponding to the common electrode pattern, and the first electrode has at least one first pattern And the at least one second pattern, the first pattern is electrically connected to the first data line and the scan line, respectively, and the second pattern is electrically connected to the second data line and the scan line, wherein the first data line and the second data line are respectively The scan line and the first electrode are disposed on the first substrate, and the common electrode pattern is disposed on the second substrate.

Moreover, in order to achieve the above object, a liquid crystal display panel according to the present invention comprises a first substrate, a second substrate, a plurality of pixel structures, and a liquid crystal layer, wherein the first substrate is disposed opposite to the second substrate, and the liquid crystal The layer is disposed between the first substrate and the second substrate, and each of the pixel structures includes a first data line, a second data line, a scan line, and a first electrode, and the first data line and the second data line The first electrode is disposed between the first data line and the second data line, and the first electrode has at least one first pattern and at least one second pattern, and the first pattern and the second pattern are respectively combed The first pattern is electrically connected to the first data line and the scan line, and the second pattern is electrically connected to the second data line and the scan line, wherein the first data line and the second data line are respectively connected The scan line and the first electrode are disposed on the first substrate.

According to the above, in the liquid crystal display panel and the pixel structure thereof, the first data line and the second data line are individually transmitted with different signals to the first pattern and the second pattern of the first electrode. Wherein, if the first electrode is a pixel electrode, the first pattern and the second pattern may separately form two different liquid crystal capacitors corresponding to one common electrode pattern, thereby respectively regulating the common voltage in each pixel structure. Level. Alternatively, if the first pattern is a pixel electrode pattern and the second pattern is a common electrode pattern, the first pattern and the second pattern may also use the individual voltage signals transmitted by the first data line and the second data line to control each picture. The common voltage level in the prime structure. Compared with the prior art, the present invention utilizes a pair of pixel electrode patterns and a common electrode pattern, so that each pixel structure can individually adjust the corresponding common voltage level, thereby improving brightness and color in the conventional liquid crystal display panel. The problem of deviation can further improve the quality and reliability of the liquid crystal display panel.

Hereinafter, a liquid crystal display panel and a pixel structure thereof according to a preferred embodiment of the present invention will be described with reference to the related drawings.

Please refer to FIG. 5, which is a cross-sectional view of a liquid crystal display panel 2 in accordance with a preferred embodiment of the present invention. The liquid crystal display panel 2 includes a first substrate 21, a second substrate 22, a liquid crystal layer 23, and a complex pixel structure (not shown). The first substrate 21 is disposed opposite to the second substrate 22, and the liquid crystal layer 23 is disposed between the first substrate 21 and the second substrate 22. The pixel structures are arranged in a matrix, and each pixel structure is disposed between two adjacent data lines and two adjacent scan lines. In addition, the liquid crystal display panel 2 can be a twisted nematic (TN) type liquid crystal display panel, a multi-region vertical alignment (MVA) type liquid crystal display panel, an optically compensated bend (OCB) type liquid crystal display panel, and an axis. An Axisymmetric Aligned (ASM) type liquid crystal display panel, a lateral electric field switching (IPS) type liquid crystal display panel or a fringe electric field switching (FFS) type liquid crystal display panel.

Referring to FIG. 5, FIG. 6, FIG. 7A, FIG. 7B and FIG. 8, FIG. 6 is a top view of a pixel structure 20 in the liquid crystal display panel 2, and FIG. 7A and FIG. 6 is a schematic view showing the structure of the A-A' and B-B' hatching lines, and FIG. 8 is a schematic plan view of the common electrode 221 of the pixel structure 20 in the liquid crystal display panel 2. In the present embodiment, the liquid crystal display panel 2 is exemplified by a twisted nematic (TN) type liquid crystal display panel. The pixel structure 20 is disposed on the first substrate 21 and the second substrate 22. The first substrate 21 is a glass substrate, and the second substrate 22 is another glass substrate.

As shown in FIG. 5 and FIG. 6 , the pixel structure 20 is provided with a first electrode 211 , a first data line DL ₁ , a second data line DL ₂ , and a first scan line SL ₁ on the first substrate 21 . And a second scan line SL ₂ , a first thin film transistor T ₁ , a second thin film transistor T _{2 ,} and a storage electrode 24 . The first data line DL ₁ and the second data line DL ₂ are substantially parallel, and the first electrode 211 is located between the first data line DL ₁ and the second data line DL ₂ . In addition, in the embodiment, the first electrode 211 is a pixel electrode.

The first electrode 211 has at least a first line pattern and a second pattern 211b 211a, 211a of the first pattern and the second pattern 211b disposed adjacent lines, the first pattern 211a and the first line via a thin film transistor T ₁ and the first The data line DL ₁ and the second scan line SL _{2 are} electrically connected, and the second pattern 211 b is electrically connected to the second data line DL ₂ and the second scan line SL ₂ via the second thin film transistor T ₂ . The first pattern 211a has a first potential, and the second pattern 211b has a second potential.

As can be seen from FIG. 6 , FIG. 7A and FIG. 7B , the first pattern 211 a is electrically connected to the drain D _{1 of the} first thin film transistor T ₁ by a first hole O ₁ , and the second pattern 211 b is connected by a first two holes ₂ O ₂ is electrically connected to the second thin film transistor T ₂ the drain D. The storage electrode 24 is disposed in parallel with the first scan line SL ₁ and the second scan line SL ₂ , and is electrically connected to the first pattern 211 a by a third hole O ₃ . The wiring pattern 25 is electrically connected to the second pattern 211b by the second hole O ₂ and electrically connected to the drain D _{2 of the} second thin film transistor T ₂ , and one part of the wiring pattern 25 is stored and stored. The electrodes 24 are correspondingly arranged.

As shown in FIG. 8 , the pixel structure 20 is provided with a common electrode pattern 221 on the second substrate 22 , and the common electrode pattern 221 is disposed corresponding to the first electrode 211 of the first substrate 21 and located on the first data line DL _{1 .} Between the second data line DL ₂ . The common electrode pattern 221 has a third potential, and the third potential is a coupling potential of the first potential of the first pattern 211a and the second potential of the second pattern 211b. In addition, the common electrode patterns 221 may be arranged in a line arrangement, a matrix arrangement, or a triangular arrangement, but are not limited thereto. In the present embodiment, the common electrode patterns 221 are arranged at intervals in a matrix arrangement.

Please refer to FIG. 6 and FIG. 9 at the same time, wherein FIG. 9 is an equivalent circuit diagram of the pixel structure 20 of FIG. Here, the storage capacitor C _{s t 1} is defined by the storage electrode 24 corresponding to the wiring pattern 25, in other words, since the storage electrode 24 is electrically connected to the first pattern 211a, the wiring pattern 25 and the second pattern 211b The electrical connection is such that the storage capacitor C _{s t 1} is formed between the first pattern 211a and the second pattern 211b of the first electrode 211. In addition, the first pattern 211a of the first electrode 211 and the common electrode pattern 221 form a first liquid crystal capacitor C _{L C a} , and the second pattern 211b of the first electrode 211 and the common electrode pattern 211 form a second liquid crystal capacitor C _{L C b} . The common voltage V _{c o m 1} is defined by the voltage of the common electrode pattern 221 . In addition, in this embodiment, the areas of the first pattern 211a and the second pattern 211b in the first electrode 211 may be the same or different, and therefore, the first formed by the first electrode 211 and the common electrode pattern 221 is adjusted. The values of the liquid crystal capacitor C _{L C a} and the second liquid crystal capacitor C _{L C b are} used to regulate the value of the common voltage V _{c o m 1} in each pixel structure 20.

Please refer to FIG. 7A, FIG. 7B, FIG. 9 and FIG. 10 , wherein FIG. 10 is the timing of the second scan line SL ₂ , the nodes V _{P a} , V _{P b} and the common voltage V _{c o m 1} in FIG. 9 . schematic diagram.

First, in the first picture time, when the second scan line SL ₂ inputs a signal to the first electrode 211, the first thin film transistor T ₁ and the second thin film transistor T _{2 are} turned on, and pass through the first data line. DL ₁ inputs a negative pixel data to the first pattern 211a of the first electrode 211, and the second data line DL ₂ inputs a positive pixel data to the second pattern 211b of the first electrode 211, so that the node The potentials of V _{P a} and V _{P b} and the common voltage V _{c o m 1} are V _{1 1} , V _{2 1} and V _{3 1 , respectively} . When the second scan line SL ₂ stops inputting the signal to the first electrode 211, the first thin film transistor T ₁ and the second thin film transistor T _{2 are} momentarily turned off, at which time the first thin film transistor T ₁ and the second thin film are electrically In the crystal T ₂ , the gates G ₁ and G ₂ and the drains D ₁ and D ₂ generate a parasitic capacitance effect, so that the nodes V _{P a} and V _{P b} are affected by the feedthrough effect, and the potentials thereof are V _{1 2} and V _{2 , respectively. 2} and the common voltage V _{c o m 1} is V _{3 2} .

Then, when the next screen time comes, the second scan line SL ₂ inputs the signal again to turn on the first thin film transistor T ₁ and the second thin film transistor T ₂ , and input a positive pixel through the first data line DL ₁ . The data is sent to the first pattern 211a of the first electrode 221, and the second data line DL _{2 is} input with a negative pixel data to the second pattern 211b of the first electrode 211, so that the nodes V _{P a} and V _{P b are} common to each other. The potentials of the voltage V _{c o m 1} are V _{1 3} , V _{2 3} and V _{3 1 , respectively} . When the second scan line SL ₂ stops inputting the signal to the first electrode 211, the first thin film transistor T ₁ and the second thin film transistor T _{2 are} momentarily turned off, at which time the first thin film transistor T ₁ and the second thin film are electrically In the crystal T ₂ , the gates G ₁ and G ₂ and the drains D ₁ and D ₂ generate a parasitic capacitance effect, so that the nodes V _{P a} and V _{P b} are affected by the feedthrough effect, and the potentials thereof are V _{1 4} and V _{2 , respectively. 4} and the common voltage V _{c o m 1} is V _{3 1} . In this way, the second scan line SL ₂ and the data lines DL ₁ and DL _{2 are} repeatedly coupled to the switches of the first thin film transistor T ₁ and the second thin film transistor T ₂ to perform data writing to the liquid crystal display panel 2 . action.

The present invention is a technique for separately transmitting different signals to the first pattern 211a and the second pattern 211b of the first electrode 211 by using the first data line DL ₁ and the second data line DL ₂ in the pixel structure 20, Further, the design in which the common electrode patterns 221 are spaced apart from each other is provided. Therefore, when adjusting the brightness and color of the liquid crystal display panel 2, different pixel data can be given to the pixel structure 20 at different positions to adjust the first pattern 211a and the second pattern of the first electrode 211 in each pixel structure 20. The first liquid crystal capacitor C _{L C a} and the second liquid crystal capacitor C _{L C b} formed by the common electrode pattern 211 and the common electrode pattern 211 enable the voltage value of the common voltage V _{c o m 1} to be individually controlled. In other words, each pixel structure 20 of the present invention can independently control each pixel structure 20 by regulating the pixel data input to the first pattern 211a and the second pattern 211b of the first electrode 211 or by using the area size thereof. The voltage of the common voltage V _{c o m 1} of the CCP enables the voltage value of the common voltage V _{c o m 1} in each pixel structure 20 to be individually controlled, thereby improving the brightness and color deviation in the conventional liquid crystal display panel 2. The problem can further improve the quality and reliability of the liquid crystal display panel 2.

Referring to FIG. 11 , FIG. 12 , FIG. 13A and FIG. 13B , FIG. 11 is a schematic cross-sectional view of another liquid crystal display panel 3 , and FIG. 12 is a schematic top view of a pixel structure 30 in the liquid crystal display panel 3 . 13A and 13B are schematic views showing the structure along the line C-C' and DD' of FIG. In the present embodiment, the liquid crystal display panel 3 is exemplified by a lateral electric field switching (IPS) type liquid crystal display panel.

As shown in FIG. 12, FIG. 13A and FIG. 13B, the pixel structure 30 is provided with a first electrode 311, a first data line DL ₁ ', a second data line DL ₂ ', and a first substrate 31. A scan line SL ₁ ', a second scan line SL ₂ ', a first thin film transistor T ₁ ', a second thin film transistor T ₂ ', and a storage electrode 34. The first data line DL ₁ ′, the second data line DL ₂ ′, the first scan line SL ₁ ′, the second scan line SL ₂ ′, the first thin film transistor T ₁ ′ and the second in the embodiment The thin film transistor T ₂ ′ is the first data line DL ₁ , the second data line DL ₂ , the first scan line SL ₁ , the second scan line SL ₂ , the first thin film transistor T ₁ and the first embodiment described in the previous embodiment. The second thin film transistor T ₂ , its function, structure and arrangement relationship have been described in the previous embodiments, and will not be described herein.

Different from the first embodiment, the first electrode 311 has at least one first pattern 311a and a second pattern 311b, and the first pattern 311a and the second pattern 311b are comb-like and interlaced with each other. Settings. Wherein the first pattern 311a through the first thin-film crystal-based T ₁ SL ₂ 'is electrically connected to the second pattern 311b via the second thin film transistor-based T _2' 'and the first data line DL _1' and a second scan line It is electrically connected to the second data line DL ₂ ′ and the second scan line SL ₂ ′. In addition, the drain D ₁ ' of the first thin film transistor T ₁ ' is electrically connected to the first pattern 311 a by a first hole O ₁ ', and the drain D ₂ ' of the second thin film transistor T ₂ ' The second pattern O ₂ ′ is electrically connected to the second pattern 311 b . In this embodiment, the first pattern 311a of the first electrode 311 is a pixel electrode pattern, the second pattern 311b is a common electrode pattern, and the common electrode pattern has a common potential, and the common potential is The potential of the second data line DL ₂ ' is provided.

In addition, the storage electrode 34 is disposed in parallel with the first scan line SL ₁ ′ and the second scan line SL ₂ ′, and the storage electrode 34 is electrically connected to the first pattern 311 a by a third hole O ₃ ′. A wiring pattern 35 is electrically connected to the second pattern 311b by the second hole O ₂ ′ and electrically connected to the drain D ₂ ′ of the second thin film transistor T ₂ ′, and a part of the wiring pattern 35 is The storage electrode 34 is correspondingly disposed.

Please refer to FIG. 12 and FIG. 14 , wherein FIG. 14 is an equivalent circuit diagram of the pixel structure 30 of FIG. 12 . Here, the storage capacitor C _{s t 1} ' is defined by the corresponding arrangement of the storage electrode 34 and the wiring pattern 35. In other words, since the storage electrode 34 is electrically connected to the first pattern 311a, the wiring pattern 35 and the second pattern are The 311b is electrically connected, so that the storage capacitor C _{s t 1} ' is formed between the first pattern 311a and the second pattern 311b of the first electrode 311. In addition, the first pattern 311a and the second pattern 311b of the first electrode 311 form a liquid crystal capacitor C _{L C} '. The common voltage is defined by the voltage difference between the first pattern 311 a and the second pattern 311 b in the first electrode 311 . In addition, in this embodiment, the areas of the first pattern 311a and the second pattern 311b in the first electrode 311 may be the same or different, thereby adjusting the common voltage value in each pixel structure 30.

In summary, in the liquid crystal display panel and the pixel structure thereof according to the present invention, different signals are individually transmitted from the first data line and the second data line to the first pattern and the second pattern of the first electrode. Wherein, if the first electrode is a pixel electrode, the first pattern and the second pattern may separately form two different liquid crystal capacitors corresponding to one common electrode pattern, thereby respectively regulating the common voltage in each pixel structure. Level. Alternatively, if the first pattern is a pixel electrode and the second pattern is a common electrode, the first pattern and the second pattern may also use the individual voltage signals transmitted by the first data line and the second data line to control each pixel structure. The common voltage level in the middle. Compared with the prior art, the present invention utilizes a pair of pixel electrode patterns and a common electrode pattern, so that each pixel structure can individually adjust the corresponding common voltage level, thereby improving brightness and color in the conventional liquid crystal display panel. The problem of deviation can further improve the quality and reliability of the liquid crystal display panel.

The above is intended to be illustrative only and not limiting. Any equivalent modifications or alterations to the spirit and scope of the invention are intended to be included in the scope of the appended claims.

1, 2, 3. . . LCD panel

10, 20, 30. . . Pixel structure

11. . . Thin film transistor substrate

111, 121. . . Substrate

112. . . Pixel electrode

12, 22, 32. . . Color filter substrate

122. . . Color filter

123. . . Common electrode

13, 23, 33. . . Liquid crystal layer

14, 24, 34. . . Storage electrode

21, 31. . . First substrate

211, 311. . . First electrode

211a, 311a. . . First pattern

211b, 311b. . . Second pattern

221. . . Common electrode pattern

22, 32. . . Second substrate

25, 35. . . Wiring pattern

C _{L C} , C _{L C a} , C _{L C b} , C _{L C} '. . . Liquid crystal capacitor

C _{s t} , C _{s t 1} , C _{s t 1} '. . . Storage capacitor

D ₁ , D ₂ , D ₁ ', D ₂ '. . . Bungee

DL _{n + 1} , DL _n , DL ₁ , DL ₂ , DL ₁ ', DL ₂ '. . . Data line

G ₁ , G ₂ , G ₁ ', G ₂ '. . . Gate

O ₁ , O ₂ , O ₃ , O ₁ ', O ₂ ', O ₃ '. . . Hole

S ₁ , S ₂ , S ₁ ', S ₂ '. . . Source

SL ₁ , SL ₂ , SL ₁ ', SL ₂ ', SL _n , SL _{n + 1} . . . Scanning line

T, T ₁ , T ₂ , T ₁ ', T ₂ '. . . Thin film transistor

V ₁ , V _{1 1} , V _{1 2} , V _{1 3} , V _{1 4} , V ₂ , V _{2 1} , V _{2 2} , V _{2 3} , V _{2 4} , V ₃ , V _{3 1} , V _{3 2} , V ₄ . . . Potential

V _{c o m} , V _{c o m 1} . . . Common voltage

V _P , V _{P a} , V _{P b} . . . node

1 is a schematic cross-sectional view of a conventional twisted nematic liquid crystal display panel; FIG. 2 is a top view of a pixel structure of FIG. 1; FIG. 3 is an equivalent circuit diagram of a pixel structure of FIG. 4 is a timing diagram of a scanning line and a node V _P in FIG. 3; FIG. 5 is a schematic cross-sectional view of a liquid crystal display panel according to a preferred embodiment of the present invention; FIG. 6 is a liquid crystal display according to a preferred embodiment of the present invention. A schematic plan view of one of the pixel structures in the panel; FIG. 7A is a schematic structural view taken along line A-A' in FIG. 6; FIG. 7B is a schematic structural view along a line B-B' in FIG. 6; FIG. FIG. 9 is a schematic diagram of an equivalent circuit diagram of the pixel structure in FIG. 6; FIG. 10 is a second scan line, node V _{P a in} FIG. one timing voltage V _E V _{P b} and the common electrode pattern is a schematic diagram; FIG. 11 cross-sectional schematic view showing one of the liquid crystal display panel according to another preferred embodiment of the present invention; FIG. 12 panel system to another pixel structure of the liquid crystal display A top view of the schematic; Figure 13A is taken along line C-C' in Figure 12 Schematic structural diagram; FIG. 13B schematic view showing one of 'cross-sectional view taken along line D-D in FIG. 12 structure; and FIG. 14 is a line equivalent circuit diagram of one pixel structure in FIG. 12.

20. . . Pixel structure

211. . . First electrode

211a. . . First pattern

211b. . . Second pattern

twenty four. . . Storage electrode

25. . . Wiring pattern

DL ₁ , DL ₂ . . . Data line

O ₁ , O ₂ , O ₃ . . . Hole

SL ₁ , SL ₂ . . . Scanning line

T ₁ , T ₂ . . . Thin film transistor

Claims (13)

A pixel structure is disposed on a first substrate and a second substrate, a liquid crystal layer is disposed between the first substrate and the second substrate, and the first substrate is disposed opposite to the second substrate, The pixel structure includes: a first data line; a second data line disposed substantially in parallel with the first data line; and a scan line intersecting the first data line and the second data line; a first electrode is disposed between the first data line and the second data line, the first electrode has at least a first pattern and at least one second pattern, wherein the first pattern is electrically connected to the first a data line and the scan line, the second pattern is electrically connected to the second data line and the scan line, respectively, the first data line, the second data line, the scan line and the first electrode system are disposed on On the first substrate, a common electrode pattern is disposed on the second substrate, and the common electrode pattern is disposed corresponding to the first electrode and located between the first data line and the second data line, where the The first pattern has a first potential, the second pattern a second potential, the common electrode pattern has a third potential, wherein the third potential is a coupling potential of the first potential and the second potential; a first thin film transistor is electrically connected to the first data a line and the first pattern; a second thin film transistor electrically connected to the second data line and the second pattern, wherein the first thin film transistor and the second thin film electromorphic system are disposed on the first substrate, wherein the first film The drain of the transistor is electrically connected to the first pattern through a first hole, and the drain of the second thin film transistor is electrically connected to the second pattern through a second hole. The pixel structure of claim 1, wherein the first electrode is a pixel electrode. The pixel structure of claim 1, wherein the first substrate is a glass substrate and the second substrate is another glass substrate. The pixel structure of claim 1, further comprising: a storage electrode disposed on the first substrate, the storage electrode being electrically connected to the first pattern. The pixel structure of claim 4, further comprising: a wiring pattern disposed on the first substrate, the wiring pattern being electrically connected to the anode of the second thin film transistor, and the The wiring pattern forms a storage capacitor with the storage electrode. The pixel structure of claim 5, wherein the storage electrode is electrically connected to the first pattern by a third hole, and the storage electrode is disposed opposite to the wiring pattern to form the storage capacitor. A liquid crystal display panel comprising: a first substrate; a second substrate disposed opposite to the first substrate; a plurality of pixel structures, each pixel structure comprising a first data line, a second data line, a scan line, a first electrode, a common electrode pattern, a first thin film transistor and a second thin film transistor The first data line and the second data line are disposed substantially in parallel. The first electrode and the common electrode pattern are located between the first data line and the second data line, and the first electrode is common to the first data line. Corresponding to the electrode pattern, the first electrode has at least one first pattern and at least one second pattern, the first pattern is electrically connected to the first data line and the scan line, respectively, and the second pattern is respectively electrically Connecting the second data line and the scan line, the first data line, the second data line, the scan line and the first electrode are disposed on the first substrate, and the common electrode pattern is disposed in the second On the substrate, the first pattern has a first potential, the second pattern has a second potential, and the common electrode pattern has a third potential, wherein the third potential is the first potential and the second potential Coupling potential The first thin film transistor is electrically connected to the first data line and the first pattern, and the second thin film transistor is electrically connected to the second data line and the second pattern, respectively, the first thin film transistor and the second thin film transistor The second thin film electro-crystal system is disposed on the first substrate, wherein the first thin film transistor is electrically connected to the first pattern through a first hole, and the second thin film transistor is connected to the first The second pattern is electrically connected to the second pattern; and a liquid crystal layer is disposed between the first substrate and the second substrate. The liquid crystal display panel of claim 7, wherein the first electrode is a pixel electrode. The liquid crystal display panel of claim 7, wherein the first substrate is a glass substrate and the second substrate is another glass substrate. The liquid crystal display panel of claim 7, wherein the pixel structure further comprises: a storage electrode disposed on the first substrate, the storage electrode being electrically connected to the first pattern. The liquid crystal display panel of claim 10, wherein the pixel structure further comprises: a wiring pattern disposed on the first substrate, the wiring pattern being electrically connected to the second thin film transistor The connection is made, and the wiring pattern forms a storage capacitor with the storage electrode. The liquid crystal display panel of claim 11, wherein the storage electrode is electrically connected to the first pattern by a third hole, and the storage electrode is disposed opposite to the wiring pattern to form the storage capacitor. The liquid crystal display panel of claim 7, wherein the liquid crystal display panel is a torsion type liquid crystal display panel, a multi-region vertical alignment type liquid crystal display panel, an optically compensated curved liquid crystal display panel or an axisymmetric arrangement type. LCD panel.