TWI381502B - Flat panel display and wafer bonding pad - Google Patents

Description

Flat panel display and wafer bonding pad

The present invention relates to a flat panel display and a wafer bond pad, and more particularly to a wafer bond pad having a flat display with signal transmission impedance matching each other and a low signal transmission impedance.

With the development of the information industry, the volume requirements for various types of displays are increasing in the market, and as a result, various displays are constantly becoming thinner. For example, flat panel displays such as liquid crystal displays and organic light-emitting displays have replaced traditional image tube displays as mainstream products of displays.

Figure 1A is a schematic diagram of a conventional flat panel display. Referring to FIG. 1A , the flat panel display 100 includes a display panel 110 , a plurality of flexible circuit boards 120 , a plurality of driving chips 130 , and a control circuit board 140 . The display panel 110 includes a display area A and a peripheral circuit area P. The driving chip 130 is disposed in the peripheral circuit region P. The driving chip 130 is electrically connected to the control circuit board 140 through the corresponding flexible circuit board 120.

As the size of the display panel 110 is larger and the resolution of the screen is higher, the number of driving wafers 130 required is also increasing. In order for all of the driver chips 130 to receive substantially the same level of ground signals or other signals such as power signals, the number of configurations of the flexible circuit board 120 is typically increased. At the same time, the length of the control circuit board 140 must also be lengthened so that all of the flexible circuit boards 120 can be connected to the control circuit board 140. Since the number of uses of the flexible circuit board 120 is increased, and the area of the control circuit board 140 is also increased, the material cost of the flat display 100 is increased.

Fig. 1B is a partial top view showing a region where the driving wafer of the display panel shown in Fig. 1A is located; Fig. 1C is a cross-sectional view taken along line I-I' of Fig. 1B. Referring to FIGS. 1A and 1B simultaneously, the display panel 100 further includes a plurality of wafer bonding pads 150 and 151 for connecting the driving wafer 130. When the driving wafer 130 is disposed on the display panel 110, the wafer bonding pad 150 is covered by the driving wafer 130.

Next, referring to FIG. 1B and FIG. 1C simultaneously, the wafer bonding pad 150 includes: a first conductor layer 152, a first dielectric layer 154, a second conductor layer 156, and a second dielectric layer 158 which are sequentially stacked. The third conductor layer 160. The first dielectric layer 154 has a plurality of first contact openings 154A. The second dielectric layer 158 has a plurality of second contact openings 158A and a plurality of third contact openings 158B. The second contact opening 158A corresponds to the first contact opening 158B to expose a portion of the first conductor layer 152, and the third contact opening 158B exposes a portion of the second conductor layer 156. In addition, the third conductor layer 160 covers a portion of the first conductor layer 152 exposed by the second dielectric layer 158 and the first contact opening 154A, and covers a portion of the second conductor exposed by the third contact opening 158B. On layer 156.

The first contact opening 154A and the third contact opening 158B are arranged in pairs, and the pair of contact openings (154A, 158B) are arranged side by side. Therefore, the signal transmission path between the conductor layers in the wafer bonding pad 150 has only a single direction. For example, when a signal is to be transmitted from the first conductor layer 152 to the second conductor layer 156, its signal will be transmitted in the direction D. Since the third conductor layer 160 is generally made of a transparent conductive material, such as indium tin oxide, it has a high transmission impedance.

The invention provides a flat panel display, which can solve the problem that the material cost of the flexible flat panel and the control circuit board is relatively large in the conventional flat panel display.

The invention further provides a wafer bonding pad which can solve the problem of high transmission impedance in the conventional wafer bonding pad.

The present invention provides a flat panel display comprising: a display panel, a flexible circuit board, a plurality of gate drive wafers, a plurality of first source drive wafers, a plurality of second source drive wafers, and a control circuit board. The control circuit board is electrically connected to the flexible circuit board. The display panel includes: a display area and a peripheral circuit area. The display panel has a plurality of first wires and a second wire in the peripheral circuit region, wherein one of the first wires or one of the second wires is a circuitous trace, that is, the first wire Or at least one of the second wires is a trace of the twist. The flexible circuit board electrically connects the first wire and the second wire, wherein the first wire and the second wire respectively extend from the lower side of the flexible circuit board to two opposite sides of the display panel. The gate driving chip is disposed in the peripheral circuit region and is electrically connected to one of the first wires. The first source driving chip is disposed in the peripheral circuit region, and is electrically connected to the flexible circuit board through another portion of the first wire. The second source driving chip is disposed in the peripheral circuit region and electrically connected to the flexible circuit board through the second wire.

In an embodiment of the invention, the flexible circuit board comprises: a first sub-FPC and a second sub-FPC. The first sub-flexible circuit board is electrically connected to the first source driving chip through the first wires, and the second sub-flexible electrical film is electrically connected to the second source driving chip through the second wires.

In one embodiment of the invention, the number of the first source drive wafers is equal to the number of second source drive wafers.

In one embodiment of the invention, the number of the first source drive wafers is different from the number of second source drive wafers.

In an embodiment of the invention, at least two of the first wires or the second wires are electrically insulated from each other.

In an embodiment of the invention, the first wire is a power signal transmission line or a ground signal transmission line.

In an embodiment of the invention, the first wire is a multilayer wire structure.

In an embodiment of the invention, the second wire is a power signal transmission line or a ground signal transmission line.

In an embodiment of the invention, the second wire is a multilayer wire structure.

In an embodiment of the invention, each of the first wires or the second wires has a chip bonding pad, and the die pad is located in one of the first source driving chips or one of the second sources. The pole drive is below the wafer. The die bond pad of each of the first wires includes a first conductor layer, a first dielectric layer, a first conductor layer, a second conductor layer, a second dielectric layer, and a third conductor layer. The first dielectric layer covers the first conductor layer, wherein the first dielectric layer has a plurality of first through holes. The second conductor layer is disposed on the first dielectric layer. The second dielectric layer covers the second conductor layer and the first dielectric layer, wherein the second dielectric layer has a plurality of alternately arranged second contact openings and third contact openings, and the second contact openings correspond to the first The openings are contacted, and the distance between each of the first contact openings and the adjacent two third openings is substantially equal. In addition, the third conductor layer covers the second dielectric layer, the second conductor layer exposed by the third contact opening, and the first conductor layer exposed by the first contact opening, wherein the first conductor layer passes through the third conductor layer Electrically connected to the second conductor layer.

In an embodiment of the invention, the first contact opening and the third contact opening of the wafer bonding pad are alternately arranged along a width direction of the first wire. The second conductor layer has, for example, a plurality of protrusions, and the third contact opening exposes a partial area of the protrusion, and each of the second contact openings is located between two adjacent protrusions. The material of the first conductor layer and the second conductor layer includes a metal, and the material of the third conductor layer includes a transparent conductive material.

In an embodiment of the invention, the display panel further has a plurality of third wires and fourth wires located in the peripheral circuit region, and each of the third wires is electrically connected to the two adjacent first source driving chips. And each of the fourth wires is electrically connected between the two adjacent second source driving chips.

In the flat panel display of the present invention, since the wire design structure using the trace of the winding is disposed between the flexible circuit board and the driving wafer, the transmission impedance of each of the wires can be individually adjusted to match each other. Therefore, the flat panel display of the present invention can utilize a relatively small number of flexible circuit boards to obtain the same level of power or ground signals for each of the drive wafers. In addition, the wafer bond pads of the present invention are designed by paralleling conductor layers to reduce transmission impedance and reduce the area of the wafer bond pads.

The above and other objects, features and advantages of the present invention will become more <RTIgt;

Fig. 2A is a view showing an embodiment of the liquid crystal display of the present invention. Referring to FIG. 2A, the flat panel display 200 includes a display panel 210, a flexible circuit board 220, a plurality of gate driving chips 230, a plurality of first source driving wafers 240, and a plurality of second source driving wafers 250. And a control circuit board 260. The control circuit board 260 is electrically connected to the flexible circuit board 220. The display panel 210 includes a display area A and a peripheral circuit area P. The gate driving chip 230, the first source driving wafer 240, and the second source driving wafer 250 are disposed in the peripheral circuit region P.

The display panel 210 has a plurality of first wires 212A and second wires 212B located in the peripheral circuit region P. The flexible circuit board 220 is electrically connected to the first wire 212A and the second wire 212B, wherein the first wire 212A and the second wire 212B respectively extend from the lower side of the flexible circuit board 220 to the opposite sides of the display panel 210. The gate driving chip 230 is electrically connected to a portion of the first wires 212A. The first source driving chip 240 is electrically connected to the flexible circuit board 220 through another portion of the first wires 212A. The second source driving chip 250 is electrically connected to the flexible circuit board 220 through the second wire 212B.

The display panel 210 further has a plurality of third wires 216A and fourth wires 216B located in the peripheral circuit region P, and each of the third wires 216A is electrically connected between the two adjacent first source driving wafers 240, and Each of the fourth wires 216B is electrically connected between the two adjacent second source driving wafers 250.

In a preferred embodiment, the flexible circuit board 220 of the present embodiment is located between the plurality of first source driving chips 240 and the plurality of second source driving chips 250, but is not limited thereto. At the same time, the first conductor 212A and the second conductor 212B connecting the first source driving wafer 240 and the second source driving wafer 250 are concentrated in this embodiment. Therefore, in the present embodiment, the control circuit board 260 does not need to be additionally increased in length in order to connect the flexible circuit board 220. In other words, the present embodiment helps to save the area and material cost required to control the circuit board 260, as well as reduce the amount and material cost required for the flexible circuit board 220.

In a preferred embodiment, when the display panel 210 performs display, the first source driving chip 240 and the second source driving chip 250 receive substantially the same level of power signal or ground signal to maintain Appropriate picture quality, but not limited to this. Therefore, the power signal or the ground signal sent by the driver on the control circuit board 260 must be transmitted in a corresponding transmission condition in each of the first wire 212A and the second wire 212B, and the degree of signal attenuation needs to be avoided. Impact. In other words, when the first wire 212A is a power signal transmission line or a ground signal transmission line, in a preferred embodiment, the signal transmission paths of the different first wires 212A should have similar or substantially the same transmission impedance, but Not limited to this. Similarly, when the second wire 212B is a power signal transmission line or a ground signal transmission line, in a preferred embodiment, the signal transmission paths of the different second wires 212B should have approximate or substantially the same transmission impedance, but Not limited to this. For embodiments in which different first conductors 212A or different second conductors 212B have similar or substantially identical transmission impedances, reference is made to FIG. 2B and related description.

Fig. 2B is a partial enlarged view of the peripheral line region of the display panel of Fig. 2A. In a peripheral line region P of the display panel 210, a portion of the first wires 212A or a portion of the second wires 212B is a circuitous trace, for example, two first lines labeled L1 and L2. Wire 212, but not limited to this. Such a design allows the signal transmission impedance of each of the first wires 212A to be compensated.

The display panel 210 is also provided with a plurality of wafer bond pads 214 for engaging the drive wafers (230, 240 or 250). These first leads 212A are connected to the wafer bond pads 214, respectively. In practice, one end of each of the first wires 212A is connected to the die bond pad 214, and the other end is connected to the underside of the flexible circuit board 220. Each of the first wires 212A and each of the second wires 212B has a different distance between the connected wafer bonding pads 214 and the flexible circuit board 220, but each of the first wires 212A is designed by a trace of the traces. The signal transmission path with each of the second wires 212B may have similar or substantially the same transmission impedance.

In this way, even if the power signal or the ground signal emitted by the driver on the control circuit board 260 is attenuated during the transmission, the first source driving chip 240 and each of the second source driving chips 250 can be received. Signals to substantially the same level. In a preferred embodiment, in this embodiment, a portion of the first conductive line 212A or a portion of the second conductive lines 212B is designed as a meandering trace, so each of the first conductive lines 212A and each of the second conductive lines The overall signal transmission impedance of 212B can be adjusted to match each other, but not limited to this. Under such a design, the line width of the first wire 212A and the second wire 212B can be adjusted without re-adjustment, which can help improve the yield of the wire process.

In another preferred embodiment, when the first wire 212A and the second wire 212B are formed, the line width can be adjusted according to the length of each line to make the transmission impedance of the first wire 212A and the second wire 212B. Match each other, but not limited to this. However, under such a design, the first wire 212A or the second wire 212B having a longer partial length of the wire has a line width wider than the first wire 212A or the second wire 212B having a shorter partial length of the wire, the former having Smaller or narrower line width.

In this embodiment, in a preferred embodiment, the number of the first source driving wafers 240 and the number of the second source driving wafers 250 may be equal, for example, four each, but not This is limited. In addition, the display panel 210 of FIG. 2A may be a liquid crystal display panel, a plasma display panel, or a flat display panel such as a laser display panel, and is not limited thereto. In a preferred embodiment, since the display panel 210 has various components composed of a plurality of conductor layers, such as a thin film transistor, a gate line or a data line, the first wire 212A and the second wire 212B can be utilized. These conductor layers are made, but are not limited thereto. That is, the first wire 212A and the second wire 212B may be a multi-layer wire structure which is the same material used for other components inside the display panel 210. When the first wire 212A and the second wire 212B are multi-layer wire structures, it also helps to increase the cross-sectional area of signal transmission to reduce the signal transmission impedance.

In a preferred embodiment, at least two of the first wires 212A or the second wires 212B are electrically insulated from each other, but are not limited thereto. When one or more of the first wires 212B and the second wires 212B transmit the same signal, but the transmission impedances are different, the driver transmitting the same signal may be correspondingly adjusted from the driver on the control circuit board 260. The strength of the signal of the two wires 212A and the second wire 212B. As such, the first source driving wafer 240 and the second source driving wafer 250 can receive signals of substantially the same level. When more than two of the first wires 212A transmit the same signal, but the transmission impedances are different, the intensity of the signal of the first wire 212A transmitting the same signal may be adjusted correspondingly from the driver on the control circuit board 260. As such, the first source drive wafer 240 can receive signals of substantially the same level. When two or more second wires 212B transmit the same signal but their transmission impedances are different, the intensity of the second wire 212B signal transmitting the same signal can be adjusted correspondingly from the driver on the control circuit board 260. As such, different second source drive wafers 250 can receive signals of substantially the same level. That is to say, at least two of the first wires 212A or the second wires 212B of the present invention are electrically insulated from each other, so that the transmission signals can be individually adjusted to make the flat display 200 have good display quality.

In a preferred embodiment, in order to further improve the signal transmission quality of the display panel 210 in the peripheral line region P, the present invention further provides a design of the wafer bonding pad 214, which is described below. 3A is a partially enlarged schematic view showing a region where a wafer bonding pad and a driving wafer are located according to an embodiment of the present invention; and FIG. 3B is a cross-sectional view taken along a line II-II' of FIG. 3A. Referring to FIG. 3A, the rectangular region S is the region where the driving wafer is located, and the wafer bonding pad 214 is also disposed in the rectangular region S. That is, the wafer bond pads 214 are substantially below a single first source drive wafer 240 or second source drive wafer 250. The wafer bonding pad 214 includes: a first conductor layer 310, a first dielectric layer 320, a second conductor layer 330, a second dielectric layer 340, and a third conductor layer 350; the wafer bonding pad 214 is disposed on a substrate (not labeled) on.

Referring to FIGS. 3A and 3B , the first dielectric layer 320 covers the first conductor layer 310 , and the first dielectric layer 320 has a plurality of first contact openings 322 . The second conductor layer 330 is disposed on the first dielectric layer 320. The second dielectric layer 340 covers the second conductive layer 330 and the first dielectric layer 320, and the second dielectric layer 340 has a plurality of alternately arranged second contact openings 342 and third contact openings 344, the second contact The opening 342 corresponds to the first contact opening 322, so the first contact opening 322 is actually also alternately arranged with the third contact opening 344. In a preferred embodiment, the distance between each of the first contact openings 322 and the adjacent two third contact openings 344 is substantially equal, but is not limited thereto.

In addition, the third conductor layer 350 covers the second conductor layer 330 exposed by the second dielectric layer 340, the third contact opening 344, and the first conductor layer 310 exposed by the first contact opening 322. The first conductor layer 310 can be electrically connected to the second conductor layer 330 through the third conductor layer 350. In a preferred embodiment, the material of the first conductor layer 310 and the second conductor layer 330 may include: an opaque metal such as aluminum, tantalum or molybdenum or an alloy thereof, and the material of the third conductor layer 350 may include: indium A transparent conductive material such as tin oxide or indium zinc oxide, but not limited thereto. For example, when the display panel 210 of FIG. 2A is a liquid crystal display panel, the conductive material layer of the display panel 210 includes: a scan line composed of a first conductor layer and a gate of the active device, and a data composed of the second conductor layer. The drain and source of the line and the active element, and the pixel electrode composed of the third conductor layer. Therefore, in a preferred embodiment, the die bond pads 214 can be fabricated using these layers of conductive material, but are not limited thereto.

Please continue to refer to FIG. 3A and FIG. 3B simultaneously. In the embodiment, the first contact opening 322 and the third contact opening 344 are alternately arranged along a predetermined direction. In the present embodiment, the first contact opening 322 and the third contact opening 344 are alternately arranged, for example, along the direction of the line II-II', and may be alternately arranged along the width direction of the wire 212. In a preferred embodiment, the die bond pad 214 is directly connected to the wire 212 (that is, the first wire 212A or the second wire 212B described above), but is not limited thereto. In addition, the second conductor layer 330 has a plurality of protrusions 332, and the third contact opening 344 exposes a partial area of the protrusion 332, and the first contact opening 322 or the second contact opening 342 is located between the two adjacent protrusions 332. .

The wafer bond pad 214 of the present embodiment, in a preferred embodiment, is alternately arranged with the exposed first conductive layer 310 and the exposed second conductive layer 330, and each of the first contact openings 322 is adjacent to the corresponding one. The distance between the two third contact openings 344 is substantially equal, but is not limited thereto. Therefore, in a preferred embodiment, when the signal of the first conductor layer 310 is transmitted to the second conductor layer 330, the signal can be transmitted along two paths at the same time, for example, the direction D1 and the direction D2, and the first exposed The conductor layer 310 is connected in parallel with the exposed second conductor layer 330, for example, through the third conductor layer 350, but is not limited thereto.

Compared with the die bond pad 150 of FIG. 1B, the signal can only be transmitted in one direction, and the signal transmission path between the first conductor layer 310 and the second conductor layer 330 of the embodiment has more aspects. For example, the transfer in two directions. Therefore, the wafer bonding pad 214 of the present embodiment is designed to help increase the signal transmission path between the first conductor layer 310 and the second conductor layer 330, so that the transmission impedance of the wafer bonding pad 214 can be reduced.

In addition, as can be seen from FIG. 3A, the area occupied by the die bond pad 214 in the rectangular region S is affected by the distribution of the first contact opening 322 and the third contact opening 344. The first contact opening 322 and the third contact opening 344 of the embodiment are alternately arranged in a predetermined direction instead of being paired and arranged side by side. Therefore, the wafer bond pad 214 disclosed in this embodiment can retain a large area in the center of the rectangular region S, and the other circuit wiring can be selectively disposed in the center of the rectangular region S. In other words, in addition to providing good signal transmission quality, the wafer bond pad 214 disclosed in this embodiment can more effectively save the layout area to improve the wiring elasticity or degree of freedom in the rectangular region S.

Figure 4 is a diagram showing another embodiment of the flat panel display of the present invention. The same component symbols in the flat panel display 400 as in the flat panel display 200 of FIG. 2A represent the same meaning and will not be further described herein. Referring to FIG. 4, the flexible circuit board 420 includes a first sub-FPC 422 and a second sub-FPC 424. The first sub-flexible circuit board 422 is electrically connected to the first source driving chip 240 through the first wire 212A, and the second sub-flexible film 424 is driven through the second wire 212B and the second source. 250 electrical connection.

In summary, the flat display device of the present invention concentrates the first wire and the second wire in the peripheral circuit region to reduce the required area of the control circuit board. Therefore, the flat display device of the present invention contributes to saving the material cost of the control circuit board. At the same time, the present invention also designates one of the first wires and one of the second wires as traces of the bypass so that the signal transmission impedances of the wires match each other. Therefore, the flat display device of the present invention has good signal transmission quality and good display quality. In addition, the wafer bonding pad proposed by the present invention can provide a smaller signal transmission path and can have a smaller configuration area. Therefore, the design of the wafer bond pad disposed on the flat display device also contributes to improving the signal transmission quality of the flat display device, and further makes the line layout of the flat display device more flexible.

Although the present invention has been disclosed in the above preferred embodiments, it is not intended to limit the present invention, and any one of ordinary skill in the art to which the present invention pertains may make some changes without departing from the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims.

100, 200, 400. . . Flat panel display

110, 210. . . Display panel

120, 220, 420. . . Flexible circuit board

130. . . Driver chip

140, 260. . . Control board

150, 151, 214. . . Wafer bond pad

152, 310. . . First conductor layer

154, 320. . . First dielectric layer

154A, 322. . . First contact opening

156, 330. . . Second conductor layer

158, 340. . . Second dielectric layer

158A, 342. . . Second contact opening

158B, 344. . . Third contact opening

160, 350. . . Third conductor layer

212. . . wire

212A, L1, L2. . . First wire

212B. . . Second wire

216A. . . Third wire

216B. . . Fourth wire

230. . . Gate driver chip

240. . . First source driver chip

250. . . Second source driver chip

422. . . First sub-flexible circuit board

424. . . Second sub-flexible circuit board

A. . . Display area

D, D1, D2. . . direction

I-I’, II-II’. . . Section line

P. . . Peripheral area

S. . . Rectangular area

Figure 1A is a schematic diagram of a conventional flat panel display.

Fig. 1B is a partial top view of the area where the driving wafer of the display panel of Fig. 1A is located.

Fig. 1C is a cross-sectional view taken along line I-I' of Fig. 1B.

2A is a liquid crystal display according to an embodiment of the present invention.

Fig. 2B is a partial enlarged view of the peripheral line region of the display panel in Fig. 2A.

FIG. 3A is a partially enlarged schematic view showing a region where a wafer bonding pad and a driving wafer are located according to an embodiment of the invention.

Fig. 3B is a cross-sectional view taken along line II-II' of Fig. 3A.

Figure 4 is a diagram showing another embodiment of the flat panel display of the present invention.

212A, L1, L2. . . First wire

212B. . . Second wire

214. . . Wafer bond pad

Claims (14)

A flat panel display comprising: a display panel having a display area, a peripheral circuit area, and a plurality of first wires and second wires in the peripheral circuit region; a flexible circuit board, and the first wires And the second wires are electrically connected, and the first wires and the second wires respectively extend from the lower side of the flexible circuit board to two opposite sides of the display panel; the plurality of first source drivers a chip disposed in the peripheral circuit region and electrically connected to the flexible circuit board through a portion of the first wires; a plurality of second source driving chips disposed in the peripheral circuit region and transmitting through the The second wires are electrically connected to the flexible circuit board; the plurality of gate driving chips are disposed in the peripheral circuit region and electrically connected to another portion of the first wires; and a control circuit board, The flexible circuit board is electrically connected to the flexible circuit board; wherein the flexible circuit board is located between the first source driving wafer and the second source driving wafers. The flat-panel display of claim 1, wherein the flexible circuit board comprises: a first sub-flexible circuit board, the portion of the first conductive line and the first source-driven wafer An electrical connection; and a second sub-flexible circuit board electrically connected to the second source driving chips through the second wires. A flat panel display according to claim 1, wherein the The number of the first source drive wafers is equal to the number of the second source drive wafers. The flat panel display of claim 1, wherein at least one of the first wires or the second wires is a meandering trace. The flat panel display of claim 1, wherein at least two of the first wires or the second wires are electrically insulated from each other. The flat panel display of claim 1, wherein the first wires or the second wires are power signal transmission lines or ground signal transmission lines. The flat panel display of claim 1, wherein the first wires or the second wires are multi-layer wire structures. The flat panel display of claim 1, further comprising a wafer bonding pad under the first source driving wafer or the second source driving wafer. The flat panel display of claim 8, wherein the wafer bonding pad comprises: a first conductor layer; a first dielectric layer overlying the first conductor layer and having a plurality of first contact openings a second conductor layer disposed on the first dielectric layer; a second dielectric layer overlying the second conductor layer and the first dielectric layer, having a plurality of second contact openings arranged alternately And a third contact opening, wherein the second contact openings correspond to the first contact openings; and a third conductor layer covering the second dielectric layer, the third contact opening The second conductor layer exposed by the port and the first conductor layer exposed by the first contact opening, wherein the first conductor layer is electrically connected to the second conductor layer through the third conductor layer. The flat panel display of claim 9, wherein the distance between each of the first contact openings and the adjacent two third contact openings is substantially equal. The flat-panel display of claim 9, wherein the first contact openings and the third contact openings are alternately arranged along a width direction of the first wires or the second wires. The flat-panel display of claim 9, wherein the second conductor layer has a plurality of protrusions, the third contact openings exposing a partial area of the protrusions, and each of the second contact openings is located Between two adjacent protrusions. The flat-panel display of claim 9, wherein the material of the first conductor layer and the second conductor layer comprises aluminum, tantalum, molybdenum or an alloy thereof, and the material of the third conductor layer comprises indium tin oxide or Indium zinc oxide. The flat panel display of claim 1, further comprising a plurality of third wires and fourth wires located in the peripheral circuit region, each of the third wires electrically connecting two adjacent first source drivers And each of the fourth wires is electrically connected to two adjacent second source driving chips.