1380586 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種適用於一源極驅動器之輸出緩衝 器，且特別是有關於一種適用於一源極驅動器之輸出緩衝 器及適用於一液晶顯示器之一源極驅動器。 【先前技術】 液晶顯示裝置較傳統顯示裝置來說，.具有較小、較薄 且耗電量少的優點。因此，液晶顯示裝置廣泛地應用於筆 記型電腦及手機等電子裝置上。液晶顯示裝置的源極驅動 器係用以轉換數位資料為類比資料，並且在一驅動週期 時，將類比資料經由輸出緩衝器送入晝素陣列中，而在非 驅動週期時，停止傳送類比資料。然而，在非驅動週期時， 輸出緩衝器之輸出節點係處於面阻抗（Hi-Z )狀態。短路 電流情形容易在高阻抗的狀態下產生，而使電路的溫度上 升，產生不良的後果。 因此，如何設計一個新的適用於一源極驅動器之輸出 緩衝器及適用於一液晶顯示器之一源極驅動器，以避免短 路電流的產生，乃為此以業界亟待解決的問題。 【發明内容】 因此，本發明之一態樣是在提供一種輸出緩衝器，係 用於源極驅動器，輸出緩衝器包含：輸入級及輸出級。輸 入級包含輸入節點，第一輸出端以及第二輸出端，其中輸 入節點自源極驅動器之數位類比轉換器接收類比資料。輸 4 1380586 出級包含：P型金氧半電晶體、N型金氧半電晶體、第一 開關及第二開關。P型金氧半電晶體包含閘極、連接至第 一供應電壓之源極以及連接至輸出節點之汲極；N型金氧 半電晶體包含閘極、連接至第二供應電壓之源極以及連接 至輸出節點之汲極；第一開關連接於P型金氧半電晶體之 閘極與第一輸出端之間；以及第二開關連接於P型金氧半 電晶體之閘極與第一供應電壓之間；其中第一及第二開關 接收閂鎖訊號，使當閂鎖訊號位於第一狀態時，第一開關 關閉且第二開關開啟，進一步使P型金氧半電晶體之閘極 接收第一供應電壓，俾關閉輸出級以防止短路電流情形產 生，而當閂鎖訊號位於第二狀態時，第一開關開啟且第二 開關關閉，俾開啟輸出級以傳送類比資料至輸出節點。 本發明之又一目的係在於提供一種源極驅動器，係用 於液晶顯示器，源極驅動器包含：複數個暫存器、複數個 數位類比轉換器以及複數個輸出緩衝器。暫存器用以接收 數位資料；數位類比轉換器分別連接一暫存器，以自暫存 器接收及轉換數位資料為類比資料；以及輸出緩衝器分別 連接一數位類比轉換器，各輸出緩衝器包含：輸入級及輸 出級。輸入級包含輸入節點，第一輸出端以及第二輸出端， 其中輸入節點自源極驅動器之數位類比轉換器接收類比資 料。輸出級包含：P型金氧半電晶體、N型金氧半電晶體、 第一開關及第二開關。P型金氧半電晶體包含閘極、連接 至第一供應電壓之源極以及連接至輸出節點之汲極；N型 金氧半電晶體包含閘極、連接至第二供應電壓之源極以及 連接至輸出節點之汲極；第一開關連接於P型金氧半電晶 5 1380586 體之閘極與第一輸出端之間；以及第二開關連接於p型金 氧半電晶體之閘極與第一供應電壓之間；其中第一及第二 開關接收閂鎖訊號，使當閂鎖訊號位於第一狀態時，第一 開關關閉且第二開關開啟，進一步使P型金氧半電晶體之 閘極接收第一供應電壓，俾關閉輸出級以防止短路電流情 形產生，而當閂鎖訊號位於第二狀態時，第一開關開啟且 第二開關關閉，俾開啟輸出級以傳送類比資料至輸出節點。 應用本發明之優點係在於藉由第一及第二開關，在傳 送類比資料時開啟輸出缓衝器，並在未傳送時完全關閉輸 出緩衝器，避免輸出緩衝器仍處於導通狀態時產生之短路 電流，而輕易地達到上述之目的。 【實施方式】 請參照第1圖，係為本發明之一實施例之液晶顯示器 1之示意圖。液晶顯示器1包含畫素陣列10、源極驅動器 12及閘極驅勤器14。源極驅動器12係透過複數個資料線 11而與晝素陣列10連接，閘極驅動器14則透過複數個掃 瞄線13而與晝素陣列10連接。閘極驅動器14之各掃瞄線 13係用以依一排列順序開啟晝素陣列10上的一列晝素點。 請同時參照第2圖，係為液晶顯示器1更詳細之示意 圖。晝素陣列10包含複數個晝素點200。源極驅動器12 包含複數個移位暫存器202、複數個資料暫存器204、複數 個準位移轉器206、複數個數位類比轉換器208以及複數 個輸出緩衝器210。移位暫存器202間係彼此串接以實質 地接收數位資料201。各資料暫存器204分別連接一移位 6 j器以接收數位f料2G卜各準位移轉器施 貝料暫存器204以對來自資料暫存 連接 進行一雷厭嘴仏加，、 貝付督吞态204之數位貢料2〇1 接-準位移^器施各數位類比轉換器·分別連 η 201 轉換來自準位移轉器206之數位資 枓2〇1為類比資料203。各於致位夤 位類比轉換器。各數衝器210分別連接—數 器14及一列畫素點綱間知晦線13係連接於閘極驅動 第3圖係為本發明之〜訾 意圖。輸出緩衝請包4::之輸出緩衝器210之示 級3〇包含輪入節點3〇1，第輪=30及輸出級31。輪入 303，其中輸入節點3G1自如—端搬以及第二輸出端 數位類比轉換器接收類比第4^所示源極驅動器12之 Μ金氧半電晶體31〇、〜全貝/丄2()3°輸出級31包含·· 314及第二開㈣。ρ型：氧金2電晶體312、第-開關 接至第—供應電壓彻電晶體310包含閘極、連1380586 VI. Description of the Invention: [Technical Field] The present invention relates to an output buffer suitable for a source driver, and more particularly to an output buffer suitable for a source driver and suitable for use in a One of the liquid crystal display source drivers. [Prior Art] A liquid crystal display device has advantages of being smaller, thinner, and less power-consuming than a conventional display device. Therefore, liquid crystal display devices are widely used in electronic devices such as notebook computers and mobile phones. The source driver of the liquid crystal display device converts the digital data into analog data, and sends the analog data to the pixel array via the output buffer during a driving cycle, and stops transmitting the analog data during the non-driving cycle. However, during the non-drive cycle, the output node of the output buffer is in the area impedance (Hi-Z) state. Short-circuit current conditions are easily generated in a high-impedance state, causing the temperature of the circuit to rise, with undesirable consequences. Therefore, how to design a new output buffer suitable for a source driver and a source driver for a liquid crystal display to avoid short-circuit current is an urgent problem to be solved in the industry. SUMMARY OF THE INVENTION Accordingly, it is an aspect of the present invention to provide an output buffer for a source driver that includes an input stage and an output stage. The input stage includes an input node, a first output, and a second output, wherein the input node receives analog data from a digital analog converter of the source driver. Transmission 4 1380586 The class includes: P-type gold oxide semi-transistor, N-type gold-oxygen semi-transistor, first switch and second switch. The P-type MOS transistor includes a gate, a source connected to the first supply voltage, and a drain connected to the output node; the N-type MOS transistor includes a gate, a source connected to the second supply voltage, and Connected to the drain of the output node; the first switch is connected between the gate of the P-type MOS transistor and the first output; and the second switch is connected to the gate of the P-type MOS transistor and the first Between the supply voltages; wherein the first and second switches receive the latch signal such that when the latch signal is in the first state, the first switch is turned off and the second switch is turned on, further causing the gate of the P-type MOS transistor The first supply voltage is received, the output stage is turned off to prevent the short circuit current condition from being generated, and when the latch signal is in the second state, the first switch is turned on and the second switch is turned off, and the output stage is turned on to transfer the analog data to the output node. Another object of the present invention is to provide a source driver for a liquid crystal display, the source driver comprising: a plurality of registers, a plurality of digital analog converters, and a plurality of output buffers. The temporary register is configured to receive digital data; the digital analog converter is respectively connected to a temporary register to receive and convert the digital data from the temporary storage device as analog data; and the output buffer is respectively connected to a digital analog converter, each output buffer includes : Input stage and output stage. The input stage includes an input node, a first output, and a second output, wherein the input node receives analog data from a digital analog converter of the source driver. The output stage comprises: a P-type MOS transistor, an N-type MOS transistor, a first switch and a second switch. The P-type MOS transistor includes a gate, a source connected to the first supply voltage, and a drain connected to the output node; the N-type MOS transistor includes a gate, a source connected to the second supply voltage, and Connected to the drain of the output node; the first switch is connected between the gate of the P-type MOS transistor 5 1380586 and the first output; and the second switch is connected to the gate of the p-type MOS transistor And a first supply voltage; wherein the first and second switches receive the latch signal, so that when the latch signal is in the first state, the first switch is turned off and the second switch is turned on, further enabling the P-type MOS transistor The gate receives the first supply voltage, the output stage is turned off to prevent the short circuit current condition from being generated, and when the latch signal is in the second state, the first switch is turned on and the second switch is turned off, and the output stage is turned on to transmit the analog data to Output node. The advantage of the application of the present invention is that the first and second switches enable the output buffer when the analog data is transmitted, and completely close the output buffer when not transmitting, thereby avoiding the short circuit generated when the output buffer is still in the on state. Current, and easily achieve the above purpose. [Embodiment] Please refer to Fig. 1, which is a schematic view of a liquid crystal display 1 according to an embodiment of the present invention. The liquid crystal display 1 includes a pixel array 10, a source driver 12, and a gate driver 14. The source driver 12 is connected to the pixel array 10 through a plurality of data lines 11, and the gate driver 14 is connected to the pixel array 10 through a plurality of scanning lines 13. Each of the scan lines 13 of the gate driver 14 is used to turn on a column of pixel points on the pixel array 10 in a sorted order. Please refer to Fig. 2 at the same time, which is a more detailed diagram of the liquid crystal display 1. The halogen array 10 includes a plurality of pixel points 200. The source driver 12 includes a plurality of shift registers 202, a plurality of data registers 204, a plurality of quasi-displacers 206, a plurality of digital analog converters 208, and a plurality of output buffers 210. The shift registers 202 are serially connected to each other to substantially receive the digital data 201. Each of the data registers 204 is respectively connected with a shifting device to receive the digits of the material 2G, and each of the quasi-displacement transducers is configured to perform a thundering of the data temporary storage connection. The digital metric of the tweeted state 204 is connected to the digital converter. The digital analog converter from the quasi-displacement converter 206 is the analog data 203. Each of the in-position analog converters. Each of the plurality of stampers 210 is connected to the comparator 14 and a column of pixels. The line 13 is connected to the gate drive. Fig. 3 is an illustration of the present invention. Output buffer Please indicate that the output buffer 210 of the package 4:: includes the wheel node 3〇1, the first wheel=30 and the output stage 31. The wheel 303, wherein the input node 3G1 is free-to-end and the second-output digital analog converter receives the metal-oxide-semiconductor 31〇, ~Bei/丄2() of the source driver 12 of the fourth embodiment The 3° output stage 31 includes ·· 314 and a second open (four). ρ type: oxygen gold 2 transistor 312, the first switch is connected to the first supply voltage, the transistor 310 includes a gate, a connection
之及極；N型金氧半電晶體^ ^及連接至輸出節點3U 應電壓VSSA之嗎楛 匕含閘極、連接至第二供 SSA之源極以及連接至輪出節點川之汲極。 第一開關314連接於1>沏 第-輪出端302之間，第二^氧半電晶體310之閘極與 晶體3U)之閘極盥第一供;^，M6連接於P型金氧半電 開關3H㈣接收之間。第-1 閃鎖訊號L，而第二開關31二接其/第一開關—314係接收 的各移位暫衫观實質上㈣鎖㈣L。第2圖中 第2圖）。於本實施例中，第鎖訊號L (未繪示於 開關314及第二開關316係 1380586 為P型金氧半電晶體。須注意的是，第一輸出端302及輸 出節點311間係連接有電容318，第二輸出端3〇3及輸出 節點311間係連接有電容320。其中電容318及電容320 均為米勒電容。 請同時參照第2圖、第3圖及第4圖。其中第4圖係 為閃鎖訊號L、類比資料203、資料線11上的訊號D及掃 晦線上的訊號G ’在資料傳輸週期400時，於本發明之一 實施例之時序圖。閂鎖訊號L具有第一狀態401及第二狀 態402。當問鎖訊號L·位於第一狀態4〇1，於本實施例中係 為高態’各移位暫存器202接收數位資料2〇1並立刻傳送 數位資料201至對應的資料暫存器204。資料線11實質上And the N-type MOS transistor ^ ^ and connected to the output node 3U should be the voltage VSSA 匕 闸 闸 闸 、 、 、 、 、 、 、 、 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 The first switch 314 is connected between the first and second round ends 302, the gate of the second oxygen semiconductor transistor 310 and the gate of the crystal 3U) is first supplied; ^, M6 is connected to the P-type gold oxide The semi-electrical switch 3H (four) is received between. The first -1 flash lock signal L, and the second switch 31 is connected to the first switch - 314 is received by each of the shifting shirts (4) lock (four) L. Figure 2 in Figure 2). In the present embodiment, the first lock signal L (not shown in the switch 314 and the second switch 316 is 1380586 is a P-type MOS transistor. It should be noted that the first output 302 and the output node 311 are connected. There is a capacitor 318, and a capacitor 320 is connected between the second output terminal 3〇3 and the output node 311. The capacitor 318 and the capacitor 320 are both Miller capacitors. Please refer to FIG. 2, FIG. 3 and FIG. 4 simultaneously. Figure 4 is a timing diagram of an embodiment of the present invention in a flash lock signal L, an analog data 203, a signal D on the data line 11, and a signal G' on the broom line at a data transmission period of 400. Latch signal L has a first state 401 and a second state 402. When the lock signal L· is in the first state 4〇1, in the present embodiment, it is a high state, and each shift register 202 receives the digital data 2〇1 and The digital data 201 is immediately transmitted to the corresponding data register 204. The data line 11 is substantially
亦嗳閂鎖訊號L的控制。因此，在閂鎖訊號[位於第一具 I 401時’輸出節點311係位於高阻抗狀態，以停止自牵 出緩衝器210傳送類比資料2〇3至資料線u，進而使資靖 線11上的訊號D為一低態。然而，輸出缓衝器別之第一 广第-開關314及316及資料暫存器2()4亦接收閃鎖訊! ^制，使當_訊號L位於第一狀態4〇1時，各㈣ m 保留住數位貧料2G1，第一開關314關閉，j 極：：二16開啟’進—步使？型金氧半電晶體310之6 供應電壓乂觀，俾關閉輸出級31 (使” 金氧丰^體_關閉）以防止短路電流情形產生。 而昜閂鎖訊號L位於第-此吨 功 低態，資料暫存器204透^^録402 ’於本實施例1 換器傳送數位㈣2Qf，準位移轉器施㈣比數位輕 門關叫’以轉換成類比資料203。第一 "，啟且第二開關316關閉，俾開啟輸出級31以« 8 1380586 运類比資料203至輸出節點311。於開啟週期4〇3間，掃 晦線13的訊號G為高態，而進一步開啟—列晝素點細。 開啟ϋ期彻及_訊號L位於第—狀態4〇ι #時間兩 者的交集係為-初始職，以初始資料的傳輪。而開啟週 期403及閃鎖訊號L位於第二狀態4〇2的時間，兩者的交 集則為驅動週期，以實際的傳送類比資料2〇3 ◊因此，在 驅動週期時，掃瞄線13開啟一列晝素點2〇〇，而此列畫素 點200將自對應的輸出緩衝器21〇的輸出節點3ιι，^由 資料線11而接收類比資料203。 請同時參照第4圖及第5Α圖。第5Α圖係為本發明之 另一實施例中，輸出緩衝器21〇在第一狀態4〇1下的示意 圖。閂鎖訊號L位於第一狀態401時係為高態，因而使第 一開關314關閉且使第二開關316開啟。第一開關314的 關閉係使輸入級30及輸出級31間的連接斷開，而第二開 關316的開啟係使Ρ型金氧半電晶體31〇之閘極接收第一 供應電壓VDDA，以使Ρ型金氧半電晶體31〇完全停止工 作。因此’此時弟一巧關及第二開關316係關閉了輸出級 31。請同時參照第4圖及第5Β圖。第5Β圖係為本發明之 另一實施例中’輸出緩衝器210在第二狀態4〇2下的示意 圖。問鎖訊说L位於第一狀態402時係為低態，因而使第 一開關314開啟且使第二開關316關閉。第一開關314的 開啟係使輸入級30及輸出級31相連接，而第二開關 的關閉係使Ρ型金氧半電晶體310之閘極停止接收第一供 應電壓VDDA，以使Ρ型金氧半電晶體310開始工作。因 此，此時第一開關314及第二開關316係開啟了輸出級31。 9 1380586 請參照第6圖。第6圖係為本發明又一實施例中，輸 出緩衝器210’之示意圖。本實施例中輸出緩衝器210’的輸 入級30係與前述之實施例相同，而輸出級31’則包含：P 型金氧半電晶體310’、N型金氧半電晶體312’、第一開關 600、第二開關602、第三開關604及第四開關606。P型 金氧半電晶體310’包含閘極、連接至第一供應電壓VDDA 之源極以及連接至輸出節點311’之汲極；N型金氧半電晶 體312’包含閘極、連接至第二供應電壓VSSA之源極以及 連接至輸出節點31Γ之汲極。第一開關600連接於P型金 氧半電晶體310’之閘極與第一輸出端302之間，第二開關 602連接於P型金氧半電晶體310’之閘極與第一供應電壓 VDDA之間。第三開關604連接於N型金氧半電晶體312, 之閘極與第二輸出端303之間，第四開關606連接於N型 金氧半電晶體312’之閘極與第二供應電壓VSSA之間。 第一、第二、第三及第四開關600、602、604、606接 收閂鎖訊號，其中第一開關600及第三開關604係接收閂 鎖訊號L，而第二開關602及第四開關606係接收閂鎖訊 號Σ。請同時參照第4圖、第6圖及第7A圖。第7A圖係 為本發明之另一實施例中，輸出缓衝器210’在第一狀態401 下的示意圖。閂鎖訊號L位於第一狀態401時係為高態， 因而使第一、第三開關600、604關閉且使第二開關602、 第四開關606開啟。第一開關600的關閉及第二開關602 的開啟係使P型金氧半電晶體310’之閘極接收第一供應電 壓VDDA，而第三開關604的關閉及第四開關606的開啟 係使N型金氧半電晶體312’之閘極接收第二供應電壓 1380586 VSSA，而使輸出級31’完全停止工作而防止了短路電流情 況。 請同時參照第4圖、第6圖及第7B圖。第7B圖係為 本發明之另一實施例中，輸出緩衝器210’在第二狀態402 下的示意圖。閂鎖訊號L位於第二狀態402時係為低態， 因而使第一、第三開關600、604開啟且使第二開關602、 第四開關606關閉。第一開關600的開啟係使輸入級30及 輸出級31相連接，而第二開關602的關閉係使P型金氧半 電晶體310’之閘極停止接收第一供應電壓VDDA，以使P 型金氧半電晶體310’開始工作。第三開關604的開啟係使 輸入級30’及輸出級31’相連接，而第四開關606的關閉係 使N型金氧半電晶體312’之閘極停止接收第二供應電壓 VSSA，以使P型金氧半電晶體310’開始工作。因此，此時 第一、第二、第三及第四開關600、602、604、606係開啟 了輸出級31’以傳送類比資料203至輸出節點311’。 本發明之優點係在於藉由開關，在傳送類比資料時開 啟輸出緩衝器，並在未傳送時完全關閉輸出缓衝器，避免 輸出缓衝器仍處於導通狀態時產生之短路電流。 雖然本發明已以實施方式揭露如上，然其並非用以限 定本發明，任何熟習此技藝者，在不脫離本發明之精神和 範圍内，當可作各種之更動與潤飾，因此本發明之保護範 圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、優點與實施例 11 1380586 能更明顯易懂，所附圖式之說明如下： 第1圖係為本發明之一實施例之液晶顯示器之示意 圖； 第2圖係為液晶顯示器更詳細之示意圖； 第3圖係為本發明之一實施例之輸出緩衝器之示意 圖， 第4圖係為閂鎖訊號、類比資料、資料線上的訊號及 掃瞄線上的訊號，在資料傳輸週期時，於本發明之一實施 例之時序圖； 第5A圖係為本發明之另一實施例中，輸出緩衝器在 第一狀態下的示意圖； 第5B圖係為本發明之另一實施例中，輸出缓衝器在第 二狀態下的示意圖； 第6圖係為本發明又一實施例中，輸出緩衝器之示意 圖， 第7A圖係為本發明之另一實施例中，輸出緩衝器在 第一狀態下的示意圖；以及 第7B圖係為本發明之另一實施例中，輸出緩衝器在第 二狀態下的示意圖。 【主要元件符號說明】 10 :晝素陣列 12 :源極驅動器 14 :閘極驅動器 201 :數位資料 I .液晶顯示裔 II :資料線 13 :掃瞄線 200 :晝素點 12 1380586 202 :移位暫存器 203 :類比資料 204 :資料暫存器 206 :準位移轉器 208 :數位類比轉換器 210、210’ ：輸出緩衝器 30 :輸入級 301 :輸入節點 302 :第一輸出端 303 :第二輸出端 31、31’ ：輸出級 311、311’ ：輸出節點 310、310’ ： P型金氧半電晶 體 312、312’ ： N型金氧半電晶314 :第一開關 體 316 :第二開關 318、320 :電容 400 :資料傳輸週期 401 :第一狀態 402 :第二狀態 403 :開啟週期 600 :第一開關 602 :第二開關 606 :第四開關 604 :第三開關 13Also control of the latch signal L. Therefore, when the latch signal [located at the first device I 401], the output node 311 is in a high impedance state to stop the analog data 2〇3 from the pull-out buffer 210 to the data line u, thereby enabling the capital line 11 to The signal D is a low state. However, the first wide-scale switches 314 and 316 and the data register 2() 4 of the output buffer also receive the flash lock signal, so that when the signal L is in the first state 4〇1, each (4) m retains the digital poor material 2G1, the first switch 314 is closed, j pole:: two 16 open 'into-step? The type of MOS transistor 310 is supplied with a voltage of 俾, and the output stage 31 is turned off to prevent the short-circuit current from occurring. The 昜 latch signal L is at the first ton. State, the data register 204 passes through the record 402' in the first embodiment of the converter to transfer the digits (four) 2Qf, the quasi-displacement converter (four) than the digital light door is called 'to be converted into analog data 203. First " And the second switch 316 is turned off, and the output stage 31 is turned on to drive the analog data 203 to the output node 311. During the turn-on period 4〇3, the signal G of the broom line 13 is high, and further turned on—the column The opening point is fine. The opening period is _ signal L is in the first state - the state 4 〇ι # time the intersection of the two is - initial position, with the initial data of the pass. And the opening period 403 and the flash lock signal L is located in the second When the state is 4〇2, the intersection of the two is the driving cycle, and the actual transmission analog data is 2〇3. Therefore, during the driving cycle, the scanning line 13 turns on a column of pixel points 2〇〇, and this column is drawn. The prime point 200 will be from the output node 3 of the corresponding output buffer 21〇, from the data line 11 Analog data 203. Please refer to FIG. 4 and FIG. 5 at the same time. FIG. 5 is a schematic diagram of the output buffer 21 第一 in the first state 4〇1 according to another embodiment of the present invention. Latch signal L When in the first state 401, it is in a high state, thus closing the first switch 314 and turning on the second switch 316. The closing of the first switch 314 disconnects the connection between the input stage 30 and the output stage 31, and the second The opening of the switch 316 causes the gate of the 金-type MOS transistor 31 to receive the first supply voltage VDDA, so that the 金-type MOS transistor 31 〇 is completely stopped. The second switch 316 turns off the output stage 31. Please refer to FIG. 4 and FIG. 5 simultaneously. FIG. 5 is a schematic diagram of the output buffer 210 in the second state 4〇2 in another embodiment of the present invention. The latch is said to be in a low state when the first state 402 is in the first state 402, thereby causing the first switch 314 to be turned on and the second switch 316 to be turned off. The opening of the first switch 314 causes the input stage 30 and the output stage 31 to be connected. The closing of the second switch causes the gate of the 金-type MOS transistor 310 to stop receiving the first The voltage VDDA is applied to start the Ρ-type MOS transistor 310. Therefore, at this time, the first switch 314 and the second switch 316 turn on the output stage 31. 9 1380586 Please refer to Fig. 6. Fig. 6 is In another embodiment of the present invention, a schematic diagram of the output buffer 210'. In this embodiment, the input stage 30 of the output buffer 210' is the same as the foregoing embodiment, and the output stage 31' includes: a P-type MOS half. The transistor 310', the N-type MOS transistor 312', the first switch 600, the second switch 602, the third switch 604, and the fourth switch 606. The P-type MOS transistor 310' includes a gate, a source connected to the first supply voltage VDDA, and a drain connected to the output node 311'; the N-type MOS transistor 312' includes a gate and is connected to the The source of the two supply voltage VSSA and the drain connected to the output node 31Γ. The first switch 600 is connected between the gate of the P-type MOS transistor 310' and the first output terminal 302, and the second switch 602 is connected to the gate of the P-type MOS transistor 310' and the first supply voltage. Between VDDA. The third switch 604 is connected between the gate of the N-type MOS transistor 312 and the second output terminal 303, and the fourth switch 606 is connected to the gate of the N-type MOS transistor 312' and the second supply voltage. Between VSSA. The first, second, third, and fourth switches 600, 602, 604, and 606 receive the latch signal, wherein the first switch 600 and the third switch 604 receive the latch signal L, and the second switch 602 and the fourth switch The 606 receives the latch signal Σ. Please also refer to Figure 4, Figure 6, and Figure 7A. Figure 7A is a schematic diagram of the output buffer 210' in a first state 401 in another embodiment of the present invention. When the latch signal L is in the first state 401, it is in a high state, so that the first and third switches 600, 604 are turned off and the second switch 602 and the fourth switch 606 are turned on. The closing of the first switch 600 and the opening of the second switch 602 cause the gate of the P-type MOS transistor 310' to receive the first supply voltage VDDA, and the closing of the third switch 604 and the opening of the fourth switch 606 are enabled. The gate of the N-type MOS transistor 312' receives the second supply voltage 1380586 VSSA, and the output stage 31' is completely stopped to prevent the short-circuit current condition. Please refer to Figure 4, Figure 6, and Figure 7B at the same time. Figure 7B is a schematic diagram of output buffer 210' in a second state 402 in another embodiment of the present invention. When the latch signal L is in the second state 402, it is in a low state, thus turning on the first and third switches 600, 604 and turning off the second switch 602 and the fourth switch 606. The opening of the first switch 600 connects the input stage 30 and the output stage 31, and the closing of the second switch 602 causes the gate of the P-type MOS transistor 310' to stop receiving the first supply voltage VDDA, so that P The type of gold oxide semi-transistor 310' starts working. The opening of the third switch 604 connects the input stage 30' and the output stage 31', and the closing of the fourth switch 606 causes the gate of the N-type MOS transistor 312' to stop receiving the second supply voltage VSSA, The P-type MOS transistor 310' is brought into operation. Therefore, at this time, the first, second, third, and fourth switches 600, 602, 604, and 606 turn on the output stage 31' to transfer the analog data 203 to the output node 311'. The advantage of the present invention is that by means of the switch, the output buffer is turned on when the analog data is transmitted, and the output buffer is completely turned off when not transmitted, thereby avoiding the short-circuit current generated when the output buffer is still in the on state. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and the present invention can be modified and modified without departing from the spirit and scope of the present invention. The scope is subject to the definition of the scope of the patent application attached. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, advantages and embodiments of the present invention will become more apparent from the description of the appended claims. 2 is a schematic diagram of a liquid crystal display; FIG. 3 is a schematic diagram of an output buffer according to an embodiment of the present invention, and FIG. 4 is a latch signal, an analog data, and a data line. The signal of the signal and the scanning line, in the data transmission period, is a timing chart of an embodiment of the present invention; FIG. 5A is a schematic diagram of the output buffer in the first state according to another embodiment of the present invention; 5B is a schematic diagram of an output buffer in a second state in another embodiment of the present invention; FIG. 6 is a schematic diagram of an output buffer in another embodiment of the present invention, and FIG. 7A is a diagram In another embodiment of the present invention, a schematic diagram of an output buffer in a first state; and a seventh diagram is a schematic diagram of an output buffer in a second state in another embodiment of the present invention. [Main component symbol description] 10: Alizarin array 12: Source driver 14: Gate driver 201: Digital data I. Liquid crystal display II: Data line 13: Scan line 200: Alias point 12 1380586 202: Shift Register 203: analog data 204: data register 206: quasi-displacement converter 208: digital analog converter 210, 210': output buffer 30: input stage 301: input node 302: first output 303: Two output terminals 31, 31': output stages 311, 311': output nodes 310, 310': P-type MOS transistors 312, 312': N-type MOS semi-electrode 314: first switch body 316: Two switches 318, 320: capacitor 400: data transmission period 401: first state 402: second state 403: on period 600: first switch 602: second switch 606: fourth switch 604: third switch 13