1378642 六、發明說明： •【發明所屬之技術領域】 本發明相關於一種緩衝控制電路，尤指一種可控制停滞 時間之緩衝控制電路。 【先前技術】 在開關式電源系統（弓witching power supply )或D類放 大器（class D amplifier)中，一般會使用推挽式（push-pull) 連接的兩個電晶體開關，透過交互地導通和關閉來改變驅動 電流的方向。請參考第1圖，第1圖為一切換式電壓轉換器 100之示意圖。切換式電壓轉換器100包含一緩衝控制電路 10、一鑛齒波產生器（sawtooth wave generator) 20、一脈衝 寬度調變（pulse width modulation，PWM )電路 30、一開關 電路40、一回授電路50、一誤差放大器（error amplifier) 60、和一電感L，可將輸入電壓VIN轉換為輸出電壓V〇ut 以驅動一負載（由電容CL來表示）。開關電路40包含兩電 晶體開關QP和QN，導通之電晶體開關QP可提供充電電感 L的路徑，而導通之電晶體開關QN可提供放電電感L的路 徑。回授電路50可偵測輸出電壓V〇UT之變化，透過兩串聯 電阻R1和R2將輸出電壓VOUT分壓以產生相對應之回授電 4 1378642 壓Vfb。依據參考電壓Vref和回授電壓Vfb之間的大小差 異，誤差放大器60可產生相對應之比較電壓VC0MP。在接收 到誤差放大器10傳來之比較電壓VC0MP和鋸齒波產生器20 傳來之鋸齒波訊號後，PWM電路30可產i相對應之控制訊 號CS。緩衝控制電路10可依據控制訊號CS同步產生開關 訊號SWP與SWN，藉由開啟或關閉開關電路40之電晶體 開關QP和QN來充電或放電電感L，因此能產生所需要的 負載電流及穩定的輸出電壓。 開關電路40在運作時，電晶體開關QP和QN之責任週 期一般皆為50%，透過交互地導通和關閉來改變驅動電流的 方向。然而，為避免兩個電晶體同時導通造成不要的電流浪 湧（inrush current )，緩衝控制電路10在開關動作引入了停 滯時間（dead-time)特性。請參考第2圖，第2圖為先前技 術中緩衝控制電路10之示意圖。緩衝控制電路10包含反向 器51〜58、一反及閘（NAND gate) 15，以及一反或閘（NOR gate) 25。緩衝控制電路10透過反及閘15和反或閘25來切 換開關訊號SWP和SWN之電位，以及透過串接之反向器 51〜56來提供一停滯時間TD。當控制訊號CS由低電位切 換至高電位時，開關訊號SWP會立即切換至高電位，而開 關訊號SWN會延遲TD後才會切換至高電位；當控制訊號 CS由高電位切換至低電位時，開關訊號SWN會立即切換至 低電位，而開關訊號SWP會延遲TD後才會切換至低電位。 5 1378642 先刖技術之緩衝控制電路10使用串接之反向器來提供訊號 延遲，因此能避免同時導通兩電晶體開關Qp* QN。然而， 串接之反向器佔據極大的電路空間，如此會增加生產成本。 【發明内容】 本發明提供一種可控制停滯時間之緩衝控制電路，其包 含-輸入端，用來接收-控制訊號；—第—輸出端，用來輸 出-第-開關訊號；-第二輸出端，用來輸出—第二開關訊 號，一上升停滯時間鎖定電路，包含一第一邏輯元件，用來 依據該控制訊號提供一第一脈衝訊號；一第一開關，用來依 據一第二脈衝訊號控制該第二開關訊號之波形上升邊緣；一 第二開關’用來依據該控制訊號控制該第二開關訊號之波形 下降邊緣；以及一下降停滞時間鎖定電路，包含一第二邏輯 元件，用來依據該控制訊號提供該第二脈衝訊號；一第三開 關，用來依據該第一脈衝訊號控制該第一開關訊號之波形下 降邊緣，以及一第四開關，用來依據該控制訊號控制該第一 開關訊號之波形上升邊緣。 【實施方式】 在說明書及後續的申請專利範圍當中使用了某些詞彙 來指稱特定的元件。所屬領域中具有通常知識者應可理解 6 1378642 製造商可能會用T同的名詞來稱呼同樣的元件。本說明書及 後續的申請專利範圍並不以名稱的差異來作為區別元件的 方式，而是以元件在功能上的差異來作為區別的基準◊在通 ； 篇說明書及後續的請求項當中所提及的「包含」係為-開放 式的用語，故應解釋成「包含但不限定於」。另外，「耦接」 一詞在此係包含任何直接及間接的電氣連接手段。因此，若 文中描述一第一裝置耦接於一第二裝置，則代表該第一裝置 φ 可直接電氣連接於該第二裝置，或透過其他裝置或連接手段 間接地電氣連接至該第二裝置。 請參考第3圖’第3圖為本發明中一緩衝控制電路200 之示意圖。緩衝控制電路200包含一上升停滯時間鎖定電路 300和一上升停滯時間鎖定電路400，可依據一控制訊號CS 同步產生開關訊號SWP與SWN。上升停滯時間鎖定電路300 包含一反或閘35、反向器31和32，以及電晶體開關QP1、 QP2、QN1和QN2，可控制開關訊號SWN之波形上升邊緣 (rising edge)。下降停滯時間鎖定電路400包含一反及閘 45、反向器41和42，以及電晶體開關QP3、QP4、QN3和 QN4,可控制開關訊號SWP之波形下降邊緣（falling edge)。 在此實施例中，電晶體開關QP1〜QP4為P型金屬氧化物半 導體場效電晶體（p-type metal oxide semiconductor field effect transistor，P-MOSFET)，而電晶體開關 QN1 〜QN4 為 N型金屬氧化物半導體場效電晶體（n-type metal oxide 7 1378642 QN1之下拉能力有限，使得開關訊號SWN在時間點T2時 才會被拉至高電位。因此，本發明之緩衝控制電路200能在 開關訊號SWN之訊號上升邊緣提供一停滯時間TD1 (Τ2-Τ1)。 在時間點Τ3時，控制訊號CS由高電位切換至低電位， 此時電晶體開關QP1為導通而電晶體開關QN3為關閉，端 點Ν1會被拉至高電位而端點Ν2為浮動電位，因此能透過 反向器31立即拉低開關訊號SWN之電位，而此時開關訊號 SWP仍維持在高電位。同時，具低電位控制訊號CS會透過 反向器32和42分別將端點Ν3和Ν4拉至高電位，此時電 晶體開關QN2為導通而電晶體開關QP4為關閉，因此端點 Ν5會被拉至低電位，而端點Ν6為浮動電位。另一方面，具 低電位之控制訊號CS會透過反或閘35於端點Ν7產生一具 高電位之脈衝訊號ΡΗ，進而開啟電晶體開關QN4，因此端 點Ν6之電位會被拉低。此時電晶體開關QP3會被開啟，端 點Ν2會被拉至端點Ν4之高電位，因此能透過反向器41拉 低控制開關訊號SWP之電位。由於電晶體開關QN6的開啟 時間很短，端點Ν6之電位下降幅度不大，因此電晶體開關 QP3之上拉能力有限，使得開關訊號SWP在時間點Τ4時才 會被拉至低電、位。因此，本發明之緩衝控制電路200能在開 關訊號SWP之訊號下降邊緣提供一停滯時間TD2(T4-T3)。 9 1378642 本發明之緩衝控制電路200可應用於如第1圖所示之切 換式電壓轉換器100,或是其它系統（例如D類放大器）中。 本發明利用上升停滯時間鎖定電路300和下降停滯時間鎖定 電路400來提供訊號延遲，在開關訊號SWP和SWN之波形 上升邊緣和波形下降邊緣之間分別提供停滯時間TD1和 TD2，如此可避免同時導通兩電晶體開關QP和QN而造成 不要的電流浪湧，影響系統穩定度。相較於先前技術之緩衝 控制電路10,本發明之缓衝控制電路200佔據較小的電路空 間，因此能降低生產成本。 以上所述僅為本發明之較佳實施例，凡依本發明申請專 利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 ) 第1圖為一切換式電壓轉換器之示意圖。 第2圖為先前技術中一緩衝控制電路之示意圖。 第3圖為本發明中一緩衝控制電路之示意圖。 第4圖為本發明之緩衝控制電路運作時之訊號圖。 【主要元件符號說明】 20 鋸齒波產生器 15、45 反及閘 1378642 30 PWM電路 40 開關電路 50 回授電路 60 誤差放大器 25、35 N1 〜N8 10 、 200 反或閘 端點 緩衝控制電路 m PH 脈衝訊號 PL L 電感 CL CS 控制訊號 100 31、 32、4卜 42、 51 〜58 QP1 〜QP4、QN1- 、QN4、 Vin 、V〇ut、Vfb、 VreF、 SWP、SWN開關訊號 脈衝訊號 電容 切換式電壓轉換器 反向器1378642 VI. Description of the invention: • Technical field to which the invention pertains The invention relates to a buffer control circuit, and more particularly to a buffer control circuit capable of controlling dead time. [Prior Art] In a switched power supply system or a class D amplifier, two transistor switches connected by a push-pull connection are generally used, which are alternately turned on and Turn off to change the direction of the drive current. Please refer to FIG. 1 , which is a schematic diagram of a switching voltage converter 100 . The switching voltage converter 100 includes a buffer control circuit 10, a sawtooth wave generator 20, a pulse width modulation (PWM) circuit 30, a switch circuit 40, and a feedback circuit. 50. An error amplifier 60 and an inductor L convert the input voltage VIN into an output voltage V〇ut to drive a load (represented by a capacitor CL). The switch circuit 40 includes two transistor switches QP and QN, the turned-on transistor switch QP provides a path for the charge inductor L, and the turned-on transistor switch QN provides the path for the discharge inductor L. The feedback circuit 50 detects the change of the output voltage V〇UT, and divides the output voltage VOUT through the two series resistors R1 and R2 to generate a corresponding feedback power 4 1378642 voltage Vfb. Depending on the difference in magnitude between the reference voltage Vref and the feedback voltage Vfb, the error amplifier 60 can generate a corresponding comparison voltage VC0MP. After receiving the comparison voltage VC0MP from the error amplifier 10 and the sawtooth wave signal from the sawtooth generator 20, the PWM circuit 30 can generate the corresponding control signal CS. The buffer control circuit 10 can synchronously generate the switching signals SWP and SWN according to the control signal CS, and charge or discharge the inductor L by turning on or off the transistor switches QP and QN of the switching circuit 40, thereby generating the required load current and being stable. The output voltage. When the switching circuit 40 is in operation, the duty cycles of the transistor switches QP and QN are generally 50%, and the direction of the driving current is changed by alternately turning on and off. However, to avoid unwanted current surges in the simultaneous conduction of the two transistors, the buffer control circuit 10 introduces a dead-time characteristic in the switching action. Please refer to FIG. 2, which is a schematic diagram of the buffer control circuit 10 of the prior art. The buffer control circuit 10 includes inverters 51 to 58, a NAND gate 15, and a NOR gate 25. The buffer control circuit 10 switches the potentials of the switching signals SWP and SWN through the inverse gate 15 and the inverse gate 25, and provides a dead time TD through the series inverters 51 to 56. When the control signal CS is switched from a low level to a high level, the switching signal SWP will immediately switch to a high level, and the switching signal SWN will delay to TD before switching to a high level; when the control signal CS is switched from a high level to a low level, the switching signal The SWN will immediately switch to a low level, and the switching signal SWP will delay to TD before switching to a low level. 5 1378642 The buffer control circuit 10 of the prior art uses a serially connected inverter to provide signal delay, thereby avoiding simultaneous conduction of the two transistor switches Qp* QN. However, the series reverser occupies a large circuit space, which increases production costs. SUMMARY OF THE INVENTION The present invention provides a buffer control circuit capable of controlling a dead time, comprising: an input terminal for receiving a control signal; a first output terminal for outputting a -first-switching signal; and a second output terminal For outputting a second switching signal, a rising dead time locking circuit, comprising a first logic component for providing a first pulse signal according to the control signal; and a first switch for using a second pulse signal Controlling a rising edge of the waveform of the second switching signal; a second switch 'for controlling a falling edge of the waveform of the second switching signal according to the control signal; and a falling dead time locking circuit comprising a second logic component for Providing the second pulse signal according to the control signal; a third switch for controlling a falling edge of the waveform of the first switching signal according to the first pulse signal, and a fourth switch for controlling the first signal according to the control signal The rising edge of the waveform of a switching signal. [Embodiment] Certain terms are used throughout the specification and the following claims to refer to particular elements. Those with ordinary knowledge in the field should understand 6 1378642 Manufacturers may use the same nouns of T to refer to the same components. The scope of this specification and the subsequent patent application do not use the difference of the name as the means of distinguishing the components, but the difference in the function of the components as the basis for the difference; the references mentioned in the specification and subsequent claims The "contains" is an open-ended term and should be interpreted as "including but not limited to". In addition, the term "coupled" is used herein to include any direct and indirect electrical connection. Therefore, if a first device is coupled to a second device, it means that the first device φ can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connection means. . Please refer to FIG. 3'. FIG. 3 is a schematic diagram of a buffer control circuit 200 according to the present invention. The buffer control circuit 200 includes a rising dead time locking circuit 300 and a rising dead time locking circuit 400 for synchronously generating switching signals SWP and SWN according to a control signal CS. The rising dead time locking circuit 300 includes an inverse or gate 35, inverters 31 and 32, and transistor switches QP1, QP2, QN1 and QN2 for controlling the rising edge of the switching signal SWN. The falling dead time locking circuit 400 includes a reverse gate 45, inverters 41 and 42, and transistor switches QP3, QP4, QN3 and QN4 for controlling the falling edge of the waveform of the switching signal SWP. In this embodiment, the transistor switches QP1 to QP4 are p-type metal oxide semiconductor field effect transistors (P-MOSFETs), and the transistor switches QN1 to QN4 are N-type metals. The oxide semiconductor field effect transistor (n-type metal oxide 7 1378642 QN1 has a limited pull-down capability, so that the switching signal SWN is pulled to a high potential at the time point T2. Therefore, the buffer control circuit 200 of the present invention can be used for the switching signal. The rising edge of the SWN signal provides a dead time TD1 (Τ2-Τ1). At the time point Τ3, the control signal CS is switched from the high potential to the low potential, at which time the transistor switch QP1 is turned on and the transistor switch QN3 is turned off. The point Ν1 will be pulled to the high potential and the terminal Ν2 will be the floating potential, so the potential of the switching signal SWN can be immediately pulled down by the inverter 31, and the switching signal SWP remains at the high potential at this time. At the same time, the low potential control signal is CS will pull the terminals Ν3 and Ν4 to the high potential through the inverters 32 and 42, respectively, when the transistor switch QN2 is turned on and the transistor switch QP4 is turned off, so the terminal Ν5 will be pulled to Low potential, and the terminal Ν6 is a floating potential. On the other hand, the control signal CS with a low potential generates a high-potential pulse signal 透过 through the inverse gate 35 at the terminal Ν7, thereby turning on the transistor switch QN4. The potential of the terminal Ν6 will be pulled low. At this time, the transistor switch QP3 will be turned on, and the terminal Ν2 will be pulled to the high potential of the terminal Ν4, so that the potential of the control switching signal SWP can be pulled down through the inverter 41. Since the turn-on time of the transistor switch QN6 is short, the potential drop of the terminal Ν6 is not large, so the pull-up capability of the transistor switch QP3 is limited, so that the switching signal SWP is pulled to the low level at the time point Τ4. Therefore, the buffer control circuit 200 of the present invention can provide a dead time TD2 (T4-T3) at the falling edge of the signal of the switching signal SWP. 9 1378642 The buffer control circuit 200 of the present invention can be applied to the switching as shown in FIG. The voltage converter 100, or other system (such as a class D amplifier). The present invention utilizes the rising dead time locking circuit 300 and the falling dead time locking circuit 400 to provide signal delay at the switching signals SWP and SWN. The dead time TD1 and TD2 are respectively provided between the rising edge of the waveform and the falling edge of the waveform, so as to avoid unnecessary current surge caused by simultaneously turning on the two transistor switches QP and QN, which affects system stability. Compared with prior art buffering The control circuit 10, the buffer control circuit 200 of the present invention occupies a small circuit space, and thus can reduce the production cost. The above is only a preferred embodiment of the present invention, and the average variation of the patent application scope according to the present invention And modifications are intended to be within the scope of the invention. [Simple description of the diagram] Fig. 1 is a schematic diagram of a switching voltage converter. Figure 2 is a schematic diagram of a buffer control circuit in the prior art. Figure 3 is a schematic diagram of a buffer control circuit in the present invention. Figure 4 is a signal diagram of the operation of the buffer control circuit of the present invention. [Main component symbol description] 20 Sawtooth generator 15, 45 Inverting gate 1378642 30 PWM circuit 40 Switching circuit 50 Feedback circuit 60 Error amplifier 25, 35 N1 ~ N8 10, 200 Reverse or gate terminal buffer control circuit m PH Pulse signal PL L Inductance CL CS Control signal 100 31, 32, 4 Bu 42, 51 ~ 58 QP1 ~ QP4, QN1-, QN4, Vin, V〇ut, Vfb, VreF, SWP, SWN switching signal pulse signal capacitance switching Voltage converter inverter