TWI377774B - Controller having output current control for a power converter - Google Patents

Description

1377774 IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to a power converter, and more particularly to a controller of a resonant power converter that controls the current of the resonant type converter. [Prior Art] Power converters are widely used to provide regulated voltage and current. Nowadays, the power conversion is transferred to the ridge stream of the launcher, and the system will be equipped with a current-distribution circuit-control circuit. However, the current_circuit at the output leads to the identification of the wire, especially when the output current is higher. In addition, the control circuit at the output side prints the space of the circuit board a > nntCircuitBoard, PCB) and increases the manufacturing cost of the power converter. Therefore, based on the above problems, the present invention provides a circuit of a power converter that is used in conjunction with a switching circuit of a power converter for use in controlling a job. Since the switching current of the power converter is generally less than the output current', switching the current control output current reduces power consumption. In addition, the control circuit can be integrated with the switching circuit as an integrated circuit to effectively reduce the space and cost of the power converter. SUMMARY OF THE INVENTION The main object of the present invention is to provide a control system for power consumption, which utilizes the output of the power converter to transfer the output of H, and reduces the size and space. The present invention provides a controller for a power converter that is applied to a resonant power converter. The controller of the present invention controls the output of the power converter by controlling the switching current of the power converter. The controller includes a first circuit for detecting a switching current of one of the power converters to generate a first signal, and a second circuit coupled to the transformer to detect a discharge time of the transformer to generate a second Signal; a third circuit 'based on the second signal to the first signal / / / 4 accumulated knife X produced third 峨; - switching circuit, receiving the third signal and - reference voltage to generate, switching signal 'to switch The transformer turns off the output current of the power conversion. Among them, in order to achieve the purpose of the β-engineering current, the time of the third circuit is often designed to be related to the switching frequency of the switching signal. In order to give your reviewers a better understanding and understanding of the structural features and energy efficiency of the present invention, please refer to the preferred embodiment and the detailed description, as follows: [Embodiment] "Monthly Figure 1 is a circuit diagram of a resonant power conversion rider of an embodiment of the present invention. This month's /, vibrating power converter includes - transformer 1 (), which is equipped with - auxiliary winding team, - human side winding ΝΡ and - secondary winding Ns controller %, which is generated - switching The signal VPWM is passed through the -discriminating transistor 2' to turn off the output voltage V of the power converter with (4) hard-to-change shoes (1). With output current! . . Please refer to the second figure together, which is a resonant power converter of the embodiment of the present invention. When the switching 峨Vp_ is high (10), the power transistor 20 is driven to conduct, and thus the secondary side switching current & is generated on the secondary side of the transformer (1). The peak value IpA of the primary side switching current Ip can be expressed as follows: (1) I ΡΑ=~^~ χΤ〇Ν where vIN is the input voltage, applied to the variable pressure stomach 1G; Lp is the first side of the transformer 1 () The inductance value of the winding NP; Τ0Ν is the switching signal VPWM<- conduction time. Once the VPWM is switched to the scale, the energy of the transformer 1() will be transferred to the transformer 丨0 and the transmission will be transmitted to the wheel of the god converter through the rectifier (10). The 1377774 rectifier 40 is coupled. There is a filter capacitor 45. The secondary side of the variable pressure benefit 10 has a secondary side switching current Is, and the peak value of the two switching powers can be expressed as follows:

Is, =^l, TDSD Ls (2) where ' V. The output voltage of the power converter; the forward bias of the Vf system rectification (4), the inductance value of the secondary side winding (10) of the transformer 1G, and the discharge time of the secondary side switching current h.

At this time, the auxiliary winding Na of the 'transformer K' generates a reflected voltage V, which can be expressed as follows: νΑυχ=ψ·^(Υ0+νΡ) 1NS (3) !SA ^~χΙΡΑ 2ns (4) where The tn^Tns is the auxiliary winding ratio of the transformer (4) and the winding of the secondary winding Ns. When the secondary side switching current g is zero, the reflected voltage ¥ begins to decrease, which also means that the energy of the (4) 1G will be completely released in this action, which is the characteristic of the resonant power converter, that is, the transformer H) The energy is completely released before the start of the down-switching cycle. Therefore, as shown in the second figure, the discharge time of the equation (2) can be known by measuring the time from the falling edge of the switching signal VPWM to the falling point of the reflected voltage VAux. Referring to the first figure, the controller 70 includes a power supply terminal vcc, a voltage detection terminal DET, a ground terminal GND, a current sensing terminal VS, a feedback terminal FB, an output terminal 〇υτ, and a current compensation. The terminal COM output terminal OUT is switched by 峨ν_, and the electrical hard-to-measure 1777774 terminal DET is coupled to the auxiliary winding NA through a resistor 50 to detect the reflected voltage VAUX. The reflected voltage VAUX charges a power supply capacitor 65 through a rectifier 60 to supply power to the controller 70. The current sensing terminal VS is coupled to a current sensing device, such as a current sensing resistor 30, one end of which is coupled to one source of the power transistor 20, and the other end is coupled to the ground end to convert the primary side switching. The current Ip is the secondary side switching current signal Vs. Referring to the first figure, the power converter is provided with a light combiner 55 on the secondary side of the transformer 1 , and the input end of the light consuming device 55 is transmitted through a resistor 51 to output an output voltage and a second pole. The sense voltage driving of the body 53 drives the output terminal to generate a feedback signal Vfb, and transmits it to the feedback terminal FB of the controller 7 to form a feedback control circuit. The current compensation terminal c〇MI is coupled with a compensation capacitor. 32. Referring to the second figure, the circuit diagram of the controller of the embodiment of the present invention. The controller 70 of the present invention includes a -first-circuit 1〇〇' which is formed at the current sensing end vs, that is, is consumed by current sensing.

The output current of the device is proportional to 10.

The device 75 is configured to control the output current through a first AND gate 91 and a first error amplifier; a first comparison-first-front-reverse H 95 is absent to control the switching signal vPWM according to the input of the brain-sense amplifier 1377774. Pulse width. The error amplifier amplifies the third signal 并^^ and provides a loop gain for controlling the output current. The current control loop includes a circuit for detecting the primary side switching current Ip for adjusting the pulse width of the switching signal VPWM. The current control loop controls the magnitude of the primary side switching current Ip in accordance with the reference voltage VreFI. As shown in the equation (4), the secondary side switching current Is is proportional to the primary side switching current Ip. Referring to the waveform shown in the second figure, the power of the power transfer (four) flow 1 () county second picking switch current Is feeding, the power conversion stealing output current 1 〇 can be expressed as follows:

I〇=Isa 乂

Tds (5) -, medium TDS is the discharge time of the voltage change ΐ(), which is equal to the discharge time TDSD of the secondary side switching current is', so the fine electric correction system of the twister can be adjusted. Referring to the reference diagram, the present invention utilizes a current sensing resistor 3 〇 conversion - a secondary side switching current Ip :: 彳 to switch the motor money %. The first-circuit excitation system measures the primary side switching current signal Vs,

Λ produces the first minus. The third circuit 3 (8) generates a third signal Vx for the first signal to the integral, and the third signal % can be expressed as follows:

Fx=HxI〇s 2 T' (6) where VA can be expressed as follows:

1 NP A (7) where T is the third circuit 3 〇〇 temple hang number ' Rs series current sense resistor 3 〇 lightning resistance capture reference equation (4) to the resistance value type (7), the third The signal VX can be expressed as follows: (8) 1377774

Vx^xTfPxRsXl〇 where 'deserved' is the output current 丨 of the third signal system and the power converter. Proportional, so when the third signal Vx is enhanced, the current I is output. It also increases, but the maximum value of the third signal vx is adjusted by the current control loop and is limited by the reference voltage U value. In other words, the special motor control loop controls the switching pulse signal according to the value of the reference voltage to control the ii51 flow. . Under _(4) of the current control chest, the maximum age current (painting) can be expressed as follows: ^O(MAX) = ^-X ~~~£l_x ^sw x Vr\ (9)

Tm 'HGAxGswJp where 'K is a constant equal to Ti/T; VR1 is the voltage value of reference voltage v_; GA is the gain of the error amplifier; Gsw is the gain of the switching circuit 8〇. If the loop gain of the current control loop is very high (GAxGsw»l), the maximum output current I〇(MAX> can be expressed as follows: ^〇(ΜΑΧ) =Κχ^£-χϊβΙ

Tns Rs (10) Therefore, the maximum output current I0(瞧) of the power converter can be adjusted to a fixed current according to the reference frame. A graph of the variation of the output voltage Vo of the present invention with respect to the output current 10 is as shown in the fourth figure. The switching circuit 80 of the present invention further includes a flip-flop circuit 9G including a first flip-flop 95 output switching 峨Vp_, _ switching converter. The first-front-and-reverse (four)--the clock-end 1373774 is the output end of the light-to-inverting Is 93, and the set signal PLS generated by the fourth circuit can be set to the first-and-right-reverse by the first-inverter 93 system. %. One of the first flip-flops is received - the supply voltage H - the flip-flop 95 - the output Q _ is connected - the second and the gate 92 is the first input - the second and the gate 92 The two input terminals are coupled to the output end of the first inverter 93 and the output of the second AND gate 92 is connected to the output terminal 〇υτ of the controller 7〇. The reset terminal r of the first flip-flop 95 is coupled to one of the output terminals of the first gate 91. The first input terminal of the first gate 91 receives a voltage loop signal, and the voltage loop signal is a voltage. The control circuit 600 generates a voltage control circuit 6 for adjusting the output voltage V of the power converter. . The second input terminal of the first AND gate 91 is coupled to the output end of the first comparator 75 for receiving a current loop signal S1 outputted by the first comparator 75 for the purpose of controlling the output current. The third input terminal of the first AND gate 91 receives a first reset signal RST generated by the fourth circuit 4〇〇. The current loop signal & and the voltage loop signal Sv are the second reset signal and the third reset signal, respectively. That is, the first reset signal RST, the current loop signal 8, and the voltage loop signal Sv, the first flip-flop 95 can be reset to shorten the pulse width of the switching signal VPWM, so that the output voltage V〇 can be adjusted. The output current is 1〇. One of the first comparators 75 is coupled to the output of one of the first operational amplifiers 71. The negative terminal of the first comparator 75 is coupled to the fourth circuit 400 for receiving the fourth circuit 400. One of the ramp signals RAMP. Please refer to the fifth figure, which is a circuit diagram of a voltage control loop according to an embodiment of the present invention. The voltage control circuit 600 of the present invention comprises a second transistor 610, three resistors 611, 612, 613, an adding circuit 620 and a second comparator 630. The gate of the second transistor 610 is coupled to the feedback terminal FB of the controller 70 and one end of the resistor 611. The drain of the second transistor 610 is connected to the other end of the 11 1377774 resistor 611 and receives the supply of electricity & The source of the second transistor _ is the same as the terminal of the resistor 612, and the other end of the resistor 612 is connected to one end of the resistor 613, and the other end of the resistor 613 is lightly connected to the ground. One of the positive ends of the second comparator 63 is lightly connected to the feedback terminal FB via the second transistor 610 and the resistors 612 and 613 for level displacement and attenuation, and the negative terminal of the second comparator 630 is connected. The output terminal of the adding circuit 62 is configured to receive the slope signal surface p and the secondary side switching current signal Vs, and the summing circuit 62 〇 adds the primary side switching current signal VS and the slope signal RAMP to obtain the slope compensation, so that the second The output of the comparator 63() is the output voltage loop signal Sv. Please refer to the sixth diagram of the circuit of the first embodiment of the present invention. The first circuit 100 of the present invention includes a peak-to-peak detection circuit 305, which includes a third comparator 31A, and the positive terminal of the third comparator 31G controls the current sensing terminal of the g7G. The secondary side switching current signal vsi value is proportional to the value of the primary side switching power Ip, and one of the negative terminals of the third comparator 31 is lightly connected to a fourth capacitor 315, and the fourth capacitor 315 is used for boxing once. The side switches the peak value of the current signal Vs. The fourth electric valley 315 is charged by a first fixed current source 32, and the first fixed current source 315 is connected to the supply voltage vcc; The fourth capacitor 315 and the first fixed current source 32A are connected to the first switch 330. The two ends of the first switch 330 are respectively coupled to the first fixed current source 32〇 and the fourth electric valley 315'. The turn-on and turn-off of the switch 330 is controlled by the output of the third comparator 310, such that the potential across the fourth capacitor 315 is a peak signal Vsm peak signal Vsp as shown in the second figure, and the primary side switching current Ip The peak IPA is proportional. The fourth capacitor 315 is connected in parallel with a second switch 312 for controlling the discharge of the fourth capacitor 315, and the second switch 312 is controlled by the fourth circuit 400 to generate a clear signal CLR. The first circuit 100 further includes a 12th 丄 377774 and a drain of the fourth transistor 125. The drain of the fourth transistor 125 is further mixed with the seventh capacitor i24 and the fourth inverter ^I52. The source is connected to ground. The output of the fourth inverter 1$2 is connected to the input terminal of the fourth and gate 156, and the other input of the fourth and the gate w is coupled to the output of the third and gate 155. The capacitance value of the third current 丨(2) and the seventh capacitor 124 of one of the third fixed current sources 123 determines the pulse width of the voltage sampling signal STB. The second circuit 200 also includes a second operational amplifier im, which acts as a buffer amplifier. One of the second operational amplifiers 101 is coupled to a negative terminal. The positive terminal of the second operational amplifier 101 is coupled to the voltage detecting terminal DET of the controller 7A. The voltage detecting terminal DET is coupled to the auxiliary winding Na of the transformer 1 through the resistor 50 for detecting the reflected voltage vAUX. A second sampling circuit 103 includes a fourth switch 1〇9 and an eighth capacitor 112. The two ends of the fourth switch 109 are respectively coupled to the output end of the second operational amplifier 1〇1 and the eighth capacitor 112. The conduction and cutoff of the fourth open_1〇9 is controlled by the voltage sampling signal STB' for sampling the reflected voltage VAUX as a sampling signal, which is a detection voltage ν〇 to know the discharge time, the detection voltage vDET It will be clamped to the eighth capacitor 112. The fourth comparator 1〇5 of one of the second circuits 200 is for detecting a decrease in the reflected voltage Vaux. The positive terminal of one of the fourth comparators 105 is connected to the eighth capacitor U2, the negative terminal of the fourth comparator 1〇5 is coupled to an offset voltage ιοό, and the offset voltage 106 is coupled to the fourth comparison. Between the negative terminal of the device 1〇5 and the output terminal of the second operational amplifier 101, a threshold voltage is applied to detect the amount of decrease in the reflected voltage vAUX. Therefore, when the decrease of the reflected voltage Vaux exceeds the voltage value of the offset voltage 1〇6, the output of the fourth comparator 105 is an end signal of a high level. One of the fifth inverters 115 of the second circuit 200 receives the switching signal VpwM; one of the sixth inverters 116 receives the voltage sampling signal stb; the fifth and the gate 119 of the 14 1377774 The input end is lightly connected to one of the output ends of the fourth comparator 105; a second flip-flop ι 7 and a first-for-negative H 118 are respectively provided with an upper edge triggering - resetting one of the setting end and the high level trigger The set terminal S and the reset terminal of the terminal-reactor 118 respectively connect the output of the sixth inverter 116 and the reception switching signal VPWM. The output terminal q of the third flip-flop 118 consumes the second input of the fifth and gate 119. The output terminal of the second flip-flop 117 outputs the second signal sDS. The set terminal s of the second flip-flop 117 is lightly connected to the round-out end of the fifth inverter 115, so the first signal SDS is enabled. In the off state of the switching signal VPWM, the reset terminal R of the second flip-flop 117 is lightly connected to the output terminal of the fifth AND gate 119, that is, the fifth gate 119 receives the stop signal and transmits to the first-front-reverse When the device 117, the second signal SDS will be disabled. The pulse width of the second signal & is related to the discharge time Tds of the transformer. Please refer to the eighth figure, which is a circuit diagram of a third circuit of an embodiment of the present invention. The third circuit 300 of the present invention comprises a voltage-to-current conversion circuit 4〇5, which includes a third operational amplifier 410, a plurality of resistors 450-455 and a fifth transistor 420. The positive terminal of the third operational amplifier 41A receives the first signal vA, and the negative terminal of the third operational amplifier 41A is coupled to the source of the resistor 45〇455 and the fifth transistor 420. The output terminal of the third operational amplifier 410 is connected to the gate of the fifth transistor 420, and the drain of the fifth transistor 420 is coupled to the drain of the transistor 42. The second operational amplifier 410 generates a programmable first current bo according to the voltage value of the first signal vA. The complex current mirror includes a plurality of transistors 421 425 425 for mapping the first current bo to generate a plurality of currents I422 〜 I425, the sources of the transistors 421 425 425 being coupled together and being lightly connected to the supply voltage Vcc, the transistor 421425 The gates are also coupled together and coupled to the drain of the transistor 421. The resistors 450-455 and a ninth capacitor 489 and a tenth capacitor 49 determine the time constant of the third circuit 300. 15 1377774 A fifth switch 460 is reduced between the current ~k and the two capacitors 489, 490, and the fifth switch 460 is only turned on during the period of the discharge time tds, that is, the conduction system of the fifth switch 46 is controlled by the first Second signal SDS. A sixth switch 462 is connected in parallel to the two capacitors 489, 490 to control the brightness of the two electric valleys 489, 490, and the sixth switch 462 is controlled by the clear signal CLR generated by the fourth circuit 4?. The two ends of a seventh switch 486 are respectively coupled between the ninth capacitor 489 and the fifth switch 46A.

A third sampling circuit 465' includes an eighth switch 461 and an output capacitor 472, and the eighth switch 461 is between the two capacitors 489, 490 and the output capacitor 472. The eighth switch 461 is controlled by the fourth circuit. The shackle signal SMp generated by the 400 is used for periodically turning on and off to sample the voltage from the two capacitors 489, 490 to the output capacitor 472, so that the second signal Vx can be obtained by the output capacitor 472. The third signal vx can be expressed as follows:

Vx

'X^AX ^DS (11) where 'Rx is the resistance value of the resistor 450~455; cx is the capacitance value of the capacitor 489, 4900 in order to make the time constant (rx, cx) of the third circuit 300 and the switching signal The switching frequency of the vPWM is related to the resistance values of the resistors 450-455, the capacitance values of the capacitors 489 and 490, and the currents 1422 to 1425, which are programmable control by a plurality of switches 430 to 435 coupled to the resistors 450 to 455, Two switches 462 and 486 coupled to the two capacitors 489 and 490 and a plurality of switches 482 to 485 coupled to the transistors 422 to 425. The switches 430 to 435 and the switches 482 to 486 are controlled by the fourth statement Νν···Ν〇 generated by the fourth circuit 400. Please refer to the ninth diagram, which is a circuit diagram of a fourth circuit of an embodiment of the present invention. The fourth circuit 400 1377774 includes a cutoff circuit 210, a turn-on circuit 250, and a timing circuit 290. The cut-off circuit • 210 receives the switching signal VpwM, generates a ramp signal during the turn-on time of the switching signal VpwM. RAMP, and generates a first reset signal RST according to the ramp signal RAMP to determine the switching signal. The maximum on-time of the VPWM. The turn-on circuit 250 generates a set-signal PLS ’ according to the end of the second signal SDS. The turn-on circuit 250 further generates the clear signal CLR and the slam-lock signal SMP according to the set signal PLS. The timer circuit 290 receives the clear signal CLR and the shackle signal SMP to generate the fourth signal Nn...N〇. ® Please refer to the tenth figure, which is a circuit diagram of the cut-off circuit of the fourth circuit of the embodiment of the present invention. The receiving circuit 210 includes a seventh inverter 241' whose receiving end receives the switching signal VPWM and the output end is coupled to the gate of a sixth transistor 217. A fourth fixed current source 211 is coupled to a second capacitor 223 and connected to the drain of the sixth transistor 217. The source of the sixth transistor 217 is coupled to the ground. The fixed current source 211 and the eleventh capacitor 223 generate the ramp signal RAMP according to the on state of the switching signal Vpwm. a fifth comparator 215, wherein a positive terminal receives the reference voltage Vref2 and a negative terminal is coupled to the first capacitor 223, and generates a first reset signal RST according to the ramp signal RAMP to determine the maximum turn-on period of the switching signal VpwM. . The output of the fifth comparator 215 is coupled to a first input end of a first anti-gate 245, and the second input end and the third input end of the first anti-gate 245 respectively receive a voltage loop signal, and The current circuit signal s 丨, the output of the first NAND gate 245 is coupled to the gate of a seventh transistor 218, and the source of the seventh transistor 218 is coupled to the ground. A fifth fixed current source 212 is coupled to a twelfth capacitor 224 and coupled to the drain of the seventh transistor 218 and to the first input of the sixth and gate 246. The fourth fixed current source 211 and the fifth fixed current source 212 described above are all coupled to the supply voltage vcc. The output of the first inverting gate 245 is further coupled to the input terminal of the eighth inverter 242, and the output of the eighth inverter 242 is connected to one of the sixth and the second gate 246. The output of the sixth and gate 246 generates a first reset signal capture. The fifth fixed current source 212 and the twelfth capacitor 224 ensure a minimum pulse width of the first reset signal RST. - Referring to the tenth-figure, a circuit diagram of a conduction circuit of a fourth circuit of the embodiment of the present invention. The turn-on circuit 250 includes an eighth transistor 251, the gate of which receives the second signal & and the input of the second and sixth fixed current source 253, the thirteenth capacitor 252 and a ninth inverter 261 The Luan surface is connected together, and the output end of the ninth inverter 261 is lightly connected to one of the first input terminals ' of the seventh and gate 265', and the sixth fixed current source 253 is also lightly connected to the supply voltage Vcc. The input end of a tenth inverter 262 receives the second signal SDs' and the output end is coupled to the first input end of one of the second input terminal 197 and the second NAND gate 263. The second input end of the second anti-gate 263. The receiving end of the trough side signal VALY 'the second anti-gate 263 is connected to the third input end of the seventh and the gate 265 'the seventh level 265 The output generates a set signal pLS. The seventh and gate 265 generates the setting signal PLS according to the cutoff of the second signal sDS and the enabling of the selectable wave trough test signal VALY. The trough debt signal VALY is used to turn on the switching signal VPWM to synchronize with the resonant frequency of the power converter and achieve flexible switching. The sixth fixed current source 253 and the thirteenth capacitor 252 described above determine the pulse width of the set signal PLS. The first pulse wave generating circuit 270 and the second pulse wave generating circuit 28 generate the latch signal SMP and the clear signal CLR according to the set signal pLS, respectively. The circuit diagrams of the first pulse wave generating circuit 27A and the second pulse wave generating circuit 280 are as shown in Fig. 12. The timing and waveform of the setting signal pLS, the shackle signal SMp and the clear signal CLR are as shown in the thirteenth diagram. Referring to Figure 12, there is shown a circuit diagram of a pulse wave generating circuit of an embodiment of the present invention. The invention relates to a pulse generating circuit of the present invention comprising a second time delay circuit 350 and a second click signal generating circuit 360 by means of two pulse generating circuits for generating the latch signal SMP and the clear signal CLR. The second time delay circuit 350 includes an eleventh inverter 35, a seventh fixed current source 352, a ninth transistor 353, a fourteenth capacitor 354, and an eighth sum gate 355. The input end of the eleventh inverter 351 receives the set signal pls. The wheel end of the eleventh inverter 351 is coupled to the gate of the ninth transistor 353. The drain of the ninth transistor 353 is coupled to one of the seventh fixed current source 352, the fourteenth capacitor 354, and the eighth and gate 355, and the source of the ninth transistor 353 is coupled to the ground. The seventh fixed current source 352 is also coupled to the supply voltage Vcc. In addition, the other input terminal of the eighth and gate 355 receives the setting signal PLS. The second click signal generating circuit 360 includes a twelfth inverter 361, an eighth fixed current source 362, a tenth transistor 363, a fifteenth capacitor 364, a ninth gate 365 and a first Thirteen inverters 366. The input end of the twelfth inverter 361 is coupled to the output terminal of the eighth and gate 355. The output of the twelfth inverter 361 is coupled to the gate of the tenth transistor 363. The drain of the tenth transistor 363 is coupled to the input terminal of the eighth fixed current source 362, the fifteenth capacitor 364 and the twelfth inverter 366, and the source of the tenth transistor 363 is coupled to the ground. Further, the eighth fixed current source 362 is coupled to the supply voltage Vcc. The first input terminal and the second input terminal of the ninth gate 365 are respectively coupled to the output ends of the thirteenth inverter 366 and the output terminals of the eighth and gate 355. The ninth and second 365 _out ends of the second click signal generating circuit 360 are the output terminals of the pulse wave generating circuit. The output signal of the pulse wave generating circuit is the click signal output by the second click signal generating circuit 360, that is, the plug-in number SMP or the clear-down CLR, and the input signal is transmitted to the first-time delay circuit 350. _ Input setting signal PLS. The seventh mosquito current source says 19 1377774 - the capacitance value of the current 1352 and the fourteenth capacitor 354 determines one of the second time delay circuits 35 • • the delay time, and one of the second time delay circuits 350 is lightly connected to the The input terminal of the second click signal generating circuit 360, that is, the output terminal of the eighth and gate 355 is connected to the input terminal of the twelfth inverter 361. The capacitance of the eighth fixed current source 362 - the current ^ and the fifteenth capacitor 364 - the value determines the pulse width of the click signal.

Referring to the twelfth aspect, the waveform I of the turn-on circuit of the embodiment of the present invention, the latch signal SMP and the clear signal CLR are as shown in the thirteenth diagram. The present invention triggers the first pulse wave generating circuit 270 to generate the pickup signal SMP after the lapse of the -first delay time Td by setting the positive edge of the signal pLS, which is a first pulse width Τρι. When the signal is clicked, the positive edge of the setting signal PLS at the same time triggers the second pulse wave generating circuit 28 to generate a clear signal (xR) having a second pulse width Τρ2 after a second delay time* Τ〇2. The second delay time τ 〇 2 - is longer than the first delay time Tm. Please refer to FIG. 14 ' is a circuit diagram of the timing circuit of the fourth circuit of the embodiment of the present invention. The timing circuit 290 includes a counter 29 The buffer 293, a fifth circuit 295 and a fourteenth inverter 297. The input of the fourteenth inverter 297 receives the clear signal CLR, and the output is coupled to the counter 291. The fifth circuit 295 For generating a clock signal CLK, the counter 291 receives the clock signal CLK and the clear signal CLR to generate a binary code. The temporary buffer 293 generates a fourth signal according to the shackle signal SMP sampling the binary code. One of the five circuits 295 The number (RYcY) is associated with the time constant (RxCx) of the third circuit 3' and the binary carry code of the counter 291 represents the switching period of the switching signal VpwM, so the switching period τ of the switching signal VPWM can be determined as: T - RyxCyX NCmmt (12) · 1377774 where 'Ncout is the value of the fourth signal Nn...n〇. Therefore, the third signal vx is related to the secondary side switching current Is and the power converter's wheel current ^ Equation (8) and equation (u) can be expressed as follows:

Where m is a constant, which can be expressed as follows:

Ry xCy RxxCx

(14)

Since the time constant Rxcx is controlled and programmed according to the fourth signal (9), the value of (RYCYXNC0UT) is equal to the value of Rxcx, so the third signal νχ is proportional to the output current of the power converter. The above description is only for the purpose of the present invention, and is not intended to limit the scope of the present invention, so that the shapes, structures, features, and spirits described in the claims are equally Variations and modifications are intended to be included within the scope of the invention.

21 1377774 [Simplified description of the drawings] The first figure is a circuit diagram of a resonant power converter according to an embodiment of the present invention; The second figure is a waveform diagram of a resonant power converter according to an embodiment of the present invention; The circuit diagram of the controller of the embodiment of the invention; - the fourth diagram is a graph of the output voltage of the embodiment of the invention with respect to the change of the output current; the fifth diagram is the circuit diagram of the voltage control loop of the embodiment of the invention; The circuit diagram of the first circuit of the embodiment of the present invention; the seventh diagram is a circuit diagram of the second circuit of the embodiment of the present invention; the eighth diagram is the circuit diagram of the third circuit of the embodiment of the present invention; The circuit diagram of the fourth circuit of the embodiment of the present invention; and the circuit diagram of the circuit of the fourth circuit of the embodiment of the present invention; 2 is a circuit diagram of a pulse wave generating circuit of a conducting circuit of an embodiment of the present invention; FIG. 13 is a waveform diagram of a conducting circuit of an embodiment of the present invention; and FIG. A circuit diagram of a circuit of the timing circuit of the fourth embodiment of the embodiment. [Figure number comparison description]

10 Transformer 20 Power transistor 30 Current sense resistor 32 Compensation capacitor 40 Rectifier 45 Filter capacitor 50 Resistor 51 Resistor 53 Senser diode 55 Photocoupler 60 Rectifier 65 Power supply capacitor 22 1377774

70 controller 71 first operational amplifier 75 first comparator 80 switching circuit 90 output circuit 91 first AND gate 92 second and gate 93 first inverter 95 first flip-flop 100 first circuit 101 second operational amplifier 103 second sampling circuit 105 fourth comparator 106 offset voltage 109 fourth switch 112 eighth capacitor 115 fifth inverter 116 sixth inverter 117 second flip-flop 118 third flip-flop 119 fifth Gate 120 second fixed current source 121 sixth capacitor 122 third transistor 123 third fixed current source 124 seventh capacitor 125 fourth transistor 126 first time delay circuit 127 first click signal generating circuit 150 second inversion 151 third inverter 152 fourth inverter 155 third sum gate 156 fourth and gate 200 second circuit 210 cutoff circuit 211 fourth fixed current source 212 fifth fixed current source 215 fifth comparator 217 sixth Transistor 218 seventh transistor 223 eleventh capacitor 224 thirteenth capacitor 241 seventh inverter 23 1377774

242 eighth inverter 245 first reverse gate 246 sixth and gate 250 conduction circuit 251 eighth transistor 252 thirteenth capacitor 253 sixth fixed current source 261 ninth inverter 262 tenth inverter 263 Second NAND gate 265 seventh and gate 270 first pulse generation circuit 280 second pulse generation circuit 290 timing circuit 291 counter 293 temporary buffer 295 oscillator 297 fourteen inverter 300 third circuit 305 peak detection Measuring circuit 307 first sampling circuit 310 third comparator 312 second switch 315 fourth capacitor 320 first fixed current source 325 third switch 330 first switch 335 fifth capacitor 350 second time delay circuit 351 eleventh inversion 352 seventh fixed current source 353 ninth transistor 354 fourteenth capacitor 355 eighth and gate 360 second click signal generating circuit 361 twelfth inverter 362 eighth fixed current source 363 tenth transistor 364 Fifteen capacitor 365 ninth gate 366 thirteen inverter 400 fourth circuit 405 voltage to current conversion circuit 410 third operational amplifier 24 1377774

420 fifth transistor 421 transistor 422 transistor 423 transistor 424 transistor 425 transistor 430 switch 431 switch 432 switch 433 switch 434 switch 435 switch 450 resistor 451 resistor 452 resistor 453 resistor 454 resistor 455 resistor 460 fifth switch 461 Eight switch 462 sixth switch 465 third sampling circuit 472 output capacitor 482 switch 483 switch 484 switch 485 switch 486 seventh switch 489 ninth capacitor 490 tenth capacitor 600 voltage control loop 610 second transistor 611 resistor 612 resistor 613 resistor 620 Adding circuit 630 Second comparator CLR Clear signal FB Feedback terminal GND Ground terminal Il20 Second current Il23 Third current I420 First current 1352 Current I362 Current 1〇 Output current Ip Primary side switching current IpA Primary side switching current peak 25 1377774

Is secondary side switching current Isa secondary side switching current peak value Na auxiliary winding NP primary side winding Ns secondary side winding OUT output terminal PLS setting signal RAMP ramp signal RST first reset signal SMP latch signal STB voltage sampling signal Sds Second signal s, current loop signal Sv voltage loop signal T switching period TD1 first delay time Td2 second delay time Tdsd discharge time T〇n conduction time Tpi first pulse width Tp2 second pulse width VALY valley detection signal Vaux Reflected voltage VCC Power supply terminal DET Voltage detection terminal VS Current sensing terminal VA First signal Vdet Detection voltage Vfb Feedback signal Vin Input voltage V〇 Output voltage VpwM Switching signal VrefI Reference voltage VreF2 Reference voltage Vs Primary side switching current signal VSP peak signal

Claims (1)

1377774 X. Patent Application Range: 1. A controller for a power converter for use in a resonant power converter comprising: a first circuit, a current sensing device consuming one of the resonant power converters a second signal is generated according to a switching current of the transformer of the resonant power converter; a second circuit coupled to the transformer generates a second signal according to a discharge time of the transformer; a circuit for integrating the first signal according to the second signal to generate a third signal; and a switching circuit for receiving the third signal and a reference voltage to generate a switching signal, wherein the switching signal is used to switch the transformer To adjust the output current of one of the resonant power converters. 2. The controller of claim 1, wherein a time constant of the third circuit is associated with a switching frequency of the switching signal. 3. The controller of claim 1, further comprising a fourth circuit for generating a fourth signal according to a switching frequency of the switching signal, wherein the fourth signal is used to program the third circuit The time constant is used to integrate. 4. The controller of claim 3, wherein the fourth circuit generates a set signal at the end of the second signal, and generates a ramp signal during the on time of the switching signal, and according to the slope signal A first reset signal is generated to determine a maximum on time of the switching signal. 5. The controller of claim 4, wherein the fourth circuit comprises: a conducting circuit that receives the second signal, the conducting circuit generating the setting signal at the end of the second signal and based on The set signal generates a clear signal and a lock signal; 27 a cutoff circuit receives the switching signal, the cutoff circuit generates the ramp signal during the on time of the switching signal, and generates the first reset signal according to the slope signal And determining the maximum on time of the switching signal; and a timing circuit 'receiving the clear signal and the shackle signal to generate the fourth signal. The controller of claim 5, wherein the timing circuit further comprises: a fifth circuit for generating a clock signal; a counter for receiving the clock signal and the clear signal to generate a binary code; And a temporary buffer, sampling the binary code according to the latch signal to generate the fourth signal; wherein a time constant of the fifth circuit is associated with a time constant of the third circuit, the binary of the counter The code system is one of the switching periods of the switching signal. The controller of claim 1, wherein the switching circuit comprises: an operational amplifier that receives the third signal and the reference voltage to generate an error signal; and a comparator that receives the error signal and a slope The signal generates a second reset signal; and an output circuit 'receives a set signal to drive the switching signal to be turned on, and receives a first reset signal or the second reset signal to drive the switching signal to be turned off. The controller of claim 1, wherein the first circuit comprises: a peak detecting circuit coupled to the current sensing device to generate a peak signal according to a peak value of the switching current; A first sampling circuit is coupled to the peak detecting circuit to sample the peak signal to generate the first signal. 1377774. The controller of claim 1, wherein the second circuit comprises: a second sampling circuit coupled to the transformer, sampling a reflected voltage of the transformer, generating a sampling signal for obtaining Knowing the discharge time; a comparator, an input of which is coupled to the transformer via an offset voltage to detect the transformer. The reflected voltage, the other input of the comparator receives the sampled signal, the comparator One of the outputs outputs an end signal; and a flip-flop 'receives the switching signal and the end signal to generate the second signal, the second signal is enabled according to the cut-off state of the switching signal, and the The second signal is disabled based on the end signal. 10. The controller of claim 1, wherein the third circuit comprises: - a capacitor 'for generating the third signal; a conversion circuit for receiving the first signal to generate a first a current for charging the capacitor; a switch 'coupled between the first current and the capacitor' - the second signal controls the switch to control the first current to charge the capacitor; and - a third sampling circuit And coupling the capacitor to sample the voltage of the capacitor to generate the third signal; wherein a resistance of the conversion circuit, the capacitor and the first current system determine a time constant of the third circuit. 11. The controller of claim 10, wherein the resistance value of the resistor, the capacitance value of the capacitor, and the current value of the first current are determined by a fourth signal. 29