1374601 (1) 九、發明說明 【發明所屬之技術領域】 本發明是有關電壓鉗位電路（電壓位準變換電路）、 切換電源裝置以及用於此的半導體積體電路裝置，例如有 關適用於應用在將高電壓變換爲低電壓的切換電源裝置上 有效的技術。 【先前技術】 當作使用MOSFET的電壓紺位電路的例子，則有記載 於日本特開平6 - 694 35號公報、特開平5-3 27465號公報 〇 [專利文獻1]日本特開平6 - 69435號公報 [專利文獻2]日本特開平5 — 327465號公報 【發明內容】 [發明欲解決的課題] 於上述公報記載的電壓鉗位電路中，形成 MOSFET 之產生鉗位的輸出電壓的輸出側節點會造成浮動，漏電流 會流入到這’一旦輸出節點側上昇到閘極電壓以上時，就 會有電壓鉗位動作無法進行等的問題。 本發明之目的在於提供一種以簡單的構造而穩定地作 動的電壓鉗位電路和可高速作動的切換電源裝置。本發明 的前述及其他目的和新型的特徵，由本說明書的記述及所 附圖面即可明白。 -4- (2) (2)1374601 [用以解決課題的手段] 於本案所揭示的發明中，若簡單說明代表性發明的槪 要’即如下所記載。亦即，在供給輸入電壓的輸入端子連 接源極、汲極路徑的其中一方，且對閘極賦予應限制的特 定電壓，在源極、汲極路徑的另一方與電路的接地電位之 間，使用設置電流源的MOSFET，由上述源極、汲極路徑 的另一方，獲得對應於輸入電壓的鉗位輸出電壓。1374601 (1) VENTION DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a voltage clamping circuit (voltage level conversion circuit), a switching power supply device, and a semiconductor integrated circuit device therefor, for example, for application An effective technique for switching a high voltage to a low voltage switching power supply unit. [Prior Art] An example of a voltage snubber circuit that uses a MOSFET is described in Japanese Laid-Open Patent Publication No. Hei 6- 694-35, No. Hei 5-3-27465. [Patent Document 1] JP-A-6-69435 [Problem to be Solved by the Invention] In the voltage clamp circuit described in the above publication, an output side node of a clamped output voltage of a MOSFET is formed. This will cause floating, and leakage current will flow into this. Once the output node side rises above the gate voltage, there is a problem that the voltage clamping operation cannot be performed. SUMMARY OF THE INVENTION An object of the present invention is to provide a voltage clamping circuit which can be stably operated with a simple configuration and a switching power supply device which can be operated at a high speed. The above and other objects and novel features of the present invention will be apparent from the description and appended claims. -4- (2) (2) 1374601 [Means for Solving the Problem] In the invention disclosed in the present invention, the summary of the representative invention will be briefly described as follows. In other words, one of the source and the drain path is connected to the input terminal to which the input voltage is supplied, and a specific voltage to be limited is applied to the gate, between the other of the source and the drain path and the ground potential of the circuit. Using the MOSFET provided with the current source, the clamp output voltage corresponding to the input voltage is obtained from the other of the source and drain paths described above.
於具備：在電感串列形態地連接電容器而形成平滑輸 出電壓，且控制由輸入電壓流入到電感的電流，並使上述 輸出電壓成爲特定電壓的的第1開關元件、和當上述第1開 關元件爲OFF狀態時，將有上述電感所發生的反電動勢電 壓鉗位於特定電位的第2開關元件的切換電源電裝置中， 設有：藉由對應於上述輸入電壓的高電壓訊號利用第1驅 動電路來驅動上述第1開關元件，藉由上述高電壓利用第2 驅動電路來驅動上述第2開關元件，以較上述輸入電壓還 低的低電壓產生作動，且以由上述電容器所得到的輸出電 壓成爲特定電壓的方式形成PWM訊號而設置形成上述第1 驅動電路與第2驅動電路之驅動訊號的控制邏輯電路，並 將上述第1開關元件的驅動訊號，對應於上述低電壓而加 以電壓鉗位並回歸到上述第2驅動電路之輸入端的第1電壓 鉗位電路：和將上述第2開關元件對應於上述低電壓而加 以電壓鉗位並回歸到上述第1驅動電路的輸入端的第2電壓 鉗位電路：並以上述第1和第2開關元件不會同時成爲ON -5- (3) (3)1374601 狀態的方式進行切換控制，作爲上述電壓鉗位電路而在供 給上述驅動訊號的輸入端子連接源極、汲極路徑的其中一 方，且對閘極賦予上述低電壓，並使用在源極、汲極路徑 的另一方與電路的接地電位之間設置電流源的MOSFET， 且由上述源極、汲極路徑的另一方獲得對應驅動訊號的回 歸訊號。 藉此，能實現以高速且低消耗的電力，穩定地進行電 壓鉗位動作。 【實施方式】 [用以實施發明的最佳形態] 第1圖乃表示有關本發明的電壓鉗位電路的其中一實 施例的電路圖。同圖的電壓鉗位電路乃使由半導體積體電 路裝置的外部輸入端子所供給之較高的訊號振幅VCC的輸 入訊號Vin，朝向電壓鉗位於形成在半導體積體電路裝置 的輸入電路IB的作動電壓VDD位準所對應之輸入電壓VI的 輸入電路。 在輸入端子Vin設有作爲靜電破壞防護電路的二極體 D 1和D2。雖未特別限制，但具有該實施例的輸入電路的 半導體積體電路裝置乃具有較高的電壓VCC、和低於電壓 VCC之電壓VDD的兩個電源端子。上述二極體D1乃設置在 上述輸入端子Vin和高電源端子VCC之間，上述二極體D2 乃設置在上述輸入端子Vin和電路的接地電位VSS之間。雖 未特別限制，但上述電源電壓VCC乃如約12V之較高的電 (4) (4)1374601 壓，上述電源電壓VDD乃如約5V之較低的電壓。於第1圖 中，記號Vi η乃以代表輸入端子及輸入訊號兩者而被使用 〇 上述輸入端子Vin乃連接於構成身爲輸入節點的電壓 鉗位電路的N通道MOSFETM1之其中一方的源極、汲極路 徑。對該MOSFETM1的閘極供給電源電壓VDD作爲應限制 的電壓。由上述MOSFETM1源極、汲極路徑的另一方獲得 藉由上述電源電壓VDD被鉗位的輸出電壓，且傳送到輸入 電路IB的輸入端子。該實施例中，爲了實現穩定地進行上 述MOSFETM1所致之電壓鉗位動作，在上述源極、汲極路 徑的另一方與電路的接地電位之間設置可流入直流性的電 流成份的電流源1〇。並對於上述電流源1〇以並列形態地設 有電容器Ci » 該實施例中，輸入端子Vin乃如於同圖作爲波形所揭 示般，供給如VCC — 0V ( 12V - 0V )之較大的訊號振幅的 輸入訊號，由上述MQSFETM1的源極、汲極路徑的另一方 乃如（VDD—Vth) — 0V般地，變換成藉由電流VDD所限 制之較小的訊號振幅。而通過輸入電路IB的輸出訊號Vo乃 如於同圖作爲波形所揭示般，如VDD _ 0V ( 5V — 0V )的 CMOS振幅。在此，Vth乃爲MOSFETM1的臨限値電壓。如 果MOSFETM1的基板連接在輸入端子Vin，M0SFETM1與連 接由輸入端子Vin往輸入電路IB之方向的二極體之狀況產 生相同作用，無法得到電壓鉗位效果。又，雖然將 M0SFETM1的基板連接在VSS亦可，但臨限値電壓Vth會因 1374601 (5) ^ I. 3 基板偏壓效應而變高，來自輸入端子V in的輸入訊號不會 到達下一段的輸入電路IB的邏輯臨限，藉此有可能會引起 錯誤動作。因此，本實施例中，MOSFETM1乃形成於電性 地自基板分離的P型井區域，相關的P型井（通道區域）乃 連接於屬於上述MOSFETM1的輸出側的源極、汲極路徑的 另一方。藉此就能穩定地進行鉗位動作。 於第2圖乃表示用以說明有關本發明的電壓鉗位電路 的動作的特性圖。第2圖（A)乃爲輸出入電壓特性圖，在 輸入電壓Vih乃由0V變化成VCC時，雖然輸出電壓VI到 VDD — Vth爲止是對應於輸入電壓Vm而變化，但即使輸入 電壓Vin上昇到VDD_Vth以上，輸出電壓VI仍會成爲VDD 一 Vth的一定位準，且進行電壓鉗位動作。 第2圖（B)乃爲輸入電壓一電流特性圖，對輸入電壓 V in的上昇，僅流入電流源I。所致之一定電流。藉此對應 於電流源I。的電流値而謀求低耗電。順便一提，使用電阻 元件和二極體等的定電壓元件也能進行電壓鉗位動作，但 此時如爲了電路的高速化，降低電阻元件的電阻値時，則 輸入電流Π會變大》相反的，如爲了低耗電，提高電阻元 件的電阻値時，就會犧牲電路的高速化。 第2圖（C)乃爲電壓變化特性。該實施例中，因爲輸 入訊號Vin通過MOSFETM1的源極、汲極路徑來傳送，鉗 位輸出電壓VI會與輸入電壓Vin之上升幾近同步而變化。 根據前述第2圖（B)及第2圖（C)，於本案發明的電壓 鉗位電路中，可達到高速化與低耗電化並存。 (6) (6)1374601 於第3圖表示用以說明本發明的電壓鉗位電路的等效 電路圖。如同圖所示，於MOSFETM1之輸出側的節點VI會 形成因電路絕緣不良等之高電阻LR所致之漏電流路徑的 情形、電流源1〇不存在的情形下，雖電壓鉗位動作會無法 作動，但能藉由設置電流源1〇抑制上述輸出節點VI的電位 上昇’進行穩定的電壓鉗位動作。因此，電流源1〇只要設 定在大於不會被視爲不良的漏電流的微小電流，就可如第 2圖（B)地達成低耗電化。 於第4圖表示說明本發明的電壓鉗位電路的等效電路 圖。如同圖所示，於MOSFETM1的源極、汲極間存在著寄 生電容Cds。當輸入訊號Vin因該寄生電容Cds變化成如 VCC的高電壓時，會有因耦合發生使輸出側VI變化成電源 電壓VDD以上的問題。爲了避免此問題，於電流源1〇並列 形態地設置電容器Ci。藉此，寄生電容Cds與電容器Ci會 串列形態地被連接，並對應於其電容比的反比而將輸入電 壓Vin分壓，上述輸出側VI就不會形成爲電源電壓VDD以 上。再者，於輸入電路IB中，雖然構成輸入電路的 MOSFET的閘極電容是存在於MOSFETM1的另一方的端子 與接地電壓VSS之間或MOSFETM1的另一方的端子與電源 電壓VDD之間等，但僅依靠該閘極電容，仍會如上述般， 會因耦合而輸出側VI變化成電源電壓VDD以上。因此，上 述電容器Ci即使與輸入電路IB的輸入電容相比仍充分地較 大。 於第5圖表示有關本發明的電壓鉗位電路的其中一實 -9- (7) (7)1374601 施例的具體性電路圖。MOSFETM1乃爲與前述第1圖的 MOSFETM1相同，電容器Ci乃藉由MOS電容所構成。輸入 電路1B乃由：以P通道MOSFETM3與N通道MOSFETM4所構 成之輸入側的CMOS反相電路、和以P通道MOSFETM5與N 通道MOSFETM6所構成之輸出側的CMOS反相電路的並列 電路所構成。雖未有特別限制，但在輸出側的C Μ 0 S反相 電路的輸入端子與電路的接地電位之間，係設有Ν通道 MOSFETM7 ,輸出訊號V。會回歸到閘極。 藉此，輸入側的CMOS反相電路，係在輸出訊號Vo爲 低位準時，M0SFETM7成爲OFF狀態，而具有對應於 MOSFETM3和M4之電導比的第1邏輯臨限値。對此，在輸 出訊號Vo爲高位準時，M0SFETM7成爲ON狀態， MOSFETM4和M0SFETM7成爲並聯形態，變化成低於上述 第1邏輯臨限値的邏輯臨限値電壓。藉此，於輸入電路IB 中，具有當輸入訊號由低位準變化成高位準時，成爲上述 較高的第1邏輯臨限値電壓，當由高位準變化成低位準時 ，成爲較上述還低的第2邏輯臨限値的滯後傳送特性。藉 此，在輸入訊號Vin成爲上述第1邏輯臨限値電壓以上時， 如不成爲低於其的第2邏輯臨限値電壓以下的話，則輸出 訊號Vo不會變化，故當輸入訊號Vin在輸入電路的邏輯臨 限値電壓附近時，即使發生雜訊，輸出訊號Vo仍不會回應 於此而變化，所以能進行穩定的輸入訊號的取得。 該實施例中，電流源1〇是藉由降壓型的N通道 MOSFETM2所構成。該MOSFETM2乃連接著閘極和源極， -10- (8) (8)1374601 藉此進行定電流動作。該電流源Ιο可爲以對閘極施加特定 電壓之增強型的Ν通道MOSFET所構成，也可爲以多結晶矽 層等所構成的高電阻元件所構成。於同圖中’省略前述靜 電破壞防護用的二極體。 構成電容器Ci的MOSFET雖未特別限制’但可採用Ρ通 道MOSFET的閘極電容。該閘極電容乃例如採用 MOSFETM4等相當於普通MOSFET數十個量的MOSFET所構 成，具有約如lpF的電容値的方式所形成。順便一提，此 時的MOSFETM1乃如通道寛W爲20/z m、通道長L爲800nm ，MOSFETM2乃如通道寛W爲20// m、通道長L爲8// m地分 別形成較大的尺寸。對此，構成CMOS反相電路的N通道 M0SFETM4乃如通道寬W爲8/zm、通道長L爲2//m，N通道 M0SFETM6乃如通道寬W爲7 /z m、通道長L爲8OOnm地分別 成爲較小的尺寸。 於第6圖表示用以說明有關本發明的電壓鉗位電路的 動作波形圖於第6圖中，表示輸入電壓Vin、甜位電壓VI 及輸出電壓Vo的實際測定波形圖。電壓鉗位電路乃爲前述 第5圖所示的電路，輸入電壓Vin乃爲如0-1 2V的高振幅， 低電壓VDD爲5V。如同圖所示，相對於輸入電壓Vin而得 到如VIDD — Vth ( MOSFETM 1的臨限値電壓）的鉗位電壓 VI，通過具有前述滯後特性的2個CMOS反相電路，得到 CMOS位準的輸出電壓Vo。 於第7圖表示呈現以有關本發明的電壓鉗位電路的電 容器Ci的電容値作爲參數的輸入電壓17ιη和鉗位電壓VI之 -11 - 1374601 Ο) 關係的上升特性圖。在電容器Ci=0，亦即未連接電容器 Ci的狀態，藉由利用MOSFETM1的源極、汲極間的寄生電 容Cds的耦合，鉗位電壓VI也上昇約7.8V，然後藉由前述 電流源1〇進行放電而緩緩地下降。亦即利用MOSFETM3和 M4的CMOS反相電路的輸入電容較小，藉由與上述寄生電 容Cds的分壓，亦上述約7.8V上昇。 如上述電容器Ci的電容値爲Ci=0.5pF時、Ci = lpF時 、Ci = 1.5pF時、Ci = 2pF時，鉗位電壓VI可抑制成約3.6V 、3V、2.6V、2.2V。因爲電容器Ci亦爲輸入電路之輸入電 容，若提高電容値，通過MOSFETM1的鉗位電壓VI爲止的 充電時間，或上升時的放電時間也會變長，故本實施例設 定在認爲所需要最小的Ci= lpF。在上述寄生電容Cds的耦 合動作乃適當設定上述電容器Ci的電容値，藉此利用該耦 合就能高速進行鉗位電壓VI的上升、下降。 於第8圖表示有關本發明的電壓鉗位電路的輸入電壓 Vin的上升特性圖。同圖乃放大表示第6圖的下降部分的時 間。該實施例的電壓鉗位電路乃輸入電壓Vin以Ins由0V上 升至12V時，以與此幾近相同的時間，藉用在前述寄生電 容Cds的耦合而上升到3V附近，藉由在M0SFETM1的充電 動作，於最後上升到VDD(5V) - Vth爲止。在由2段的 CMOS反相電路所構成之輸入電路IB中，以2ns左右的訊號 傳送延遲時間而將輸出電壓Vo上升至高位準。 於第9圖表示有關本發明的電壓鉗位電路的輸入電壓 Vin的下降特性圖。同圖乃放大表示第6圖的下降部分的時 -12- (10) (10)1374601 間。該實施例的電壓鉗位電路乃輸入電壓Vin會以lns* 1 2V下降至ον ’以與於此幾近相同的時間而利用在前述寄 生電容Cds的耦合和利用在MOSFETM1的放電動作而下降 到輸入電路IB的邏輯臨限値電壓以下爲止。對於最後成爲 0V ’則更需要lns ’但如前述，以輸入電路IB的觀點而言 ’則如上述般爲等於0V者。由2段的CMOS反相電路所形成 的輸入電路IB中’以2ns左右的訊號傳送延遲時間而將輸 出電壓Vo下降到低位準。 於第10圖表示使用有關本發明的電壓鉗位電路的切換 電源裝置的其中一實施例的區塊圖。該實施例的切換電源 裝置乃由控制1C和驅動1C所形成，屬於將由高電壓所構成 的輸入電壓Vin降壓到由低電壓所構成的輸出電壓Vout的 降壓型切換電源。雖未特別限制，但上述降壓型切換電源 是屬於將100V的商用交流電壓變換成像是12V的直流電壓 所形成的高電壓，進一步變換成用於構成微電腦的CPU ( 中央處理裝置）、記憶體電路等之作動的約3V左右的低電 壓。 係設置：將電容器C0串聯形態地連接於電感L0而形 成平滑輸出電壓Vout，並控制從如約12V的輸入電壓Vin流 入到上述電感L0的電流，而使上述輸出電壓Vout成爲特定 電壓的驅動1C的第1開關元件、和將當上述第1開關元件爲 OFF狀態時發生在上述電感L0的反電動勢電壓鉗位於特定 電位（PGND)的第2開關元件。爲了使上述輸出電壓Vout 成爲特定電壓，以電阻R1和R2分壓，而輸出電壓Vout會供 (11) (11)1374601 給到設置在控制1C的錯誤放大器EA，且與特定電壓相比 。該錯誤放大EA的輸出電壓、和以三角波發生電路TWG所 形成的三角波會供給到電壓比較電路CMP，其輸出訊號會 傳送到控制電路CONT而形成PWM (脈衝寬調變）訊號。 該PWM訊號乃作爲上述驅動1C的上述第1開關元件和第2開 關元件的控制訊號使用。亦即藉由PWM訊號來控制上述第 1開關元件的ON期間，並進行流入到上述電感LO之電流的 控制。 控制1C雖未特別限制，但供給像是12V的高電壓VDD ，上述錯誤放大器的輸入電壓因是較小的電壓，故藉由內 部電源電路形成5V左右的低電壓，使前述錯誤放大器EA 、比較器CMP及三角波發生電路TWG和形成上述PWM訊號 的控制電路CONT動作。因此，控制1C亦可作爲直接供給 像是5V的低電壓者。 於上述驅動1C中，對於上述電派電壓端子VDD雖未特 別限制，但可供給與輸入電壓Vin相同之像是12V的高電壓 。端子REG係連接著供後述之內部降壓電源電路Reg的輸 出電壓穩定化的電容器C2的外部端子，端子VLDRV乃如後 述，供給驅動上述第2開關元件的驅動電路的作動電壓。 端子BOOT係如後述般，連接用以將驅動上述第1開關元件 之驅動電路的作動電壓加以昇壓的自舉電容C1。在該電容 C1的另一方的電極乃連接在設有電感LO的輸出端子LX。 端子DISBL乃輸入進行驅動1C之動作控制（ΟΝ/OFF)的 動作控制訊號。 -14- (12) (12)1374601 於第11圖表示第10圖的驅動1C的其中一實施例的區塊 圖。上述第1開關元件乃藉由功率MOSFETQ1所構成，且藉 由第1驅動電路（高側驅動器高側驅動器）HSD且藉由對 應上述輸入電壓Vin的昇壓電壓訊號被驅動。亦即因 MOSFETQ1是以N通道型所構成，故對閘極供給對應於輸 入電壓Vin的驅動電壓，而使輸出電壓僅降低臨限値電壓 量。 在此，爲了實現可對電感LO供給輸入電壓Vin，當 MOSFETQ1爲OFF狀態時，亦即輸出端子LX藉由身爲鉗位 用之開關元件的M0SFETQ2的ON狀態，幾近在電路的接地 電位PGND時，通過肖特基能障二極體SBD(Schottky-barrier diode)並藉由內部電流Reg所形成的約5V的電壓而 將自舉電容C1加以充電。而在M0SFETQ2成爲OFF狀態， M0SFETQ1成爲ON狀態時，藉由自舉電容C1伴隨 M0SFETQ1之源極輸出電壓的上升，端子BOOT亦僅會上升 蓄存於上述自舉電容C1的電壓，而該電壓會通過第1驅動 電路HSD傳送到M0SFETQ1的閘極。藉此，在MOSFETQ1的 閘極，對於輸入電壓Vin來說也僅昇高蓄存在上述自舉電 容C1的電壓，輸出端子LX的電壓可昇高到電壓Vin。 該實施例中，屬於上述第2開關元件的MOSFETQ2可藉 由第2驅動電路（低側驅動器）LSD利用上述高電壓加以 驅動。就是以從端子VLDRV所賦予的電壓使第2驅動電路 LSD作動。於上述端子VLDRV可如前述施加12V亦可，供 給5 V左右的低電壓亦可。此乃使用者可任意設定。在以如 -15- (13) (13)1374601 上述12V的高電壓動作的情形下，MOSFETQ2可減小〇N電 阻値，且可減低切換電源的無效電流。 於前述控制1C中，藉由以低於上述輸入電壓的低電壓 所作動之控制電路CONT，以由上述電容器CO所獲得的輸 出電壓Vout爲特定電壓（例如3V左右）的方式形成PWM訊 號。於驅動1C中，形成上述第1驅動電路HSD和第2驅動電 路LSD的驅動訊號的控制邏輯電路，乃如同圖中以虛線所 示，由以利用電源電路Reg所形成的低電壓而作動的閘極 電路G1〜G5所構成》於切換電源中，身爲上述第1開關元 件的M0SFETQ1和身爲第2開關元件的M0SFETQ2，爲了防 止因貫通電流的元件破壞，必須同時以不會成爲ON狀態 的方式設定空載時間。 於是，將供給至身爲第1開關元件之M0SFETQ1的閘極 之驅動訊號，藉由以前述第1圖或第5圖所示的電壓鉗位電 路CP3對應於上述低電壓，將供給至被輸入至電壓鉗位電 路CP3之輸入節點的M0SFETQ1的閘極的驅動訊號加以電 壓鉗位，而形成傳送到上述第2驅動電路LSD之輸入訊號 的閘極電路GL5的回歸訊號。將供給至身爲上述第2開關 元件的M0SFETQ2的閘極之驅動訊號，藉由前述第1圖或第 5圖所示的電壓鉗位電路CP2對應於上述低電壓，將供給致 被輸入至電壓鉗位電路CP2的輸入節點的MOSFETQ2的閘 極的驅動訊號加以電壓鉗位，而形成傳送到上述第1驅動 電路HSD之輸入訊號的閘極電路G4的回歸訊號。亦即，電 壓鉗位電路CP3和CP2係作爲將如上述的高振幅的驅動訊 -16- (14) (14)1374601 號變換成低振幅的訊號的位準移位電路而作動，且第1和 第2開關元件不會同時成爲ON狀態，也就是說接受 MOSFETQ1爲OFF狀態的訊號貝丨J使MOSFETQ2成爲ON狀態， 且接受MOSFETQ2爲OFF狀態的訊號則使MOSFETQ1成爲ON 狀態來設定空載時間。 該實施例中，作爲進行如前述的位準移位動作的電路 ，使用電壓鉗位電路。該實施例的電壓鉗位電路乃其傳送 特性爲高速，MOSFETQ1和Q2不會同時成爲ON狀態的方式 來設定減少空載時間。亦即，如果切換周期相同，相對於 空載時間較少，則能以更高的精度來進行電壓控制。 因閘極電路G4的輸出訊號如前述般，身爲低電壓訊號 ，故透過變換爲高電壓訊號的位準移位電路LSU而作爲上 述第1驅動電路HSD的輸入訊號。而該位準移位電路LSU及 第1驅動電路HSD則讓輸出端子LX的電位會成爲電路的基 準電位。上述控制邏輯電路、電源電路Reg及PWM的輸入 電路IB、以下說明的電壓鉗位電路C P 1、及低位準的檢測 電路UVL則成爲由端子CGND所供給的電路的基準電位。 亦即將該些電路的接地電位CGND分爲用以鉗位前述電感 的反電動勢電壓之接地電位PGND，而謀求作動的穩定化 來自控制驅動1C之動作有效/無效（〇n/〇FF)的 DISBL的輸入訊號可在5V〜12 V的訊號振幅使用。因此， 假設在像是12V高的訊號振幅使之作動的情形，設置如第1 圖所示的電壓鉗位電路CP1。藉此，即使在如12V之較高 -17- (15) (15)1374601 訊號振幅的作動，還是能進行低耗電的作動。假設供給像 是5 V的低電壓的輸入訊號的情形，則雖然不會進行實質性 的鉗位動作，但作動本身並不會受到任何影響。 若根據如上述的實施例，就能以高速且低耗電而穩定 地進行電壓鉗位動作，又可藉由高速回應輸入電壓之變化 的電壓鉗位動作，縮短切換電源裝置的第1開關元件與第2 開關元件之切換的空載時間。 於第12圖表示第10圖的驅動1C的其它實施例的區塊圖 。該實施例中，驅動1C乃成爲將3個矽晶片密封於一個封 裝體所構成的多晶片模組構造。亦即功率MOSFETQ1及 MOSFETQ2乃如在同圖以虛線所示，分別形成在別的矽等 的半導體基板上（矽晶片）CHP1和CHP2，將構成上述功 率MOSFETQ1及MOSFETQ2以外的驅動1C的電路形成在一個 矽等的半導體基板上（矽晶片）CHP3，該些會被密封在 一個封裝體而構成上述驅動1C。於此種多晶片模組構成的 驅動1C中，乃如前述第1 1圖所示，相較於將構成驅動1C的 所有電路形成在一個半導體基板上，能以低成本製作高性 能的產品。 以上根據本發明人所完成的發明，根據前述實施形態 已具體說明，但本發明並不限於前述實施形態，在不脫離 其主旨的範圍可做各種變更。例如在第1圖、第6圖中， MOSFETM1的大小、電容器Ci的電容値及電流源1〇的電流 乃因應於電壓鉗位用途而適當設定者。本發明可廣泛應用 於使用在電壓鉗位電路（電壓位準變換電路）及切換電源 -18- (16) (16)1374601 裝置的半導體積體電路裝置。 【圖式簡單說明】 [第1圖]表示有關本發明的電壓鉗位電路的其中一實 施例的電路圖。 [第2圖]說明有關本發明的電壓鉗位電路的動作的特 性圖。 [第3圖]說明本發明的電壓鉗位電路的等效電路圖。 [第4圖]說明本發明的電壓鉗位電路的等效電路圖。 [第5圖]表示有關本發明的電壓鉗位電路的其一實施 例的具體電路圖。 [第6圖]說明有關本發明的電壓鉗位電路的動作波形 圖。 [第7圖]表示串接於有關本發明的電壓鉗位電路的輸 入電壓和鉗位電壓的關係的特性圖。 [第8圖]有關本發明的電壓鉗位電路的輸入電壓的上 升特性圖。 [第9圖]有關本發明的電壓鉗位電路的輸入電壓的下 降特性圖。 [第10圖]表示採用有關本發明的電壓鉗位電路的切換 電源裝置的其中一實施例的區塊圖。 [第11圖]表示第10圖的驅動1C的其中一實施例的區塊 圖。 [第12圖]表示第10圖的驅動1C的其它實施例的區塊圖 -19- (17) (17)1374601 【主要元件符號說明】A first switching element that forms a smooth output voltage by connecting a capacitor in an inductor series, controls a current flowing from an input voltage to an inductor, and causes the output voltage to be a specific voltage, and the first switching element In the OFF state, the switching power supply device of the second switching element having the specific potential is clamped by the counter electromotive voltage generated by the inductance, and the first driving circuit is provided by the high voltage signal corresponding to the input voltage. The first switching element is driven to drive the second switching element by the second driving circuit by the high voltage, and is operated at a low voltage lower than the input voltage, and the output voltage obtained by the capacitor is obtained. Forming a PWM signal to form a PWM signal, and providing a control logic circuit for forming a driving signal of the first driving circuit and the second driving circuit, and clamping a driving signal of the first switching element to the low voltage and clamping the voltage Returning to the first voltage clamp circuit at the input end of the second drive circuit: and the second switch a second voltage clamp circuit that is voltage-clamped and returned to the input end of the first drive circuit in response to the low voltage: the first and second switching elements are not simultaneously turned ON -5- (3) (3) Switching control is performed in a state of 1374601, and one of a source and a drain path is connected to an input terminal to which the driving signal is supplied as the voltage clamping circuit, and the low voltage is applied to the gate, and is used in the source. A MOSFET of a current source is disposed between the other of the pole and the drain path and the ground potential of the circuit, and the other of the source and the drain path obtains a regression signal corresponding to the driving signal. As a result, it is possible to stably perform the voltage clamping operation with high-speed and low-consumption power. [Embodiment] [Best Mode for Carrying Out the Invention] Fig. 1 is a circuit diagram showing an embodiment of a voltage clamping circuit according to the present invention. The voltage clamping circuit of the same figure is used to clamp the input signal Vin of the higher signal amplitude VCC supplied from the external input terminal of the semiconductor integrated circuit device toward the voltage clamped to the input circuit IB formed in the semiconductor integrated circuit device. The input circuit of the input voltage VI corresponding to the voltage VDD level. The input terminals Vin are provided with diodes D 1 and D2 as electrostatic breakdown preventing circuits. Although not particularly limited, the semiconductor integrated circuit device having the input circuit of this embodiment has two power supply terminals of a higher voltage VCC and a voltage VDD lower than the voltage VCC. The diode D1 is provided between the input terminal Vin and the high power supply terminal VCC, and the diode D2 is provided between the input terminal Vin and the ground potential VSS of the circuit. Although not particularly limited, the above-mentioned power supply voltage VCC is a high electric (4) (4) 1,374,601 voltage of about 12 V, and the above-mentioned power supply voltage VDD is a lower voltage of about 5 V. In Fig. 1, the symbol Vi η is used to represent both the input terminal and the input signal, and the input terminal Vin is connected to the source of one of the N-channel MOSFETs M1 constituting the voltage clamping circuit as the input node. , bungee path. The gate of the MOSFET M1 is supplied with a power supply voltage VDD as a voltage to be limited. An output voltage clamped by the power supply voltage VDD is obtained from the other of the source and drain paths of the MOSFET M1, and is transmitted to an input terminal of the input circuit IB. In this embodiment, in order to stably perform the voltage clamping operation by the MOSFET M1, a current source 1 capable of flowing a DC current component is provided between the other of the source and drain paths and the ground potential of the circuit. Hey. A capacitor Ci is provided in parallel with the current source 1〇. In this embodiment, the input terminal Vin is supplied with a larger signal such as VCC — 0V ( 12V - 0V ) as disclosed in the same figure as a waveform. The input signal of the amplitude is converted into a smaller signal amplitude limited by the current VDD by the other of the source and drain paths of the MQSFET M1 as (VDD - Vth) - 0V. The output signal Vo through the input circuit IB is as shown in the same figure as the waveform, such as CMOS amplitude of VDD _ 0V (5V - 0V). Here, Vth is the threshold voltage of MOSFETM1. If the substrate of the MOSFET M1 is connected to the input terminal Vin, the MOSFET M1 has the same function as the diode connected to the input terminal Vin to the input circuit IB, and the voltage clamping effect cannot be obtained. Moreover, although the substrate of the MOSFET M1 is connected to the VSS, the threshold voltage Vth is increased by the bias voltage of the 1374601 (5) ^ I. 3 substrate, and the input signal from the input terminal V in does not reach the next segment. The logic of the input circuit IB is limited, which may cause an erroneous action. Therefore, in the present embodiment, the MOSFET M1 is formed in a P-type well region electrically separated from the substrate, and the associated P-type well (channel region) is connected to the source and drain paths belonging to the output side of the MOSFET M1. One party. Thereby, the clamping operation can be performed stably. Fig. 2 is a characteristic diagram for explaining the operation of the voltage clamp circuit of the present invention. Fig. 2(A) is an output voltage characteristic diagram. When the input voltage Vih is changed from 0V to VCC, the output voltage VI varies depending on the input voltage Vm until VDD_Vth, but the input voltage Vin rises. Above VDD_Vth, the output voltage VI will still be a positioning target of VDD-Vth, and the voltage clamping action will be performed. Fig. 2(B) is an input voltage-current characteristic diagram, and only the current source I flows into the rise of the input voltage V in . A certain current caused by it. This corresponds to the current source I. The current is low and the power consumption is low. By the way, the voltage clamping operation can be performed using a constant voltage element such as a resistor element or a diode. However, if the resistance 値 of the resistance element is lowered for the speed of the circuit, the input current Π becomes large. On the contrary, if the resistance 値 of the resistance element is increased for low power consumption, the speed of the circuit is sacrificed. Figure 2 (C) shows the voltage change characteristics. In this embodiment, since the input signal Vin is transmitted through the source and drain paths of the MOSFET M1, the clamp output voltage VI changes in synchronism with the rise of the input voltage Vin. According to the second (B) and second (C) aspects of the present invention, in the voltage clamp circuit of the present invention, high speed and low power consumption can be achieved. (6) (6) 1374601 An equivalent circuit diagram for explaining the voltage clamp circuit of the present invention is shown in Fig. 3. As shown in the figure, the node VI on the output side of the MOSFET M1 forms a leakage current path due to high resistance LR such as poor circuit insulation, and in the case where the current source 1 〇 does not exist, the voltage clamping operation cannot be performed. Actuation, but it is possible to suppress the potential rise of the output node VI by setting the current source 1 ' to perform a stable voltage clamping operation. Therefore, if the current source 1 is set to be smaller than a small current which is not regarded as a defective leakage current, the low power consumption can be achieved as shown in Fig. 2(B). Fig. 4 is a view showing an equivalent circuit diagram of the voltage clamp circuit of the present invention. As shown in the figure, a parasitic capacitance Cds exists between the source and the drain of the MOSFET M1. When the input signal Vin changes to a high voltage such as VCC due to the parasitic capacitance Cds, there is a problem that the output side VI changes to the power supply voltage VDD or more due to the coupling. In order to avoid this problem, the capacitor Ci is arranged side by side in the form of a current source 1?. Thereby, the parasitic capacitance Cds and the capacitor Ci are connected in series, and the input voltage Vin is divided in accordance with the inverse ratio of the capacitance ratio thereof, and the output side VI is not formed as the power supply voltage VDD or higher. Further, in the input circuit IB, the gate capacitance of the MOSFET constituting the input circuit exists between the other terminal of the MOSFET M1 and the ground voltage VSS or between the other terminal of the MOSFET M1 and the power supply voltage VDD. Only by relying on the gate capacitance, as described above, the output side VI changes to the power supply voltage VDD or more due to the coupling. Therefore, the capacitor Ci described above is sufficiently large even compared to the input capacitance of the input circuit IB. Fig. 5 is a circuit diagram showing a specific embodiment of the voltage clamp circuit of the present invention, which is -9-(7)(7)1374601. The MOSFET M1 is the same as the MOSFET M1 of Fig. 1 described above, and the capacitor Ci is constituted by a MOS capacitor. The input circuit 1B is composed of a CMOS inverter circuit on the input side composed of a P-channel MOSFET M3 and an N-channel MOSFET M4, and a parallel circuit of a CMOS inverter circuit on the output side composed of a P-channel MOSFET M5 and an N-channel MOSFET M6. Although there is no particular limitation, a channel MOSFET M7 is provided between the input terminal of the C Μ 0 S inverting circuit on the output side and the ground potential of the circuit, and the output signal V is output. Will return to the gate. Thereby, the CMOS inverter circuit on the input side is in a state where the output signal Vo is at a low level, and the MOSFET M7 is turned off, and has a first logic threshold corresponding to the conductance ratio of the MOSFETs M3 and M4. On the other hand, when the output signal Vo is at the high level, the MOSFET M7 is turned on, and the MOSFET M4 and the MOSFET M7 are in a parallel configuration and are changed to a logic threshold voltage lower than the first logic threshold. Therefore, in the input circuit IB, when the input signal changes from a low level to a high level, the first logic threshold voltage becomes higher, and when it changes from a high level to a low level, it becomes lower than the above. 2 Logic delay 値 lag transmission characteristics. Therefore, when the input signal Vin is equal to or higher than the first logic threshold voltage, if the voltage is not lower than the second logic threshold voltage, the output signal Vo does not change, so when the input signal Vin is When the logic threshold of the input circuit is near the voltage, even if noise occurs, the output signal Vo does not change depending on this, so that stable input signals can be obtained. In this embodiment, the current source 1 is formed by a step-down N-channel MOSFET M2. The MOSFET M2 is connected to the gate and the source, and -10- (8) (8) 1374601 is used for constant current operation. The current source Ιο may be an enhancement type Ν channel MOSFET to which a specific voltage is applied to the gate, or may be a high resistance element formed of a polycrystalline germanium layer or the like. In the same figure, the above-mentioned diode for electrostatic damage protection is omitted. The MOSFET constituting the capacitor Ci is not particularly limited, but the gate capacitance of the Ρ channel MOSFET can be employed. The gate capacitance is formed by, for example, a MOSFET equivalent to several tens of MOSFETs such as MOSFET M4, and has a capacitance 约 of about lpF. By the way, at this time, the MOSFET M1 has a channel 寛W of 20/zm and a channel length L of 800 nm, and the MOSFET M2 has a larger channel such as a channel 寛W of 20//m and a channel length L of 8//m. size. In this regard, the N-channel MOSFET M4 constituting the CMOS inverter circuit has a channel width W of 8/zm and a channel length L of 2//m, and the N-channel MOSFET M6 has a channel width W of 7 /zm and a channel length L of 8 00 nm. They become smaller sizes respectively. Fig. 6 is a view showing an operation waveform chart for explaining a voltage clamp circuit according to the present invention. Fig. 6 is a view showing actual measurement waveforms of an input voltage Vin, a sweet bit voltage VI, and an output voltage Vo. The voltage clamp circuit is the circuit shown in the above fifth embodiment, and the input voltage Vin is a high amplitude such as 0-1 2V, and the low voltage VDD is 5V. As shown in the figure, the clamp voltage VI such as VIDD — Vth (the threshold voltage of MOSFET M 1 ) is obtained with respect to the input voltage Vin, and the CMOS level output is obtained by the two CMOS inverter circuits having the aforementioned hysteresis characteristics. Voltage Vo. Fig. 7 is a graph showing the rise characteristic of the relationship between the input voltage 17 i of the capacitor Ci of the voltage clamp circuit of the present invention as a parameter and the clamp voltage VI of -11 - 1374601 Ο). In the state where the capacitor Ci=0, that is, the capacitor Ci is not connected, the clamping voltage VI also rises by about 7.8V by the coupling of the source and drain parasitic capacitance Cds of the MOSFET M1, and then the current source 1 is used. 〇 The discharge is slowly lowered. That is, the input capacitance of the CMOS inverter circuit using the MOSFETs M3 and M4 is small, and the above-mentioned parasitic capacitance Cds is also divided by about 7.8 V as described above. When the capacitance 値 of the capacitor Ci described above is Ci = 0.5 pF, Ci = lpF, Ci = 1.5 pF, and Ci = 2 pF, the clamp voltage VI can be suppressed to about 3.6 V, 3 V, 2.6 V, and 2.2 V. Since the capacitor Ci is also the input capacitance of the input circuit, if the capacitance 値 is increased, the charging time until the clamp voltage VI of the MOSFET M1 or the discharge time during the rise becomes longer, so the present embodiment sets the minimum required Ci = lpF. In the coupling operation of the parasitic capacitance Cds, the capacitance 値 of the capacitor Ci is appropriately set, whereby the clamping voltage VI can be increased and decreased at a high speed by the coupling. Fig. 8 is a graph showing the rise characteristic of the input voltage Vin of the voltage clamp circuit of the present invention. The same figure is an enlarged view of the time of the falling portion of Fig. 6. In the voltage clamping circuit of this embodiment, when the input voltage Vin rises from 0 V to 12 V in Ins, it rises to around 3 V by the coupling of the parasitic capacitance Cds in the same time, by the MOSFET M1. The charging action lasts until VDD (5V) - Vth. In the input circuit IB composed of two stages of CMOS inverter circuits, the output voltage Vo is raised to a high level by a signal transmission delay time of about 2 ns. Fig. 9 is a graph showing the drop characteristic of the input voltage Vin of the voltage clamp circuit of the present invention. The same figure is enlarged to show the time between the -12- (10) (10) 1374601 of the falling portion of Figure 6. The voltage clamping circuit of this embodiment is such that the input voltage Vin drops to ον ' at lns* 1 2V to the same time as the above, and the coupling of the parasitic capacitance Cds is utilized and the discharge operation of the MOSFET M1 is used to drop to The logic threshold of the input circuit IB is below the voltage. For the last time to become 0V', lns' is more required. However, as described above, from the viewpoint of the input circuit IB, it is equal to 0V as described above. In the input circuit IB formed by the two-stage CMOS inverter circuit, the output voltage Vo is lowered to a low level by a signal transmission delay time of about 2 ns. Fig. 10 is a block diagram showing an embodiment of a switching power supply unit using the voltage clamping circuit of the present invention. The switching power supply device of this embodiment is formed by the control 1C and the drive 1C, and belongs to a step-down switching power supply that steps down the input voltage Vin composed of a high voltage to an output voltage Vout composed of a low voltage. The buck switching power supply is a high voltage formed by converting a commercial AC voltage of 100 V into a DC voltage of 12 V, and further converting it into a CPU (Central Processing Unit) and a memory for constituting a microcomputer. A low voltage of about 3V, which is operated by a circuit or the like. The system is configured to connect the capacitor C0 in series to the inductor L0 to form a smooth output voltage Vout, and control the current flowing from the input voltage Vin such as about 12 V to the inductor L0 to make the output voltage Vout a specific voltage. The first switching element and the second switching element that clamps the counter electromotive voltage generated in the inductance L0 when the first switching element is in the OFF state at a specific potential (PGND). In order to make the above-mentioned output voltage Vout a specific voltage, the resistors R1 and R2 are divided, and the output voltage Vout is supplied to (11) (11) 1374601 to the error amplifier EA set in the control 1C, and compared with the specific voltage. The output voltage of the erroneous amplification EA and the triangular wave formed by the triangular wave generating circuit TWG are supplied to the voltage comparison circuit CMP, and the output signal is transmitted to the control circuit CONT to form a PWM (Pulse Width Modulation) signal. The PWM signal is used as a control signal for the first switching element and the second switching element of the driving 1C. That is, the ON period of the first switching element is controlled by the PWM signal, and the current flowing into the inductor LO is controlled. The control 1C is not particularly limited, but is supplied with a high voltage VDD of 12 V. Since the input voltage of the error amplifier is a small voltage, a low voltage of about 5 V is formed by the internal power supply circuit, and the error amplifier EA is compared. The CMP and the triangular wave generating circuit TWG and the control circuit CONT forming the PWM signal operate. Therefore, the control 1C can also be used as a direct supply to a low voltage such as 5V. In the above-described driving 1C, the above-described electronic power voltage terminal VDD is not particularly limited, but a high voltage of 12 V which is the same as the input voltage Vin can be supplied. The terminal REG is connected to an external terminal of a capacitor C2 for stabilizing the output voltage of the internal step-down power supply circuit Reg, which will be described later, and the terminal VLDRV is supplied with an operating voltage of a drive circuit for driving the second switching element as will be described later. The terminal BOOT is connected to a bootstrap capacitor C1 for boosting the operating voltage of the driving circuit for driving the first switching element, as will be described later. The other electrode of the capacitor C1 is connected to an output terminal LX provided with an inductance LO. The terminal DISBL is an operation control signal for inputting the operation control (ΟΝ/OFF) for driving 1C. -14- (12) (12) 1374601 A block diagram of one embodiment of the drive 1C of Fig. 10 is shown in Fig. 11. The first switching element is constituted by the power MOSFET Q1, and is driven by a first driving circuit (high side driver high side driver) HSD by a boosted voltage signal corresponding to the input voltage Vin. That is, since the MOSFET Q1 is constituted by the N-channel type, the driving voltage corresponding to the input voltage Vin is supplied to the gate, and the output voltage is reduced only by the threshold voltage. Here, in order to supply the input voltage Vin to the inductor LO, when the MOSFET Q1 is in the OFF state, that is, the output terminal LX is in the ON state of the MOSFET Q2 which is the switching element for clamping, the ground potential PGND of the circuit is almost At this time, the bootstrap capacitor C1 is charged by a Schottky-barrier diode and a voltage of about 5 V formed by the internal current Reg. When the MOSFET Q2 is turned off and the MOSFET Q1 is turned on, the bootstrap capacitor C1 increases the source output voltage of the MOSFET Q1, and the terminal BOOT also rises only the voltage stored in the bootstrap capacitor C1. The gate is transferred to the gate of the MOSFET Q1 through the first drive circuit HSD. Thereby, at the gate of the MOSFET Q1, only the voltage of the above-described bootstrap capacitor C1 is raised for the input voltage Vin, and the voltage of the output terminal LX can be raised to the voltage Vin. In this embodiment, the MOSFET Q2 belonging to the second switching element can be driven by the high voltage by the second drive circuit (low side driver) LSD. That is, the second drive circuit LSD is operated by the voltage given from the terminal VLDRV. The terminal VLDRV may be applied with 12 V as described above, and may be supplied with a low voltage of about 5 V. This can be arbitrarily set by the user. In the case of a high voltage operation of 12V as described above, -15-(13) (13) 1374601, MOSFET Q2 can reduce 〇N resistance 値 and can reduce the reactive current of the switching power supply. In the above control 1C, the PWM signal is formed such that the output voltage Vout obtained by the capacitor CO is a specific voltage (e.g., about 3 V) by the control circuit CONT which is operated at a lower voltage than the input voltage. In the drive 1C, the control logic circuit for forming the drive signals of the first drive circuit HSD and the second drive circuit LSD is as shown by a broken line in the figure, and is operated by a low voltage formed by the power supply circuit Reg. In the switching power supply, the MOSFETs Q1 that are the first switching elements and the MOSFETs Q2 that are the second switching elements are required to be in an ON state at the same time in order to prevent destruction of the components due to the through current. Mode sets the dead time. Then, the driving signal supplied to the gate of the MOSFET Q1 which is the first switching element is supplied to the input by the voltage clamp circuit CP3 shown in the first or fifth embodiment corresponding to the low voltage. The drive signal of the gate of the MOSFET Q1 to the input node of the voltage clamp circuit CP3 is voltage clamped to form a return signal of the gate circuit GL5 that is input to the input signal of the second drive circuit LSD. The driving signal supplied to the gate of the MOSFET Q2 as the second switching element is supplied to the voltage by the voltage clamping circuit CP2 shown in the first or fifth embodiment corresponding to the low voltage. The driving signal of the gate of the MOSFET Q2 of the input node of the clamp circuit CP2 is voltage clamped to form a return signal of the gate circuit G4 which is input to the input signal of the first driving circuit HSD. That is, the voltage clamping circuits CP3 and CP2 act as a level shifting circuit for converting the high-amplitude driving signal-16-(14)(14)1374601 as described above into a low-amplitude signal, and the first The second switching element does not turn ON at the same time, that is, the signal MOSFET Q1 is turned off when the MOSFET Q1 is turned off, and the MOSFET Q2 is turned off, and the MOSFET Q1 is turned ON to set the dead time. . In this embodiment, as a circuit for performing the level shifting operation as described above, a voltage clamp circuit is used. The voltage clamp circuit of this embodiment is configured to reduce the dead time in such a manner that the transfer characteristic is high speed and the MOSFETs Q1 and Q2 do not simultaneously turn into an ON state. That is, if the switching period is the same and the dead time is small, the voltage control can be performed with higher precision. Since the output signal of the gate circuit G4 is a low voltage signal as described above, it passes through the level shift circuit LSU which is converted into a high voltage signal as an input signal of the first drive circuit HSD. The level shift circuit LSU and the first drive circuit HSD cause the potential of the output terminal LX to become the reference potential of the circuit. The control circuit IB, the power supply circuit Reg and the PWM input circuit IB, the voltage clamp circuit C P 1 described below, and the low level detection circuit UVL are the reference potentials of the circuit supplied from the terminal CGND. In other words, the ground potential CGND of the circuits is divided into a ground potential PGND for clamping the back electromotive voltage of the inductor, and stabilization of the operation is performed from the DISBL that controls the operation of the drive 1C to be enabled/disabled (〇n/〇FF). The input signal can be used at a signal amplitude of 5V to 12V. Therefore, it is assumed that the voltage clamp circuit CP1 shown in Fig. 1 is provided in the case where the signal amplitude of 12V is activated. Thereby, even at a higher signal level of -17-(15) (15) 1374601, such as 12V, low-power operation can be performed. Assuming that a low-voltage input signal such as 5 V is supplied, although the actual clamping operation is not performed, the actuation itself is not affected. According to the embodiment as described above, the voltage clamping operation can be stably performed with high speed and low power consumption, and the first switching element of the switching power supply device can be shortened by the voltage clamping action of responding to the change of the input voltage at a high speed. The dead time of switching with the second switching element. Fig. 12 is a block diagram showing another embodiment of the drive 1C of Fig. 10. In this embodiment, the drive 1C is a multi-wafer module structure in which three tantalum wafers are sealed to one package. In other words, the power MOSFET Q1 and the MOSFET Q2 are formed on the other semiconductor substrates (矽 wafers) CHP1 and CHP2 as shown by broken lines in the same figure, and the circuits constituting the driving 1C other than the power MOSFET Q1 and the MOSFET Q2 are formed. A semiconductor substrate (矽 wafer) CHP3, which is sealed on one package, constitutes the above-described drive 1C. In the drive 1C of the multi-chip module, as shown in the above-mentioned first aspect, a high-performance product can be manufactured at a low cost as compared with the case where all the circuits constituting the drive 1C are formed on one semiconductor substrate. The invention made by the inventors of the present invention has been described in detail above with reference to the embodiments, but the invention is not limited thereto, and various modifications may be made without departing from the spirit and scope of the invention. For example, in the first and sixth figures, the size of the MOSFET M1, the capacitance of the capacitor Ci, and the current of the current source 1 are appropriately set in accordance with the voltage clamp application. The present invention can be widely applied to a semiconductor integrated circuit device using a voltage clamp circuit (voltage level conversion circuit) and a switching power supply -18-(16) (16) 1374601 device. BRIEF DESCRIPTION OF THE DRAWINGS [Fig. 1] is a circuit diagram showing an embodiment of a voltage clamping circuit of the present invention. [Fig. 2] A characteristic diagram for explaining the operation of the voltage clamp circuit of the present invention. [Fig. 3] An equivalent circuit diagram of the voltage clamp circuit of the present invention will be described. [Fig. 4] An equivalent circuit diagram of the voltage clamp circuit of the present invention will be described. Fig. 5 is a specific circuit diagram showing an embodiment of a voltage clamping circuit according to the present invention. Fig. 6 is a view showing the operation waveforms of the voltage clamp circuit of the present invention. Fig. 7 is a characteristic diagram showing the relationship between the input voltage and the clamp voltage which are connected in series with the voltage clamp circuit of the present invention. [Fig. 8] A graph showing the rise characteristic of the input voltage of the voltage clamp circuit of the present invention. [Fig. 9] A graph showing the drop characteristic of the input voltage of the voltage clamp circuit of the present invention. [Fig. 10] A block diagram showing an embodiment of a switching power supply device employing a voltage clamping circuit of the present invention. [Fig. 11] A block diagram showing an embodiment of the drive 1C of Fig. 10. [Fig. 12] Block diagram showing another embodiment of the drive 1C of Fig. 10 -19-(17) (17) 1374601 [Explanation of main component symbols]
Dl，D2…二極體 Ml 〜M6··· MOSFET I 〇.…電流源 *Dl, D2... diode Ml ~ M6 · · · MOSFET I 〇 .... current source *
Ci…電容器Ci... capacitor
Cds…寄生電容 IB…輸入電路 CPNT···控芾IJ電路 EA…錯誤放大器 CMP…電壓比較電路 TWG…三角波發生電路 CL···自舉電容 L 0…電感 C〇，CM·"電容器 HSD…第1驅動電路 _ LSD…第2驅動電路 CP1〜CP3…電壓鉗位電路Cds...parasitic capacitance IB...input circuit CPNT···control IJ circuit EA...error amplifier CMP...voltage comparison circuit TWG...triangular wave generation circuit CL···bootstrap capacitor L 0...inductance C〇,CM·"capacitor HSD ...first drive circuit_LSD...second drive circuit CP1~CP3...voltage clamp circuit
Reg…電源電路 ^ LSU···位準移位電路 - G 1〜G 5…間極電路 SBD…肯特基能障二極體Reg...Power Circuit ^ LSU···Level Shift Circuit - G 1~G 5...Interpole Circuit SBD...Kentucker Barrier Diode
Ql，Q2···功率MOSFET (第1，第2開關元件） CHP1〜CHP3··.矽晶片 -20-Ql, Q2···Power MOSFET (1st, 2nd switching element) CHP1~CHP3··.矽 wafer -20-