101年7月27日修正替換頁 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種類比階層偵測器，且特別是有關 於一種用於具多級處理架構之類比數位轉換系統之類比 階層偵測電路。 【先前技術】 自然界的訊號都為類比訊號，加上現今CMOS數位電 路越來越成熟以及數位信號處理的精確度越來越高，因此 類比數位轉換器變得額外重要。若不考慮内部電路架構或 電路設計，以操作頻率來觀察，可將轉換器劃分為奈奎式 轉換器（Nyquist rate)和超取樣轉換器（Oversampling)兩大 類。奈奎式轉換器（Nyquist rate)的各種架構中，若以轉換 速度與精確度可粗略劃分成三大類：快速轉換器、中速轉 換器以及低速轉換器。 快速轉換器都是直接進行比較，是最常見的也是最基 本的類型，如快閃式類比數位轉換器（Flash)、兩階式類比 數位轉換器（Two-Step)、管線式類比數位轉換器（Pipelined ADC)、摺疊式類比數位轉換器（Folding ADC)以及内插式 類比數位轉換器（Interpolating)。中速轉換器在性能與價格 上面屬於比較中庸的，通常是利用一些演算法來實現，主 要是利用二分法的方式層層的找出類比輸入信號所對應 的值，輸出方式是採取串列輸出也就是高位元至低位元一 次輸出一個位元值，如連續近似_換器（Approximation)以 1373921 101年7月27日修正替換頁 及演算法轉換器（Algorithmic) »低速轉換器有計數法 (Counter)和過取樣法（Oversampling)轉換器，如多重斜率 類比數位轉化器（Multi-S丨0Pe )以及比數位 轉換器。 許多具多級處理架構之類比數位轉換器 (Analog-to-Digital Converter; ADC)架構中都存在著一個 數位類比轉換器（Digital-to-Analog Converter; DAC)’ 第 1 圖係繪示一習用管線式類比數位轉換系統之示意圖’此管 線式類比數位轉換系統的每一級i都是由相同架構所組 成並且都會提供數位碼的輸出位元。再利用每一級輸入信 號Vin(i)與數位類比轉換器所產生之類比訊號，經過減 法器後，提供給下一級所剩之餘數（residual)電壓。 此餘數電壓經放大後成為下一級輸入信號Vin(i+1)’ 將此級輸入信號Vin(i+1)進行數位轉換並產生另一個餘數 電壓及輸入信號Vin(i+2)給它的下一級電路。而整個電路 的輸出值便是由每一級所產生的數位輸出信號所組成。由 於此架構中需利用數位類比轉換器將各個子類比數位轉 換器的數位輸出信號轉換為對應的類比電壓’然後經減法 器被前一級輸入信號相減而得到餘數電壓’但數位類比轉 換器本身就有非理想效應的存在，因此會造成信號上的誤 差。 數位類比轉換器之種類甚多，主要的有電阻串數位/ 類比轉換器（Resistor-string DAC)、電荷重分佈數位/類比 轉換器（Charge Redistribution DAC)及電流互轉數位/類比 6 101年7月27日修正替換頁 轉換器（Current Steering DAC)。而為了節省面積，目前普 遍已利用交換電容的方式將數位類比轉換器和減法器合 併成一個電路，共用一個運算放大器，由於D/A部份屬於 電荷重分配型態’ 一般稱為MDAC(multiplying DAC)，其 優點為可在同一個電路完成數位轉類比、減法及放大餘數 電壓的功能，且因為只用到一個運算放大器，所以也減少 了晶片面積，但在數位轉類比的部份，由於是利用交換電 容的方式，因為電容的不匹配，所以也會造成信號上的誤 差。 本發明係對上述缺點進行改善，以類比階層偵測電路 取代數位類比轉換器’同樣可達成類比數位轉換器之功 效。 【發明内容】 為解決上述和其他的問題，並且達到本發明所主張的 技術優點，本發明提供一種類比階層偵測電路，只要類比 數位轉換器電路架構中包含數位類比轉換器，以便輪出下 一級所需的餘數電壓者皆可適用之。 因此本發明的目的就是在提供一種適用於具多級處 理架構之類比數位轉換系統之類比階層偵測電路。 根據本發明之上述目的，提出一種類比階層偵測電 路。依照本發明一較佳實施例，此類比階層偵測電路包含 溫度碼產生器、數位碼轉換器、電壓開關、位準選擇器以 及類比訊號輸出端。其中的數位碼轉換器包含數個邏輯 101年7月27日修正替換頁 閘，如EX-NOR邏輯閘與NOT邏輯閘、或NAND閘與NOT 邏輯閘。 依據本發明另一實施方式是在提供一種數位階層選 擇器，包括一數位碼轉換器以及一位準選擇器，數位碼轉 換器係用以接收複數個溫度位元值（Qi,Q2,…，Qm)，進而產 生複數個選擇值（S^S^...，Sm)。位準選擇器具有複數個傳輸 閘，其輸入端依序接收複數個位元值（乂以2，…，Vm)，其輸 出端為一類比訊號輸出端以提供一類比電壓值，複數個傳 輸閘用以依序根據複數個選擇值（S^S^…，Sm)決定其啟閉。 經由數位碼轉換器中各個邏輯閘進行的數位碼轉 換，將輸入類比階層偵測器的溫度碼轉換成數位碼，以控 制電壓開關直接將輸入類比階層偵測器的最高階層電壓 值傳送至類比訊號輸出端。由於階層電壓值為快閃式類比 數位轉換器經由電阻電壓分壓而得，因而可取代習知的數 位類比轉換器具有之非理想效應，更能達到快速傳遞訊 號、節省晶片面積以及降低系統功率消耗等功效。 【實施方式】 參照第2圖，其繪示依照本發明一較佳實施例的一種 類比數位轉換器。此類比數位轉換器包含了 N位元快閃式 類比數位轉換器（N-bit Flash ADC)、類比階層偵測電路、 解多工器（Demultiplexer)與移位/保存暫存器（Shift/Hold Register)。 此N位元快閃式類比數位轉換器接收前一級的數位類 1373921 101年7月27日修正替換頁 比轉換器所輪入的電壓Vin⑴後’由溫度碼產生器依照不 门，考電壓Vref範圍規劃溫度碼（詳述於第1表），再將溫 度碼經由解多工器傳輸至移位/保持暫存器，以備輸出最2 的數位資料。溫度碼亦經由數位碼轉換器，使溫度碼轉換 成數位碼，以控制數位階層選擇器裡的位準選擇器當作開 關將電壓vin傳送至類比訊號輪出端，並通知下一級電壓 Vin(i+1)輪入。 請參照第3圖，其繪示依照本發明之第一較佳實施例 的一種類比階層偵測電路。第一類比階層偵測電路1〇〇包 含了數位階層選擇器11〇,數位碼轉換器12〇及位準選擇 器130，配合溫度碼產生器14〇組成。其中的數位碼轉換 器120包含數個邏輯閘，如not邏輯閘m，ex n〇r^ 輯閘122。位準選擇器130則包含傳輸閘131以及類比訊 號輸出端132〇另外’溫度碼產生器14〇包含有比較器14卜 經由數位碼轉換器120中各個邏輯閘進行的數位碼轉 換，將溫度碼產生器140之比較器141輪出之溫度瑪輸入 數位階層選擇器110，使溫度碼轉換成數位碼，以控制位 準選擇器130中的傳輸閘131，該傳輸閘131作為電壓開 關’直接將輪入第一類比階層彳貞測電路100的階層電壓值 傳送至類比訊號輸出端132作輸出。 請參照第4圖，其繪示依照本發明第二較佳實施例的 一種類比階層偵測電路。第二類比階層偵測電路2〇〇包含 了數位階層選擇器210，數位碼~轉換器220及仇準選擇器 230 ’配合溫度碼產生器240組成。其中的數位瑪轉換器 1373921 101年7月27曰修正替換頁 220包含數個邏輯閘，如Ν〇τ邏輯閘221，ΝΑΝβ邏輯閘 222;使用該等NAND邏輯閘222，與第一實施例之ex n〇r 邏輯閘122相較可以適度減少電晶體數目。位準選擇器23〇 則包含傳輸閘231以及類比訊號輸出端232。另外，溫度 碼產生器240包含有比較器241。 經由數位碼轉換器220中各個邏輯閘進行的數位碼轉 換，將溫度碼產生器24〇之比較器241輸出之溫度碼輸入 數位階層選擇器210，使溫度碼轉換成數位碼，以控制位 準選擇器230中的傳輪閘231，該傳輸閘231作為電壓開 關，直接將輸入第二類比階層偵測電路2〇〇的階層電壓值 傳送至類比訊號輸出端232作輸出。 上述第一實施例及第二實施例之技術結構組成，藉由 各個邏輯閘進行的數位碼轉換，可直接將輸入類比階層偵 測電路的階層電壓值傳送至類比訊號輸出端，以達成訊號 傳遞快速’且節省系統功率消耗之目的。 本發明特別以較佳之一實施例說明如下： ‘ 以供應參考電壓Vref為例，參照下列之第1表所示， 該第1表之Vin設有四種不同電壓值，分別是：〜 0.25Vref、0.25 Vref 〜〇.5Vref、0.5 Vref 〜0.75Vref、0.75 Vref 〜1 Vref 。該第1表係以負邏輯為實施例β 假設位元數Ν=2 ’當vin介於0.25Vref〜〇.5Vref之間， 溫度碼產生器内含之比較器接收上述諸值，利用其差值產 生溫度位元值，進而組成一溫度碼”001”，則數位碼轉換器 接收該溫度碼並將溫度碼所產生之數位碼轉換成選擇 10 1373921 101年7月27日修正替換頁 值”110” ’，而位準選擇器接受Vin後，依據選擇值”11〇”， 進而使Si控制之開關為ON，直接將偵測之階層電壓Vi 傳送至類比訊號輸出端。 由於Vi的電壓值為2位元快閃式類比數位轉換器經 由電阻電壓分壓所得之輸入類比數位轉換器階層電壓，如 此一來，可以避免經由習知的數位類比轉換器轉換其具有 的非理想效應。 第1表[Description of the invention on July 27, 2011] Description of the Invention: [Technical Field] The present invention relates to an analog class detector, and more particularly to an analog digital device for multi-level processing architecture An analog class detection circuit of the conversion system. [Prior Art] Natural signals are analog signals, and today's CMOS digital circuits are becoming more and more mature and digital signal processing is becoming more and more accurate. Therefore, analog digital converters become extra important. If the internal circuit architecture or circuit design is not considered, the converter can be divided into two categories: Nyquist rate and Oversampling. In the various architectures of the Nyquist rate, the conversion speed and accuracy can be roughly divided into three categories: fast converters, medium speed converters, and low speed converters. Fast converters are direct comparisons and are the most common and basic types, such as flash analog-to-digital converters (Flash), two-stage analog-to-digital converters (Two-Step), and pipeline analog-to-digital converters. (Pipelined ADC), folded analog-to-digital converter (Folding ADC), and interpolated analog-to-digital converter (Interpolating). The medium-speed converter is relatively moderate in performance and price. It is usually implemented by some algorithms. The main method is to find the value corresponding to the analog input signal by using the dichotomy method. The output mode is to adopt serial output. That is, the high-order to the low-order one output one bit value at a time, such as the continuous approximation (Approximation) to 1373291, the revised page of July 27, 101 and the algorithm converter (Algorithmic) » the low-speed converter has a counting method ( Counter) and Oversampling converters, such as multi-slope analog-to-digital converters (Multi-S丨0Pe) and analog-to-digital converters. Many digital-to-digital converters (DACs) exist in many Analog-to-Digital Converter (ADC) architectures with multi-level processing architectures. Schematic of a pipelined analog-to-digital conversion system. Each stage i of this pipelined analog-to-digital conversion system is composed of the same architecture and provides an output bit of a digital code. The analog signal generated by each stage input signal Vin(i) and the digital analog converter is used, and after the subtractor, the remaining residual voltage is supplied to the next stage. The remainder voltage is amplified to become the next-stage input signal Vin(i+1)', and the input signal Vin(i+1) is digitally converted and another residual voltage and the input signal Vin(i+2) are given thereto. The next level of circuit. The output value of the entire circuit is composed of the digital output signals generated by each stage. Because this architecture needs to use a digital analog converter to convert the digital output signals of each sub-class to the digital converter into a corresponding analog voltage 'and then subtract the previous input signal by the subtractor to obtain the residual voltage' but the digital analog converter itself There is a non-ideal effect, which can cause errors in the signal. There are many types of digital analog converters, mainly including resistor string/analog converter (Resistor-string DAC), charge redistribution digital/analog converter (Charge Redistribution DAC) and current interdigital digital/analog ratio. Revised the replacement page converter (Current Steering DAC) on the 27th of the month. In order to save the area, it is generally common to combine the digital analog converter and the subtractor into one circuit by means of a switched capacitor, sharing an operational amplifier, since the D/A part belongs to the charge redistribution type 'generally called MDAC (multiplying) DAC) has the advantage of performing digital analogy, subtraction and amplification of the residual voltage in the same circuit, and because only one operational amplifier is used, the chip area is also reduced, but in the digital analogy part, It is the way to use the switched capacitor, because the capacitor does not match, it will also cause errors in the signal. SUMMARY OF THE INVENTION The present invention is directed to the improvement of the above disadvantages, and the analog level converter is replaced by an analog level detection circuit to achieve the same effect as an analog digital converter. SUMMARY OF THE INVENTION To solve the above and other problems, and to achieve the technical advantages of the present invention, the present invention provides an analog level detection circuit, as long as the analog digital converter circuit architecture includes a digital analog converter for rounding The remainder voltage required for the next stage is applicable. SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide an analog level detection circuit suitable for use in analog digital conversion systems having a multi-stage processing architecture. According to the above object of the present invention, an analog class detection circuit is proposed. In accordance with a preferred embodiment of the present invention, such a ratio detection circuit includes a temperature code generator, a digital bit code converter, a voltage switch, a level selector, and an analog signal output. The digital code converter contains several logics to correct the replacement page gates on July 27, 101, such as EX-NOR logic gates and NOT logic gates, or NAND gates and NOT logic gates. Another embodiment of the present invention provides a digital level selector including a digital bit code converter and a quasi-selector for receiving a plurality of temperature bit values (Qi, Q2, ..., Qm), which in turn generates a plurality of selection values (S^S^..., Sm). The level selector has a plurality of transmission gates, and the input terminal sequentially receives a plurality of bit values (乂2, . . . , Vm), and the output end thereof is an analog signal output terminal to provide an analog voltage value, and the plurality of transmissions The gate is used to determine its opening and closing according to a plurality of selection values (S^S^..., Sm). Converting the temperature code of the input analog detector to a digital code through the digital code conversion performed by each logic gate in the digital code converter, so as to control the voltage switch to directly transmit the highest level voltage value of the input analog class detector to the analogy Signal output. Since the layer voltage value is obtained by the voltage division of the flash analog analog converter, it can replace the non-ideal effect of the conventional digital analog converter, and can achieve fast transmission of signals, saving wafer area and reducing system power. Consumption and other effects. Embodiments Referring to Figure 2, an analog-to-digital converter is illustrated in accordance with a preferred embodiment of the present invention. This type of digital converter includes an N-bit flash analog-to-digital converter (N-bit Flash ADC), an analog level detection circuit, a demultiplexer (Demultiplexer), and a shift/save register (Shift/Hold). Register). The N-bit flash analog-like digital converter receives the first-level digital class 1379321. The correction replacement page on July 27, 101 is after the voltage Vin(1) of the converter is turned on by the temperature code generator, the test voltage Vref The range is programmed with the temperature code (detailed in Table 1), and the temperature code is transferred to the shift/hold register via the demultiplexer for output of the most digit data. The temperature code is also converted to a digital code by a digital code converter to control the level selector in the digital level selector as a switch to transmit the voltage vin to the analog signal wheel output, and notify the next level voltage Vin ( i+1) Round. Please refer to FIG. 3, which illustrates an analog level detection circuit in accordance with a first preferred embodiment of the present invention. The first analog level detection circuit 1 includes a digital level selector 11A, a digital bit converter 12A and a level selector 130, which are combined with a temperature code generator 14A. The digital code converter 120 includes a plurality of logic gates, such as not logic gates m, ex n〇r^ gates 122. The level selector 130 includes a transfer gate 131 and an analog signal output terminal 132. The other 'temperature code generator 14' includes a digital code conversion performed by the comparator 14 via each logic gate of the digital code converter 120. The temperature of the comparator 141 of the generator 140 is input to the digital level selector 110 to convert the temperature code into a digital code to control the transmission gate 131 in the level selector 130, which acts as a voltage switch 'directly The layer voltage value that is inserted into the first analog class detection circuit 100 is transmitted to the analog signal output terminal 132 for output. Please refer to FIG. 4, which illustrates an analog hierarchy detection circuit in accordance with a second preferred embodiment of the present invention. The second analog level detection circuit 2 includes a digital level selector 210, and the digital code to converter 220 and the hash selector 230' are combined with a temperature code generator 240. The digital-to-matrix converter 1373921, July 27, 2011, the correction replacement page 220 includes a plurality of logic gates, such as Ν〇τ logic gate 221, ΝΑΝβ logic gate 222; using the NAND logic gates 222, and the first embodiment Ex n〇r Logic Gate 122 can reduce the number of transistors moderately. The level selector 23 包含 includes a transfer gate 231 and an analog signal output 232. In addition, the temperature code generator 240 includes a comparator 241. Through the digital code conversion by each logic gate of the digital code converter 220, the temperature code outputted by the comparator 241 of the temperature code generator 24 is input to the digital level selector 210, and the temperature code is converted into a digital code to control the level. In the selector 230, the transmission gate 231 functions as a voltage switch, and directly transmits the layer voltage value input to the second analog layer detecting circuit 2 to the analog signal output terminal 232 for output. According to the technical structures of the first embodiment and the second embodiment, the digital voltage conversion performed by each logic gate can directly transmit the layer voltage value of the input analog layer detection circuit to the analog signal output terminal to achieve signal transmission. Fast 'and save system power consumption purposes. The present invention is specifically described as a preferred embodiment as follows: ' Taking the supply reference voltage Vref as an example, referring to the following Table 1, the Vin of the first table is provided with four different voltage values, respectively: ~ 0.25 Vref 0.25 Vref ~ 〇.5Vref, 0.5 Vref ~ 0.75Vref, 0.75 Vref ~ 1 Vref. The first table uses negative logic as the embodiment β to assume the number of bits Ν=2'. When vin is between 0.25Vref and 〇.5Vref, the comparator included in the temperature code generator receives the above values, and uses the difference. The value produces a temperature bit value, which in turn constitutes a temperature code "001", and the digital code converter receives the temperature code and converts the digital code generated by the temperature code into a selection 10 1373921 July 27, 101 revised replacement page value" 110" ', and after the level selector accepts Vin, according to the selected value "11", and then the Si control switch is turned ON, the detected layer voltage Vi is directly transmitted to the analog signal output terminal. Since the voltage value of Vi is the input analog digital converter layer voltage obtained by the voltage division of the 2-bit flash analog analog converter, the conversion of the digital converter can be avoided by the conventional digital analog converter. Ideal effect. Table 1
Vin q3 q2 Qi S3 s2 Si Analog Out 0Vref 〜0.25Vref 0 0 0 1 1 1 0 0_25 Vref ~ 0.5Vref 0 0 1 1 1 0 v, 0.5 Vref ~ 0.75Vref 0 1 1 1 0 1 v2 0.75 Vref 〜lVref 1 1 1 0 1 1 V3 而下列的第2表則列出了有N個位元數與m個比較器 的電路輸出結果。其中的m = 2N-l。該第2表係以正邏 輯為實施例’故選擇值結果與使用負邏輯之第1表呈相反。 1373921 101年7月27日修正替換頁Vin q3 q2 Qi S3 s2 Si Analog Out 0Vref ~0.25Vref 0 0 0 1 1 1 0 0_25 Vref ~ 0.5Vref 0 0 1 1 1 0 v, 0.5 Vref ~ 0.75Vref 0 1 1 1 0 1 v2 0.75 Vref ~lVref 1 1 1 0 1 1 V3 and the following Table 2 lists the circuit output with N number of bits and m comparators. Where m = 2N-l. The second table has positive logic as an embodiment. Therefore, the result of the selection value is opposite to the first table using the negative logic. 1373921 July 27, 101 revised replacement page
VinO) Qn Qd-1 * * ' • Cb Q. Sm Sm-Γ •Si S, AnalogjOui 0喻;^ 0 〇 · · · 0 0 0 〇 · * * • 0 0 0 0 0 * * * * 0 1 0 〇 * * * • 0 1 V, 0 1 · 1 1 0 1… • 0 0 V„M 二㈣ i)<v. 11·.· 1 1 1 〇 * * • 0 0 Vm 數位類比轉換器主要有幾個非理想效應：偏移誤差 (Offset error)、增益誤差（Gain error) '微分非線性誤差 (Differential nonlinearity error)、積分非線性誤差（Integral nonlinearity error) 〇 偏移誤差（Offset error)為，當數位輸入碼為〇時，其對 應的電壓如不是理想之0伏特，則其間的誤差稱為偏移誤 差（Offset error)，此誤差會使輸入之數位信號產生不精確 的類比輸出"增益誤差（Gain error)為，理想的數位類比轉 換器其斜率與實際上的數位類比轉換器斜率不同，之間的 斜率差稱為增益誤差（Gairi error)，產生的原因主要是參考 電壓（Reference voltage)或者是階梯係數（Scale factor)的不 精確有關。微分非線性誤差（DNL，Differential Non-Linearity error)是指一個實際的階梯高度和理想的 1LSB階梯高度之間的差，因此，若階梯寬度或高度正好是 1LSB，則微分非線性誤差就等於零，倘若DNL大於1LSB， 則轉換器有可能成為非單調（non-monotonic)函數。這表示 當輸入的振幅增加時，輸出的振幅會變小。積分非線性誤 12 1373921 101年7月27日修正替換頁 差（INL，Integral Non-Linearity error)為，實際的轉換函數 與理想直線之間的偏差值。 參照第5圖，其繪示一種習用之具有D/A與減法器功 能的電荷重分配型態之MDAC電路，將此MDAC電路與 本發明之實施例所提出的類比階層偵測電路100的電晶體 數目做比較，並將兩電路相異處所用MOS電晶體的數目 比較繪示於第6圖中，本發明所使用的電晶體數目比 MDAC少41 %，並隨著位元數的增加，則使用的電晶體數 目差異越大’由於本發明部份皆為數位電路，電晶體的 SIZE可為最小值’故可知本電路所需晶片面積將遠比電荷 重分配型態MDAC電路為小。 藉由上述之結構組成及實施例，本發明與習用相較具 有下列優點： 1.因數位轉類比部份由本發明之類比階層偵測電路 所取代’省去被動元件中的電容以降低製程偏移所造成的 電容不匹配而導致的誤差，並且節省了大量的傳輸閘，減 少晶片面積。 2·此種類比階層偵測電路不僅適用於管線式類比轉 換系統，只要電路架構中利用數位類比轉換器達到下一級 電路所需要的餘數電壓，皆可採用此類比階層偵測器。 雖然本發明已以一較佳實施例揭露如上，然其並非用 以限定本發明，任何熟習此技藝者，在不脫離本發明之精 神和範圍内，當可作各種之更動與潤飾，因此本發明之保 護範圍當視後附之申請專利範圍所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他方式、特徵、優點與實施例 13 1373921 101年7月27日修正替換頁 能更明顯易僅，所附圖式之詳細說明如下： 第1圖係繪示一習用管線式類比數位轉換系統之示意 圖。 第2圖係缯示依照本發明一較佳實施例的一種數位類 比轉換器之示意圖。 第3圖係繪示依照本發明一較佳實施例的一種類比階 層镇測電路之示意圖。 第4圖係繪示依照本發明一較佳實施例的一種類比階 層偵測電路之示意圖。 第5圖係繪示一種習用之MDAC電路圖。 第6圖係繪示依照本發明一較佳實施例的—種類比階 層偵測電路和習用MDAC電路的電晶體數目比較圖。 【主要元件符號說明】 100 :第一類比階層偵測電路 110 :數位階層選擇器 120 :數位碼轉換器 121 : NOT邏輯閘 122 : EX-NOR 邏輯閘 130 :位準選擇器 131 :傳輸閘 132 :類比訊號輸出端 140 :溫度碼產生器 Ml :比較器 200 :第二類比階層偵測電路 210 :數位階層選擇器 22〇 :數位碼轉榼器 221 : NOT邏輯閘 222 : NAND邏輯閘 230 :位準選擇器 231 =傳輸閘 232.類比訊號輸出端 240 :溫度碼產生器 241 :比較器VinO) Qn Qd-1 * * ' • Cb Q. Sm Sm-Γ •Si S, AnalogjOui 0 喻;^ 0 〇· · · 0 0 0 〇· * * • 0 0 0 0 0 * * * * 0 1 0 〇* * * • 0 1 V, 0 1 · 1 1 0 1... • 0 0 V„M 2 (4) i)<v. 11·.· 1 1 1 〇* * • 0 0 Vm Digital Analog Converter There are several non-ideal effects: Offset error, Gain error 'Differential nonlinearity error', Integral nonlinearity error OffOffset error Therefore, when the digital input code is 〇, if the corresponding voltage is not ideal 0 volts, the error between them is called offset error, which will cause the input digital signal to produce inaccurate analog output " Gain error is that the slope of an ideal digital analog converter is different from the slope of the actual digital analog converter. The difference between the slopes is called the Gairi error, and the cause is mainly the reference voltage. Reference voltage) or the inaccuracy of the scale factor Differential Non-Linearity error (DNL) is the difference between an actual step height and an ideal 1LSB step height. Therefore, if the step width or height is exactly 1 LSB, the differential nonlinearity error is equal to zero. If DNL is greater than 1LSB, the converter may become a non-monotonic function. This means that when the amplitude of the input increases, the amplitude of the output will become smaller. Integral nonlinear error 12 1373921 July 27, 2011 Correction replacement INL (Integral Non-Linearity error) is the deviation between the actual conversion function and the ideal line. Referring to Figure 5, a conventional charge redistribution type with D/A and subtractor functions is shown. The MDAC circuit compares the MDAC circuit with the number of transistors of the analog layer detecting circuit 100 proposed by the embodiment of the present invention, and compares the number of MOS transistors used for the difference between the two circuits in the sixth In the figure, the number of transistors used in the present invention is 41% less than that of MDAC, and as the number of bits increases, the difference in the number of transistors used is larger. Digital circuits, SIZE transistor may be a minimum value 'it was found that the required chip area than the present charge redistribution circuit patterns MDAC circuit is small. With the above structural composition and embodiment, the present invention has the following advantages compared with the conventional ones: 1. The factor-bit analogy portion is replaced by the analogous level detection circuit of the present invention' omitting the capacitance in the passive component to reduce the process bias. The error caused by the mismatch of capacitance caused by the shift, and the saving of a large number of transmission gates, reducing the wafer area. 2. This type of class detection circuit is not only suitable for pipeline analog conversion systems. As long as the digital analog converter is used in the circuit architecture to reach the residual voltage required by the next stage circuit, such a ratio detector can be used. Although the present invention has been described above in terms of a preferred embodiment, it is not intended to limit the invention, and it is obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS In order to make the above and other aspects, features, advantages and embodiments of the present invention 13 1373921, the revised page of July 27, 101, can be more obvious, the detailed description of the drawings is as follows: The figure shows a schematic diagram of a conventional pipeline analog digital conversion system. Figure 2 is a schematic diagram of a digital analog converter in accordance with a preferred embodiment of the present invention. FIG. 3 is a schematic diagram showing an analog-level town level measurement circuit in accordance with a preferred embodiment of the present invention. 4 is a schematic diagram of an analog layer detection circuit in accordance with a preferred embodiment of the present invention. Figure 5 is a diagram showing a conventional MDAC circuit. Figure 6 is a diagram showing a comparison of the number of transistors of a type-specific layer detection circuit and a conventional MDAC circuit in accordance with a preferred embodiment of the present invention. [Main component symbol description] 100: First analog level detection circuit 110: Digital level selector 120: Digital code converter 121: NOT logic gate 122: EX-NOR logic gate 130: level selector 131: transmission gate 132 Analog signal output terminal 140: temperature code generator M1: comparator 200: second analog level detection circuit 210: digital level selector 22: digital code switch 221: NOT logic gate 222: NAND logic gate 230: Level selector 231 = transfer gate 232. Analog signal output 240: Temperature code generator 241: Comparator