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TWI368149B - Automated method and system for estimation of layout-induced variations in threshold voltage in an integrated circuit layout and computer program therefor - Google Patents

Automated method and system for estimation of layout-induced variations in threshold voltage in an integrated circuit layout and computer program therefor

Info

Publication number
TWI368149B
TWI368149B TW097102496A TW97102496A TWI368149B TW I368149 B TWI368149 B TW I368149B TW 097102496 A TW097102496 A TW 097102496A TW 97102496 A TW97102496 A TW 97102496A TW I368149 B TWI368149 B TW I368149B
Authority
TW
Taiwan
Prior art keywords
layout
estimation
computer program
integrated circuit
threshold voltage
Prior art date
Application number
TW097102496A
Other languages
English (en)
Other versions
TW200903289A (en
Inventor
Victor Moroz
Dipankar Pramanik
Original Assignee
Synopsys Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Synopsys Inc filed Critical Synopsys Inc
Publication of TW200903289A publication Critical patent/TW200903289A/zh
Application granted granted Critical
Publication of TWI368149B publication Critical patent/TWI368149B/zh

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/36—Circuit design at the analogue level
    • G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0128—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/013—Manufacturing their source or drain regions, e.g. silicided source or drain regions
    • H10D84/0133—Manufacturing common source or drain regions between multiple IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
TW097102496A 2007-06-01 2008-01-23 Automated method and system for estimation of layout-induced variations in threshold voltage in an integrated circuit layout and computer program therefor TWI368149B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/757,335 US7584438B2 (en) 2007-06-01 2007-06-01 Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array

Publications (2)

Publication Number Publication Date
TW200903289A TW200903289A (en) 2009-01-16
TWI368149B true TWI368149B (en) 2012-07-11

Family

ID=40089706

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097102496A TWI368149B (en) 2007-06-01 2008-01-23 Automated method and system for estimation of layout-induced variations in threshold voltage in an integrated circuit layout and computer program therefor

Country Status (7)

Country Link
US (3) US7584438B2 (zh)
EP (1) EP2156343A4 (zh)
JP (1) JP5269070B2 (zh)
KR (1) KR101098570B1 (zh)
CN (1) CN101681386A (zh)
TW (1) TWI368149B (zh)
WO (1) WO2008150554A2 (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7584438B2 (en) * 2007-06-01 2009-09-01 Synopsys, Inc. Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array
JP5560700B2 (ja) * 2009-12-24 2014-07-30 富士通セミコンダクター株式会社 設計支援装置、設計支援方法及び設計支援プログラム
KR101827848B1 (ko) * 2010-10-22 2018-03-23 삼성디스플레이 주식회사 박막 트랜지스터 및 이를 구비한 표시 장치
US9064072B2 (en) * 2012-07-31 2015-06-23 International Business Machines Corporation Modeling semiconductor device performance
US9904772B2 (en) * 2013-12-02 2018-02-27 Samsung Electronics Co., Ltd. Screening solid state ionic conductors for high ionic conductivity
CN107220477B (zh) * 2017-04-21 2020-07-10 华东师范大学 一种基于非均匀分布界面陷阱的nbti退化模型获取方法
CN107292026A (zh) * 2017-06-21 2017-10-24 杭州电子科技大学 一种工艺参数波动引起mosfet性能变化的估计方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3144967B2 (ja) * 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
JP2000269105A (ja) * 1999-03-12 2000-09-29 Toshiba Corp プロセスシミュレータ、プロセスシミュレーション方法、デバイスシミュレータおよびデバイスシミュレーション方法
JP3566608B2 (ja) 1999-12-28 2004-09-15 Ｎｅｃエレクトロニクス株式会社 半導体集積回路
US6931613B2 (en) * 2002-06-24 2005-08-16 Thomas H. Kauth Hierarchical feature extraction for electrical interaction calculations
US7302376B2 (en) * 2002-08-15 2007-11-27 International Business Machines Corporation Device modeling for proximity effects
JP4907847B2 (ja) 2004-03-17 2012-04-04 オンセミコンダクター・トレーディング・リミテッド メモリ
JP2006012945A (ja) * 2004-06-23 2006-01-12 Seiko Epson Corp デバイスシミュレーション装置、デバイスシミュレーション方法及びデバイスシミュレーションプログラム
JP2006211851A (ja) 2005-01-31 2006-08-10 Tachi S Co Ltd パワー式格納シートのモータ制御方法およびそのモータ制御装置
US7337420B2 (en) * 2005-07-29 2008-02-26 International Business Machines Corporation Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models
US7584438B2 (en) * 2007-06-01 2009-09-01 Synopsys, Inc. Method for rapid estimation of layout-dependent threshold voltage variation in a MOSFET array
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system

Also Published As

Publication number Publication date
CN101681386A (zh) 2010-03-24
EP2156343A4 (en) 2012-09-19
US8347252B2 (en) 2013-01-01
US7584438B2 (en) 2009-09-01
JP2010529648A (ja) 2010-08-26
WO2008150554A3 (en) 2009-12-23
EP2156343A2 (en) 2010-02-24
US20130125075A1 (en) 2013-05-16
KR101098570B1 (ko) 2011-12-26
US20080301599A1 (en) 2008-12-04
JP5269070B2 (ja) 2013-08-21
WO2008150554A2 (en) 2008-12-11
US20090288049A1 (en) 2009-11-19
KR20100005101A (ko) 2010-01-13
TW200903289A (en) 2009-01-16

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