[go: up one dir, main page]

TWI367489B - Non-volatile memory with background data latch caching during erase operations and methods therefor - Google Patents

Non-volatile memory with background data latch caching during erase operations and methods therefor

Info

Publication number
TWI367489B
TWI367489B TW096115928A TW96115928A TWI367489B TW I367489 B TWI367489 B TW I367489B TW 096115928 A TW096115928 A TW 096115928A TW 96115928 A TW96115928 A TW 96115928A TW I367489 B TWI367489 B TW I367489B
Authority
TW
Taiwan
Prior art keywords
volatile memory
data latch
background data
erase operations
methods therefor
Prior art date
Application number
TW096115928A
Other languages
Chinese (zh)
Other versions
TW200809863A (en
Inventor
Jason Lin
Yan Li
Original Assignee
Sandisk Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US11/382,001 external-priority patent/US7619922B2/en
Application filed by Sandisk Corp filed Critical Sandisk Corp
Publication of TW200809863A publication Critical patent/TW200809863A/en
Application granted granted Critical
Publication of TWI367489B publication Critical patent/TWI367489B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/32—Timing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
    • G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/106—Data output latches
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
    • G11C7/1087—Data input latches
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
TW096115928A 2006-05-05 2007-05-04 Non-volatile memory with background data latch caching during erase operations and methods therefor TWI367489B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/382,001 US7619922B2 (en) 2005-04-01 2006-05-05 Method for non-volatile memory with background data latch caching during erase operations
US11/381,998 US7609552B2 (en) 2005-04-01 2006-05-05 Non-volatile memory with background data latch caching during erase operations

Publications (2)

Publication Number Publication Date
TW200809863A TW200809863A (en) 2008-02-16
TWI367489B true TWI367489B (en) 2012-07-01

Family

ID=38668524

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096115928A TWI367489B (en) 2006-05-05 2007-05-04 Non-volatile memory with background data latch caching during erase operations and methods therefor

Country Status (2)

Country Link
TW (1) TWI367489B (en)
WO (1) WO2007131059A2 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7158421B2 (en) 2005-04-01 2007-01-02 Sandisk Corporation Use of data latches in multi-phase programming of non-volatile memories
US7206230B2 (en) 2005-04-01 2007-04-17 Sandisk Corporation Use of data latches in cache operations of non-volatile memories
US7463521B2 (en) 2005-04-01 2008-12-09 Sandisk Corporation Method for non-volatile memory with managed execution of cached data
US7447078B2 (en) 2005-04-01 2008-11-04 Sandisk Corporation Method for non-volatile memory with background data latch caching during read operations

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6725322B1 (en) * 1999-02-22 2004-04-20 Renesas Technology Corp. Memory card, method for allotting logical address, and method for writing data
US6856568B1 (en) * 2000-04-25 2005-02-15 Multi Level Memory Technology Refresh operations that change address mappings in a non-volatile memory
JP2003233993A (en) * 2002-02-08 2003-08-22 Matsushita Electric Ind Co Ltd Rewriting method of nonvolatile storage device
US7206230B2 (en) * 2005-04-01 2007-04-17 Sandisk Corporation Use of data latches in cache operations of non-volatile memories

Also Published As

Publication number Publication date
WO2007131059A3 (en) 2008-03-13
TW200809863A (en) 2008-02-16
WO2007131059A2 (en) 2007-11-15

Similar Documents

Publication Publication Date Title
TWI340460B (en) Memory cell with improved program/erase windows
TWI368223B (en) Flash memory data writing method and controller using the same
ZA200803637B (en) Data management method in flash memory medium
GB2478874B (en) Memory management method, information precessing device, program creation method, and program
TWI373048B (en) Erasing flash memory using adaptive drain and/or gate bias and related erase method
IL185175A0 (en) Direct file data programming and deletion in flash memories
EP2047368A4 (en) Nonvolatile memory system, and data read/write method for nonvolatile memory system
EP1788582A4 (en) Erasing method for nonvolatile storage, and nonvolatile storage
GB2430291B (en) Erase algorithum multi-level bit flash memory
EP1929482A4 (en) Portable data storage using slc and mlc flash memory
GB2432444B (en) Flash memory device and word line enable method thereof
GB2449454B (en) Control data modification within a cache memory
EP2377129A4 (en) Non-volatile memory device for concurrent and pipelined memory operations
IL183978A0 (en) Non-volatile memory and method with multi-stream updating
EP1883931A4 (en) Predictive methods and apparatus for non-volatile memory
IL185174A0 (en) Direct data file storage in flash memories
TWI349194B (en) Storage device and method for loading data
IL185307A0 (en) Direct data file storage implementation techniques in flash memories
EP2170617A4 (en) Non-volatile memory data integrity validation
TWI346955B (en) Non-volatile memory device and method of programming a multi level cell in the same
GB0819679D0 (en) Data storage
GB2430776B (en) System and method of accessing non-volatile computer memory
EP1721321A4 (en) Non-volatile memory array with simultaneous write and erase feature
EP1866781A4 (en) Mechanism and method for managing data storage
GB2445118B (en) Hierarchical data storage

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees