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TWI366831B - Circuit and method for generating column path control signals in semiconductor device - Google Patents

Circuit and method for generating column path control signals in semiconductor device

Info

Publication number
TWI366831B
TWI366831B TW096122415A TW96122415A TWI366831B TW I366831 B TWI366831 B TW I366831B TW 096122415 A TW096122415 A TW 096122415A TW 96122415 A TW96122415 A TW 96122415A TW I366831 B TWI366831 B TW I366831B
Authority
TW
Taiwan
Prior art keywords
circuit
semiconductor device
control signals
path control
column path
Prior art date
Application number
TW096122415A
Other languages
English (en)
Other versions
TW200820264A (en
Inventor
Seung Wook Kwack
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200820264A publication Critical patent/TW200820264A/zh
Application granted granted Critical
Publication of TWI366831B publication Critical patent/TWI366831B/zh

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4076Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4093Input/output [I/O] data interface arrangements, e.g. data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/14Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/02Arrangements for writing information into, or reading information out from, a digital store with means for avoiding parasitic signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048Data bus control circuits, e.g. precharging, presetting, equalising
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175Coupling arrangements; Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Dram (AREA)
TW096122415A 2006-10-17 2007-06-22 Circuit and method for generating column path control signals in semiconductor device TWI366831B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060101002A KR100771551B1 (ko) 2006-10-17 2006-10-17 반도체 소자의 컬럼경로 제어신호 생성회로 및 컬럼경로제어신호 생성방법

Publications (2)

Publication Number Publication Date
TW200820264A TW200820264A (en) 2008-05-01
TWI366831B true TWI366831B (en) 2012-06-21

Family

ID=38816345

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096122415A TWI366831B (en) 2006-10-17 2007-06-22 Circuit and method for generating column path control signals in semiconductor device

Country Status (4)

Country Link
US (1) US7577046B2 (zh)
JP (1) JP2008103054A (zh)
KR (1) KR100771551B1 (zh)
TW (1) TWI366831B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4662536B2 (ja) * 2004-12-28 2011-03-30 パナソニック株式会社 タイミング調整方法及び装置
US8526209B2 (en) * 2010-12-28 2013-09-03 Stmicroelectronics International N.V. Complementary read-only memory (ROM) cell and method for manufacturing the same
KR102007364B1 (ko) * 2012-08-28 2019-08-05 에스케이하이닉스 주식회사 반도체 메모리 장치
CN116052737B (zh) * 2023-03-28 2023-08-29 长鑫存储技术有限公司 列控制电路以及存储装置

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01182996A (ja) * 1988-01-14 1989-07-20 Hitachi Ltd メモリ制御回路
JP2788729B2 (ja) * 1988-02-09 1998-08-20 日本電気アイシーマイコンシステム株式会社 制御信号発生回路
US6629222B1 (en) * 1999-07-13 2003-09-30 Micron Technology Inc. Apparatus for synchronizing strobe and data signals received from a RAM
JP2001216783A (ja) * 1999-11-22 2001-08-10 Mitsubishi Electric Corp 制御信号発生回路およびそれを備える半導体装置
US6622256B1 (en) * 2000-03-30 2003-09-16 Intel Corporation System for protecting strobe glitches by separating a strobe signal into pointer path and timing path, filtering glitches from signals on pointer path thereof
US6466491B2 (en) * 2000-05-19 2002-10-15 Fujitsu Limited Memory system and memory controller with reliable data latch operation
JP2002100189A (ja) * 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置
US6918048B2 (en) * 2001-06-28 2005-07-12 Intel Corporation System and method for delaying a strobe signal based on a slave delay base and a master delay adjustment
KR100403635B1 (ko) * 2001-11-06 2003-10-30 삼성전자주식회사 동기식 반도체 메모리 장치의 데이터 입력 회로 및 데이터입력 방법
KR20030052563A (ko) * 2001-12-21 2003-06-27 주식회사 하이닉스반도체 반도체기억소자에서 로우 어드레스 스트로브의 프리챠징시간 특성을 개선하기 위한 제어회로
US6819602B2 (en) 2002-05-10 2004-11-16 Samsung Electronics Co., Ltd. Multimode data buffer and method for controlling propagation delay time
KR20040056602A (ko) * 2002-12-24 2004-07-01 주식회사 하이닉스반도체 알씨디 타임의 특성을 향상시킬 수 있는 반도체 기억 장치
US7219269B2 (en) * 2003-07-28 2007-05-15 Credence Systems Corporation Self-calibrating strobe signal generator
KR20050076202A (ko) * 2004-01-20 2005-07-26 삼성전자주식회사 지연 신호 발생 회로 및 이를 포함한 메모리 시스템
KR100624261B1 (ko) * 2004-04-20 2006-09-18 주식회사 하이닉스반도체 디디알 에스디램의 데이터 입력 장치 및 방법
KR100579629B1 (ko) * 2004-06-04 2006-05-15 주식회사 대우일렉트로닉스 Ddr메모리의 데이터 스트로브 신호 제어 장치
JP4416580B2 (ja) * 2004-06-28 2010-02-17 株式会社リコー 遅延制御装置
JP4662536B2 (ja) * 2004-12-28 2011-03-30 パナソニック株式会社 タイミング調整方法及び装置
US7280417B2 (en) * 2005-04-26 2007-10-09 Micron Technology, Inc. System and method for capturing data signals using a data strobe signal
JP4786262B2 (ja) * 2005-09-06 2011-10-05 ルネサスエレクトロニクス株式会社 インターフェイス回路

Also Published As

Publication number Publication date
TW200820264A (en) 2008-05-01
US7577046B2 (en) 2009-08-18
JP2008103054A (ja) 2008-05-01
US20080089147A1 (en) 2008-04-17
KR100771551B1 (ko) 2007-10-31

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