TWI364980B - Solid-state imaging device and imaging apparatus - Google Patents

Description

1364980 IX. Description of the invention [Technical field to which the invention pertains]

The present invention relates to a solid-state image pickup device and an image pickup apparatus, which are examples of semiconductor devices for detecting a physical quantity distribution. More specifically, the present invention relates to a mechanism comprising a plurality of arranging unit elements having sensitivity to electromagnetic wave input such as light or radiation from the outside, and reading by the unit elements is converted into an electrical signal. An entity quantity distribution converts an analog electrical signal into digital data and outputs digital data to the outside. [Prior Art] In recent years, in the example of a solid-state image pickup device, a metal oxide semiconductor (MOS) image sensor and a complementary metal oxide semiconductor (CMOS) image sensor have been attracting great attention, which can solve the charge. Various disadvantages of the coupling device (CCD) camera sensor. For example, 'a CMOS camera has an amplifying circuit for each pixel, for example, a φ such as a floating diffusion amplifier, and when the CMOS camera sensor reads out a pixel signal' as an address control, a so-called line parallel output type or line type is often used. The method wherein one column of a pixel array unit is selected and a column of pixels is simultaneously accessed in a column by column, that is, all pixels of a column are simultaneously and parallelly read by the pixel array unit. Furthermore, the 'solid-state imaging device can adopt a method in which an analog pixel signal read from a pixel array unit is converted into digital data by an analog-to-digital converter (A/D converter), and the digital data is output to external. -4- 1364980 This is like a parallel parallel output type camera sensor, and various types of signal output circuits have been developed. A method is proposed as the most advanced type in which an A/D converter is provided for each line and a pixel signal is outputted to the outside as digital data (for example, refer to Japanese Patent Application Laid-Open No. 2005-278135)

Furthermore, in an A/D conversion method, various methods have been considered in terms of circuit specifications, processing speed, and resolution. Single slope integration or ramp comparison A/D conversion method for A/D conversion method. In this method, a class of analog signal is compared to a reference signal for digital signal conversion, and a counting process is performed in parallel with the comparison operation. According to this, the number signal of the unit signal is obtained by counting 値 when the comparison operation is completed. This method is also employed in the above patent documents. SUMMARY OF THE INVENTION The addition processing has been performed in a solid-state image pickup device such as a digital camera, which is used as a device for converting light into an electric signal to be output as an image signal. For example, the addition processing used to reduce the number of pixels depends on an example such that when pixels are captured, all pixels are read or when the animation is captured, the pixels are added and thinned for high speed. read out. Since a CMOS camera sensor converts a pixel signal into an electrical signal for each pixel, this addition processing function can be easily added thereto. The solid-state image pickup device disclosed in the above patent document also employs this addition processing system. However, by performing a simple addition process, the coefficients of the added target pixels are made uniform, but due to the relationship of the spatial positions of the pixels after the addition, the high-resolution addition image cannot be obtained at all times. This is typically because the spatial locations after the addition are not equidistant. The present invention has been accomplished in view of the above circumstances and provides a mechanism for obtaining an added image with high resolution. In a solid-state image pickup device according to an embodiment of the invention, it comprises: a comparator and a counter. The comparator is first compared to a pixel and the like.

A predetermined level (e.g., a reset position or signal level) of the pixel signal and a gradually changing reference signal are used to convert the predetermined level into digital data. The counter is connected in parallel to the comparison processing performed by the comparator, performs a counting process' and obtains the pre-aligned digital data by retaining the count 値 when the comparison processing is completed. In other words, as a mechanism relating to A/D conversion of a pixel signal, an A/D conversion system of a so-called single-slope integration type or a ramp-wave signal comparison type is employed. In the mechanism according to an embodiment of the present invention, an addition spatial position adjustment unit is provided. The addition spatial position adjusting unit is configured to control a selection operation of a selected spatial position of a plurality of pixels processed in the φ comparator and a ratio of weighted 値 at the time of addition, to adjust a spatial position of the pixel after the addition. The sentence "by adjusting the ratio of the weights 値 at the time of addition to adjust the spatial position of the pixels after the addition" indicates that the spatial position of the added pixels is adjusted so that the resolution of the added image is higher than A simple addition is performed in which each weighted 値 of the added target pixel is uniform. Preferably, for this purpose, the addition spatial position adjustment unit controls the weighted turns ratio at the time of addition such that the spatial position of each pixel after addition is arranged to be equidistant. -6- 1364980 If the pixel is provided with a color filter for generating a color image, the addition spatial position adjustment unit controls selection of a spatial position of a majority of pixels performed by the comparator to enable pixels having the same color The sum is added 'and the proportion of the weights 値 at the time of addition is controlled such that the -space position of each pixel is arranged equidistantly.

If the spatial position of each pixel after adjustment is adjusted by setting an appropriate weight 値, the pixel positions after the addition can be arranged equidistantly in an optimum state. As a result, it is possible to surely prevent the resolution from becoming lower or the possibility of lowering the resolution, and if the images are added by the simple addition processing, the resolution is sometimes lowered. The solid-state camera device may sometimes be of a single-chip type or a module type having a camera function, in which a camera unit, a signal processor or an optical system is packaged. Furthermore, the present invention can be applied not only to a solid-state image pickup device but also to an image pickup apparatus. At this time, the image pickup apparatus can achieve the same advantages as φ in the solid-state image pickup device. The image pickup apparatus can be, for example, a camera or a mobile device having a camera function. In addition, "imaging, not only for capturing a normal image with a camera" but also for broadly detecting fingerprints. These and other features and aspects of the present invention are described in detail with reference to the accompanying drawings. The example will be described in detail with reference to the accompanying drawings. In the following examples, a CMOS solid-state image pickup device is used as an example, which is a 1364980 Χ-Υ address type solid-state image pickup device. Furthermore, each of the CMOS solid-state image pickup devices is used. The pixel is composed of an NMOS. However, this is an example and the device is not limited to the MOS image pickup device. All of the embodiments described later can be applied to all semiconductor devices for detecting the physical quantity distribution, which include a plurality of arrangements in a straight line or matrix. A shaped unit element that is sensitive to light or electromagnetic waves input from outside.

[Summary of Solid-State Imaging Device] Fig. 1 is a schematic diagram of a CMOS solid-state imaging device (CMOS imaging sensor) according to an embodiment of the present invention. The solid-state image pickup device 1 has a pixel unit in which a plurality of pixels including a light receiving element (e.g., a charge generator) are output, which output signals corresponding to the amount of incident light, and are arranged in rows and columns (i.e., two-dimensional matrix shape). The signal output from each pixel provides a voltage signal. The solid-state imaging device 1 includes both a co-correlated double sampling (CDS) processing functional unit and an analog digital converter (ADC), which are arranged in parallel in a row. The "CDS processing function unit and the ADC are arranged in parallel in a row" means that most of the CDS processing function units and the ADC system are arranged in a manner substantially parallel to the vertical signal line 19 (row signal line) in the vertical line. When the apparatus is viewed in a plane, most of the functional units may be arranged only on one end side of the row direction of the pixel array unit 1 (outside of the lower portion in the drawing). Alternatively, the functional units may be arranged separately on one end side of the row direction of the pixel array unit 1 (outside of the lower portion of the drawing) and on the other side opposite to one end (upper portion in the drawing). In the latter case, preferably, horizontal scanners for performing readout scanning (horizontal scanning) in the column side-8 - 1364980 are arranged on both sides of the pixel array unit 10 so that the horizontal scanner can Independent operation. For example, a typical example in which a CDS processing functional unit is arranged in parallel with an ADC is a row type in which a CDS processing functional unit and an ADC system for each vertical line are arranged for use in a portion called a row region. The line area is arranged on the output side of the camera unit, and the signal system is sequentially read out to the output side. Or, not just the line type, you can also specify one

The CDS processing functional unit and an ADC to a majority (for example, two) adjacent signal lines 19 (vertical lines), or a CDS functional unit and an ADC can be assigned to N vertical signal lines 1 9 (vertical lines) to N other lines (N is A positive integer; where there is (N-1) between the two lines. Since any structure other than the row type has a structure in which a CDS processing functional unit and an ADC are shared by a plurality of vertical signal lines 19 (vertical lines), a switching circuit (switch) is provided for supply. Most of the rows of pixel signals from pixel array 10 are coupled to a CDS processing functional unit and an ADC. The memory used to store the output signal may necessarily depend on the processing in the latter step. In either case, by specifying a CDS processing functional unit and an ADC to a plurality of vertical signal lines 19 (vertical lines), signal processing can be performed on the pixel signals after the pixel signals are read out in pixel unit of motion. Therefore, the architecture of each unit pixel can be simplified compared to performing similar signal processing in each unit pixel, and therefore, a smaller and lower cost image sensor of multiple pixels can be implemented. In addition, the pixel signals in a single column can be placed at the same time by the line -9-

1364980 Most signal processors arranged in parallel are processed in parallel. The number processor can operate at a slower speed than the output of the output circuit or one of the devices and the processing performed by an ADC. Rate consumption, band efficiency, noise, etc. are advantageous. In other words, when the rate consumption and band performance are similarly set, the entire sensor can be operated. The row type architecture can operate at low speeds and has advantages in power consumption, noise, and also does not require switching circuits (switches). The examples describe the line type except for special instructions. As shown in FIG. 1, a solid-state camera according to an embodiment of the present invention includes: a pixel array unit 1 〇, wherein a plurality of unit pixels 3 are series and rows, which are also referred to as pixel units or a camera unit; and a drive 7 provides external pixels. The array unit 1 〇; the read current supply 24 gives an operating current (read current) for reading out the pixel signal to the unit pixel 3 in the unit 10; the line processor 26 includes the line A/D in the vertical line The circuit 25; - the reference signal generator supplies the reference signal Vslop for A/D conversion to the processing § an output unit 29. These functions can be used with any reference signal Vslop set on the same semiconductor substrate as long as it has a waveform that varies linearly with a predetermined slope: and has a smooth slope-shaped waveform, or a one-step waveform, which sequentially changes can use. The row A/D circuit 25 in this embodiment has a function A/D converter which takes one as the basic position of the pixel signal So, which is implemented for the power of the CDS function, which is implemented below the high-speed band performance. The image device 1 is arranged as a dynamic controller for arranging the pixel arrays at each of the two terminals for use on the user's computer. A signal, the level of change of the level, including a quasi-reset -10- 1364980 level Srst and a signal level Ssig independently converted to digital data, and - the reference processor, which performs the reset level Srst The difference between the A/D conversion result and the A/D conversion result of the signal level Ssig is processed, and the digital data of the signal component represented by the difference between the reset level Srst and the signal level Ssig is obtained.

In the previous stage or the subsequent stage of the line processor 26, an automatic gain control (AGC) circuit having a signal amplifying function is disposed in the same semiconductor region, if necessary, in which a row processor 26 is arranged. When AGC, the analog amplification is performed at the previous stage of the line processor 26, and at the time of AGC, the digital amplification is performed at the next stage of the line processor 26. Since the tone seems to be corrupted when the n-bit digital data is simply enlarged, it is preferable that the data is amplified in an analogous form and then converted again. The drive controller 7 includes control circuitry for sequentially reading signals from the pixel array unit 1 。. For example, the drive controller 7 includes: a horizontal scanning circuit (row scanning circuit) 12' having a horizontal decoder 12a and a horizontal driving unit 12b which controls line addressing or line scanning; and vertical scanning with a vertical decoder 14a and a vertical driving unit 14b A circuit (column scanning circuit) 14, which controls column addressing or column scanning, and a communication/timing controller 20 having an internal clock function. In the vicinity of the communication/timing controller 20 of Fig. 1, a clock converter 23 can be arranged which generates a high speed clock generator having a pulse having a clock frequency faster than the input clock frequency. The communication/timing controller 20 generates an internal clock via the terminal 5a in accordance with the input clock (main clock) CLK0, or a high-speed clock is generated in the clock converter 23. -11 - 1364980 A high-speed A/D conversion process is performed using a signal in accordance with the high-speed clock generated in the clock converter 23. The use of a high speed clock also makes it possible to perform motion extraction or compression that requires fast calculations. It is also possible to convert the parallel data output from the processor 26 into serial data and output it to the outside of the device as the video material D1. With this architecture, high-speed operation can be performed with fewer bits than the A/D conversion digital data.

The clock converter 23 has a built-in multiplying circuit for generating a clock frequency that is higher than the input clock frequency. The clock converter 23 receives the low speed clock CLK2 from the communication/timing controller 20 and generates a clock having twice the frequency of at least the low speed clock CLK2. If kl is the frequency multiple of the low speed clock CLK2', the k1 multiplying circuit can be set for the clock converter 23, and various known circuits can be used as the multiplying circuit. In Figure 1 'for the sake of simplicity, not all rows and columns are shown. However, 'actually, tens to thousands of unit pixels 3 are arranged in each column or each row to form the pixel array unit 1 〇. Typically, each unit pixel 3 includes a photodiode as a light receiving unit (charge generator) and an in-pixel amplifier having an amplifying semiconductor element (e.g., a transistor). The in-pixel amplifier can be a circuit capable of outputting a signal charge which is generated and accumulated in the charge generator in the unit pixel 3 as an electric signal, and various structures can be used as an in-pixel amplifier. It is usually used as a diffusion amplifier structure. For example, a floating diffusion amplifier comprising four transistors arranged in a single charge generator is typically used in CMOS type inductors. The four transistors are: a readout selection transistor, which is an example of the charge readout unit-12-1364980 (transfer gate/readout gate); - reset transistor] which is an example of a reset gate: ~ vertical Selecting a transistor; and amplifying the transistor of a source follower structure, which is a detecting element 'to detect a possible charge in the floating diffusion (for example, refer to FIG. 2 as described later) »

Alternatively, it is possible to use a floating diffusion amplifier having a three transistor 'i.e., an amplifying transistor connected to a drain line (DRN) for amplifying a signal voltage corresponding to the signal generated by the charge generator; The crystal ' is used to reset the charge generator; and a read select transistor (transistor gate)' is a vertical shift register that is scanned via a transfer line (TRF). In the solid-state image pickup device 1, the pixel array unit 1 can be made to perform color imaging by using a dichroic filter. More specifically, any color filter of the color separation filter may be arranged in a so-called Bayer configuration, arranged in the pixel array unit 10 for receiving electromagnetic waves of each charge generator (for example, a photodiode) (this implementation) The light in the example) is used to complete color imaging, wherein the filter is made up of a combination of color filters having multiple colors. If the color filter is arranged in a Bayer configuration as shown in Figures 8 and 12-14, G (green) and R (red) filters or B (blue) and G (green) filters are arranged. In the same column, they are arranged in a two-dimensional grid. The unit pixel 3 is connected to the vertical scanning circuit 14' via the column control line 15 for selecting a column and connected to the line processor 26' via the vertical signal line 19, wherein the row A/D circuit 25 is arranged in each vertical line. The column control line 15 represents all of the lines from the vertical scanning circuit 14 to the pixels. The horizontal scanning circuit 12 has a function of a readout scanner for reading the count from the processor 26 to the horizontal signal line 18. The output circuit 28 is set to the next stage (output side) of the horizontal signal line 18 from -13 to 1364980.

A digital arithmetic unit 29 can be provided in the previous stage of the output circuit 28 if necessary. "If necessary" means when there is a need for other processing in the horizontal direction. Therefore, the digital arithmetic unit 29 has a function of performing the addition processing of the majority of the line data for the horizontal direction. In addition, depending on the line connection to the horizontal signal line 18, a memory is provided to store the data of the majority of the added target lines. For example, when a plurality of target lines are transmitted to the line connection of the digital arithmetic unit 29 via the horizontal signal line 18 of the individual system, it is not necessary to record the billion body, if a majority of the added target line is passed through the horizontal signal line of the system. For the transfer, the data level scanning circuit 12 that needs the memory to store the added target line is synchronized with the low speed clock CLK2, sequentially selects the row A/D circuit 25 in the line processor 26, and directs the signal to the horizontal signal line (horizontal Output line) 1 8. For example, the horizontal scanning circuit 12 has a horizontal decoder 12a for defining a readout line in the horizontal direction (selecting the individual row A/D circuit 25 of φ in the row processor 26), and a horizontal drive unit 12b for the line Each signal of processor 26 is directed to horizontal signal line 18 in accordance with a read address defined by horizontal decoder 12a. The horizontal signal line 18 is arranged, for example, for the number of bits η processed by the row A/D circuit 25 (n is a positive integer), and if 1 〇 (= η) bits, the pixel array unit 10 line is arranged Corresponds to the number of bits. Each element of the drive controller 7, such as the horizontal scanning circuit 12 and the vertical scanning circuit 14, is formed together with the pixel array unit 10 on a semiconductor region made of a single crystal germanium or the like, which is similar to that used by a half. Guide-14-1364980 The technique of bulk body circuit fabrication technology is carried out to form a solid-state image pickup device such as a semiconductor system. These individual functional units form part of the solid-state imaging device 1 of the present embodiment, also referred to as "single-wafer type" (provided on the same semiconductor substrate), and each functional unit is integrally formed in a single crystal germanium. In the semiconductor region which is formed, this is performed by using a semiconductor integrated circuit manufacturing technique, and becomes a CMOS image pickup device such as a semiconductor system.

The solid-state image pickup device 1 may be of a single wafer type in which individual components are integrally formed in the same semiconductor component, but it is not shown, and may also be a module type having an image pickup function, in addition to the pixel array unit 10, driving In addition to the various signal processors of the controller 7 and the line processor 26, an optical system such as a pick-up lens, an optical low-pass filter, or an infrared cut-off oven mirror is packaged. The horizontal scanning circuit 12 and the vertical scanning circuit 14 include, for example, a decoder, and start a shift operation (scanning) in response to the control signals CN2 and CN1 supplied from the communication/timing controller 20. Therefore, the column control line 15 contains various pulse signals for driving the unit pixel 3 (e.g., the pixel reset pulse RST, the transfer pulse TRG, and a vertical selection pulse VSEL). Although not seen, the communication/timing controller 20 has a functional block of a timing generator TG (eg, a read address control device) that supplies a clock and predetermined timing pulse signals required for each unit operation, and a functional block of a communication interface, which receives a main clock CLK0 supplied from an external main controller via the terminal 5a, and receives data DATA indicating an operation mode and the like supplied from an external main controller via the terminal 5b, and outputs a solid-state photo -15- 1364980 Information from device 1 to the external host controller. For example, the communication/timing controller 20 outputs a horizontal address signal to the horizontal decoder 12a and outputs a vertical address signal to the vertical decoder 14a. Each decoder receives the signal and selects the corresponding column or row.

At this time, since the unit pixels 3 are arranged in a two-dimensional matrix, the high-speed reading of the pixel signals and the pixel data is performed by the following procedure: performing (vertical) scanning reading, in which pixel signals are The analog pixel signal generated by the generator 5 and output via the vertical signal line 19 is accessed and read in column units (in a row parallel manner), and then (horizontal) scan reading is performed, where the pixel signal (this example) The digital pixel data in the column is accessed in the column direction in the column direction, which is the arrangement direction of the vertical rows, and is read out to the outside. Of course, not only the scanning read but also the random access can be done by directly specifying the address of the pixel unit 3 to be read out so that only the necessary unit pixel 3 can be read. The communication/timing controller 20 supplies a clock obtained by dividing the clock CLK1 having the same frequency as the main clock CLK0 via the terminal 5a, dividing the clock CLK1 by 2, or further dividing the clock CLK1 by the obtained low-speed clock to each unit in the device, for example The horizontal scanning circuit 12, the vertical scanning circuit 14, and the line processor 26 are provided. In the following, a clock obtained by dividing by 2 or a clock having a lower clock than all taken is referred to as a low-speed clock CLK2. The vertical scanning circuit 14 selects a column of the pixel array unit 10 and supplies the necessary pulses to the selected column. For example, the vertical scanning circuit 14 has a vertical decoder 14a for defining one of the readout columns in the vertical direction (selecting one column of the pixel array unit 10), and a vertical driving unit 14b for supplying a pulse of -16 - 1364980 The control line 15 to the unit pixel 3 is the read address (in the column direction) defined by the vertical decoder 14a for driving. The vertical decoder 14a also selects a column as an electronic shutter in addition to defining a readout column. In this embodiment, it is possible to perform an A/D conversion operation, that is, a normal frame mode, to progressively scan to read information of all the unit pixels 3 and increase the frame rate by N times according to each operation mode. The frame rate, for example, the speed of the normal frame mode is twice.

Preferably, in addition to performing sequential scanning in the normal frame rate mode by the horizontal decoder 12a, the horizontal scanning circuit 12 or the vertical scanning circuit 14 includes a bit address decoder to arbitrarily select the columns and rows to be processed so that The addition read operation or the decimal read operation can be performed in the high speed frame mode. In particular, when the dichroic filter for capturing color images is provided in each unit pixel 3 of the pixel array unit 1 相对 in relation to the addition read operation, preferably, at least in the vertical scanning circuit 14 The addition processing can be performed on the unit pixels 3 having the same color. In order to perform the addition processing in the vertical direction in parallel with the A/D conversion processing, preferably, a vertical decoder 14a is provided for selecting any of the control lines 15 at least in the vertical scanning circuit 14. When capturing a color image, color mixing occurs if the addition process is performed on pixels having different color filter elements. On the other hand, if the addition processing is performed on pixels having the same color, for example, pixels in odd or even columns in the Bayer configuration, color mixing does not occur.

"Parallel to A/D conversion, performing the addition processing in the vertical direction" indicates the count obtained by the A/D -17-1364980 conversion processing result on the last addition processing target column in the majority addition processing target column 値A state is displayed in which the results of the A/D conversion processing performed on the pixel signals of the unit pixels 3 in the majority of the processing target columns are added. In particular, if the CDS processing is performed together with the A/D conversion in the counter 254, the count 値 shows the addition result of the pixel signal components. In other words, this means that the addition processing in the vertical direction is performed together with the A/D conversion processing in the row A/D circuit 25.

Of course, this is not necessary in this case. It is also possible to perform the addition processing by digital arithmetic processing after reading out the readout columns listed in the vertical direction of the sequential scanning, and use the simple scanning circuit for sequentially selecting the readout columns without using the arbitrarily selectable readout. The vertical decoder 14a of the column. However, when external memory (for line memory of most columns) is necessary, the data of the majority of the added target columns is stored. Alternatively, in addition to the line processor 26, the plurality of addition target columns are individually read and added to the digital arithmetic processing. At this time, external memory (line memory for a plurality of columns) is not required, however, the disadvantage is that the circuit scale is larger because the row processor 26 (row A/D circuit 25) and the reference signal are generated. The processor 27, the horizontal scanning circuit 12 and the vertical scanning circuit 14 do not need to be placed in each of the plurality of columns. For example, if the addition process performs two columns, the above two circuits are arranged with the pixel array unit 10 in between. On the contrary, if the addition processing in the vertical direction is performed in parallel with the A/D conversion processing in the row A/D circuit 25, there is an advantage that the external memory or the majority system line processor 26 is not required. In response to this, the present embodiment employs a mechanism for performing the addition processing in the vertical direction and the A/D conversion processing in the line 18-1364980 A/D circuit 25 together.

On the other hand, the addition processing in the horizontal direction for the unit pixels 3 having the same color can be performed by the simple sequential scanning circuit in which the readout lines are sequentially selected by sequentially scanning the horizontal direction to read out. The addition of the target unit pixel 3 having the same color is selected in the arithmetic processing without using the horizontal decoder 12a which can arbitrarily select the readout line to the output circuit 28. Alternatively, the addition processing may be performed, and at the same time, the switching is performed in the order of the readout columns selected by the horizontal decoder 12a so that the addition target unit pixels having the same color are read out in the order of selection in the horizontal direction. The elements of 3 are sequentially transferred to elements of unit pixels of the same color that are sequentially transmitted by digital arithmetic processing (e.g., using a digital arithmetic unit 29). Furthermore, as described in Japanese Patent Application No. 2005-278 135, that is, its fourth and fifth embodiments, an architecture may be employed in which it may be implemented, for example, in odd rows (for example, the first row and the third row). ), or adding pixels on even lines (for example, the second line and the fourth line), or a combination of lines in which pixels are added can be arbitrarily switched by arranging a selection switch to be in the pixel array unit 10 The row A/D circuit 25 switches a read target line, and by arranging each pair of line processors 26 (row A/D circuit 25), reference signal generator 27, horizontal scanning circuit 12, and vertical scanning circuit 14, To switch the pixel array unit 1 〇. In the solid-state image pickup device 1 having this configuration, the pixel signals output from the unit pixel 3 are supplied to the row A/D circuit 25 in the line processor 26, via each vertical line, via the vertical signal line 19 » -19- 1364980 Each row of A/D circuits 25 in row processor 26 receives the analog signal So of a pixel in a column and processes the analog signal So. For example, each row of A/D circuits 25 has an analog-to-digital converter (ADC) circuit 'which converts the analog signal to, for example, a 1-bit digital signal' and is used, for example, for the low-speed clock CLK2.

The A/D conversion process performed in the line processor 26 uses a parallel A/D conversion method for each column, using the row A/D circuit 25 arranged in each row to store the analog signals stored in each column in parallel. get on. At this time, a single slope integral (or ramp signal comparison) A/D conversion technique is used. Since this technique can implement the A/D converter in a simple structure, even if the A/D converters are arranged in parallel, the circuit scale does not increase. In order to add a single-slope integral A/D conversion, the processing target analog signal is converted into a digital signal based on the self-conversion until the matching reference signal Vslop and a processing target signal voltage. In principle, the ramp waveform reference signal Vslop is supplied to the comparator (voltage comparator), and at the same time, the count starts with the clock signal. The A/D conversion is performed to count the clock until the pulse signal is obtained. This represents the comparison between the analog pixel signal input via the vertical signal line 19 and the reference signal Vsl 〇p. Furthermore, at this time, the pulse signal input in the voltage mode is input to the vertical signal line 19' via the vertical signal line 19', and it is possible to perform an operation with a/D conversion to remove the pixel after resetting the pixel. The difference between the signal level (called the noise level or the reset level) and the true signal level Vsig corresponding to the amount of light. This operation is equivalent to the so-called CD S processing. In this way, the noise signal components such as fixed pattern noise (FPN) or reset noise are therefore shifted by -20-1364980. [Details of reference signal generator and row A/D circuit]

The reference signal generator 27 includes a DA converter (DAC) 27a. The reference signal generator 27 synchronizes the count clock CKdac with the step sawtooth wave, or the ramp signal (hereinafter also referred to as the reference signal Vsl op), which is started by the communication/timing controller 20, which is started by the control data CN4. Then, the generated step sawtooth reference signal Vslop for A/D conversion is supplied as a reference signal or an ADC reference signal to each of the row A/D circuits 25 in the line processor 26. Although not shown, a noise suppression filter is preferably provided. The reference signal Vslop generated by the multiplied clock (high-speed clock) generated by the multiplying circuit in the clock converter 23 can be changed faster than the one generated by the input of the terminal 5a according to the main clock CLK0. The control data CN4 supplied from the communication/timing controller 20 to the DA converter 27a of the reference signal generator 27 contains information to comply with the rate of change of the digital data with respect to time, so that the reference signal Vslop for each comparison process is basically Have the same rate of change. More specifically, a counting system is changed every unit time in synchronization with the count clock CKdac, and a counting converter is converted into a voltage signal by a DA converter of a current addition type. Under the control of the communication/timing controller 20, the DA converter 27a of the present embodiment can change (in a specific example, become larger) the variation characteristic of the reference signal Vslop during the comparison processing in the voltage comparator 2 52 (at In the specific case, the slope is). -21 - 1364980

The slope of the reference signal can be adjusted by using the method of changing the frequency (clock cycle) of the count clock CKdac. For example, when the frequency of the count clock CKdac supplied to the DA converter 27a is started to be the same as the frequency of the count clock CKQ, preferably, once the predetermined count is reached, the frequency of the count clock CKdac becomes 2 Am times faster than the count. The frequency of the clock CK0. Specifically, when the first predetermined count is reached, the frequency of the count clock CKdac is twice as fast as the frequency of the count clock CKO, and when the second predetermined count is reached, the frequency of the count clock CKdac is four times faster than the count. The frequency of the clock CK0. The above method is only an example, and the change in slope is not limited to this method. For example, any circuit can be used in a method in which, when the cycle of the count clock CKdac supplied to the reference signal generator 27 is kept constant, the output has a potential calculated by y = a - 10,000 * ,, where χ is a count 値, ^ is the start 値, and /3 is the slope (rate of change) of the reference signal Vslop contained in the control data CN4' or 'based on the slope (rate of change) indicating the ramp voltage included in the control data CN4 Information, the voltage Δ SLP change of each count clock CKdac is adjusted. The adjustment of the slope of the reference signal Vsl〇p can be implemented by adjusting the current per unit clock by changing the current in the unit current source in addition to changing the clock cycle. The row A/D circuit 25 includes a voltage comparator 252 and a counter 254 and has an n-bit A/D conversion function. The voltage comparator 252 compares the reference signal Vslop generated from the DA converter 27a of the reference signal generator 27 with the vertical signal line 19 (H〇, (1), ...) supplied from the unit pixel 3 to each column of the control line I5 (V0). 'VI '...) analog pixel signal. The -22- 1364980 counter 254 counts the time ' until the voltage comparator 252 completes the comparison process and stores the resulting count. In the present embodiment, the 'reference signal Vslop is supplied from the DA converter 2 7 a to the voltage comparators 2 5 2 arranged in the individual columns, and the comparison processing is processed for each voltage comparator 252 by use. The common reference signal Vslop on the pixel signal voltage Vx is performed.

The communication/timing controller 20 has a control function to switch the count processing mode of the counter 254 depending on whether or not the voltage comparator 25 2 performs the comparison operation of the pixel signal reset level vrst or the signal component Vsig. - The control signal CN5 is supplied by the communication/timing controller 20 to the counter 254 in each row A/D circuit 25 to instruct the counter 254 to execute the down mode or the up mode. The step reference signal Vslop generated for the reference signal generator 27 is input together to one input terminal RAMP of the voltage comparator 252 and to the other input terminal RAMP of the other voltage comparator 252. The vertical φ signal line 19 corresponding to the vertical line is connected to the other input terminal of the voltage comparator 252, and the pixel signal voltages from the pixel array unit 10 are individually input. The output signal of the voltage comparator 2 52 is supplied to the counter 254. The count clock CK0 is input together by the communication/timing controller 20 to the clock terminal CK of the counter 254 and to the other clock terminal CK of the other counter 254. Similar to the reference signal Vslop, a multiplied clock (high speed clock) generated for the multiplication circuit of the clock converter 23 can be used as the count clock CK0. At this time, a higher resolution can be accomplished than with the main clock -23- 1364980 CLK0 input via the terminal 5a. The counter 25 4 has a characteristic that uses a common up/down counter (U/D CNT) regardless of the count mode, and the counting process can be completed by switching between the lower number operation and the upper number operation.

Although the architecture of the counter 254 is not shown, the counter 254 can be implemented by modifying the wiring configuration of the data storage unit 265 with a latch into the synchronous counter, and by receiving a single count clock CK0. Internal count. However, in the present embodiment, it is preferable to use a non-synchronous counter as the counter 254, which can output a count output 値 without being synchronized with the count clock CK0. Basically, a sync counter can also be used, however, when a sync counter is used, all flip-flops, in other words, the operation of the counter base element are limited by the count clock CK0. Therefore, if higher frequency operation is required, it is preferable to use a non-synchronous counter suitable for high speed operation because its operation limit frequency is determined only by the limit frequency φ rate of the first flip-flop. Although all the details will be described later. However, the line processor 26 (particularly the row A/D circuit 25) and the reference signal generator 27 in this embodiment have the following features: each bit during the high-speed frame rate mode using the addition read operation The frequency of the count clock (referred to as the count cycle) and/or the slope of the reference signal Vslop supplied to the row A/D circuit 25 for each column is appropriately changed 'to perform a vertical weight applying different weights to each column The addition processing in the direction 'Thus, the spatial position of each of the colors in the vertical direction after the addition can be appropriately adjusted to be appropriately spaced to obtain an image having a high resolution of -24-1364980. Preferably, the weighted addition performed by the digital arithmetic unit 29 is also performed in the vertical direction so that the spatial position of each color in the added horizontal direction can be adjusted to an appropriate pitch to achieve high An image of resolution. More specifically, at the time of the addition processing, by performing the weighted digital addition processing to change the weight of the added target pixel, the center of the added pixel is not eccentric in the vertical direction or the horizontal direction, but is moved. To a larger weight

On the side that is applied. "Change the weight of the addition target pixel" means that at least one pixel of the addition target pixel in the vertical direction and the horizontal direction has a different weight from the other pixels. For example, if the addition processing of two pixels is performed, the individual weighting can be set to a ratio of 1 to n (n is greater than 1). Preferably, η is a positive integer greater than 2 or any 値, such as 2, 3, 4, ..., etc., preferably η is a power of 2, such as 2, 4, 8, etc. Furthermore, in the case of digital addition processing, particularly in terms of processing time or dynamic range, 'preferably, a method is employed in which the slope of the reference signal Vslop remains the same when the majority of the added target columns are processed, the counter The frequency of the clock is switched. Consider the acceleration of each bit of the flip-flop, preferably using the method - in which only the flip-flops in the more efficient or lower-effect bits are made to operate at high speed, rather than making all bits positive. The counters are all operating at a speed. - The control pulse is input from the horizontal scanning circuit 12 to the counter 25 4 via the control line 1 2 c. The counter 25 4 has a latch function for retaining the count result 'and' to maintain a count 直到 until -25 - 1364980 - control pulse is received via the control line c 2 c as an instruction. The output side of the row A/D circuit 25 and the output from the counter 254 can be connected to the horizontal signal line 18. Alternatively, as shown, a data storage unit 256 stored as a η-bit memory stored in the counter 254 and a switch 258 arranged between the counter 254 and the data storage unit 256 may be arranged in the counter. The next level of 254.

If the architecture including the data storage unit 256 is employed, the gate transfer instruction pulse CN8 as the control pulse is supplied to the switch 258 and other switches in the other vertical rows by the communication/timing controller 20 at a predetermined timing. Switch 2S8. Upon receiving the memory transfer command pulse CN8, the switch 258 transmits a count corresponding to the counter 254 to the data storage unit 256. The data storage unit 256 holds/stores the transmitted counts. The mechanism for storing the counter 254 at a predetermined timing to the data storage unit 2 5 并不 is not limited to the architecture in which the switch 258 is placed. For example, the mechanism can also be implemented by using an architecture in which the counter 254 is directly connected to the data storage unit 256 and the output enable of the counter 254 is controlled by the memory transfer command pulse CN 8 or by using an architecture. The memory transfer command pulse CN8 is used as a latch clock to determine the data acquisition timing of the data storage unit 256. The data storage unit 256 receives control pulses from the horizontal scanning circuit 12 via the control line 12c. The data storage unit 256 stores the count 値' obtained from the counter 254 until the control pulse is received as an instruction via the control line c2c. The horizontal scanning circuit 12 has a function as a readout scanning unit, and is processed in the data storage unit 256 in parallel with the processing of each of the voltage comparators 252 and the counters 2 54 in the line processor 26 in parallel. Count 値. The output of the data storage unit 256 is connected to the horizontal signal line 18. The horizontal signal line 18 has an n-bit wide signal line which is the bit width of the row A/D circuit 25, and is connected to the output circuit 28 via an inductive circuit corresponding to the individual output lines, not shown. .

In particular, if the data storage unit 256 is included in the architecture, the count results stored for the counter 254 can be transferred to the data storage unit 256. Therefore, the counting operation of the counter 254, that is, the A/D conversion processing and the reading operation of the counting result of the horizontal signal line 18 can be individually controlled, so that the pipeline operation can be realized, in which the A/D conversion processing and the signal to the outside are performed. The readout operations can be performed in parallel with each other. In this architecture, the row A/D circuit 25 performs a counting operation at the pixel signal readout period corresponding to the horizontal blanking period, and outputs the counting result at a predetermined timing. More specifically, first, the voltage comparator 25 2 compares the ramp voltage supplied from the reference signal generator 27 with the pixel signal voltage input via the vertical signal line 19, and when the two voltages are equal to each other, the voltage comparator 252 The comparator output is inverted. For example, the voltage comparator 252 sets the Η level of a source potential to be inactive, and sets the level to the L level (operating state) when the pixel signal voltage is equal to the reference signal Vs lop. The counter 254 starts the counting operation in synchronization with the ramp voltage supplied from the reference signal generator 27, and the following number mode or the upper mode starts the counting operation. When the receiving comparator outputs the inverted information, the counter 254 stops the counting operation and asks for the lock (maintains /Storage) The count at that time is taken as the pixel data, thus completing the -27-1364980 A/D conversion. Subsequently, the counter 254 sequentially outputs the storage/hold pixel data to the outside of the line processor 26 or via the output according to the shift operation of the horizontal selection signal CH(i) input by the horizontal scanning circuit 12 at a predetermined timing via the control line 12c. 5c is output to the outside of the wafer having the pixel array unit 10.

Other various signal processing circuits may also be included in the elements forming the solid-state image pickup device 1, and since they are not directly related to the present embodiment, they are not displayed. [Pixel Unit] Fig. 2 is a view showing the structure of the unit pixel 3 used in the solid-state image pickup device 1 of Fig. 1, and the line connection between the drive unit, the drive control line, and the pixel transistor. The structure of each unit pixel (pixel unit) 3 in the pixel array unit 1 is similar to that of a general CMOS image sensor. In this embodiment, the 4TR structure is generally used in a CMOS sensor or φ to use a 3TR structure including a tri-electrode. Needless to say, these pixel structures are merely examples, and any structure can be used as long as it is an array structure used in a general CMOS image sensor. In an in-pixel amplifier, for example, a floating diffusion amplifier can be used. For example, a pixel amplifier (hereinafter referred to as "4TR structure") having four transistors generally used in a CMOS sensor can be used for each charge generator. 4 TR structure comprises: a readout selection transistor, which is an example of a charge readout unit (transfer gate/readout gate); a reset transistor for resetting the gate; a vertical selection transistor; and - source The pole follows the amplifying transistor, which is a detector for detecting the potential change of the floating diffusion of -28-1364980. For example, the unit pixel 3 having the 4TR structure shown in Fig. 2 includes a charge generator 32 and a four-electrode connected thereto. Specifically, the charge generator 32 has a charge accumulation function for accumulating charges; and a photoelectric conversion function for receiving light and converting the received light into a charge. The four transistors include a read select transistor (transfer transistor) 34, which is an example of a charge readout unit (transfer gate/read gate); a reset transistor 3 6, which is an example of a reset gate A vertical selection transistor 40; and a source follower amplifying transistor 42' are detectors for detecting a change in potential of the floating diffusion 38. The unit pixel 3 includes a floating diffusion amplifier (FDA) pixel signal generator 5 having a floating diffusion 38. The floating diffusion is an example of a charge injection unit having a charge product function and is a diffusion layer having a parasitic capacitance. The read selection transistor (second transfer unit) 34 is a transfer line (read selection line 55) 55 driven by a transfer drive buffer BF1, which is supplied with a transfer signal Φ TRG by φ. The reset transistor 36 is a reset line (RST) 56 driven by the reset drive buffer BF2, and the buffer BF2 is supplied with a reset signal Φ RST. The vertical selection transistor 40 is driven by the selection drive buffer BF3. The buffer BF3 is supplied with a vertical selection signal <i> VSEL via a vertical selection line (SEL) 52. Each of the drive buffers can be driven by a vertical drive circuit 14b in the vertical scan circuit 14. The source of the reset transistor 36 in the pixel signal generator 5 is connected to the floating diffusion 38 and its drain is connected to the power supply VD (which can be common to the power supply Vdd), and the one-pixel reset pulse RST is heavy Set drive buffer -29-1364980 BF2 input to gate (reset gate RG). For example, the drain of the vertical selection transistor 40 is connected to the source of the amplification transistor 42, and the source is connected to the pixel line 51, and its gate (referred to as "vertical selection gate SELV") is connected to Line 52 is selected vertically. However, the wiring structure is not limited thereto, and the vertical selection transistor 40 may have its drain connected to the power source Vdd and its source connected to the drain of the amplifying transistor 42, and the vertical selection gate SELV may be connected to the vertical selection line 52. .

The vertical selection signal 6VSEL is supplied to the vertical selection line 52. The amplifying transistor 42 has its gate connected to the floating diffusion 38, its drain connected to the power supply Vdd via the vertical selection transistor 40, and its source connected to the pixel line 51 and the vertical signal line 53 (19). Furthermore, one end of the vertical signal line 53 extends toward the line processor 26, and the vertical signal line 53 is routed toward the line processor 26, connected to the sense current supply 24, thereby forming a source follower architecture. A substantially constant operating current (read current) is supplied between the vertical signal line 53 and the amplifying transistor 42. In particular, sense current supply 24 includes an NMOS transistor (definitely referred to as a "load MOS transistor") 2 42 disposed in each vertical row, and - reference current source 244 contains current shared for all vertical rows A data storage unit 256, and an NMOS transistor 246 are generated, the gate and the drain are connected in common and the source is connected to a source line 248. Each of the drain electrodes connected to the NMOS transistor 242 is connected to the corresponding vertical signal line 53 in the row and its source is connected to the source line 248 as a ground line. Therefore, the gate of the NMOS transistor -30-1364980 242 arranged in each vertical row is connected to the gate of the NMOS transistor 246 to form a current mirror circuit which acts as a current to the vertical signal line 19. source. The source line 248 is connected to the ground (GND) at its end in the horizontal direction (the vertical lines shown in the left and right of Fig. 1), which is the substrate bias. The operating current (read current) for the ground applied to the NMOS transistor 242 is supplied from the left and right ends of the wafer.

The load control signal SFLACT for allowing the current generator 24 5 to output a predetermined current is supplied to the current generator 245 by a load controller not shown, if necessary. When the signal is read, the current generator 245 having an active load control signal SFLACT is continuously allowed to use the load NMOS transistor 242 connected to the amplifying transistor 42 to flow a predetermined constant current at a predetermined constant current. In other words, the load NMOS transistor 242 supplies a sense current to the amplifying transistor 42 by forming a source follower and an amplifying transistor 42 disposed in the selected column, thereby outputting a signal to the vertical signal line 53. In the above-described 4TR structure, since the floating diffusion 38 is connected to the gate of the amplifying transistor 42, and the amplifying transistor 42 outputs a potential corresponding to the floating diffusion 38 in the voltage mode via the pixel line 51 (hereinafter referred to as "FD" Potential ") to vertical signal line 5 3 (1 9). The reset transistor 36 resets the floating diffusion 38. The read select transistor (transfer transistor) 34 transfers the signal charge generated by the charge generator 32 to the floating diffusion 38. A number of pixels are connected to the vertical signal line 19 to select a pixel, and only the vertical selection transistor 40 in the selected pixel is turned on. Therefore, only the selected pixel is connected to the vertical signal line 19, and the pixel signal of the selected -31 - 1364980 is output to the vertical signal line 19» [Interface example between the voltage comparator and the counter] FIG. 3 is a diagram, An example of a connection interface displayed next to voltage comparator 252 and counter 2 54 is shown.

When the pixel signal voltage Vx read out from the pixel array unit 10 matches the reference signal Vslop supplied from the reference signal generator 27, the voltage comparator 252 of the corresponding vertical signal line 19 in each row inverts the comparator output Comp by A non-operating state (eg, a high level) is inverted to an operating state (eg, a low level). The counter counter 254 includes a gate 502 for controlling (gates) the output of the count clock CK0 according to the comparator output Comp from the voltage comparator 252; and a count execution unit 504 for counting according to the gate 502 The clock CIN performs a counting operation. The communication/timing controller 20 supplies the slope change command signal CHNG to the φ reference signal generator 27, a count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal TH to the count execution unit, respectively. 504. In the slope change command signal CHNG, a signal system suitable for changing the slope of the reference signal Vsi〇p in accordance with the DA converter 27a is used. For example, the 'slope change instruction signal CHNG may be the count clock CKdac capable of appropriately switching the frequency (clock cycle), or may be included in the control material CN4 as the slope (change rate) /3 of the reference signal Vslop. Communication/timing controller 20 can independently adjust and change reference signal -32- 1364980

The timing of the slope of Vslop and the timing of the counting cycle of the change counter 254 (counting execution unit 504). By controlling the vertical scanning circuit 14 to control a selection operation, the selection is for selecting the spatial position of the majority of the pixels to be processed by the voltage comparator 252, and by controlling the addition of the columns for processing the plurality of columns. The communication/timing controller 20 also has an addition spatial position adjustment unit for adjusting the spatial position of the added pixels.

For example, in the addition processing operation of the first embodiment to be described later, in the majority addition target processing of the column, the slope of the reference signal Vslop of each column is kept the same, and the counting cycle (dividing speed) is Twist to switch. For example, when the weight of the previous column (addition target column) is applied to the next column (addition column), the counting cycle is completed faster in order to make the more efficient bit flip-flop operate at high speed. The count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal TH are supplied to the count execution unit 504 in the counter 254, thereby changing the frequency division operation output of each bit to L times this speed. If the speed of the frequency division operation is changed to l times the speed while maintaining the slope of the reference signal Vslop, in practice, the A/D conversion system is performed with an L/time conversion gain of L times larger. As a result, the addition processing can be performed with a weight of l times the weight. Furthermore, in the second embodiment as will be described later; the processing operation, except for the addition processing operation in the first embodiment, even in the operation for one column, at the processing of the signal level Ssig, Before the comparison processing for the voltage comparator 252 is completed, the slope change instruction signal CHNG is supplied to the reference signal generator 27 by -33-1364980 to change the slope of the reference signal Vslop to J times larger. At the same time, the count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC', and the count clock control signal TH are supplied to the count execution unit 504 in the counter 254 so that each is output to the count execution unit 504. The frequency division operation of the bit is changed to K times the speed of the previous operation (preferably K times = J times).

If the slope of the reference signal Vslop is set to J times larger and the frequency division operation is changed to K times the speed, in practice, the period of the A/D conversion process is shortened to 1/J times and the A/D conversion system is Exceeded by K/K times the A/D conversion gain. By setting K times = J times, in practice, the period of the A/D conversion process can be shortened by 1/J times and the A/D conversion gain can be kept constant, so that the linearity of the A/D conversion result is not damaged. If the L-weighted column of the addition processing operation of the first embodiment is combined with the above-described addition processing ', it is possible to obtain the A/D conversion result /, 'Vsigl with respect to the pixel signals Vsig 1 and Vsig2 corresponding to the two columns. +K.Vsig2,,, ^ does not impair individual linearity, while reducing the period of A/D conversion processing by 1 / J times (=1 / K times). The communication/timing controller 20 determines the slope change command signal CHNG, the count mode control signal UDC, the reset control signal CLR, the data hold control pulse HLDC, and the count clock control signal TH based on the data DATA' from the external master controller. On/off timing. In the addition processing operation of the first embodiment, these 0n/0ff timings are determined in accordance with the weighting setting. In the addition processing operation of the second embodiment, these on/off timings are based on the relationship between photon shot noise and quantum noise -34-

1364980 system, depending on the purpose of higher accuracy or faster speed, and when the comparator output is not dynamic, the gate 52 transmission does not change the input count clock CK0 as the count clock CIN, and the count is executed 5 04, but When the comparator output is inverted to the active state, gate 502 transmits the count clock CK0. When the count clock CK0 is stopped, the count execution unit 504 stops the timer operation and maintains a count 値 to reflect the pixel signal voltage Vx at that time, that is, the count execution unit 504 converts the pixel signal voltage Vx into the bit data and holds the digit. data. [Counter] Figs. 4 and 5 are diagrams showing an example of the architecture of the counting unit 504 in the counter 254. Here, the architecture supporting 12 bits is displayed. The counting unit 504 in each row corresponding to each vertical signal line 19 has substantially a non-synchronous counting architecture, wherein the string has a D-type φ device and the counting output of the previous stage is input to the clock terminal of the next stage. Furthermore, the present embodiment is characterized by its architecture, wherein when the flip-flop itself reverses the output NQ back to a D input, each flip-flop can open a hold function of the inverting output NQ. 0ff operation. Also between these stages, there is a functional unit for switching between the number of counting modes and the number of the lowers, and a functional unit for switching a count clock according to the count output of the previous stage and the pulse from the gate 5 0 2 Count between clocks. set. Change unit stop stop count number

Execution line single positive and negative CK will be extra, on the root CIN -35 - 1364980

Specifically, the counting execution unit 504 has first flip-flops (FF) 510-00 to 510_11 (hereinafter collectively referred to as 510). The count execution unit 5 04 has a data holding unit (hold) 512_00 to 512_11 (hereinafter collectively referred to as 512) capable of holding the data of the inverting output terminal NQ between the inverting output terminals NQ and D inputs of the flip-flop 510. Each data holding unit 512 is controlled by other data holding control pulses HLDC (00 to 1 1). The data holding unit 512 has a function of maintaining the count output regardless of the input state of the flip-flop 510, for example, this can be implemented for mutual exclusion or gate. For example, when the material hold control pulse HLDC is operating H (H: high level), the data holding unit 512 holds the input data (inverted output NQ of the flip-flop 510), and when the data hold control pulse HLDC is inactive L (L) When the low level is on, the hold operation is released to transfer the input data (inverted output NQ of the flip-flop 510) to the D input of the flip-flop 510. The reset control signal CLR is input together to each reset terminal R of the flip-flop 510. When the reset control signal CLR is active, the flip-flop 510 sets, for example, a non-inverted output Q to an L level, and the inverted output terminal NQ is a Η level. Further, the counting execution unit 504 includes counting mode switches (U/D) 514_00 to 514_11 (hereinafter collectively referred to as 514) for switching the counting mode to the upper or lower number between the stages of each of the flip-flops 51. In response to the count mode control signal UDC, the count mode switch 514 switches the pattern of the data at the inverting output terminal NQ of the previous stage flip-flop 510 and outputs it after being invariant or inverted. For example, the count mode switch 5 1 4 can be implemented as a mutex or gate. -36- 1364980 For example, the counting mode switch 5 1 4 switches the inverting output terminal NQ of the flip-flop 5 1 0 between inverting and non-inverting, so that when the counting mode control signal UDC is at a high level, the counting execution unit 504 The upper operand is operated, and when the signal UDC is low, the count execution unit 504 performs the next operation

Further, the counting execution unit 504 includes counting clock switches (SEL) 516_00 to 516_10 (hereinafter collectively referred to as 516) between each of the flip-flops 510 and the counting mode switch 5 1 4 of the next stage. The count clock switch 5 16 switches the output pulse of the count mode switch 514 and the count clock C IN ' from the gate 5〇2 in response to the count clock control signals ΤΗ_00 to TH_10 (hereinafter collectively referred to as TH), respectively, and supplies them to the next stage. The clock terminal CK of the flip-flop 510. Each count clock switch 516 is controlled by another count clock control signal TH. The count clock control signal TH at the previous stage becomes active, and the signal TH at the next stage is sequentially activated at a predetermined delay timing (detail φ is described later). For example, when the S-number clock signal TH is not active, the count. clock switch 516 transmits the output of the count mode switch 514, and when the count clock control signal TH is switched to the active state, it transmits the count clock CIN from the gate 502. . The count clock switch 5 1 6 takes the count clock C IN from the gate 5 〇 2 in the following manner. In the first example shown in Fig. 4, the wiring is arranged such that the clock of the flip-flop 510 in the previous stage is held for each line. On the other hand, in the second example shown in Fig. 5, the count clock lines 5丨7_00 - 37 - 1364980 to 517_11 (hereinafter collectively referred to as 517) are supplied and wired together to each row and at each flip-flop 510. The count clock C IN between the stages and the gate 502 is taken out by the count clock line 517. In the example shown in Fig. 4, less wiring is required than the count clock CIN of the second example of Fig. 5. However, when the count clock CIN is sequentially transferred to the more efficient bit flip-flop 510, the lower-effect bit flip-flop 510 is still operating even if the data output therefrom is processed to be inactive.

On the other hand, in the second example shown in Fig. 5, although it is necessary to use more of the count clock CIN wiring as shown in Fig. 4, it has an advantage in that less power consumption is achieved. This is because the counting operation of the flip-flop 510 at the previous stage can be stopped after the switching, for example, by setting a clock stop unit (stop) 518 between the gate 502 and the count clock line 517 for the individual stages (_00 to _1〇), in response to the count clock control signal TH, the supply of the count clock to the flip-flop 5 1 0 is stopped. Both the first and second embodiments can be used to allow the counting execution unit 504 to operate as a non-synchronized binary counter, and by allowing the counting clock switch 516 to operate in response to the counting clock control signal TH, counting execution The unit 504 has a function of transmitting each clock input of the flip-flop 510 at each stage to the clock input of the flip-flop 510 at the next stage (lower-effect bit side). In other words, the higher-speed clocks for the lower-effect bit outputs are sequentially transferred to the next-stage side (the more efficient bit side) at a predetermined timing, so that the higher-efficiency bit output for the count clock CIN is divided. The frequency operation system is completed faster in sequence. For example, the 1/4 frequency division operation of the count clock CIN before switching can be changed to the 1/2 frequency division operation of the count clock CIN after the switch - 38 - 1364980 after the count clock is switched, because of the counting operation ( The frequency division operation is performed by a faster clock than before, so the A/D conversion can be performed at a higher speed, and the linearity of the A/D conversion is maintained by adjusting the slope of the reference signal Vslop. This will be described in more detail below. [Operation of Solid-State Camera: Basic Operation]

Fig. 6 is a timing chart showing the signal acquisition differential, which is the basic operation of the row A/D circuit 25 of the solid-state image pickup device 1 shown in Fig. 1. The analog pixel signal detected for the unit pixel 3 of the pixel array unit 10 is converted into a digital signal in accordance with the following operation. For example, a search is performed to find a point at which the reference signal Vslop is lowered by a predetermined slope in a ramp waveform and a point at which each voltage of the reference component or the signal component of the pixel signal from the unit pixel 3 matches. A count clock self-reference signal Vslop is used as a point of comparison processing to a point corresponding to the reference element or signal element matching the reference signal, counting the time period. As a result, the counts corresponding to each of the reference elements and the signal elements are obtained. In other words, the voltage comparator 252 disposed at 25 in each row compares the analog pixel signal voltage γ 读出 read out to the vertical signal line 19 with the reference signal Vslop. At this time, the counter 254 disposed in each row is similar to the voltage comparator 252 being actuated, and the certain potential of the reference signal Vsl〇p is changed to the correspondence of the counter 254 to the pixel signal voltage. Vx is converted to digital data. In the present description, the change of the reference signal Vslop is to convert the change in voltage into a change in time. Count -39- 1364980 254 counts the time by quantifying a certain cycle (clock) to convert to digital data. If it is assumed that the reference signal Vsl〇p changes Δν in the time period Δt and the counter 254 is operated in the At loop, the counter 値 becomes N when the reference signal Vslop is changed to ΝχΔν. The pixel signal So (pixel signal voltage Vx) output from the vertical signal line 19 temporally causes the signal level Ssig appearing after the reset level Srst containing the pixel signal noise as a reference level. If the first operation is performed on the reference level (reset level Srst, which is actually equal to the reset level Vrst), then the second operation is performed by the addition signal component V sig and the reset level Srst The signal level obtained is on Ssig. This operation is detailed below. In the first operation 'that is, in the A/D conversion period Trst for resetting the level Srst, the communication/timing controller 20 first sets a reset control signal CLR to the operation Η ' and resets each of the self-counters 254 The output 値 of the non-inverting output terminal Q of a flip-flop 510 is "〇,", and the counter 254 is also set to the lower mode (tl). At this time, the communication/timing controller 20^ sets the data retention. The control pulse HLDC is the operation Η, and the counting mode control signal UDC is the low level (ie, the lower number mode). ^ At this time, the vertical selection signal Φ VSEL in the _out target column Vri in the unit pixel 3 is set to be activated. Η, and the pixel signal So is allowed to be output to the vertical signal line 19, and almost simultaneously the reset signal 4RST is set to the operation Η and 38 is set to the reset potential (t1 to t2). The reset potential is output to the vertical signal Line 19 serves as the pixel signal So. Therefore, the reset level Srst appearing on the vertical signal line 19 becomes the pixel signal voltage VX. At this time, since the pixel in-pixel amplifier of each unit pixel 3 (pixel letter -40 - 1364980 amplifier) 5) changes are given The potential of the converged reset signal Sr st is changed.

After the first readout operation of the pixel signal read out from the unit pixel 3 in the read target column Vn to the corresponding vertical signal line 19 (H0, H1, ...) is stabilized, that is, after the reset level Sr st converges The communication/timing controller 20 supplies control data CN4 for generating the reference signal Vsi op to the reference signal generator 27. Here, in order to cause the counting operation performed by the counter 254 to start changing simultaneously with the reference signal Vslop, the data of the hold control pulse HLDC is used as the control data CN4 and is set to be inactive L(tlO) ^ in response to this, when When the reference signal Vslop is used as a comparison voltage to the input terminal RAMP of one of the voltage comparators 252, the reference signal generator 27 inputs a step-by-step or linear voltage waveform which changes with time as a sawtooth wave (slope wave shape), starting from the beginning The voltage SLP_ini starts. The voltage comparator 252 compares the reference signal Vslop with the pixel signal voltage Vx of the vertical signal line 19 supplied from the pixel array unit 10. Simultaneously with the input signal RAM1 input to the input terminal RAMP of the voltage comparator 252, the comparison period in the voltage comparator 252 is synchronized with the reference signal Vslop supplied from the reference signal generator 27 by the counter 2 54 disposed in each column. It was measured. Actually, the data hold control pulse HLDC is set to be inactive L to generate the reference signal Vslop, and the hold operation of the data holding unit 512 is performed, and therefore, the counter 254 starts counting from the start to the first count operation. More specifically, the counting operation starts from the negative direction. The voltage comparator 2 5 2 compares the oblique -41 - 1364980 wave reference signal Vslop supplied from the reference signal generator 27 with the pixel signal voltage Vx input via the vertical signal line 19, and when the two voltages are equal, the voltage comparator 252 The comparator output is inverted from the Η level to the L level. In other words, the voltage comparator compares the voltage signal (reset level Srst) corresponding to the reset level Vrst with the reference signal Vslop, and generates a low-state active (L) pulse signal having a corresponding value in the time axis direction. The level of the level Vrst is reset and the generated pulse signal is supplied to the counter 254.

As a result, the counter 2 54 almost inverts the output of the comparator while stopping the counting operation, and latches (holds/stores) the count of the time 値 as a pixel material, thereby completing the A/D conversion. In other words, the pulse of the pulse signal having a quasi-low state (L) obtained by the comparison operation of the voltage comparator 252 is counted by the count clock CK0, and a display corresponding is obtained. The count 値 of the digit 値Drst (eg, the sign is -Drst) is reset at the level of the Vrst level. After a predetermined number of cycles have elapsed, the communication/timing controller 20 sets the material hold control pulse HLDC to the actuation H (tl4). Therefore, the communication/timing controller 20 stops generating the ramp reference signal Vslop (tl4) and returns to the start voltage SLP_ini. Since in the first operation, the voltage comparator 252 detects the reset level Vrst in the pixel signal voltage Vx and the counter 254 performs the counting operation, the reset level Vrst of the unit pixel 3 is read out to reset the level Vrst Perform A/D conversion. The reset level Vrst contains offset noise, which is changed by the unit pixel 3. However, the change in the reset level Vrst is usually small, and the reset -42 - 1364980 level Vrst is approximately the same for all pixels. Therefore, the output 値 of the reset level Vr st of the pixel signal voltage Vx of the arbitrary vertical signal line 19 has been largely known.

Therefore, in the first read operation and the A/D conversion for resetting the level Vrst, the lower period (comparison period) can be shortened by adjusting the reference signal V slop . For example, the comparison operation is performed by setting the maximum period for the comparison operation (ie, the A/D conversion period for resetting the element) to a 7-bit count period (128 clocks), and performing the reset level Srst (heavy) Set on the standard Vrst). In the next second operation, that is, in the A/D conversion period Tsig for the signal level S si g , in addition to the reset level Vrst, the signal component in response to the amount of incident light of each unit pixel 3 is also Read out and perform an operation similar to the first read operation. More specifically, the communication/timing controller 20 first sets the count mode control signal UDC to the high level and the set counter 254 to the upper mode (tl6). At this time, in the unit pixel 3, when the vertical selection signal <i>VSEL in the read target column Vn is held as the operation ', a transmission signal φ TRG is set to the operation Η and the signal level Ssig is The vertical signal line vertical signal line 19 (tl8 to t19) is read out. After the second readout of the unit pixel 3 in the read target column Vn is stabilized to the vertical signal line 19 (H0, H1 '...), the communication/timing controller 20 supplies the control data CN4 for generating the reference signal Vslop to The reference signal generator 27. Meanwhile, in order to cause the reference signal Vsl op to start changing simultaneously with the counting operation of the counter 254, the data holding control pulse HLDC uses -43-1364980 as the control data CN4 and is set to be inactive L (t20). In response to this, the reference signal generator 27 inputs a one-step or linear voltage waveform as a reference signal Vslop to the comparison voltage of the input terminal RAMP of the voltage comparator 252, which waveform changes in time by a sawtooth wave (ramp wave) and Starting from the starting voltage SLP_ini. The voltage comparator 2 52 compares the reference voltage Vslop with the pixel signal voltage Vx supplied from the pixel array unit 10 to the vertical signal line 19.

Simultaneously with the reference signal Vslop input to the input terminal RAMP of the voltage comparator 252, during the comparison in the voltage comparator 252, the counter 254 in each column is synchronized with the reference signal Vslop supplied from the reference signal generator 27. . Actually, at this time, the material hold control pulse HLDC is set to be inactive L to generate the reference signal Vslop, which holds the holding operation of the data holding unit 512. Therefore, in the second counting operation, the counter 25 4 starts counting backwards with the first operation, and the digit 値Drst of the reset level Srst of the pixel signal voltage Vx obtained by the first reading (here, negative) 'And A/D conversion operation. In other words, the counting operation starts in the positive direction. The voltage comparator 252 compares the ramp reference signal Vslop supplied from the reference signal generator 27 with the pixel signal voltage Vx' input via the vertical signal line 19 when the two are equal. The voltage comparator 252 compares the output of the comparator by the clamp. Quasi-inverted to L level (t 22). In other words, the voltage comparator 2 52 compares the voltage signal (signal level Ssig of the pixel signal voltage Vx) corresponding to the reset level Vrst with the reference signal vslop, and generates a low-state active (L) pulse signal The time axis direction has a corresponding signal component -44 - 1364980

The level of Vsig is supplied to the generated pulse signal to the counter 254. As a result, the counter 254 stops the counting operation almost simultaneously with the inversion of the comparator output, and latches (holds/stores) the count at that time as the pixel data, thereby completing the A/D conversion. In other words, the width of the low-level active (L) pulse signal obtained in the time axis for the comparison operation in the voltage comparator 252 is counted by the count clock CK0, and is obtained corresponding to the pixel signal voltage Vx. The count of the signal level Ssig is 値.

In the unit pixel 3, after a predetermined number of cycles, the vertical selection signal Φ VSEL in the read target column Vn is set to be inactive L, the pixel signal So output to the vertical signal line 19 is stopped, and is used for reading. The vertical selection signal φ VSEL out of the column below the target column Vn+Ι is set to the active level (t26). At this time, the communication/timing controller 20 is prepared to process the next read target column Vn+1. For example, the count mode control signal UDC is set to the low level and the counter 254 is the lower mode. In the second operation, since the counting operation is performed by the voltage comparator 252 detecting the signal level S sig of the pixel signal voltage VX, the signal component Vsig of the unit pixel 3 is read out to perform the signal level Ssig A/D conversion. Since the signal level Ssig is a level obtained by adding the signal component Vsig to the reset level Srst, the count 値 for the A/D conversion of the signal level Ssig is basically "Drst + Dsig". However, since the upper number is started by "-Drst" which resets the A/D conversion result of the level Srst, a count 値 becomes "-Drst + (Dsig + Drst) = Dsig". If it is assumed that the A/D conversion period Trst for resetting the level Srst and -45 - 1364980 are used for the A/D conversion period Tsig of the signal level Ssig, the voltage 値 (conversion coefficient) per bit number is α [V] /bits], and the A/D conversion cycle count 値Dsig is converted to voltage 値, and the voltage 信号 of the signal component Vsig becomes α • D sig.

For example, 'as shown in FIG. 6', which represents the digit 値 in the parentheses at the position of the pixel signal voltage νχ, the reset level Srst of the pixel signal voltage Vx in the vertical signal line 19 is 10, the signal component is 60, and The signal level Ssig is 70 digits. In the A/D conversion period Trst of the reset level Srst, when the count 値Drst becomes -1 0, the 'reference signal Vslop and the pixel signal voltage Vx match (cross) and the comparator output of the voltage comparator 252 is inverted to Actuating the L level causes the counter 254 to stop the next operation. Therefore, the A/D conversion result of the reset level Srst becomes the -pixel array unit 1〇, and this is held until the end of the A/D conversion period Tsig for the signal level Ssig, which is used for reading. The period of the next pixel signal. Furthermore, in the A/D conversion period Tsig of the signal level Ssig, the signal level is read by the unit pixel 3, so that the counter 2 54 starts counting. When the reference signal Vslop becomes equal to the potential of the pixel signal voltage Vx in the A/D conversion period Trst (point P in the figure), the count 値 becomes 〇, and when the signal level of the reference signal Vslop and the pixel signal voltage Vx When the Ssigs are equal to each other, the comparator output from the voltage comparator 252 is inverted to the actuation L, whereby the counter 254 stops the upper operation. At this time, the actual number of the number counted on the counter 2 5 4 is 70 ' However, the counter 2 5 4 starts from the negative 値-1 ,, so the actual count 値 is -46- 1364980 ”- 10 + 70 = 60", making it a digit of the signal component Vsig 値 Dsig = 60.

In other words, in the present embodiment, the counter 254 performs the first operation down number and performs the second operation upper number. Therefore, in the counter 254, the differential processing (subtraction processing) is automatically performed between the count 値 "-Drst" and the count 値 "Drst + Dsig", "-Drst" is the A/D conversion period, "Drst + Dsig" The A/D conversion period for the signal level Ssig, and the count 値Dsig corresponding to the result of the differential processing are held in the counter 254 < the count corresponding to the difference processing result and held in the counter 254 値Dsig Corresponds to the signal component Vsig. As described above, by performing the comparison processing of the reset level Srst (actually equal to the reset component Vrst) and the signal level Ssig, and performing the lower-number processing and the upper-number processing together with the comparison processing, there is a corresponding correspondence. The count 値 of the subtraction result (count 値 in the second comparison period) - (count 値 in the first comparison period). At this time, the offset component of the row A/D circuit 25 must be actually considered. Therefore, the equation (count in the second comparison period) is completed (the count of the shift in the first comparison period 値) = (the reset level Srst + the signal component Vsig + the offset of the row A/D circuit 25) Component) - (Reset level Srst + offset component of row A/D circuit 25) = (signal component Vsig). It is also possible to eliminate the offset component of each row A/D circuit 25 by the above two readout processing and automatic differential processing in the counter 254 except for the change of the reset component Vrst including each of the unit pixels 3. Therefore, it is possible to obtain an A/D conversion junction -47- of the signal component VsU corresponding to the amount of incident light of each unit pixel 3.

1364980 fruit. Therefore, the row A/D circuit 25 of the present embodiment is not only used as a unit for converting an analog pixel signal into a digital pixel signal, and is also a CDS processing functional unit. In the second operation, the A/D conversion is performed by reading out the signal component Vsig corresponding to the input. Therefore, in order to judge the amount of light at the level, it is necessary to set the upper period (t20 to t24 period) so that the reference signal supplied to the voltage comparator 252 can be significantly changed. Therefore, in the present embodiment, the comparison longest period of the signal level Ssig is set to, for example, a 12-bit count period (4096 hours | comparison is performed on the signal level Ssig. In other words, for heavy Srst (reset) The longest period of the comparison processing (for resetting the A/D conversion period) of the level Vrst/reference component is set to be shorter than the longest period of the comparison processing for the letter Ssig (ie, the A/D period of the signal component) The longest period of the comparison processing of the reset level Srst is set to the longest period for the comparison processing of the signal level Ssig, and is determined to be equal to the two longest periods of the comparison processing, that is, for the reset level for the signal bit The maximum 値 of the A/D conversion period of the quasi-Ssig is equal, and the total length of the two A/D conversion periods is shortened. At this time, although the comparison bits between the first and second times are the same, the communication/timing controller 20 supplies control data to the reference signal 27, and the reference signal generator 27 generates a reference Vslop according to the control signal. Therefore, the slope of the reference signal Vslop, that is, the reference signal digital position, also ranges from the number of illuminations: comparing the Vslop operation) And set The level of the level component is set to be short and not set to Srst and . Therefore, the number of the test signal Vslop -48- 1364980 is the same for the first time and the second time. If the reference signal V si op is generated under digital control, the slope of the reference signal Vs lop is easily made the same between the first and the second. In this way, the accuracy of the A/D conversion can be made equal, and the result of the subtraction processing by the up and down counters can be correctly obtained.

The row A/D circuit 25 of the present embodiment has a data storage unit 256 at the counter 254 of the next stage. Before the operation of the counter 254, the count result obtained by processing the previous column Hx-1 is transferred to the data storage unit 256 according to the memory transfer command pulse CN 8 from the communication/timing controller 20, in other words, at A/D. After the end of the conversion period, the data in the counter 254 is stored in the data storage unit 256, and the row A/D circuit 25 starts the A/D conversion processing of the next column Vx+1. The data stored in the data storage unit 256 after the A/D conversion process is sequentially selected by the horizontal scanning circuit 12 and can be read by the output circuit 28. In the architecture in which the data storage unit 256 is not provided, since the pixel data is output to the outside of the line processor 22 only after the second read processing, that is, after the A/D conversion processing is completed, the read processing is performed - limit. On the other hand, by arranging the data storage unit 256, before the read processing (A/D conversion processing), the count indicating the result of the last subtraction processing is transmitted to the data storage unit 25, and therefore, there is no read processing. limit. Furthermore, since the count result held in the counter 254 can be transferred to the data storage unit 256, the count result of the counter 254, that is, A/D conversion, and the result of reading the count to the horizontal signal line 丨8 Read -49- 1364980 out operations can be independently controlled. Therefore, it is possible to perform a pipeline operation which performs A/D conversion processing and readout operation in parallel with signals read out to the outside.

As described above, in the solid-state imaging device 1 of the present embodiment, the upper and lower numbers can be switched. At this time, the upper counter which can switch the counting mode itself is used to perform the counting process twice, and at the same time, the processing mode is switched. The structure in which the unit pixels 3 are arranged in columns and rows is constructed in a row parallel A/D circuit in which row A/D circuits 25 are arranged in each vertical row. Therefore, it is possible to directly obtain the result of the subtraction processing between the reference level (reset level Srst) and the signal level Ssig as a result of the second count processing for each vertical line. The memory device for storing the reset level Srst and the signal level Ssig is implemented as a latch function of the counter. Therefore, it is not necessary to store another AD dedicated data in addition to the counter. In addition, it is not necessary to prepare a special subtractor for counting the difference between the digital data corresponding to the signal level (reset level Srst) of the reference component and the digital data corresponding to the signal level of the signal component. Therefore, it is possible to directly obtain the result of the subtraction processing between the reference level (reset level Srst) and the signal level Ssig as a result of the first-S tenth processing of each vertical line. The memory device for storing the count result of the reset level Srst and the signal level Ssig is performed by the latch function of the counter. Therefore, it is not necessary to provide a dedicated memory for storing AD conversion data outside the counter. It is also unnecessary to prepare a special subtractor for calculating the digital data corresponding to the signal level (reset level Srst) of the reference component -50364840 and the digital data corresponding to the signal level of the signal component. Difference. This architecture can be accomplished by combining individual up and down counters. However, at this time, it is possible, for example, to require a function element to start after loading the count of a counter (in the above example, the down counter) into another counter (upper counter in the above example). Counting operations, or subtracting each count 为 for digital counting processing.

For example, it is possible to perform the next operation in the A/D conversion period in order to reset the level Srst 'to maintain the A/D conversion result of the reset level Srst of the unit pixel 3, and for the signal level Ssig, at A The upper number operation is performed in the /D conversion period Tsig to obtain the A/D conversion result from the signal component Vsig of the reset level Srst. That is, actually, the A/D conversion function and the CDS processing of the signal component Vsig are simultaneously performed. Furthermore, since the pixel data indicated by the count 保持 held in the counter 254 displays a positive signal voltage, it is not necessary to perform a complementary calculation for changing the negative signal voltage to the positive signal voltage, which is related to the current system. Highly consistent. Furthermore, by providing the data storage unit 256 at the lower level of the counter 254, it is possible to perform the signal output operation from the data storage unit 256 via the horizontal signal line 18 and the output circuit 28 to the outside in parallel, and the reading for the current column Hx. The operation and the counting operation of the counter 2 5 4 are performed to complete more effective signal output. The count 値Dsig obtained by converting the signal component Vsig of the pixel signal voltage Vx into digital data is stored in the material storage unit 256, and then sequentially read out to the outside by the horizontal sweep circuit 12. In this manner, since the -51 - 1364980 signal charge generated by the charge generator 32 is processed as an analog electrical signal and processed in parallel by each column to the digital data, and then converted to digital data, a High-speed counting and high-speed processing. [A/D conversion + addition processing: basic operation]

Fig. 7 is a timing chart for displaying the addition processing in the vertical direction in parallel with the A/D conversion processing operation. For simplicity of explanation, the offset of the row A/D circuit is ignored. Each of the timings and signals in Fig. 7 is represented by the sequence and signal shown in one of the rows of Fig. 6, regardless of whether or not processing is the target column. In the description, the timing and signal are treated to distinguish the reference symbol representation of the target column. The same is true for other similar timing diagrams. The addition processing in the vertical direction performed in parallel with the A/D conversion processing operation is performed in the high-speed frame mode by setting the exposure period of the unit pixel to 1 /2 time compared with the normal frame mode. The pixel information is read out by all the unit pixels 3 in the pixel array unit 10. Even after the A/D conversion processing is performed, for the unit pixel 3 in a certain column, the counter 256 can express the A/D conversion result for the signal level Ssig by the count of η-bits. In the present embodiment, by using the data retention characteristic of the counter 254, the processing for adding the A/D conversions of the unit pixels 3 in the plurality of columns is performed in the counter 254. Most of the columns that are subject to addition processing can be two or more columns, or any number of columns greater than three. The acceptable relationship between the majority of the columns is not just the adjacent columns but also the columns. For example, typically, if the pixel array unit 10-52-1364980 is used to capture a color image, an appropriate column is selected in order to match the color configuration of the color separation filter, i.e., the same color element is added. For example, if configured for Bayer, the addition process is performed in an odd column or an even column.

The same is true for the addition processing in the horizontal direction. Most columns that are subject to additional processing can also be two or more columns, or any number of columns greater than three. The acceptable relationship between most columns is not just for adjacent rows but also for several rows. For example, typically, if pixel array unit 1 is used for color image capture, in order to match the color configuration of the color separation filter, i.e., the additive color components are summed, the appropriate line system is selected as the target. For example, if configured for Bayer, the addition process is performed on odd or even rows. The following description is based on the assumption that the addition processing is performed by the counter 2 5 4 between two columns of any column Iv and any column Jv (addition calculation in units of two columns), and the counter 254 is in row A/D. The circuit 25 has an up/down number function, and thereafter, the addition processing is performed by the digit arithmetic unit 29 between two lines of an arbitrary line Ih and an arbitrary line Jh (calculated by adding two rows). In other words, the explanation assumes that the addition calculation is based on two columns and two rows having a predetermined relationship. Furthermore, it is assumed that the column Iv is the addition target column and its A/D conversion system is executed first, and then the A/D conversion is performed on the column Jv. The basic operation description of the differential processing can be taken from the signal. It is understood that when the signal of the unit pixel 3 in the column Iv is read and the A/D conversion processing is performed, first, the vertical selection signal of the target column Iv is read (pVSEL_Iv). It is set as the operation Η, and allows the pixel signal So to be output to the vertical signal line 19. At this time, although not shown, all the data hold control pulses HLDC00 to HLDC1 1 are set to the actuation H (t 1 - Iv to 11 0_Ιν) -53 - 1364980, and set to no-operation L during the comparison processing, and counting processing (tl〇_Iv to t14_Iv), all the count clock control signals ΤΗ00 to TH11 are set to be inactive L (tl_Iv to t26_Iv).

It is assumed that the reset element of the column Iv is Vrst_Iv and its reset level is Srst_Iv, and the signal component of the column Iv is Vsig_Iv and its signal level is Ssig_Iv. By performing comparison processing and counting processing (tl_Iv to t26_Iv) on them, the counter 254 holds the digit 値Dsig_Iv(t26_Iv) obtained by the equation, where: (counting in the second comparison period 値) - (in the first Count in the comparison cycle 値) = "(Srst_Iv + VSig_Iv)_

Srst_Iv = Vsig_Iv". After the A/D conversion period of the column Iv is completed, it is not necessary to reset the counter 254, and the signal read operation and A/D conversion processing of the unit pixel 3 in the column Jv are sequentially performed, similarly The read operation for the processing of the column Iv is repeated. Therefore, first, the vertical selection signal φ VSEL_Iv of the previous read target column Iv is set to be inactive L, and the vertical of the next read target column Jv φ The selection signal Φ VSEL_Jv is set to the operation Η, and allows the pixel signal So to be output to the vertical signal line 19 (tl_Jv = t26_Iv)e. At this time, all the data retention control pulses HLDC00 to HLDC11 are started to be set to the actuation H (tl_). 】v to tlOJv), and in the comparison processing and counting processing (tlO_Iv to t14_Iv) is set to no action L, although not shown, all the count clock control signals ΤΗ00 to TH11 are set to no action L (tl_Jv to t26_Jv) Assume that the weight component in column Jv is Vrst_Jv, its reset level is Srst_Jv, and the signal component in column Jv is Vsig_Jv and its signal bit -54-1364980 is Ssig_Jv. By performing comparison processing on them Counting processing (t l-Iv to t26_Iv), after the A/D conversion of the column Jv, the counter 254 holds the digit 値 obtained by the equation, where: "Vsig_Iv + (Srst_Jv + Vsig_Jv)_Srst_Jv = Vsig_Iv + Vsig_Jv". In other words, The counts obtained by adding the two signal components Vsig_Iv and Vsig_Jv of the columns Iv and Jv in the vertical direction are held in the counter 254 (t26_Jv).

For example, as shown in FIG. 7, one of the digits is indicated in the parentheses of the line graph of the pixel signal voltage Vx, which assumes that the reset level Srst_Iv in the column Iv and the Srst_Jv in the column Jv are 10, the signal component Vsig_Iv and Vsig_Jv are 60, and the signal levels Ssig_Iv and Ssig_Jv are 70. At this time, in the A/D conversion of the signal level Ssig_Iv (signal component Vsig_Iv) in the column Iv, the count 値Drst_Iv (= -10) obtained by performing the A/D conversion of the reset level Srst_Iv is performed. As the upper number of the starting point, after the processing, the count 値Dsig_Iv in the counter 254 becomes 10+70=60". Subsequently, in the A/D conversion of the column Jv, the A/D conversion by the column Iv is obtained. The count 値Dsig_Iv(=60) is used as the starting point, and the lower number is first executed at the heavy level SrSt_JV, and 値Drst_Jv held in the counter 254 becomes "60-1 0 = 50". The upper number is executed on the signal level Ssig_Jv by using the count 値DrSt_Jv (= 50) as a starting point, and the count ADD ADD held in the counter 254 after processing becomes "50 + 70=1 20 This 値 denotes the result of adding the signal component Vsig_Iv in the column Iv to the signal component Vsig_Jv in the JV. In the previous example, the digital addition processing is performed by switching the upper and lower numbers -55-1364980

And is stuck in the row A/D circuit 25. At this time, if the counter can switch the counting mode by using itself, it is advantageous in that it is possible to automatically perform CDS processing for eliminating the reset component Vrst and the addition processing of the signal vsig of the unit pixel 3. This architecture can be implemented by combining individual up-counters and down-counters. However, in this case, it may be necessary to have a function element 'for example' counting in the device-counter (in this case, the lower-numbered device) to another counter ( In this example, the counting operation is started after the counting device, or each counting 相 is subtracted or added by the digital calculation processing. The counter 25 4 transmits the count 値 to the horizontal signal line 18 via the data storage unit 256 after the A/D conversion process. At this time, the addition result obtained by adding the signal components Vsig_Iv and Vsig_Jv of the two columns Iv and Jv in the vertical direction is sequentially supplied to the digital arithmetic unit 29. By repeating the operation similar to the above, it is possible to obtain an image in which the pixel information is reduced to 1/2 in the vertical direction (in the vertical (row) direction of the sensing surface). As a result, the frame rate can be increased up to twice as high as the normal frame rate mode in which all pixel information is read. The digital arithmetic unit 29 adds the signal components Vsig_Iv and Vsig_Jv (hereinafter referred to as column addition data ADD) of the two columns Iv and Jv in the vertical direction supplied from the self processor 26 and the data Add_Ih in the row Ih and The data in the row Jh is added to the data ADD_Jh, and finally, the digital data indicating the addition result of the two columns and the two rows is obtained. For example, it is assumed that the counter 254 performs an addition process for the odd column and the adjacent one of the even columns, and the digit arithmetic unit 29 performs the addition processing for the odd row and the adjacent even row. At this time, the digital arithmetic unit 29 from the data storage -56-

1364980 The storage unit 256 reads out the addition data of the even-numbered rows and the odd-numbered rows, thereby performing the addition operation between the two rows. As a result, the digital arithmetic unit 29 obtains the digital data, adds the two-line signal components Vsig_lvlh and Vsig_IvJh components Vsig_JvIh and Vsig_JvJh, and adds the odd-numbered even rows Jh in the odd-numbered rows Ih in the horizontal direction. The latter two behaviors are odd in the horizontal direction adjacent to the even column Jv of the odd column Iv. In other words, it is arranged in four pixels adjacent to two columns and two rows. The voltage Vx outputted from the unit pixel 3 via the vertical signal line 19 is converted into a digital volume by the row A/D circuit 25, and is added in a plurality of unit pixels in the vertical direction (row direction), and the unit pixel 3 is arranged. Between two columns). With the above, the following effects can be obtained. For example, from the representation of the amount of information on the pixel, this is the same as the subtraction of the pixel count (jump read) 1/2. However, since the pixels in the vertical direction are added, the pixel resources are multiplied. Therefore, even if the exposure for the unit pixel 3 is 1 /2 time to ensure that the frame rate is, for example, twice as high, the digital swap is added between the two columns of unit pixels, and the one-pixel information is multiplied. Therefore, compared with the normal frame rate mode, the sensitivity and, in other words, the shorter exposure time of the unit pixel 3 is reduced by the information amount of the information. Therefore, it is not necessary to reduce the sensitivity to a higher frame rate. Furthermore, since the addition processing is performed by and is represented by the two lines of the result 'the first number of rows and the adjacent number of rows Ih and the operation system is performed by the pixel signal and the digital system 3 (In the previous example, there is a information cycle that can be set in the vertical direction for the pixel information message. The amount of information that is set to A/D is reduced. If no image is produced, it can be built-in-57- The row A/D circuit 25 of the 1364980/down counter operates in a switching mode between the upper and lower numbers, so that a higher accuracy addition operation can be realized without using an external memory device separate from the wafer. Alternatively, an additional circuit arrangement is used as a row-parallel ADC having pixel array elements 1 and 26 mounted in the same semiconductor region.

In the above example, the addition of the pixels performed in the two columns is exemplified and explained, however, this is not limited to the processing of adding two columns, and may be used for a plurality of columns. At this time, if the number of added columns is Μ, the amount of image data can be compressed to 1/Μ. Furthermore, when the amount of image data is compressed to 1/Μ, the frame rate can be increased by a factor of two by changing the data output rate. Similar to the techniques disclosed in the above patent documents, paragraphs 68 to 71 and 87, various modifications can be made. Detailed descriptions thereof can be omitted here. [Disadvantages of Digital Addition Processing] Figs. 8A to 8D are diagrams for showing the disadvantages of the digital addition processing of the counter 254 in the vertical direction and the digital addition processing of the digital arithmetic unit 29 in the horizontal direction. The figure shows the pixel configuration performed in the addition operation in the vertical direction and the horizontal direction. If the digital addition processing is performed as above, the spatial center of the pixel in the added image is the intermediate position of the addition target pixel. This relationship is sequentially accumulated, and the pixel positions in the added image are determined. If the column order or the row order of the added target pixels is sequential, for example, 1 (Λ -58-

1364980, 2, 3, 4, ..., there is no problem, but if, for example, a column order is not sequential, for example 1, unit pixels 3, 2, 4, ... actually, when capturing monochrome images, in most cases It is not necessary to change the addition target pixel because the addition processing is usually performed, and when a single-wafer type image pickup device is used to add the same addition target pixel, a problem may occur because the addition order must be based on the color separation. The color configuration of the filter is determined. For example, it is decided to use a Bayer configuration filter as a color filter to filter R, G, and B as shown in Fig. 8A (Gr is in the column, Gb is G in the column B). When the addition processing is performed on two columns and two rows, the vertical φ VSEL is in the order of the first column, the third column, the second column, the fourth column, the seventh column, the sixth column, and the eighth column... The bottom designation is as shown in the schematic diagram (Fig. 8B), in which pixels arranged in the order of the row β are read, and two columns having the same color, i.e., even columns, are supplied to the line processor 26. When the same color is input in the vertical direction, the row A/D circuit 25 in the vertical row in each of the setters 26 performs the addition where the row A / D circuit 2 5 sequentially performs the addition processing on the following: Each image of the R component and the Gr component of each of the two columns and the fourth column having the R component and the Gr component in the three columns and the G component and the G component in the fifth and seventh columns Signals having a Gb component and a B component in the sixth column and the eighth column. In other words, when in the vertical direction, the two-phase order or line of pixels is problematic. There are problems, order. The color of the phase pixel of the mirror, which has the G selection signal in the fifth column, column. Therefore, the Harmony 26 has an odd number of columns and is processed in the row. For example, the first column and the number; in the prime signal: prime signal; when each pixel of the same color is divided into -59 - 1364980 is input to the row A/D circuit 25, the row A/D circuit 25 performs addition on the same color component. operating"

The schematic diagram after the addition processing is as shown in Fig. 8C. The center column of the two-addition target column, that is, the center in the vertical direction at the time of addition becomes the center of the added pixel. For example, each center position is: a second column after adding the first column and the third column; and a third column after adding the second column and the fourth column: in the fifth column and the seventh column The sixth column after the addition; and the seventh column after the sixth column and the eighth column are added. Once this image is targeted, the digit arithmetic unit 29 sequentially takes the column addition data ADD, and when the same color is input in the horizontal direction, performs an addition operation. For example, the digital arithmetic unit 29 sequentially performs an addition operation on the following: 'in each of the pixel signals having the R component and the Gb component in the first row and the third row: having the Gr component in the second row and the fourth row Each pixel signal of the B component; each pixel signal having an R component and a Gb component in the fifth row and the seventh row; and each of the Gr component and the B component in the sixth row and the eighth row Pixel signal. In other words, when two pixels having the same color component in the horizontal direction are input to the digital arithmetic unit 29, the digital arithmetic unit 29 performs an addition operation on the same color component. In the schematic diagram after the addition processing, there is a center line in which the two phases are added to the phase line, i.e., the center of the horizontal direction at the time of addition becomes the center of the pixel after the addition. For example, 'each center position is: the second line after the first line and the third line are added; the third line after the second line and the fourth line are added; after the fifth line and the seventh line are added, The sixth line; and the seventh line after adding the sixth line -60-1364980 and the eighth line

If the center pixel system combination shown in FIG. 8C with respect to the vertical direction is as described above, as shown on the right side of FIG. 8D, the center of the 2x2 lattice formed by each color becomes the spatial position of the added color. . For example, according to the operation code n (n is 0 or a positive integer), four columns and four rows are assumed to be a combination 'the center of the pixel R is "2 + 4n" column and, 2 + 4n" row, pixel Gr The center is the "2 + 4n" column and the '3+4n" row, the center of the pixel Gb is, '3+4η, the column and the "2 + 4η" row, and the center of the pixel 为 is, '3 + 4η" Listed with the "3+4n" row. At this time, it can be understood that the spatial position of each color is arranged equidistantly before being added, as compared with the original position of the pixel shown on the left side of FIG. 8D. After the addition, the spatial position of each color is grouped in groups of four columns and four rows, and the other groups of four columns and four rows are also considered, and the pixels are not arranged in equal distances. The problem of image resolution. Specifically, it is difficult to obtain a high-resolution addition image. φ [Improvement method of resolution of added image: first embodiment] FIGS. 9 to 11 are diagrams for displaying the first An embodiment is a method for solving the digital addition processing of the counter 254 in the vertical direction and the horizontal direction by the digital arithmetic unit 29 The problem of lowering the resolution in the digital addition processing. Figs. 9 and 10 are timing charts showing the weighted phase in the vertical direction parallel to the execution of the A/D conversion processing in the resolution improvement method of the first embodiment. Addition processing. For the sake of simplicity, the offset component of the row A/D circuit is omitted. Fig. 11 is a schematic diagram showing the resolution when in the first embodiment -61 -

1364980 The role of the count clock switch 516 operating in the improved method. The example shown in Fig. 9 and the pixel array unit ίο is for the two addition processing ' and the weighting ratio between the two phase images is set to 1 to double weighted addition). The first example shown in Fig. 9 is when the ratio is the double-weighted addition, wherein in the two-addition target column, the weighting of the first column Iv at the A/D turn is set to 1, and at A The weight of the /D conversion to the new column Jv is set to 2. On the other hand, as shown in the second example of the figure, the double-weighted addition of the ratio of 2 to 1 is added, wherein in the target column, at the time of A/D conversion, the weight of the first column Iv is 2, and at A/ In the D conversion, the weight of the next column Jv is set to 1 in the addition processing in the vertical direction, if the weighting is counted to 2, that is, if the A/D conversion gain is multiplied, then any method can be used. The first method is to reduce the reference signal Vslop (in this case, the slope is multiplied by 1/2); the second method is to increase the counter drive speed (in this case, twice the speed): and the third method is the φ test signal. The slope adjustment of Vslop and the frequency division speed adjustment of the counter are likely to arbitrarily change the slope in the first method for reducing the slope of the reference signal Vslop, but the A/D conversion period becomes longer. Say' because the switchable voltage width (i.e., dynamic range) becomes narrower in a predetermined A/D conversion period, there are several disadvantages if the a/D conversion is operated at a high speed or a wide dynamic range. Unlike the first method, the second method increases the frequency division weight of the counter can be set' without affecting the A/D conversion period or dynamic range. However, if it is supplied to the counter 254 when counting the pixel 2 (referred to as 1 to 2 when the processing is performed as I 0), the two phases are set to the 254 of the frequency of the slope used by the counter 254, although in other words The length of the reason requires speed, and the clock CK0 -62 - 1364980 itself changes, the clock frequency can be arbitrarily changed. However, due to the adoption in this embodiment, the weight 値 is set to a power of 2, if used as a bit unit The mechanism for changing the frequency dividing speed of the counter 254 does not change the clock frequency of the counting clock CK0.

On the other hand, in the slope adjustment of the combined reference signal Vslop of the third method and the frequency division speed adjustment of the counter, the individual advantages of the adjustment are combined. Even if the mechanism for changing the frequency dividing speed of the counter 254 of the one-element unit is used without changing the clock frequency of the count clock CK0, it is possible to set any weighting 値 without affecting the A/D conversion period or the dynamic range. [Weighted addition in the vertical direction] As shown in Fig. 9, when the signal of the first column IV of the two-add target column is read out and the A/D conversion process is performed thereon, first, the vertical direction of the target column Iv is read. The selection signal Φ VSEL_Iv is set to the operation Η, and allows the output of the pixel signal So to be output to the vertical signal line 19. At this time, all the data hold control pulses HLDC00 to HLDC1 1 are set to the actuation H (tl_Iv to t10_Iv) and set to the inactive L when the comparison processing and the counting process (tl〇_Iv to t14_Iv) are performed, and at the same time, All of the count clock control signals ΤΗ00 to TH11 are set to be inactive L (tl_Iv to t26_Iv). Therefore, by the comparison processing and counting processing (tl_Iv to t26_Iv), the counter 254 holds the digit 値Dsig_Iv (t26_Iv) of Vsig_Iv. This is the same as the situation shown in Figure 7. Furthermore, in order to read the signal of one column Jv under the two-addition target column, to perform the A/D conversion process, the vertical selection signal -63-1364980 <|) VSEL of the read target column Jv is set to be active η And allowing the pixel signal So to be output to the vertical signal line 19. At this time, it is not necessary to reset the counter 254, and the read operation and the A/D conversion processing of the unit pixel 3 in the column JV are sequentially executed (tl_Jv = t26_Iv). This is the same as that shown in FIG.

On the other hand, the features of this embodiment are as follows. When the next column Jv (tl_Jv to t26_Jv) is read, although the processing of the first column iv is to change the slope of the reference signal Vslop (tl_Iv to t26_Iv), the data holding control pulse HLDC00 of the data holding unit 512_0 0 is set to the active H, Continue the entire cycle (tl_Jv to t26_Jv). At the same time, the data holding control pulses HLDC01 to HLDC10 to the remaining data holding unit data holding unit 51 2_0 1 to the data holding unit 5 1 2_pixel array unit 1 are set to the actuation H (tl_Jv to t10_jv) at the beginning and at The comparison processing and the counting processing are set to the inactive L (t10_Jv to t14_Jv). Furthermore, the count clock control signal THOO is set to the operation Η, and all other count clock control signals ΤΗ01 to ΤΗ11 are set to the inactive L (tl_Iv to t26_Iv) = in this way, the data hold control pulse hldcoo first becomes active Η And the data recorded in the least significant bit flip-flop 5 1 0_00 is maintained. When the next column Jv is processed (tl_Jv to t26_Jv), the least significant bit output becomes substantially inactive. Therefore, the processing for the next column becomes a low resolution processing. When the next column Jv is processed (tl_Jv to t26_Jv), if the count clock control signal ΤΗ00 becomes active, the input clock of the least significant bit (0 bit) flip-flop 5 10_00 is transferred to the second level (1 bit) The front end of the -64 - 1364980 51 0_0 1 clock. By transmitting the least significant bit clock cycle to the lower-bit's other higher-efficiency bit output, the frequency-division operation speed is doubled except for the least significant bit, and the counter 254 counts twice as fast, and at the same time, The quantization step is performed coarser.

For example, Fig. 11 shows the slope of the reference signal Vslop (and the gain according to the slope) and the frequency dividing speed from the output of the flip-flop 510 per bit-bit when the clock control signal TH00 is counted. When the count clock control signal ΤΗ00 is switched to the operation Η, the count clock CIN supplied to the least significant bit flip-flop 51〇 is transmitted to the second-stage flip-flop 510_01, so that after switching, it is more efficient The bit flip-flop can operate faster than before switching. However, since the previous inefficient bit output becomes inactive, the quantization can be performed coarser than before. For example, if the count of the count output D00 of the first-order flip-flop 510_00 is 10 0 MHz before the count clock control signal ΤΗ 00 is switched, the loop of the count output D01 of the second-stage flip-flop 510_01 is 50 MHz. Meanwhile, when the count clock control signal ThOO is switched to the clamp level, the cycle of the count output D01 of the second-stage flip-flop 510_01 is 100 MHz, so that the frequency division operation in the more efficient bit-reactor 5 1 0 is Operates at twice the speed.

At this time, the slope of the reference signal Vslop is the same as the processing of the first column Iv (tl_Iv to t26_Iv) and the next column Jv (tl_Jv to t26_Jv). Therefore, in the first column Iv processing, the relationship between the count 値 and the voltage 为 is ΔV/Δt, and the total gain of the A/D conversion process becomes, and on the other hand, the voltage at the processing of the next column Jv値The total gain of 2AV/At and A/D -65-1364980 conversion processing becomes 2. More specifically, in the present embodiment, when the next column Jv is processed (tl_Jv to t26_Jv), the frequency dividing speed of the counter becomes k times the speed (twice in the previous example) without changing the first column Iv The slope of the processed reference signal Vslop. Therefore, when the A/D conversion processing of the signal component Vsig_Iv of the first column Iv is compared, a double gain is applied to the A/D conversion processing of the signal component Vsig_Jv of the next column Jv.

Therefore, it is assumed that the voltage 値 (conversion coefficient) of each digit in the A/D conversion of the first column Iv is a [V/bit number] and the degree of increase in the speed in the counter 254 (corresponding to the counter 25 4 The gain in the middle is Lv, and the voltage 値 (conversion coefficient) of each digit in the A/D conversion of the next column Jv becomes Lvx α. In the previous example, Lv = 2 and the voltage 値 is 2α. Therefore, after the completion of the A/D conversion of the column JV, that is, after the final count of the weighted digit addition processing is completed, the digit 値 held in the counter 254 becomes "a xVsig_Iv + 2 a xVsig_Jv". For example, assuming that the digits 括号 in parentheses on the line graph of the pixel signal Vx of Fig. 9, the signal components Vsig_Iv and Vsig_Jv in the column Iv and the column Jv are 60, and the reset levels Srst_Iv and Srst_Iv are 10. At this time, in the A/D conversion of the signal level Ssig_Iv (signal component Vsig_Iv) in the column Iv, the count 値 "Drst_Iv" (= -10) obtained by A/D conversion by the heavy level Srst_Iv is performed. As the starting point, the number 'after processing, the count 値" - 1 0 + 70 = 60 = Dsig_Iv" is held in the counter 254. Subsequently, in the A/D conversion of the column Jv, the count 値 "60 = Dsig_Iv" obtained by the A/D conversion of the column Iv - 66 - 1364980 is used as the starting point, and the reset level Srst_Jv is first made. The next number, and held in the counter 2 54 becomes "Dsig_Iv-2· Drst_Jv = 50-2xl 〇 = 40". Furthermore, the upper limit is executed on the signal level Ssig_]v, starting from the count 値40 using the start point, and after the processing, the count stored in the counter 254 becomes ,, '40 + 2\7 0= 1 8 0". The count 値 means 値"〇3丨8_1〇2.〇3丨£_扒,', which is achieved by double the number 値Dsig_Jv in the column Jv and the number in the column Iv

The sum is obtained by adding Dsig_Iv. In the first example shown in Fig. 9, the addition node 2"Dsig_Iv + Lv · Dsig_IV" is obtained by dividing the frequency of Lv (= 2) by the processing of the following column jv. However, as shown in the second example of the pixel array unit 10, when the first column Iv is processed, if the frequency division operation of the counter is multiplied by Lv (= 2) twice, the frequency division operation of the next column JV is processed. , "Lv • Dsig - Iv + Dsig_Iv" can be obtained as the result of the addition. In the previous example, only the frequency division φ operation on the higher order bit side of the counter is changed to L times, and the speed and data on the lower order bit side are considered invalid to maintain the start count clock C IN The frequency is the same speed and avoids increasing the power consumption in the counter, which is not necessary. If the increase in power consumption in the counter is acceptable, unlike the switching operation performed by the count clock switch 516, the start count clock CIN itself can also be used by using the high speed clock generated by the multiplication function of the clock converter 23. The change to the high frequency allows the count execution unit 504 to perform the frequency division operation at high speed. In this manner, since all the bit data can be used as valid data, the A/D conversion accuracy is not lowered and the addition processing in the vertical direction of -67-1364980 can be implemented in the row A/D circuit 25. . Furthermore, in order to control the flip-flop 5 1 0 to perform the counting operation (frequency dividing operation) at high speed, the circuit is structured to control such that the weighting relationship of the bit maintaining the flip-flop remains unchanged and the lower-order bit output is invalid. At this time, the frequency division operation of the remaining portion of the higher order bit output is performed at a high speed. However, this is only an example, and any architecture is possible as long as it can increase the speed of the frequency division operation of the flip-flop 510, and various modifications are possible.

For example, a switching mechanism may be provided for sequentially shifting the one-element output to the low-order side of the flip-flop 5 10 while omitting the count clock for changing the flip-flop 510 supplied to each stage. The count mode switch 516 of the supply mode. At this time, the data output from the flip-flop 510 of the next stage can be regarded as invalid. This is also like the A/D conversion data, which becomes invalid for lower order bit data. However, at this time, there is a need for a circuit for loading the count of each bit to the previous stage side at the time of switching. Therefore, the _ circuit structure will be more complicated than the previous example in which the count clock switch 516 is used to switch the count clock. However, at the time, since, for example, the supply of the count clock of the flip-flop 510 at the next stage is stopped after the switching operation, the counting operation can be stopped, so that the advantage of consuming lower power can be completed. Furthermore, although the application example illustrates the use of a non-synchronous counter as the count @254, the same idea can be applied to the use of a sync counter. For example, if a sync counter is used, then each flip-flop 510 is operated by using a common count clock and each flip-flop 510 requires a gate circuit that allows each flip-flop 510 to be a lower order The 値 of the bit is 丨 (in the upper number) or is inverted when all lower-order bits are 〇 (in the lower number). -68-

1364980 In this configuration, in order to increase the flip-flop 510, a switching circuit can be provided to cause the gate circuit to radiate. However, this circuit structure will be more complicated than the structure of switching the count clock using the count clock counter. Alternatively, if the non-synchronous counter is used to modify its frame, a circuit is provided to be carried to the lower-order side at the time of switching, and the switching mechanism is supplied to the lower-order side. [Double Weighted Addition in the Horizontal Direction and Final Phase Force Diagrams 12 to 14 show FIGS. 8A to 8D at the time of the addition operation in the horizontal direction and the vertical direction of the first embodiment, as two columns and two rows are executed The use of a color filter having a R, G, and B (G is represented as a Gb in the column R, which are distinguished from each other) is used as a dichroic filter. Figures 12A through 12F show the pixels taken as shown in Figure 8A, and the double-weighted additives shown in Figure 9. Figures 13A through 13F show that the combination of the double-weighted addition as shown in Figure 8 and the pixel-weighted addition shown in Figure 8 is applied to these pixels. The order in which the pixels are taken is different from the order in Fig. 8A and the weight addition is applied to these pixels. The speed i of the frequency division operation for the double weighted phase in the horizontal direction is out of sync for the lower order bit side switch 516: as described in the example, it is also possible to count each bit by one bit. Meta output shift] Image] The pixel configuration in the liberative improvement method. Similar to the addition process, it shows Gr, and the Bayer configuration filter in the column is: the same column and row order: applied to these pixel columns and row order, and shows [column unit 10 double The multipliers 14A to 14F show the double addition processing shown in Fig. 9. In the vertical direction -69 - 1364980, the pixel system to which the Lv-fold weight is added is transferred to the digital arithmetic unit 29, and the 'digital arithmetic unit 29 Perform the addition processing in the horizontal direction. The addition processing is performed with the processing shown in Figs. 8A to 8D.

In the present embodiment, 'Lh times (= 2) weighted addition processing is performed, and Lh-weighted addition is performed. Specifically, the addition data ADD_Jh of the next line jh is obtained by adding the Lh multiple weight to the addition data ADD_Ih of the first line ih. Typically, it is set to Lh = Lv. According to the former example, for example, it is set to double weighting. [Double Weighted Addition Example of Ratios 1 to 2] When the pixel is subjected to the same column and row order as shown in FIG. 8A and the double weighted addition shown in FIG. 9 is applied to the pixels, first, for example, As shown in FIG. 12A (same as FIG. 8A), the vertical selection signal φ VSEL is in the order of the first column, the third column, the second column, the fourth column, the fifth column, the seventh column, the sixth column, and the eighth column. Specify the number of columns from the bottom. As shown in the figure (Fig. 12B), in which the pixels are arranged in the order in which they are read by the line processor 26, when two columns having the same color are input to the odd or even columns in the vertical direction, the line processor Each row A/D circuit 25 in each of the vertical rows 26 performs an addition process. At this time, it can be understood from the description of FIG. 9 that the frequency dividing operation for the counter 254 of the next column Jv is twice as fast as the processing for the first column lv, and the addition processing is set to the first column lv. The weights of the first column, the second column, the fifth column, and the sixth column are 1, and the weighting for the next column Jv (the third column, the fourth column, the seventh column, and the eighth column) is 2 As shown on the right side of the figure, "x -70-1364980 2" indicates execution.

For example, the 'addition processing is performed sequentially: the R component in the first column, the double R component in the third column, and the Gr component in the first column; the Gb component in the second column and The double Gb component of the four columns and the B component in the second column and the double B component in the fourth column; the R component in the fifth column and the double R component in the seventh column and in the fifth The Gr component in the column and the double Gr component in the seventh column; the Gb component in the sixth column and the double Gb component in the eighth column and the B component in the sixth column and the eighth column Double the B component, and so on. In other words, when the same color component of two pixels in the vertical direction is input to the row A/D circuit 25, the 'row A/D circuit 25 makes the component of the next column JV twice the first column iv' And the addition operation of the same color component is performed. The schematic diagram after the addition operation is shown in Figure 1 2 C. The pixel center after the addition is shifted to the next column of jv applied by the larger weight, instead of the center column of the two added target columns, i.e., the center of gravity in the vertical direction at the time of addition. Specifically, instead of the center of gravity in the vertical direction at the time of addition, the position obtained by dividing the spatial distance between the first column Iv and the next column JV by 2:1 becomes the center after the addition, the center is Shift to the next column Jv side 1 / 3 歹 IJ to which a larger weight is applied (refer to Figure 1 2E). For example, each center position is: for the first column and the third column, after the double weighted addition, the displacement to the third column leaves the 1/3 column of the second column; for the second column and the fourth column, After the double-weighted addition, shift to the position of the third column side leaving the third column 1/3 column; for the fifth column and the seventh column, after the double-weighted addition, shift to the seventh The column side leaves the position of the sixth column 1/3 column -71 - 1364980; and for the sixth column and the eighth column, after the double weighted addition, shifts to the eighth column side and leaves the seventh column 1/3 The position of the column.

The digital arithmetic unit 29 sequentially acquires the column addition data ADD, and performs an addition operation on the image in the above state when the same color is input to the horizontal direction. For example, the digital arithmetic unit 29 sequentially performs the addition operation on the R component in the first row, the double R component in the third row, and the Gr component in the first row and in the third row. Double Gr component; Gb component in the second row and double Gb component in the fourth row and B component in the second row and double B component in the fourth row; R in the fifth row Component and double R component in the seventh row and the Gr component in the fifth row and the double Gr component in the seventh row; the Gb component in the sixth row and the double Gb component in the eighth row And the B component in the sixth row and the double B component in the eighth row, and so on. In other words, when the addition data of the same color component of two lines in the horizontal direction is sent to the digital arithmetic unit 29, the digital arithmetic unit 29 makes the component of the next line Jv twice the first line Iv, And the addition processing of the same color is performed. In the schematic diagram after the addition operation, the pixel center after the addition is shifted to the next row Jh side to which the larger weight is applied, instead of the center line of the two addition target rows, that is, at the time of addition The center of gravity in the horizontal direction. Specifically, it is not the center of gravity in the horizontal direction at the time of addition, by changing the position obtained by dividing the spatial distance between the first line Ih and the next line Jh by 2:1 into the center after the addition, the center Shifted to the next line to which a larger weight is applied

Jv side 1/3 line (refer to Figure 12F). -72- 1364980 For example, 'each center position is: for the first row and the third row, after the double weighted addition, the displacement to the third row leaves the second row 1/3 row: for the second row and The fourth line, after the double-weighted addition, shifts to the position where the fourth line side leaves the third line 1/3 line; for the fifth line and the seventh line, after the double-weighted addition, shifts To the seventh line side, leave the position of the 1/3 line of the sixth line; and for the sixth line and the eighth line, after the double weighted addition, shift to the eighth line side and leave the seventh line 1 / 3 line s position.

If the center shown in FIG. 1C is combined in the vertical direction after the addition, then the center distance after the addition is the ratio of the space between the first column Iv and the next column Jv is divided by 2:1. The spatial distance between the first row Ih and the next row Jh is divided by a ratio of 2:1, as shown in Fig. 1 2D. At this time, it is possible to compare the original positions of the pixels on the left side of Fig. 12D, although it is different from the state shown on the right side of Fig. 8D, the spatial positions of each color are not arranged equidistantly. [Combined double-weighted addition example in the ratio of 1:2 and 2:1] When the pixels in the same column are used and the row order and the double-weighted addition shown in Fig. 8A are combined by the operation of Fig. 9 When the operation of Figure 1 is applied to the pixel, the double-weighted addition in the ratio 1: 2 (the mode in Fig. 9) and the double-weighted addition in the ratio 2: 1 (the mode in Fig. 1) Repeated alternately. This completes the weighted addition based on the shift direction. For example, as shown in FIG. 13A (same as FIG. 12A), the vertical selection signal φ VS EL is in the first column 'third column' second column, fourth column, fifth column, -73-1364980 seventh column, sixth The order of the columns and the eighth column is specified by the bottom column. As shown (Fig. 13B), when the same color column of the odd column or the even column is input to the vertical direction, the pixel system is rearranged into the order read by the line processor 26, each placed in The row A/D circuit 25 in each of the vertical rows in the row processor 26 performs an addition operation.

At this time, the double-weighted addition by the ratio of 1:2 shown in Fig. 9 is performed by the first addition processing and the ratio of 2:1 and double-weighted addition shown in Fig. 10 It is executed for the next addition process. In this way, the counter 25 4 performs a frequency division operation on the first column Iv twice as fast as the frequency division operation of the next column JV faster than the first addition processing, and the addition processing is performed by the first column W (the first column The weights of one column and the fifth column are set to 2 to be "x2" shown on the right side of the figure, and weighted to one in the next column JV (third column and seventh column). In the next addition processing, the counter 254 performs the frequency division operation of the next column Jv twice as fast as the processing of the first column Iv, and the addition processing is performed by the first column Iv (the second column and the sixth column) The weighting is set to 1, and the weighting of the lower-column Jv (fourth and eighth columns) is 2, as indicated by "x2" on the right side of the figure. The addition processing of the first column, the fourth column, the fifth column, and the eighth column is performed by doubling the weighting. For example, the addition process is performed sequentially on the double R component in the first column, the R component in the third column, and the double Gr component in the first column and the Gr in the third column. Component; the Gb component in the second column and the double Gb component in the fourth column and the B component in the second column and the double B component in the fourth column; double R in the fifth column Component and the R component in the seventh column and the double Gr component in the fifth column and the Gr component in the seventh column -74 - 1364980; the Gb component in the sixth column and the double in the eighth column The double Gb component and the B component in the sixth column and the double B component in the eighth column, and so on.

In other words, when the same color component of two pixels in the vertical direction is input to the row A/D circuit 25, the row A/D circuit 25 makes the component of the first column Iv by the first addition operation. The addition operation of the same color component is performed twice for the next column Jv, and the same color component is performed by making the next column Jv component twice the component of the first column Iv in the next addition operation Add operations and repeat these operations. The schematic diagram after the addition operation is shown in Fig. 13C. The pixel center after the addition is shifted to the next column Jv side applied by the larger weight, instead of the center column of the two added target columns, i.e., the center of gravity in the vertical direction at the time of addition. Specifically, it is not the center of gravity in the vertical direction at the time of addition, and the position obtained by dividing the spatial distance between the first column Iv and the next column Jv by 2:1 becomes the center after the addition, and the center is Shift to the next column Jv side 1/3 I applied with a larger weight (refer to FIG. 13E). This is the same as Figure 12C. However, since the shift directions are alternately different at this time, the center of the added pixels is also different from that of Fig. 12C. For example, each center position is: for the first column and the third column, after the double weighted addition, the displacement is shifted to the position where the first column leaves the 1/3 column of the second column; for the second column and the fourth column, After the double-weighted addition, shift to the position of the third column side leaving the third column 1/3 column; for the fifth column and the seventh column, after the double-weighted addition, shift to the fifth The column side leaves the position of the 1/3 column of the sixth column; and for the sixth column and the eighth column, after the double weighted addition, -75-1364980 shifts to the eighth column side and leaves the seventh column 1/3 The position of the column. The digital arithmetic unit 29 sequentially acquires the column addition data ADD, and performs an addition operation on the image in the above state when the same color is input to the horizontal direction. At this time, as in the processing in the vertical direction, the double-weighted addition in a ratio of 2:1 and the double-weighted addition in a ratio of 1:2 are alternately performed.

More specifically, the first addition processing is performed by setting the weight of the first row Ih (the first row and the fifth row) to 2, as shown in the lower part of the figure "χ2", and the next row Jh (the third row and the The weight of the seven lines) is 1 and executed. The next column of addition processing is set to the lower side of the figure by setting the weight of the first row Ih (the second row and the sixth row) to 1 and the next column Jh (the fourth row and the eighth row) to be 2 X2” means to be executed. The addition processing of the first line, the fourth line, the fifth line, and the eighth line is performed by doubling the weight. For example, the digital arithmetic unit 29 sequentially performs the addition operation in the double R component in the first row, the R component in the third row, and the double Gr component in the first row and in the third row. The Gr component; the Gb component in the second row and the double Gb component in the fourth row and the B component in the second row and the double B component in the fourth row; double in the fifth row R component and the R component in the seventh row and the double Gr component in the fifth row and the Gr component in the seventh row; the Gb component in the sixth row and the double Gb component in the eighth row and The B component in the sixth row and the double B component in the eighth row, and so on. In other words, when the same color component of two pixels in the horizontal direction is sent to the digital arithmetic unit 29, in the first addition operation, the digit is calculated as -76-

1364980 The operation unit 29 performs the addition processing of the same color by making the component of the first line Ih the next line Jv, and the arithmetic unit 29 makes the component of the second column Jv the first column in the next addition processing. Iv , while performing the addition processing of the same color, and repeating these operations. In the schematic diagram after the addition operation, the pixel center associated with the addition in the horizontal direction is shifted to the next row to which the larger weight is applied, instead of the center row of the two addition target rows, that is, at the time of addition The center of gravity. Specifically, not in the horizontal direction at the time of addition, the position obtained by dividing the spatial distance between the first line Ih and the next line Jh by 2 points becomes the center after the addition, and the center is shifted. The next weighted Jh side 1/3 line of the large weight (refer to Fig. 13F). The case of this 1 2 D is the same, however, since the weighted shift direction is intersected, the pixel center after the addition becomes different from Fig. 12D. For example, each center position is: for the first row and the third row, the ratio of 2:1 is doubled and weighted, and the displacement is shifted to the position where the first row leaves 1/3 row; for the second row and the fourth row, In order to add by double the weight of 1: 2, shift to the third row side and leave the third row 1/3; for the fifth row and the seventh row, after double addition, shift by 2:1 ratio The position from the fifth line side to the sixth line 1 / 3 line; the sixth line and the eighth line, in the ratio of 1: 2 in the double weighted addition bit to the eighth line side leaves the seventh line 1 / 3 line s position. If the sum of the sums in the vertical direction shown in Fig. 13C is as above, 'the center of the addition is obtained by the inner division as follows--the color is 'in the 2:1 inner division-column iv and the lower- The column jv is twice, twice the number of digits, and the center of gravity of the horizontal side of the phase Jh: 1 to the application line and the change of the figure * is the weight of the line in the line of the second line, and after the shift, the heart is Group: The distance between -77- 1364980 in each space, and the distance between the first row Ih and the next row Jh in 2:1, as shown on the right side of Figure 13D. In this example, the pixels in the same column order in Fig. 8A are read out, and the weighted shift directions due to the addition processing are alternately changed. Therefore, the center of the added pixels is arranged at a more equal distance in the case where the simple addition is performed. As a result, it is possible to obtain a resolution signal (digital signal) in which simple addition is performed, and the weighting of the simple addition is uniform. [Example of switching between sequential and double-weighted addition of 1:2 ratio] When the double-weighted addition of the 1: 2 ratio shown in Fig. 9 is applied and the order of use of the column or row is different from that shown in Fig. 8A By alternately switching the order of access, in practice, the double-weighted addition of the ratio of 1:2 and the double-weighted addition of the ratio of 2:1 are alternately repeated with respect to the spatial relationship of the column and row configurations. This completes the weighted addition seen in the shift direction.

For example, as shown in FIG. 14A, in the addition processing in the vertical direction, the vertical selection signal Φ VSEL is in the third column, the first column, the second column, the fourth column, the seventh column, the fifth column, and the The order of the six columns and the eighth column is specified by the bottom column as shown (Fig. 14B), which is arranged in the order in which it is read by the line processor 26, when the same color of the odd or even columns is entered. In the vertical direction, each row A/D circuit 25 arranged in each of the vertical rows in the line processor 26 performs an addition operation. At this time, since the row A/D circuit 25 is operated at the timing shown in FIG. 9, in each addition operation, the counter 254 performs the next column Jv frequency division operation as the first column Iv -78- 1364980 is twice as fast. The addition processing is performed by setting the weight of the first column I v (the third column, the second column, the seventh column, and the sixth column) to 1 and the next column J v (the first column, the fourth column, the fifth column) And the eighth column) is weighted by 2 and is executed by the "x 2" on the right side of the figure.

Under the prior control of the vertical scanning circuit 14, there is a spatial relationship in the column arrangement, in particular, the added columns Iv and JV are switched to achieve a double weighted addition of 1:2 ratio and 2: The double-weighted addition of the ratios is alternately repeated. The addition processing performed by the weighted doubling of the first column, the fourth column, the fifth column, and the eighth column is similar to the processing of Figs. 13A to 13F. As a result, as shown in Fig. 14C, the intention after the addition becomes the same as that shown in Fig. 13C. The digital arithmetic unit 29 sequentially acquires the column addition data ADD, and performs an addition operation on the image in the above state when the same color is input to the horizontal direction. At this time, similar to the processing in the horizontal direction, the digital arithmetic unit 29 is in the order of the third line, the first line, the second line, the fourth line, the seventh line, the fifth line, the sixth line, and the eighth line. , and so on to obtain the additive data' and perform double-weighted addition in a ratio of 1:2. In each addition operation, the addition processing is performed by setting the weights of the first line ih (: the third line, the second line, the seventh line, and the sixth line)! And the weight of the next line Jh (the first line, the fourth line, the fifth line, and the eighth line) is 2, as shown by the "x2" in the lower part of the figure. The next column of addition processing is set to weight the weight of the first row Ih (the second row and the sixth row) to 1 and the next column Jh (the fourth row and the eighth row) to 2, to the lower side of the figure. X2" means to be executed. The addition processing of the first line, the fourth line, the fifth line -79- 1364980 and the eighth line is performed by doubling the weighting.

Under the prior control of the horizontal scanning circuit 12, there is a spatial relationship in the row configuration, in particular, the rows Ih and Jh to be added are switched to double the weighted addition by the 1:2 ratio and 2: The double-weighted addition of the ratios is alternately repeated. The addition processing performed by the weighted doubling of the first line, the fourth line, the fifth line, and the eighth line is similar to the processing of Figs. 13A to 13F. As a result, as shown in Fig. 14D, the intention after the addition becomes the same as that shown in Fig. 13D. In this example, at each addition processing, the double-weighted addition of the ratio 1: 2 shown in Fig. 9 is weighted for the counter 2 5 4 (specifically, for the count clock control signal TH When control is executed, in fact, related to the spatial relationship in the column and row configuration, the double-weighted addition of the ratio 1: 2 and the double-weighted addition of the ratio 2: 1 are alternately switched by alternately The order of the rows or rows is alternately repeated. As a result, similarly to Fig. 13, the center of the pixels after the addition is arranged at a more equal interval than when the simple addition is performed. As a result, a higher resolution signal (digital data) can be obtained by performing simple addition, and the weighting 値 in the simple addition is uniformly applied. It can be understood from the above description that it is not always possible to arrange the positions of the pixels to be equidistant after the addition by simply applying the weighted addition. In order to make the pixel center more evenly spaced after the weighted addition, it is necessary to consider how to select the added target pixel and use what 値 as the weight 値" and then 'when capturing the color image, the image can be affected by the color arrangement of the color separation filter. . In other words, in order to perform the addition without color mixing -80 - 1364980, and the spatial distance relationship is made to the same color configuration of the original color separation filter, the relationship between the added target pixel and the weighted 値 selection can be imagined. There are a number of restrictions. [Modified example of weighting]

In the above detailed description, the double-weighted addition processing of two columns and two rows arranged in Bayer is described. However, this is only an example. It is possible to vary the weighting 値, the spatial position of the added target column and the row, and the number of added target columns and rows. For example, for weighting 値, it is not limited to twice, and a larger number, for example, a power of 2 of 4, 8, ... can be used. For example, in the above description, the display counter 25 4 performs the frequency dividing operation at the time of A/D conversion at twice the speed, but is not limited thereto, and the flip-flop 5 10 is controlled to perform the counting operation at a higher speed (minute Frequency operation). At this time, the quantization step can be performed coarser. For example, if the counting execution unit 504 is configured as shown in FIGS. 4 and 5, by setting the count clock control signals ΤΗ00 and TH01 to be active Η, the frequency dividing operation of the counter 2 5 4 in the last 2 bits can be increased. It is 4 times faster. This allows the digital data "Dsig_Iv + 4 · Dsig_Iv" to be obtained by adding the digit 値 Dsig_Iv of the signal component Vsig_Iv in the column Ιν to the digit 値 Dsig_Jv of the signal component Vsig_Jv of the column Jj. Furthermore, by setting the count clock control signal TH02 to be active, the frequency division operation of the counter 2 5 4 of the rear unit pixel can be increased to 8 times faster. This allows the digital data "Dsig_Iv + 8 · Dsig_Iv" to be obtained by adding the digit 値Dsig_Jv of the signal component Vsig_Jv in the column JV to the digit 値Dsig_Iv of the signal component Vsig_Iv -81 - 1364980 of the column Ιν.

Similarly, if the count clock control signal TH0T (T = S-1) is set to be active, the frequency division operation of the counter 2 5 4 after the S bit can be increased to S times faster, so that a gain can be increased by 2 - S times bigger. This allows the digital data "Dsig_Iv + 2' S · Dsig_Iv" to be obtained by adding the digit 値 Dsig_Iv of the signal component Vsig_Iv in the column Ιν to the digit 値Dsig_Jv of the signal component Vsig_Jv of the factory S times column Jv. When the frequency division operation of the counter is made into a high-speed division operation (faster) via several stages, such as L1 times (= 2), L2 times (4), L3 times (= 8), etc., if lower, if lower The frequency-division operation of the order bit output is invalidated and the remaining higher-order bit outputs are executed at a higher speed to perform the quantization step more coarsely, and the start count clock for controlling the higher order bits can be maintained. For the same speed as the count clock CIN. Although it seems that the resolution of the A/D conversion for the signal component Vsig_Jv in the weighted target column Jv is lowered by the counter operation, there is no substantial difference in the entire counter operation according to the original count clock CIN, and therefore, the power is not increased. Consumption. As described above, the weighting 値 can be applied as a power of 2, for example, 2 times, 4 times, 8 times, ... and so on, by changing the setting of the count clock control signal τη, and the weighting 値 can be adjusted so that The added pixel spatial position is arranged to obtain a higher resolution image, that is, the pixel positions after the addition can be arranged at a more equal pitch. Figure 15 is a diagram showing the mechanism for setting the weighting 値 to an arbitrary integer -82- 1364980. In terms of setting the weighting, it is not only the power of 2, but also any 値. At this time, if the slope of the reference signal Vs10p is maintained at a fixed level, it is preferable to change the count clock CK0 supplied to the counter 254 to a higher speed clock.

Furthermore, when a mechanism that does not have to change the clock frequency of the count clock CK0 is employed, the setting of the count clock control signal TH is changed to change the frequency dividing speed of the counter 254 by one bit unit, and a weighting 値 is set to arbitrary Integer, the slope of the reference signal is adjusted by changing the setting of the slope change command signal CHNG. At this time, there are two relationships between the setting of the reference signal Vslop, the setting of the frequency dividing speed of the counter 2 54, and the weighting 値G to be set, as shown in Fig. 15. Specifically, assuming that the weighting 値 set is G, the method conceivable is: the first method, wherein the frequency dividing speed of the counter 254 is set to 2-n times and the slope of the reference signal Vslop is set to 2 n/G, to satisfy the formula, where "2*(n+l)>G>2·η", and the second method, wherein the frequency dividing speed of the counter 254 is set to 2~n times and the reference signal The slope is set to 2_n/G to satisfy the formula "2_n>G>2*(η-1). In any case, the product G is the A/D conversion gain obtained by increasing the frequency dividing speed. η is multiplied by the A/D conversion gain G/2_ η (the reciprocal of the multiplication coefficient of the slope) obtained by changing the slope of the reference signal Vslop. For example, if the weight 値 is set to the unit pixel 3, the frequency dividing speed is Set to twice the speed, and the slope of the reference signal Vslop is set to 2/3 times the slope in the first method. In the second method, the frequency dividing speed is set to 4 times, and the slope of the reference signal Vslop It is set to 4/3 times -83 - 1364980. This slope can be seen from the figure. In the second method, it is set to The multiplication coefficient of the frequency dividing speed of the counter 254 is larger, so that the slope of the reference signal V slop can be larger than the difference amount, and the advantage is that the A/D conversion period can be made smaller even if the resolution is lowered. In the first method, although the multiplication coefficient set to the frequency dividing speed of the counter 2 54 is small and the A/D conversion speed is long, the resolution is not lowered.

As described above, in addition to the power of 2 for changing the setting of the count clock control signal TH and the setting of the slope change command signal CHNG, it is also possible to change the weighting 藉 by using an arbitrary 値. Therefore, the weighting 値 can be adjusted so that the spatial positions of the added pixels are arranged at more complete intervals to obtain a higher resolution image. As described above, even if the pixel positions after the addition cannot be arranged by the weighting 2 of the power of 2, it is possible to set the weighting 藉 by setting the weighting 値 in any 値, so that the addition is performed. The pixel locations are then arranged at exactly equal spacing. For example, Figures 16A through 16F show "proportion of ratio 3: 1 plus addition of ratio 1:3", where the weighting 値 is set to 3, and Figures 7A to 17F show "proportion 4: 1 Addition + ratio 1: 4 addition", where the weighting 値 is set to 4. The weight of the power of 2 is adjusted and the adjustment of the power of 2 is added to the adjustment of any 値. The flexibility of the subsequent spatial adjustment of the pixel space makes it possible to find a proportional weighting 値 which allows the pixel spatial positions after the addition to be arranged equidistantly. [Method for improving the resolution of the added image: Second Embodiment] Figs. 18 to 21 show a second embodiment of the method for solving the digital addition processing of the counter 254 and the arithmetic unit in the digital direction in the vertical -84 - 1364980 direction. 29 The problem of deterioration in resolution in the digital addition processing in the horizontal direction. 18A to 18C show the disadvantages of the single oblique integral A/D conversion system. More specifically, these figures explain the effect of comparing the processing cycle on the A/D conversion performance, especially for the conversion processing speed, in which the analog pixel signal Vx is compared with the reference signal Vslop for digital data conversion, and simultaneously displayed. An example of a method for shortening the comparison processing cycle.

Fig. 19 is a timing chart for showing the addition processing in the vertical direction in parallel with the A/D conversion processing to explain the second embodiment. Figure 20 is a diagram for showing the effect of the resolution improvement method when the count clock switch 516 is operated in the second embodiment. Figure 21 is a diagram showing the relationship between the change control of the slope of the reference signal Vslop and the frequency division speed control of the counter. In addition to the addition processing operation of the first embodiment, the second embodiment has a feature in that, even in a column processing, when the signal level Ssig is processed by φ, before the comparison processing is completed, at the voltage comparator 252 Comparing the slope of the reference signal Vslop and the frequency dividing speed of the counter 254 in the comparison processing cycle are changed such that the A/D conversion gain remains unchanged in the column, that is, the weighting 像素 of the pixels in the column is maintained. For fixing 値. This makes it possible to obtain a higher resolution added image at a high speed. Specifically, the 'slope change command signal CHNG is supplied to the reference signal generator 27' to change the slope of the reference signal Vsi〇p to j times the slope' and the count mode control signal UDC, the reset control signal CLR, and the data hold control pulse The HLDC, and count clock control signal TH are supplied to the count execution unit 504 of the -85-1364980 counter 254 such that the frequency division operation of each bit output in the count execution unit 5〇4 is changed to K times speed ( Preferably, K times = J times).

While changing the slope of the reference signal Vslop to a J-fold slope, the flip-flop 5 10 is controlled to operate at a K-speed (preferably j-speed) counting operation (frequency division operation) 'but as long as the error (change) Within the allowable range, it is not necessary to be precise "at the same time" or precise: T times the multiplication factor. This is the same as the general technique of allowing an error to be controlled within a setting range as long as the error (change) is within a permissible range. However, basically (in principle), in the A/D conversion processing of the signal component Vsig, the 'multiplication coefficient and the change timing are necessarily the same to obtain the digital data Dsig of the true reflection signal component Vsig without the correction operation, even in the reference. The signal Vslop is changed to be the same before the signal level Ssig and the reference signal Vslop match. In the present embodiment, the line processor 26 (specifically, the row A/D circuit φ 25) performs a single oblique integration A/ for each reset level (reset potential) and a signal level (signal potential). D conversion processing. At the same time, the reset potential is processed by one of the upper or lower modes (in the previous example, the lower mode), and the signal potential is processed by another mode (in the previous example, the upper mode), The digital data of the difference between the two processes can be automatically obtained by the result of the counting process of the second process. In the single-slope integral A/D conversion system used in this embodiment, the resolution of the A/D conversion, that is, the size of the 1LSB is the counter 254 when the slope of the reference signal Vslop and the period and the reference signal Vslop is changed - 86- 1364980 The counting speed (that is, the frequency of the 'counting clock'). For example, if the 'hypothesis' is that the period counted by the counter 2 5 4 is ~ count cycle, the amount of change in the reference signal Vslop in the count cycle becomes the resolution of the A/D conversion (width 1 LSB). When the width of the iLSB is small (narrow), the resolution of the A/D conversion is high, and when the width of the iLSB is large (wide), the resolution of the A/D conversion is low.

Therefore, for example, when the speed is expressed by the counting speed, the faster the speed, the shorter the counting cycle. If the slope of the reference signal Vslop is the same, the variation of the reference signal Vslop, i.e., the width of 1 LSB, becomes smaller at the time of the counting cycle, so that the resolution of the A/D conversion becomes high. If the slope of the reference signal vsl〇p is the same 'if the counting speed becomes faster, the counting 値 advances to the point where the reference signal Vslop and the signal voltage on the vertical signal line 19 match, then a larger digital data can be obtained, and A The gain of the /D conversion becomes high. This means that the change in the count speed is equivalent to the adjustment of the A/D conversion increase and the control of the read gain. Furthermore, 'the slope of the reference signal Vslop is expressed. When the counting speed is the same, the larger the slope, the smaller the amount of the reference signal Vslop is changed in the period, that is, when the width is 1 LSB, the resolution of the A/D conversion is higher. . Furthermore, when the counting speed is the same, the greater the slope, the more time it takes to match the signal voltage on the reference signal Vslop and the vertical signal line 19, so that a larger digital data and an A/D conversion gain can be obtained. . _ In other words, when the count speed is the same, when the slope of the reference signal Vslop is changed to control the twist of 1 LSB, the matching time of the reference signal Vslop and the pixel voltage V X on the vertical signal line 19 is adjusted. As a result, even if the pixel signal voltage Vx on the vertical signal line 19 is kept the same, the count 値 at the time of the -87-1364980, that is, the digital data of the signal voltage is adjusted. This means that the slope change of the reference signal Vslop is equivalent to the adjustment of the A/D conversion gain and the adjustment of the read gain control. In the first embodiment, by using the above, at the time of the addition processing, the frequency dividing speed is set to a high speed (the reference signal Vslop is changed depending on the weighting 値) and weighted addition is performed.

At this time, in order to perform higher speed and higher accurate processing, it is necessary to make the line A/D circuit 25 faster. In the row A/D circuit 25, in order to achieve higher speed, if the slope of the reference signal Vslop is not adjusted, the counter 2 54 needs to operate faster. In order to increase the speed of the counter, the counting clock speed is increased. However, since the row A/D circuit 25 and the row A/D circuit 25 in each row must perform the counting operation at a high speed at a high speed, the problem of an increase in power consumption can occur. In order to complete the high-speed A/D conversion processing and solve these problems at the same time, it is thought that the speed of the A/D conversion can be made variable by compressing the counting time by adjusting the reference signal Vslop side without increasing the counting clock speed. Complete high speed processing. For example, as shown in FIG. 18A, background noise (inductor noise reference) and optical scattered noise in the pixel signal generator 5 are known in addition to signal components (signal responses) corresponding to the light particles. (Photon shot noise) is applied to an optical signal output (sensor output) regarding the light intensity output from the unit pixel 3. When the sensor output is A/D converted, if the sensor output below the level of the sensor noise reference is A/D converted, the signal from the sensor output -88-1364980 is buried in the sensor. Under the benchmark, so the conversion becomes meaningless. Therefore, the sensor output that exceeds at least the sensor noise level is the effective range for A/D conversion.

The photon shot noise is relative to the photon change corresponding to the 1/2 power optical signal. Therefore, when the amount of signal is small, there is less photon-scattering noise, so that the optical signal can be accurately converted to A/D with high-resolution A/D conversion. However, when the amount of signal is large, the photon shot noise is relatively large, so that even if the optical signal is A/D converted with high resolution, the optical signal is not always accurately due to the amount of photon shot noise. A/D conversion. In a region where the amount of optical signals is large and a large amount of photon shot noise is included, only the resolution of the signal component for removing photon shot noise may be used. For this reason, if the resolution of the A/D conversion is lowered (in other words, if the quantization step becomes thicker) within the range, the accuracy of the A/D conversion result is not problematic. In the above method, it can be imagined that the A/D conversion speed can be adjusted according to the signal by adjusting the accuracy of the A/D conversion, in other words, by adjusting the resolution or the quantization step when the signal amount becomes large. The amount gets faster. For example, as shown in FIG. 18B, when the sensor output (the amount of photoelectrons corresponding to the signal component: the unit is "au") is between the level 0 and the level 1, the quantization step is set to 1 LSB, and the sensing is performed. The output of the device is between level 1 and level 2, and the quantization step is set to 2LSB. Similarly and similarly, according to the upward level, the quantization step is thicker, that is, the resolution is lower. This means that if the sensor output level is up, the output of the lower order flip-flop 510, which constitutes the counter execution unit 504 in the counter 504, is ignored in the order of the sensor output level, only The higher order bin flip-flop 5 1 0 can be operated. On the other hand, in order to gradually change the resolution according to the sensor output level, it can be understood from the above description that the slope of the reference signal Vs lop is gradually changed to a steep slope, and the voltage change per unit time, that is, the voltage per count The difference (mV/digit) is changed as shown in Fig. 18C.

However, in the above case, since the A/D conversion gain becomes small, the linearity of the A/D conversion result with respect to the sensor output is impaired. For example, the voltage 値 (conversion coefficient) of each digit in the A/D conversion period Trst of the reset level Srst and the change point in the A/D conversion period Tsig of the signal level Ssig is α [V/bit Number], the voltage 値 (conversion coefficient) of each digit after the change point becomes a /J. Therefore, if the count 値D of the A/D conversion result is converted into voltage 値. If the count 値 at the change point is "m", it becomes "〇; · m + (Dm)· α/J", which The size of the sensor output is made inaccurate. In order to avoid this, it is conceivable to add the gain correction by making the count clock faster, offsetting the degree of change of the slope of the reference signal Vslop, that is, the relationship between the count 値 and the voltage △ Δ V / Δ t Be kept fixed. At this time, a technique of simply making the counting clock faster is not practically employed because the aforementioned problems may occur. Therefore, if a mechanism is employed in which the internal count clock does not actually change, and the count of the A/D conversion result is changed by the slope change point, it is automatically corrected according to the slope of the reference signal Vslop, for example, to "α · m + ( Dm) • α/JJ”, the count 値 becomes “α ·ιη + (0-ηι)· .D,,, makes -90-

1364980 The size of the sensor output can be accurately obtained. In the second embodiment as a mechanism for automatic correction, a mechanism for changing the frequency speed of the counter 254 is employed. It is explained in detail as follows, in which the order of addition is set to be the same as the processing shown in Fig. 13. In the A/D conversion period Trst of the reset level Srst, the reset levels Srst_Iv and Srst_Jv of the cell image 3 are read, and the counter 254 counts the reset levels Srst_Iv and Srst_Jv. At this time, all of the count clock signals ΤΗ00 to TH11 are set to be inactive L. Further, in the A/D conversion period Tsig of the signal level Ssig, the test signal Vslop is changed to be the same as the slope at the start of the A/D conversion period, and the counter 254 is counted by each of the digits 値Drst_Iv and Drst_Jv. At this time, all of the data hold control pulses HLDC00 HLDC 1 1 are set to be inactive L, and all of the count clock control signals 00 to TH11 are set to be inactive L. At a point R(t21_Iv), the slope of the reference signal Vslop is changed to a J-fold slope (for example, twice the slope), and the frequency division operation of the flip-flop 5 before the point R is made K-speed (preferably Ground, K = J). For example, in the processing of the first addition target column Iv, the slope of the reference signal Vslop is changed to twice the slope of the point R_Iv(t21_Iv), and the data holding control pulse HLDC00 to the data holding unit 512_ is switched to the actuation. When the count clock control signal ΤΗ00 is counted, the switch 5 1 6_00 is switched to the action η » at this time, the pixel signal voltage Vx_Iv in the row iv in a certain row on the vertical signal line 19 is digitally converted to the count 値m 〇_Iv. The number of the actual number of the number 254 is determined by the period between the "t21_Iv-t20_Iv" and the counting clock cycle. The number of the actual number is 254. The number of the actual number is 254. Decided because the upper number is started by the negative 値Drst_Iv

Further, at this time, since the material holding control pulse HLDC00 is set to the operation Η, the material recorded in the least significant bit flip-flop 510 is held. In fact, after the point R_Iv(t21_Iv), the least significant bit output is made invalid. Since the least significant bit output is made invalid after the point R_Iv(t21_Iv), the period after the point R_Iv(t21_Iv) becomes the low resolution period Tssig_LlIv. Furthermore, at the same time, if the count clock control signal ΤΗ00 is switched to the operation Η, and the least significant bit (in the 〇 bit) the input clock of the flip-flop 510_00 is transferred to the second-stage (at 1-bit) flip-flop 51 0_0 1 clock end. By clocking the clock of the least significant bit to the next bit, the frequency division operation of the remaining higher bit output is performed at twice the speed, except for the least significant bit, the counter 254 begins to count at twice the speed At the same time, keep the quantization step twice as thick as before. For example, Fig. 20 is an output diagram of each flip-flop 510 when the slopes of the count clock control signal ΤΗ00 and the reference signal Vslop are changed. The count clock control signal ΤΗ00 is switched to the operation 点 at the point R_Iv(t21_Iv) so that the count clock CIN supplied to the least efficient flip-flop 5 10_00 is transferred to the second-stage flip-flop 510_01, so that the lower-order flip-flop 510 Operates at high speed after switching. However, since the least significant bit output becomes invalid, 4, the quantization step becomes thicker than before. For example, if the -92- 1364980 cycle of the count output D00 of the first-stage flip-flop 510_00 is 100 MHz before the count clock control signal ΤΗ00 is switched, and the count output D01 of the second-stage flip-flop 510_01 is 50 MHz. Different from this, when the count clock control signal TH 0 0 is switched to the clamp level, and the count output D01 of the second-stage flip-flop 510_01 is 100 Hz, the frequency division operation of the higher-order bit flip-flop 510 is performed. It is operated at twice the speed.

Furthermore, regarding the pixel signal voltage Vx_Iv, the low-resolution period Tsig_LlIv after the point R_Iv(tl2_Iv), when the signal level Ssig_Iv and the reference signal Vslop match (t2 2_Iv), the counter 254 stops while remaining in the match. Count 値ζ0_Ιν. At this time, the slope of the reference signal Vslop becomes twice the speed before the point R_Iv(t21_Iv), and the higher order bit flip-flop 510 in the counter 254 also performs the frequency dividing operation at twice the speed. Therefore, the relationship between the count 値 and the voltage 变成 becomes 2 Δ V / 2 Δ t = Δ V / Δ t, and the relationship between the count 値 and the voltage 値 Δ V / Δ t is stable, which results in maintaining the A/D conversion result relative to The sensor output is linear. The final count 値ζ0_Ιν itself automatically changes to the digital data Dsig, which truly reflects the signal component Vsig, so no external circuit is required for correction. After the A/D conversion period of the column Iv is completed, it is not necessary to reset the counter 2, the read operation and the A/D conversion processing of the unit pixel 3 in the column Jv are sequentially performed, and the reading similar to the processing of the column Iv The out operation is repeated. At this time, the slope of the reference signal Vslop becomes the same as that of the column Iv. The data hold control pulse HLDC_00 and the count clock control signal ΤΗ_00 are held as active Η. In this manner, the ramp-93- 1364980 rate of the reference signal Vslop is the same as the processor of the column Iv, and the higher-order flip-flop 510 in the counter 254 performs the double-speed division operation so that the count 値 and voltage 値The relationship between the two becomes 2 Δ V / Δ t. Therefore, at the beginning of the processing of the column Jv, the pixel signal voltage Vx_Jv is processed by twice the gain compared to the processing of the column Iv.

While changing the slope of the reference signal Vslop to twice the slope of the point R(t21_Jv), the data hold control pulse HLDC01 to the data holding unit 5 1 2_0 1 is switched to the operation clock and the count clock control signal to the count clock switch 516_01 ΤΗ01 Switched to action Η. At this time, the pixel signal voltage Vx_:iv in the column J is digitally converted into the count 値mQ_Jv. The number of the actual number of counters 254 is determined by the period between the cycles of the counting clock, and the count 値m〇_Jv at the point R_Jv(t21_〗v) is determined because the upper number is negative Start at Drst_Jv. Furthermore, at this time, since the data retention control pulses HLDC00 and HLDC0 1 are active, the least significant bit (at 0 bits) of the flip-flops 51〇_〇〇 and the second level (in 1 bit) Element) The data of the flip-flop 510_01 is maintained. In fact, after the point R_Jv(tl2_Jv), the least significant bit (0 bit) output and the second level (1 bit) output are invalidated because the 0 bit And each output of 1 bit is invalid after the point R_Jv(t2 1_Jv), and the period after the point R_Jv(t2 1_Jv) becomes the lower resolution period Tsig_LlIp, and at the same time, if the count clock control signal ΤΗ0 1 becomes After the operation, the input clock of the 1-bit flip-flop 51 0_01 is transferred to the clock terminal of the third-stage (at 2-bit) flip-flop 51 0_02. By transmitting the clock to the next -94- 1364980 bit, Except that the bit and 1-bit output are executed twice as fast as the previous double-speed operation In addition, four times, the frequency division operation of the other higher order bits is output, so that the counter 2 54 starts the quadruple speed up and makes the quantization step thicker.

Furthermore, regarding the pixel signal voltage Vx_jv, the low resolution period Tsig_LlJv after the point R_Jv(t21_Jv), when the signal level Ssig_Jv and the reference signal Vslop match (t22_Jv), the counter 254 stops while maintaining the match. Count 値zO_Jv. At this time, the slope of the reference signal Vslop becomes twice the speed before the point R_Jv (t21_Jv), and the higher order bit flip-flop 510 in the counter 254 also performs the frequency dividing operation at the quadruple speed. Therefore, the relationship between the count 値 and the voltage 变成 becomes 2 Δ V / 2 Δ t = Δ V / Δ t, and the relationship between the count 値 and the voltage 値 Δ V / Δ t is stable, which maintains the A/D conversion result relative to The sensor output is linear. The final count 値zO_]v itself automatically becomes the digital data Dsig, which truly reflects the signal component Vsig, so no external circuit is required for correction. After the A/D conversion period of the column Jv is completed, it is not necessary to reset the counter 254, the read operation and the A/D conversion processing of the unit pixel 3 in the column Jv are sequentially performed, and the readout similar to the processing of the column Jv is performed. The operation is repeated. At this time, the slope of the reference signal Vslop becomes twice as large as that after the point R_Iv(t21_Iv) of the column Iv, and on the other hand, the higher order flip-flop 510 in the counter 254 performs the frequency division operation of the quadruple speed. Therefore, the relationship between the count 値 and the voltage 变成 becomes 4 Δν / Δ ΐ = 2 Δν / Δί, and the relationship between the count 値 and the voltage 系 is stabilized as before, so that the pixel signal -95-1364980 voltage Vx_jv is Double gain processing compared to the processing of column Iv. As a result, for example, if, for example, the number of bits is at the A/D conversion period Trst of the reset level Srst and the voltage 値 before the change point R in the A/D conversion period Tsig of the signal level Ssig (conversion coefficient) ) is α [V/digit]', then the final count 値 held in the counter 2 5 4 is "ΔVsig_Iv + 2a XVsig_Jv", and the weighted addition is completed.

For example, assume that the digits in parentheses on the line graph of the pixel signal voltage Vx of FIG. 19 are as shown, the signal components Vsig_Iv and Vsig_Jv in the column Iv and the column Jv are 60, and their reset levels Srst_Iv and Srst_Jv At 10, a two-bit weighted addition is performed. The counts that are kept at each time order become similar to those shown in Fig. 9. More specifically, in the A/D conversion of the signal level Ssig_Iv (signal component Vsig_Iv) in the column Iv, the count 値"-Drst_IV" obtained by the A/D conversion of the reset level Srst_Iv is performed ( = -10) As the starting point starts counting up, the count held in the counter 2 5 4 becomes η-ΐ 0+70=60=Dsig_Iv" after processing. Then in the A/D conversion of the column Jv, The lower number of the set Srst_Jv is counted as "値 = 60 = Dsig_Iv" as the start, and the 'count is counted by the A/D conversion in the column Iv, and the count held in the counter 254 becomes "50". -2x10 = 40". Further, the number used for the signal level Ssig_Jv is executed by the count 値40 as the starting point, and the count held in the counter 254 becomes "40 + 2x 70 after processing. =180". This count 値 means "Dsig_Iv + 2· Dsig_Jv"' by adding the digit 値Dsig_Iv of the signal component Vsig_Iv in the column Iv to the column -96-1364980

The digital component of the signal component Vsig_Jv in Jv is obtained from Dsig_Jv.

It can be understood from the above description that even if the slope of the reference signal Vslop is changed at the A/D conversion processing of the column, if the frequency dividing speed is changed to compensate for the slope change, the final count 値z, that is, the digital data of the signal component Vsig D si g It is not affected by the change in slope, and if the signal components Vsig are the same, the final count 値z(= Dsig) matches. This becomes unnecessary to correct the final count 値, of course, without a function unit to keep the count at the change point 値m. Since the slope of the reference signal Vsig does not become large after the change point R, the A/D conversion period can shorten the amount of difference so that the added image can be obtained at a relatively high speed. In the above description, it is explained that in the A/D conversion processing of a certain column, the slope of the reference signal Vslop is set to twice the slope and the frequency dividing operation of the counter 254 is increased to twice the speed. However, without being limited thereto, the slope of the reference signal Vslop may be changed according to the rise of the sensor output level, and the stages of φ passing through and the flip-flop 5 10 are controlled to perform the counting operation at a higher speed (frequency dividing operation). . At this time, the quantization step becomes thicker. For example, if the counting execution unit 504 is structured as shown in FIGS. 4 and 5, in the processing of the column Iv, the slope of the reference signal Vslop is set to be 4 times larger and the count clock control signal ΤΗ0 1 is set to be active Η, The frequency division operation after the 2-bit counter 254 is operated at 4 times speed is shown in FIG. Furthermore, if the slope of the reference signal Vslop is set to 8 times larger and the count clock control signal TH02 is set to be active, the operation is performed after the 3-bit counter 254 is operated at 8 times the speed -97-1364980. Divided operation. Similarly, the slope of the reference signal Vslop is set to 2·S times (S is a positive integer, "_" is a power), and the count clock control signal TH0T (T=S-1) is set to the action H, thereby completing The counter 2 of the S bit is subjected to the frequency division operation after the factory S times fast operation.

As described above, if the slope of the reference signal Vslop depends on the magnitude of the signal component Vsig (in other words, the size of the photon shot noise), it undergoes several stages of change (gradual change to a steep slope), for example, J1 times (= 2 bits). J2 times (4 times), J3 times (8 times)... and so on, the period of the full swing of the reference signal Vslop is further shortened, thereby performing A/D conversion at a higher speed. Furthermore, the frequency division operation of the counter is changed to operate at a higher speed through several stages, depending on the slope of the reference signal Vslop, such as K1 times (2 times), K2 times (4 times), K3 times (8 times). And so on, and the lower order data becomes invalid, so that the accurate count 对应 corresponding to the signal component Vsig is taken as the final output regardless of the count 値 at the point of changing the reference signal Vslop. Since more low-order bit data is invalidated, the quantization step is thicker and the resolution in A/D conversion is lower, but with regard to photon shot noise, the lower the accuracy will not be for A. The /D conversion result caused a problem. Since the time required for the comparison processing is shortened by setting the slope of the reference signal Vslop to be steeper (larger), the number of counter operations can be reduced, so that the high-speed A/D conversion, that is, the A/D conversion period is shortened. Conversely, if the A/D conversion period remains the same, the number of counting operations can be reduced, so that low power consumption is achieved. Furthermore, when the frequency division operation of the counter becomes faster by several stages, if the output of the lower order bits becomes invalid in sequence and only the division of the remaining higher order bits is -98-

The 1364980 operation operates at high speed to perform the quantization step in a coarser manner, and the start count clock that controls the compare output can be kept at the same speed as the count clock CIN. Although the resolution of the A/D conversion is lowered, the entire count is operated according to the original count clock CIN. Therefore, without increasing the power consumer, when the signal component Vsig becomes larger, the quantization step is further improved by using photon information. Rough to reduce the A/D conversion accuracy, so that A/D conversion accuracy does not seriously impair A/D conversion accuracy. The point R at which the slope of the reference signal Vslop changes is variable, and the mode is performed depending on whether or not the relationship between the photon shot noise and the quantized noise of higher accuracy or faster speed is required. Furthermore, in the former example, when the reference signal Vslop is obliquely 2 to S times, it is displayed that when S is changed by 1 and, for example, 1 ', the present invention is not limited thereto, and any variation step is Maybe, 2 ' 4, and so on. In this relationship, the mode switching is performed according to the accuracy or the faster purpose according to the photon shot noise and the quantization mismatch. When the weighted addition is performed by using photon shot noise, the number of operations can be Reducing, without seriously damaging the A/D conversion accuracy, enables high-speed A/D conversion to be performed at the time of weighted addition processing. As a result, the A/D conversion cycle is the same, and the number of counter operations can be reduced to achieve lower power consumption. [Method for improving the resolution of the added image: Third Embodiment] Fig. 20 is a view showing the actual consumption of the same high-order bit in the vertical direction by the counter 2 54. The re-grain is actually switched and is set according to the rate, 2, 3 For example, the counter accuracy between the higher quasi-symbols, for example, thus the row digit -99-1364980 is added and processed by the digital arithmetic unit 29. The third embodiment of the method for solving the resolution degradation in the horizontal direction line digital addition processing. In the third embodiment, the weighted addition processing of two columns and two rows is not performed, but the weighted addition processing of three columns and three rows. A weighted addition process of three of the row directions is not necessary. When performing the addition processing of three pixels, for example, the weight of three pixels can be

The weighting of one another or only one pixel is different from the weighting of the other two pixels. In the latter, the relationship between them is set to a ratio of 1: η : 1 (η is greater than 1). Preferably, η is a positive integer or any 値 greater than 2, for example, 2' unit pixels 3 '4'.., etc., preferably a power of 2, for example, 2, 4 '8', etc. The method used to set these weights is similar to the weighted adders for two pixels. For example, as shown in FIGS. 22A and 22B, the weighted addition operation of three columns and three rows can be completed by combining the weighted addition processing in the vertical direction and the weighted addition processing in the horizontal direction, and the addition processing in the vertical direction. The row A/D circuit 25 is executed in units of three columns in the vertical direction. In the horizontal direction, the addition processing is performed in the horizontal direction by the three-behavior unit as the arithmetic unit 29. The application form of the weighted addition processing of three columns and three rows, for example, if the coefficients of all the processing target pixels are set to be the same, then the smoothing filtering process as shown in FIG. 20A will be performed, but if a weighting 値 is set so that the center The coefficient of the pixel is set to be larger than the coefficient of the peripheral pixel, and the weighted addition processing of the enhanced center pixel can be completed as shown in FIG. At this time, for example, when pixels are read out in an interlaced scan, they may be weighted by a ratio of -100 - 1364980 1 : 2 : 1 and emphasized at the position of the center of gravity after addition to achieve high resolution. Image. The relationship between the weighted addition of the ratio of the ratio 1: 2:1 and the spatial position after the addition is as follows. More specifically, in the weighted addition of the ratio 1: 2: 1, the spatial position after the addition does not change, similar to the weighted addition of the ratio of 1: 1:1, but the center position is emphasized after the addition. The high-resolution image can be completed in the process of changing the spatial position after the addition.

[Camera device] Fig. 23 is a block diagram of an image pickup device, which is an example of a physical information acquisition device based on the above-described solid state imaging device 1. A camera device 8 is an imaging device for capturing visible light color images. The mechanism of the above-described solid-state image pickup device 1 is not only applied to a solid-state image pickup device but also to an image pickup apparatus. At this time, in the image pickup apparatus, it is possible to obtain high resolution by changing the spatial position after addition by weighted addition. At this time, the counting frequency of the counting becomes faster to control the setting of the weighting, or the slope control of the reference signal Vslop can be arbitrarily designated by setting the data to the external host controller, and the controller data indicates the switching mode to the communication/timing Controller 20. Specifically, the imaging device 8 includes: an imaging lens 802, an optical low-pass filter 804, a color filter group 812, a pixel array unit 10, a drive controller 7, a line processor 26, a reference signal generator 27, and Camera signal processor 810. The photographic lens 802 guides the light L carrying the image of the illumination device, for example, the fluorescent object Z, to the side of the imaging device to generate a shadow image of the object Z. The color filter group 812 has, for example, color filters arranged in a Bayer configuration. The drive controller 7 drives the pixel array unit 1 〇. 26 pairs of pixel array units 1 (Γ output pixel signals, execution or A/D conversion processing. Reference signal generator 27 supplies Vslop to line processor 26 » camera signal processor 810 performs processing on the image signals. Optical low pass The filter 804 is used to block the Nyquist rate component to avoid aliasing. Further, the infrared line cut filter 805 can be set to be the same as the general camera device with the optical low pass filter 804. The camera signal processor camera signal processor 820 and the camera controller 900 of the next stage of the line processor 26 are actuators for controlling the entire camera unit 8. The image signal processor 820 has a signal separator 822 and a processor 830. The separator 822 has a main color separation function. When a color filter is used, the digital image signal supplied by the A/D conversion function unit is separated, G (green), B (blue). ) Three primary colors.

Furthermore, the image signal processor 820 has a brightness signal 840' for signal processing according to the three primary colors f|, B separated by the signal separator 822, and an encoder for coloring according to the brightness signal Y/color. The signal C generates a video image VD. Although not shown, the color signal processor 83 0 has an example amplifier, a gamma correction unit, and a color difference matrix unit. White Balance R, G, B Line Processor CDS Processing Reference Signal From the infrared frequency of the frequency of 126. This system 810 has a main control color signal for use in processor 26: R (red) processor! No. R, G 860, such as white balance amplifier root - 102 - from white balance control not shown The slice balance supplied by the device is adjusted to the gain of the three primary color signals originally supplied to the signal separator 822, and supplied to the modulating unit and the luminance signal processor 840. Based on the adjusted white balance primary color signal, an accurate color is generated, and each gamma corrected output signal is input to the color difference matrix element to perform color difference matrix processing and input the acquired color to the encoder 860. 1364980

Although not shown, the luminance signal processor 840 signal generator, the low frequency luminance signal generator, and the bright luminance signal generator are generated based on the primary color signal supplied from the demultiplexer unit to generate the phase-containing signal YH. The low-frequency luminance signal generator depends on the white balance of the primary color signal, and produces only low; ^ YL. The luminance signal generator generates the luminance signal γ depending on the two types of illumination, and supplies the luminance signal γ to the encoder 86 0 to use the color difference signal RY, BY corresponding to the number of times of the color signal, and is generated by the signal processor 840. Luminance signal γ, video signal VD (= Y + S + C; S is a synchronizing signal; the digital video signal output from the encoder 860 indicates the camera signal output unit of the lower level, and then is output or recorded as data in the recording medium. In the I-signal, adjust (the gain of the white separation function unit to the gamma correction gamma correction (r) is the unit of the color R, G, B. The color difference matrix single difference signals RY, BY have, for example, high-frequency brightness Degree signal generator. High 822 primary color separation function when high frequency component brightness self-white balance amplifier supply component brightness signal signal YH, YL and encoder 8 6 0. Carrier digital signals, combine them to brightness and The conversion to digital C is the chrominance signal.) VD is supplied to the undisplayed, used as the monitor input, if necessary -103- 1364980, the digital video signal VD is transferred via D/A The conversion is converted to a video signal.

The camera controller 900 in this embodiment has a microprocessor 902, which is the core of the computer, and is represented as a central processing unit (CPU), which integrates the functions of operation and control performed by the computer and is integrated. On a very small integrated circuit; a read only memory (ROM) 904, as a dedicated read memory; a random access memory (RAM) 906, which is an example of volatile memory and available Write and read as needed; and other peripheral components not shown. Microprocessor 902, ROM 904, and RAM 906 are collectively referred to as a microcomputer. In the above, "volatile memory" means a device that erases the contents of the memory when the device is powered off. On the other hand, "non-volatile memory" means a memory device that retains memory contents even when the device's main computer is powered off. In the memory device, not only non-volatile semiconductor memory devices, but also any memory device can be used as long as they can hold the contents of the memory. Alternatively, in addition to the non-volatile semiconductor memory, φ can be used as a non-volatile memory by providing a backup power source. Furthermore, the 'memory is not limited to a semiconductor memory device, and a media architecture such as a magnetic disk or a compact disk can also be used. For example, a hard disk can also be used as a non-volatile memory. Furthermore, an architecture can also be used as the non-volatile memory 'where the information is read from the recording medium such as the CD-ROM. The camera controller 900 controls the entire system. In particular, in the aforementioned processing for completing the high-speed A/D conversion processing, the camera controller 9 has an on/off function of adjusting various control pulses 'various pulses are used in the reference signal generation -104-1364980 Control of the slope change of the reference signal Vslop and control of the frequency division speed in the counter 254. In the ROM 904, a control program of the camera controller 900 is stored, and in particular, in this example, a program for controlling the on/off timing of various control pulses of the camera controller 900 is stored. In the RAM 906, various materials processed for the camera controller 900 are stored.

Further, the camera controller 900 can insert or remove a recording medium 924, such as a card, and connect to a communication network such as the Internet. For example, in addition to the microprocessor 902, the ROM 904, and the RAM 906, the camera controller 900 has a recording unit 907 and a communication I/F (interface) 908. The recording medium 924 is used to store data, such as program data, so that The microprocessor 902 performs software processing based on the luminance system signal supplied from the luminance signal processor 840, and various settings, such as a flux range of the optical data φ DL and an exposure control process (including an electric shutter control), and The slope of the reference signal Vslop in the signal generator 27 changes the on/〇 ̄ timing of various control pulses controlled by the divided frequency in the counter 254. The memory readout unit 907 stores (installs) the data read from the recording medium 924 to the RAM 906. The communication I/F 908 connects and transmits data between communication networks, such as the Internet. In this image pickup device 8, the drive controller 7 and the line processor 26 are displayed in a module separate from the pixel array unit 10. However, it is needless to say that, in the description of the solid-state image pickup device 1, it is possible to use the single crystal solid-state image pickup device 1, in which the drive controller 7 and the line processor 26 are integrated on the same semiconductor substrate, Installed with pixel array unit 10

In the figure, the image pickup device 8 has an optical system, in addition to the pixel array unit 10, the drive controller 7, the line processor 26, the reference signal generator 27, and the camera signal processor 810, and further includes a photographic lens 802 and an optical low-pass filter. Mirror 804 or infrared cut filter 805, these are preferably formed into a module having an imaging function and including such components as a package. The above solid-state image pickup device 1 can be provided as a module having an image pickup function, as shown in the figure, which includes a pixel array unit 1 (an image pickup unit) and a signal processor of a closely related pixel array unit 1 (except for a line processor) The side of the camera signal processing unit of the next stage includes a line processor 26 provided with an A/D conversion function and a credit (CDS) processing function as a package. The entire camera unit 8 can be provided by the camera signal processor 810 as the other part of the signal processor of the next stage of the solid-state imaging device 1 in the form of a module. Alternatively, although not shown, the entire imaging device 8 can be integrated into the module-shaped solid-state imaging device 1 having an imaging function by the camera signal processor 81, wherein the pixel array unit 10 and the optical lens such as the imaging lens 802 The system is packaged together. Further, in the module of the solid-state image pickup device 1, a camera signal processor 810 corresponding to the camera signal processor 200 may be included. At this time, it is possible to think that the solid-state imaging device 1 and the imaging device 8 are identical. This camera device 8 is provided with a mobile device that is useful for performing "camera," -106-

1364980 For example, a camera or a mobile device with camera function. The “camera” is not only the detection of the normal image captured by the camera. The image pickup apparatus 8 constructed as above includes all of the functions of the foregoing 1, and the basic architecture and operation system are made the same as the above one. Therefore, in the image pickup apparatus 8, since the addition is performed to change the spatial position of the pixels after the addition, it is possible to obtain a mechanism by performing simple addition of all the uniform coefficients. For example, a program memory that causes the computer to execute the above processing, a recording medium of a 1C card, or a memory card such as a micro card is distributed. Furthermore, the program can be downloaded or updated via a web-based routing server. It is possible to store the solid state described in these embodiments; partial processing or all functions (especially regarding the function of implementing high-speed processing, in which the variable speed control of the slope variable frequency division operation of the reference signal Vslop is performed in cooperation with each other) In the semiconductor memory of the micro card, it is possible to provide a program or a recording medium storing the program as the recording medium 924. A high-speed A/D conversion program for performing high-speed A/D conversion described in the description of the image pickup apparatus 1 is installed in a software body and has a control pulse setting function for implementing a high-soft body in which reference signals are matched with each other. Vslop's oblique counter speed change control for frequency division operation. In the present specification, it is also applicable to the use of a solid-state image pickup device for a fingerprint solid-state image pickup device, which can be used to achieve a high resolution, such as a flash non-volatile semiconductor communication network, for example, the A/D conversion of the image device 1 Control and count 1C cards or examples, for example. Therefore, similar to the solid-state processing, for example, the RAM A/D conversion to rate change control and -107-1364980

The soft system is read 1 by RAM 90 6 and executed by microprocessor 902. For example, the microprocessor 902 performs a control pulse setting process based on a program stored in, for example, the ROM 904 and the RAM 906 of the recording medium to control the operation of selecting the column or row to be added, the adjustment of the counter frequency dividing speed, and the slope of the reference signal Vslop. The adjustments (changes) cooperate with each other. Therefore, it is possible to perform a function as a software for changing the spatial position of the added pixels to obtain a high-resolution image compared to performing a simple addition of all the coefficients. According to an embodiment of the present invention, Since the weighting 値 can be set in accordance with the selection operation of selecting the addition target pixel, the added pixel position can be adjusted by setting an appropriate weight 値 to minimize the degradation of the resolution. As a result, it is possible to obtain a high-resolution image. It will be appreciated by those skilled in the art that various modifications, combinations, sub-combinations and variations may occur depending on design requirements and other factors, which are within the scope of the accompanying claims or their equivalents. [Related Applications] This application contains Japanese patent applications JP2007-008 1 04 and JP2007-2914 67, respectively, which are filed on Jan. 17, 2007 and November 9, 2007, each of which is incorporated herein by reference. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a CMOS solid-state image pickup device according to an embodiment of the present invention. FIG. 2 is a structural example of a unit pixel used in the solid-state image pickup device of FIG. 1 and a driving unit and a driving control line thereof. And a line connection between the pixel transistors; -108-1364980 FIG. 3 is a diagram showing an example of a connection interface beside the voltage comparator and the counting portion; FIG. 4 is a diagram showing a first example of a counting execution unit; 5 is a diagram showing a second configuration example of the counting execution unit; FIG. 6 is a timing chart showing the signal acquisition addition processing, which is the basic operation of the row A/D circuit of the solid-state imaging device shown in FIG. 1. ;

Figure 7 is a timing chart showing the addition processing in parallel in the vertical direction of the A/D conversion processing operation; Figure 8 A-8 D is a diagram showing the digital addition processing of the counter in the vertical direction and the arithmetic with digits Disadvantages of digital addition processing of cells in the horizontal direction; FIG. 9 is a timing chart (first example), shown in the improved resolution method of the first embodiment, paralleled in the vertical direction of the A/D conversion processing operation Weighted addition processing; FIG. 10 is a timing chart (second example) showing the weighted addition processing in parallel in the vertical direction of the A/D conversion processing operation in the improved resolution method of the first embodiment; 11 is a diagram showing the action of the count clock switch in the resolution improvement method of the first embodiment; FIGS. 12A to 12F are diagrams (first example) showing the vertical direction in the resolution improvement method of the first embodiment. Pixel configuration of the addition operation in the direction and the horizontal direction; FIGS. 13A to 13F are diagrams (second example) showing the image of the addition operation in the vertical direction and the horizontal direction in the resolution improvement method of the first embodiment -109- 1364980 14A to 14F are diagrams (third example) showing the pixel arrangement of the addition operation in the vertical direction and the horizontal direction in the resolution improvement method of the first embodiment; FIG. 15 is a diagram for display An example of a mechanism for setting a weighted 任意 of an arbitrary integer;

Fig. 1 6A to 1 6F are diagrams showing "addition of ratios 3 to 1 + addition of ratios 1 to 3", in which weighting 値 is set to "3"; Figs. 17A to 17F are diagrams showing "proportion 4 to Addition of 1 + addition of ratios 1 to 4, where the weighting 値 is set to "4"; Figs. 18A to 18C are diagrams showing a method of shortening the comparison processing time in the single-slope integral A/D conversion system: Figure 19 is a timing chart showing the addition processing in parallel in the vertical direction of the A/D conversion processing for explaining the second embodiment; Figure 20 is a diagram showing when the timing clock switch is operated in the second implementation Figure 2 is a diagram showing the relationship between the slope change control of the reference signal and the frequency division speed control of the counter; Figs. 22A to 22B are diagrams showing the counter in the vertical direction A third embodiment of the method of digitally adding processing and reducing the resolution of the digital addition processing in the horizontal direction by the digital arithmetic unit; and FIG. 23 is a diagram showing an image pickup apparatus using a solid-state imaging device The architecture. -110- 1364980 [Description of main component symbols] 1 : Solid-state imaging device 3 : Unit pixel 5a : Terminal 5b : End 5 c : End

1 0 : pixel array unit 1 2 : horizontal scanning circuit 12a : horizontal decoder 12 b : horizontal driving unit 1 2 c : control line 14 : vertical scanning circuit 14a : vertical decoder 14 b : vertical driving unit 1 5 : column control line φ 1 8 : horizontal signal line 1 9 : vertical signal line 20 : communication / timing controller 23 = clock converter 24 : read current supply 25 : row A / D circuit 26 : line processor 27 : reference signal generator 27a : Digital analog converter-111 1364980 28: Output circuit 29: Digital arithmetic unit 7: Drive controller 252: Voltage comparator 254: Counter 256: Data storage unit 2 5 8: Switch 32: Charge generator 3 4: Readout selection Transistor 3 6 : Reset transistor 38 : Floating diffusion 40 : Vertical selection transistor 42 : Source follower amplification transistor 5 2 : Vertical selection line 5 5 : Transmission line 5 6 : Reset line 5 : Pixel signal generation 5 1 : pixel line 242 : NMOS transistor 244 : reference current source 246 : current generator 2 4 8 : source line 502 : gate 504 : counting execution unit 1364980

510: flip-flop 5 1 2 : data holding unit 5 1 4 : counting mode switch 5 1 6 : counting clock switch 5 1 7 : counting clock line 518 : clock stopping unit 8 : imaging device 924 : recording medium 8 02 : photography Lens 8 04 : Optical low-pass filter 8 0 5 : Infrared cut filter 8 1 0 : Camera signal processor 8 1 2 : Filter group 820 : Image signal processor 822 : Signal separator 830 : Color signal processor 840 : Luminance Signal Processor 860: Encoder 900: Camera Controller 902: Microprocessor 904: Read Only Memory 906: Random Access Memory 907: Memory Read Unit 908: Communication Interface

Claims (1)

1364980 Batch year ί (Moon 修正 仏 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 096 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 'Used to sequentially compare the predetermined level of the analog pixel signal obtained from the majority of pixels with a reference signal, the reference signal is gradually changed and used to convert the predetermined level into digital data; ;) a counter 'for paralleling The ratio 1 of the predetermined level in the comparator is compared to the processing 'performing a counting process, and when the comparison processing is completed, maintaining a count 値' to obtain digital data, which is obtained by adding the majority of the pixel signals And an add-on spatial position adjusting unit for controlling a selection operation of the selected spatial position of the majority of pixels to be processed in the comparator and a ratio of weighting 相 at the time of addition to adjust the added a spatial position of the pixel, wherein the added spatial position adjusting unit changes a slope of the reference signal used in the comparator to "1/L2 times" to set When the addition of the > to Zhi weighting the ratio "L 2" times faster. 2 - a solid-state imaging device comprising: - a comparator - for sequentially comparing a predetermined level of an analog pixel signal obtained from a plurality of pixels with a reference signal, the reference signal being gradually changed and used to convert the predetermined level a digital data; a counter' for performing a comparison process in parallel with the predetermined level in the comparator, and performing a counting process when the comparison process is completed, to maintain a count 値 to obtain digital data, which indicates And a summing space position adjusting unit for controlling a selection operation of the selected spatial position of the plurality of pixels processed in the comparator and adding time weighting 値The ratio of the spatial position of the pixel after the addition, wherein the addition spatial position adjustment unit changes the speed of the frequency division operation in the counter to "L 1 " times faster to set the addition time This ratio of the weighted 値 is as large as "L1". 3. The solid-state image pickup device according to claim 1 or 2, wherein the addition space adjustment unit changes the reference before the comparison processing of the predetermined level of some pixels in the comparator is completed. The slope of the signal is J times larger and the speed of the frequency division operation in the counter is changed to J times faster to keep the weighting of a certain pixel constant. 4. The solid-state image pickup device according to claim 3, wherein the addition spatial position adjustment unit simultaneously changes the slope of the reference signal by J times, and controls the output of each bit in the counter. The change in speed of the frequency division operation. 5. The solid-state image pickup device according to claim 1 or 2, wherein: the counter is a non-synchronous counter and has a chronograph clock switch disposed between each 兀 stage for switching one The input clock signal, and the addition 'spatial position adjustment unit controls the count clock switch to transmit a clock signal input to each bit as a high-order bit clock signal when the speed of the frequency division operation is changed. 6. The solid-state image pickup device according to claim 1 or 2, wherein: the counter is in a first predetermined level of processing the pixel signal of a certain pixel, or one of a number mode or a number mode, Performing a counting process and maintaining a count 値 when the comparison process is completed in the comparator, and when the second predetermined level of the pixel signal of the same pixel is processed, by using the held count 値 as a starting point And performing the counting process in the lower mode or another mode of the upper mode and maintaining the count 时 when the comparison process is completed in the comparator. 3. The solid-state image pickup device according to claim 6, wherein the counter maintains a count 完成 at the completion of the comparison processing of the second predetermined level of the pixel signal of the certain pixel, and is next When the first predetermined level of the pixel of the pixel is compared with the second predetermined level, the counter is switched by the same counting mode as the pixel signal of the certain pixel. The count 値 held in the counter is used as a starting point, and the counting process is performed to obtain digital data representing one of 値 obtained by adding the majority of the pixel signals. Ο 8 · The solid-state image pickup device according to claim 1 or 2, wherein most of the aforementioned comparators use the common reference signal, and perform the comparison in parallel with the pixel signal processed for each comparator deal with. 9. The solid-state image pickup device according to claim 1 or 2, wherein the addition space position adjustment unit controls a ratio of weighted 値 at the time of addition such that the space of each pixel after addition is added. The position systems are arranged at equal intervals. The solid-state image pickup device according to claim 9, wherein: the pixel is provided with a color filter to generate a color image, and -3- s 1364980 the added spatial position adjusting unit controls the selection Operate to select the spatial position of the majority of the pixels to be processed in the comparator, so that the pixels with the same color are the same, and the ratio of the weighted 値 when the addition is controlled, so that the spatial position of each pixel is Arranged to be equally spaced. U.~ kinds of camera equipment, including: & string, please refer to the solid-state camera device described in the first or second patent scope; and the '" controller for controlling the generation of control signals for controlling the added spatial position Adjust the unit. 3