九、發明說明： 【發明所屬之技術領域】. 本發明係關於-種疊對量測標記及其疊對誤差之量測 方法，特別係關於一種可置於晶粒之電路區域内之疊對量 測標記及其疊對誤差的量測方法。 【先前技術】 由於晶圓本身或製程所產生的量測誤差（Wafer or process Induced measurement error，WIS)是造成疊對量測 準確度最主要的來源。隨著製程演進，WIS值的影響更為 顯着。 傳統晶圓使用的疊對量測標記之線寬與尺寸多為約數 十微米之數量級，故習知技藝大多將疊對量測標記置放於 晶圓之切割道（scribe Une)上。但近年來製程線寬逐漸縮小 ，置於切割道上的疊對量測標記已無法提供足夠資訊給下 一製程世代的疊對量測使用。 由於光學量測的鄰近效應及製程的變異性而導致之叠 對量測誤差與疊對量測標記置放的位置有很大的關聯性， 且誤差會隨著貫物的大小而變化。故縮小疊對量測標記之 尺寸，使其能置放於晶粒（die)内的電路區域（active area)内 ，進而降低WIS值之影響，是提升量測精準度不錯的方式 之一0 【發明内容】 本發明提供一種微小而具良好誤差靈敏度的疊對量測 標記，其僅佔數平方微米的空間，因而可置放在靠近或於 1361266IX. INSTRUCTIONS: [Technical field to which the invention pertains] The present invention relates to a method for measuring a stack-to-measurement mark and its overlay error, and more particularly to a stack that can be placed in a circuit region of a die. Measuring method and measurement method of stacking error. [Prior Art] The Wafer or Process Induced Measurement Error (WIS) is the most important source of stacking accuracy. As the process evolves, the impact of WIS values is more pronounced. Conventional wafers use stack-to-measure marks with line widths and sizes that are on the order of tens of microns. Conventionally, most of the overlay marks are placed on the scribe Une of the wafer. However, in recent years, the process line width has been gradually reduced, and the overlay measurement marks placed on the scribe lines have not provided sufficient information for the stack measurement of the next process generation. Due to the proximity effect of the optical measurement and the variability of the process, the overlay measurement error is highly correlated with the position where the overlay is placed, and the error varies with the size of the object. Therefore, reducing the size of the stack of measurement marks so that it can be placed in the active area of the die, thereby reducing the influence of the WIS value, is one of the ways to improve the accuracy of the measurement. SUMMARY OF THE INVENTION The present invention provides a small stack of measurement marks with good error sensitivity, which only occupy a space of several square micrometers, and thus can be placed close to or at 1361266.
I • * ' 電路區域内，以降低WIS值並提高量測的精準度。 本發明之疊對量測標記之一實施例包含一第一標記及 一第二標記。弟一標記與一第一膜層相關聯，具有一第一 邊緣。第二標記與一第二膜層相關聯，具有一第二邊緣， . 其中該第一邊緣與該第二邊緣在水平方向之間距小於一量 * 測系統之解析度。 本發明之積體電路結構之一實施例包含一電路區域、 _ —環繞該電路區域之切割道、一第一標記及一第二標記。 第一標S己设置於S亥電路區域内，且該第一標記具有一第一 邊緣。第二標記亦設置於該電路區域内，該第二標記具有 一第二邊緣，其t該第一邊緣與該第二邊緣在水平方向之 • 間距小於一量測系統之解析度。 本發明之疊對誤差之量測方法之一實施例首先使用一 量測系統獲取一疊對量測標記影像，其中該疊對量測標記 包含具有一第一邊緣之第一標記及具有一第二邊緣之第二 鲁 標記，且該第一邊緣與該第二邊緣的間距小於該量測系統 之解析度。接著，獲取該疊對量測標記影像沿著一掃描線 之光學強度曲線，並依據該光學強度曲線計算該掃描線的 不對稱值。最後，進行—比對程序，以從一不對稱與疊 . 對誤差之關聯曲線中，找出與該不對稱值匹配之疊對誤差 【實施方式】 本案發明人之本國專利證書號1286196揭示一種依據 «·對置測標記影像之不對稱性來決定疊對誤差的方法與系 -7- 統，本發明將其内容併入本案交互參考。特而言之，本發 明提出之疊對量測標記突破了習知設計上下層標記的邊緣 距離越大越好的設計潮流。相反的，本發明例示的疊對標 記利用邊緣的鄰近效應（proximity effect)來取得疊對誤差 ’故上下層標記的邊緣距離越靠近越能顯出良好的量測靈 敏度。 圖1例示本發明之一疊對量測標記1〇之上視圖之一實 施例，圖2例示該疊對量測標記i〇沿Α_Αι剖面線之剖示圖。 該疊對量測標記10包含一結合在第一膜層或圖樣之第一標 記12以及一結合在第二膜層或圖樣之第二標記14。第一標 記12具有一正方形外框，其具有一第一邊緣（内緣）。第二標 。己14係為只心正方形，具有一第二邊緣（外緣）。實心正方 形14之外緣與第一標記之内緣夾有一間距G。該第一標記12 係埋在—或更多層材料下，第二標記14係在光阻材料16中 形成之圖樣或置於其上，如圖2所示。 ^第二標記14採用實心正方形的好處為其透過量測系統 觀2下，第二標記14的邊緣清楚，且掃描線的選取有更廣 。&圍|本發明的其他實施例中，第一標記^的形狀亦 可為K〜正方形、四矩形構成之方框或其他任何呈中心 對稱的幾何圖形。圖3及圖4分別例示第一標記32為_實心 二方形及四矩形42a'42b、42e及似所構成之方框 例0 G值的大小 的標記態樣下，I • * ' Within the circuit area to reduce the WIS value and improve the accuracy of the measurement. One embodiment of the overlay measurement marker of the present invention includes a first indicia and a second indicia. The one-mark is associated with a first film layer and has a first edge. The second mark is associated with a second film layer and has a second edge, wherein the first edge and the second edge are spaced apart in the horizontal direction by less than an amount of resolution of the system. An embodiment of the integrated circuit structure of the present invention includes a circuit region, a scribe track surrounding the circuit region, a first mark, and a second mark. The first mark S is disposed in the S circuit area, and the first mark has a first edge. The second mark is also disposed in the circuit area, and the second mark has a second edge, wherein the distance between the first edge and the second edge in the horizontal direction is less than the resolution of a measurement system. An embodiment of the method for measuring the overlay error of the present invention first obtains a stack of measurement mark images using a measurement system, wherein the overlap measurement mark includes a first mark having a first edge and has a first The second edge of the two edges is marked, and the distance between the first edge and the second edge is less than the resolution of the measurement system. Then, an optical intensity curve of the overlay of the measurement mark image along a scan line is obtained, and an asymmetry value of the scan line is calculated according to the optical intensity curve. Finally, a comparison-comparison procedure is performed to find the overlap error that matches the asymmetry value from the correlation curve of the asymmetry and the stack. [Embodiment] The inventor's national patent certificate number 1286196 discloses a kind of The method and the system for determining the stacking error according to the asymmetry of the image of the image are set, and the content of the invention is incorporated into the cross-reference of the present invention. In particular, the overlay-to-measurement markers proposed by the present invention break through the design trend of the well-designed upper and lower marks with a larger edge distance. In contrast, the overlay mark exemplified by the present invention utilizes the proximity effect of the edge to obtain the overlay error. Therefore, the closer the edge distance of the upper and lower marks is, the better the measurement sensitivity is. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a view showing an embodiment of a top view of a stack of measurement marks 1 本 of the present invention, and Fig. 2 is a cross-sectional view of the stack of measurement marks i 〇 along a line of Α_Αι. The stack of measurement marks 10 includes a first mark 12 bonded to the first film layer or pattern and a second mark 14 bonded to the second film layer or pattern. The first mark 12 has a square outer frame having a first edge (inner edge). Second standard. The 14 is a heart-only square with a second edge (outer edge). The outer edge of the solid square 14 has a spacing G from the inner edge of the first mark. The first mark 12 is buried under - or more layers of material, and the second mark 14 is formed or placed on the photoresist material 16, as shown in FIG. ^ The second mark 14 has the advantage of using a solid square for its transmission measurement system. The edge of the second mark 14 is clear and the scanning line is selected more widely. In other embodiments of the present invention, the shape of the first mark ^ may also be a square of K~square, a quadrangular rectangle or any other geometrically symmetric geometry. 3 and 4 respectively illustrate the first mark 32 being a solid square and four rectangles 42a' 42b, 42e and a mark pattern of a case where the value of the frame is 0 G value,
可決疋豐對誤差的靈敏度。圖5例示以圖j 固定第一標記〗2之方框線寬為13〇奈米，G 1361266 9The sensitivity of the error to the error can be determined. Figure 5 illustrates the frame width of the first mark 〖2 fixed by Figure j as 13 〇 nanometer, G 1361266 9
值分別為130、250及500奈米的不對稱與疊對 、友1 關聯曲 線圖。由圖5可判讀出在兩標記的邊緣間距為13〇奈米時， 其不對稱與疊對誤差之關聯曲線之變化率較5〇〇奈米時為 大。因此，較小的間距G反應出較佳的量測靈敏度。在本發 明之某些實施例中，G之大小係不大於該量測系統的光學解 析度，其中光學解析度係取決於檢測光束之波長以）及該吾 測系統之光學鏡片的數值孔徑（Numericai Apenure，。The values are 130, 250, and 500 nm asymmetry and overlap pair and friend 1 correlation curve graphs. It can be judged from Fig. 5 that when the edge spacing of the two marks is 13 〇 nanometer, the rate of change of the correlation curve between the asymmetry and the stacking error is larger than that at 5 〇〇 nanometer. Therefore, a smaller pitch G reflects a better measurement sensitivity. In some embodiments of the invention, the magnitude of G is no greater than the optical resolution of the metrology system, wherein the optical resolution is dependent on the wavelength of the detection beam and the numerical aperture of the optical lens of the system ( Numericai Apenure,.
另外’若已知用來.觀察疊對量測標記的光學儀器之解析度 後，可用該解析度為G值的上界。由於兩標記的邊緣效應^ 传G值越小則越能根據其光學性質判斷疊對誤差。在本發月 的其他實施例下，G之上界亦可由該微影製程的關鍵尺寸 (critical dimension)決定。Further, if the resolution of the optical instrument used to observe the overlay measurement mark is known, the resolution can be used as the upper bound of the G value. Since the edge effect of the two marks is smaller, the more the G value is judged, the more the overlap error can be judged based on its optical properties. In other embodiments of the present month, the G upper bound may also be determined by the critical dimension of the lithography process.
圖6例示本發明之疊對誤差之量測方法一實施例。首先 ，於步驟S601使用一量測系統獲取一疊對量測標記影像， 該疊對量測標記包含一具有一第一邊緣之一第一標記及具 有一第二邊緣之一第二標記，且該第一邊緣與該第二邊緣 的間距小於該量測系統之解析度。於步驟86〇2中，獲取該 豐對量測標記影像沿著一掃描線之光學強度曲線^掃描線 之選取可為平行一座標軸，橫跨該第一標記及該第二標記 之直線，如圖1中的A-A，。掃描線亦可為平行另一座標軸之 直線，如圖1中的B-B'，以獲得二維空間的疊對誤差。圖7 例示一光學強度曲線圖，其橫軸為尺寸刻度，縱軸為強度 單位。步驟S603，依據該光學強度曲線計算該掃描線之一 不對稱值。不對稱值之取得可先決定—對稱中心，如圖7 1361266 t 之虛線所不，再依對稱尹心兩倒差異的均方 =對稱值。最後，進行一比對程序，以從一不:稱:: 、差之關聯曲線，，找出與該不對稱值匹配之疊對誤差 ’如步驟S604。在本發明之部分實施财，不對稱録對 :差之關聯曲線可參考圖5之例示。在本發明之部分實：例 ’不對稱與疊對誤差之關聯曲線之取得可參考，但非僅 限於’本案發明人之本國專利證書號⑽⑼所揭示之内容 〇Fig. 6 illustrates an embodiment of the method for measuring the overlay error of the present invention. First, in step S601, a stack of measurement mark images is acquired by using a measurement system, the stack pair measurement mark includes a first mark having a first edge and a second mark having a second edge, and The distance between the first edge and the second edge is less than the resolution of the measurement system. In step 86〇2, the optical intensity curve along the scan line of the image is obtained, and the scan line can be selected as a parallel axis, and the line between the first mark and the second mark is AA in Figure 1. The scan line can also be a line parallel to the other coordinate axis, such as B-B' in Fig. 1, to obtain the stacking error of the two-dimensional space. Figure 7 illustrates an optical intensity graph with the horizontal axis as the scale and the vertical axis as the intensity unit. Step S603, calculating an asymmetry value of the scan line according to the optical intensity curve. The asymmetry value can be determined first—the center of symmetry, as shown by the dotted line in Figure 7 1361266 t, and then the mean square = symmetric value of the difference between the two sides of the symmetric Yin heart. Finally, an alignment procedure is performed to find the overlay error associated with the asymmetry value from a no:::, difference correlation curve, as in step S604. In the implementation of the present invention, the asymmetric recording pair: the difference correlation curve can be exemplified with reference to FIG. 5. In the present invention, the correlation curve between the asymmetry and the overlay error can be referred to, but is not limited to the contents disclosed by the inventor's national patent certificate number (10) (9).
在本發明的部分實施例中，疊對量測標記10、30、40 之大小可縮至數微米（μηι)的數量.級。例如，圖】之第一標記 12之正方形外框之邊長可等於或小於3_奈米（即3微米y。 因此’疊對量測標記不但可置於切割道上，更可置於晶粒 的電路區域内’使得疊對量測標記與電路的距離降低:\ 而減少疊對誤差·》此外’疊對量測標記lG、3q、利之大小 可隨製程演進而調整，不會因製程改變而淘汰。 微小的疊對量測標記可降低量測誤差。由於較小的疊 對量測標記㈣較小的影像區域，使影像的不同部份間= 較少的像差係數差異，因此經由這些像差產生量測誤差也 較小。此外’微小的疊對量測標記亦可降低量測誤差中， WIS值所造成的效應'。因光學量測的變形及製程的變显性 而導致之疊對量職差與疊對量測標記置放的位置有很大 的關聯性，且誤差會隨著實物的大小而變化。因此減少最 對量測標記與實際置放於主動元件區相對面積之差異性0 減少WIS的產生。 -10- 1361266 # 在本申諳案所使用的專用名詞，包含正方形、矩形、 中心點等’並非指其數學上的定義，而係指其於半導體製 程中所認知的意義。舉例來說，本申請案所指之正方料 限定於數學上完美的正方形，而包含因製造過程產生些許 變異之正方形。 本發明之技術内容及技術特點已揭示如上，然而熟悉 本項技術之人士仍可能基於本發明之教示及揭示而作種種 • 不背離本發明精神之替換及修飾。因此，本發明之保護範 圍應不限於實施例所揭示者，而應包含各種不背離本發明 之替換及修飾，並為以下之申請專利範圍所涵蓋。 【圖式簡要說明】 圖1例示一疊對量測標記之上視圖一實施例之示意圖； 圖2例示一疊對量測標記沿Α_Αι剖面線之剖示圖之示 忍圖； 圖3及圖4分別例示不同疊對量測標記之上視圖之實施 • 例之示意圖； 圖5例示以不同標記間距下的不對稱與疊對誤差關聯 曲線之示意圖； 圖6例示本發明之疊對誤差的量測方法一實施例之示 ' 意圖；以及 圖7例示一光學強度曲線圖之示意圖。 【主要元件符號說明】 10 疊對量測標記 12 第一標記 1361266 第二標記 光阻材料 間距 掃描線 知描線 疊對量測標記 第一標記 第二標記 疊對量測標記 矩形 矩形 矩形 矩形In some embodiments of the invention, the size of the stack of measurement marks 10, 30, 40 can be reduced to a number of micrometers (μηι). For example, the side of the square frame of the first mark 12 of the figure can be equal to or smaller than 3_nano (ie, 3 micrometers y. Therefore, the stacking measurement mark can be placed not only on the scribe line but also on the dies. In the circuit area, the distance between the measurement mark and the circuit is reduced: \ and the overlap error is reduced. In addition, the size of the measurement mark lG, 3q, and the size of the measurement can be adjusted with the evolution of the process, and will not be changed by the process. And the elimination. The tiny stack-to-measurement mark can reduce the measurement error. Because of the small overlap of the measurement mark (4), the smaller image area makes the difference between the different parts of the image = less aberration coefficient, so These aberrations also produce small measurement errors. In addition, 'small stack-to-measurement marks can also reduce the effect of WIS values in measurement errors'. Due to deformation of optical measurement and process variation The stack-to-quantity difference has a great correlation with the position where the stack is placed, and the error varies with the size of the object. Therefore, the reduction of the most-measured mark is actually relative to the actual placement of the active element. Area difference 0 reduces WIS generation -10- 1361266 # The terminology used in this application, including squares, rectangles, center points, etc. 'is not a mathematical definition, but rather a meaning that is recognized in the semiconductor process. For example The square material referred to in the present application is limited to a mathematically perfect square, and includes a square which is slightly mutated due to the manufacturing process. The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still be based on The present invention is not limited to the embodiments of the present invention, and the present invention is not limited by the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [Brief Description of the Drawings] Fig. 1 is a schematic view showing an embodiment of a stack of measurement marks in a top view; Fig. 2 is a cross-sectional view showing a stack of measurement marks along a line of Α_Αι Figure 3 and Figure 4 respectively illustrate the implementation of the top view of the different stack of measurement marks. Figure 5 illustrates the different marks. FIG. 6 is a schematic diagram showing an embodiment of the measurement method of the overlay error of the present invention; and FIG. 7 is a schematic diagram showing an optical intensity curve. DESCRIPTION OF SYMBOLS 10 Stack of measurement marks 12 First mark 1361266 Second mark photoresist material pitch Scan line Know line overlap mark Measurement mark First mark Second mark stack Pair measurement mark Rectangular rectangle Rectangular rectangle