TWI358819B - Resistive memory and method for manufacturing the - Google Patents

Description

Yan Nai 8819

—*达达编号:TW3432PA IX. Description of the Invention: [Technical Field] The present invention relates to a resistive memory and a method of manufacturing the same, and in particular to a scalabimy resistive Memory and its manufacturing method. [Prior Art] With the shrinkability of the traditional memory structure, the bottleneck resistive resistive memory has high scalability, fast reading and writing speed, and can be applied to metal oxide semiconductors (metal 〇 and semiconductor). , M0S) process for manufacturing. Therefore, the resistive type can be called the star of tomorrow's next-generation memory technology. The method of manufacturing the resistive memory of the hidden/visual memory is to deposit a layer of material and then etch a separate memory structure by a lithography process with a mask having an island structure. However, it is difficult to improve the resolution of the island structure in the lithography process, and it is difficult to increase the density of the memory components. SUMMARY OF THE INVENTION The present invention relates to a resistive memory and a method of manufacturing the same, which are characterized in that a memory pattern is formed by forming a line pattern, and the density of the memory element can be greatly improved. According to the present invention, a resistive memory is provided, comprising a substrate, a first signal line, a memory unit and a second signal line. First signal line 6 1358819

Sanda number: TW3432PA is disposed on the substrate, and the first signal line has a first surface. The memory unit has a second surface, and the memory unit is coupled to the first signal line by contacting the first surface with the second surface. The second signal line is disposed on the memory unit and coupled to the memory unit, wherein the area of the second surface is substantially greater than or equal to the area of the overlapping area of the first signal line and the second signal line. According to the present invention, a method of manufacturing a resistive memory is provided, which comprises the following steps. First, a first conductive material layer is formed on a substrate. Then, the first conductive material layer is engraved into a first signal line having a first surface. Then, a memory material layer having a second surface is formed, and the memory material layer is coupled to the first signal line by the first surface contacting the second surface. Next, a second conductive material layer is formed and coupled to the memory material layer. Then, the second conductive material layer is etched to form a second signal line, wherein the area of the second surface is substantially greater than or equal to the area of the overlapping area of the first signal line and the second signal line. In order to make the above description of the present invention more comprehensible, the following detailed description of the preferred embodiments, together with the accompanying drawings, will be described in detail as follows: [Embodiment] The present invention can be applied to the manufacture of resistive memory, including resistors. Resistive random access memory (RRAM) and resistive read only memory (RROM). Referring to Figures 1A-8A, there is shown a plan view showing a manufacturing process of a resistive memory of the present invention. At the same time, please refer to the 1B-8B, 1C-8C and 10th drawings, which respectively show the section line along the 1A-8A diagram.

"· Sanda number: TW3432PA AA and section line BB section 'and the flow chart of the manufacturing steps of a resistive memory of the present invention》, please refer to the drawings 1A, 1B and 1C, first, as in step 1001 The first conductive material layer 115 is formed on the substrate 100. The substrate 1 〇〇 may be provided with a selective device, such as a metal oxide semiconductor field effect transistor (MOSFET), a diode or a double carrier junction. A blP〇lar junction transistor (BJT) is coupled to the memory structure to control the operation of the memory and form a protective layer, such as a titanium nitride (TiN) or nitride group (TaN). In addition, in the step looi, a conductive first barrier material layer 11 is deposited on the substrate 1 , and then a first metal material layer 120 is deposited on the first barrier material layer 11 形成 to form a first conductive layer. Material layer 115. The first metal material layer 120 is, for example, tungsten (W), titanium (Ti), aluminum (A1), nickel (Ni), copper (Cu), ytterbium (Zr) or zinc (Zn), etc., this embodiment The middle system uses tungsten. The first barrier material layer no Luben embodiment uses titanium nitride (T i N ), which can be used as an adhesive layer to connect the first metal material layer 120 and the substrate 100, and the first metal material layer 120 can be avoided. Cracks are generated. Then, as shown in step 1002, a first patterned mask 10 is formed on the first conductive material layer 115. Next, as shown in step 1003, a first patterned mask 10 is formed on the first conductive material layer 115. In this embodiment, a step of forming a photoresist layer (not shown) on the first conductive material layer 115, and then using the lithography process to pattern the photoresist layer to become the first patterned mask 10» 1A shows that the first patterned mask 10 has several first line patterns. Figure 13 1358819

-. Sanda number: TW3432PA ^ case. - Please refer to the drawings 2A, 2B, and 2C. As shown in step kick 1003, the first patterned mask 10 is cut 1 to become the first patterned mask l〇a. Step 1〇〇3 is to narrow the line width of the pattern to form smaller components. Step 1003: using a reactive ion etching (RIE) method, a mixture of one or more of chlorine (Cl2), bromic acid (Hbr), oxygen (〇2), and argon (Ar) with other chemicals The environment is done down. According to the experimental results, in this way, the line width of 60 nm can be reduced to 20 nm. ® But if the ability of the exposure machine is sufficient to form the desired width in step 1002, step 1003 can be omitted. Referring to Figures 3A, 3B and 3C, first, as shown in step 1004, the first conductive material layer 115 is inscribed as a first signal line 115a. That is, the silver-etched first metal material layer 120 is the first metal layer 120a, and the first barrier material layer 110 is the first barrier layer U〇a. Next, as shown in step 1005, the first patterned mask i〇a is removed, and the photoresist can be removed using an oxygen plasma $(〇2 plasma) followed by a suitable agent such as EKC265 for cleaning. Then, as shown in step 1006, a first dielectric material layer 13 is deposited to cover the first signal line 115a and the substrate 1A. Step 1〇〇6 can be performed by depositing cerium oxide (silic〇n 〇xide) with high density plasma chemical vapor deposition (HDPCVD). Referring to Figures 4A, 4B and 4C, first, as shown in step ,, the planarization of the first dielectric material layer is performed as a first dielectric layer to expose the first signal line 115a. This step can be used for 趁m 使用 using chemical mechanical grinding 9 1358819

Sanda number: TW3432PA (chemical mechanical polishing, CMP) method, or etch back method to Yuancheng. Next, as shown in step Nog, the metal oxide layer 120b is formed to engage the first signal line 1 as a memory material layer. Step 1008 may oxidize a portion of the first signal line 120a by plasma oxidation, for example, using direct plasma, magnetic field enhance reactive ion plasma, or down-blow plasma. (d〇wn stream plasma) 'Compatate with oxygen (〇2) and nitrogen (no mixing, or 〇2, ^ and hydrogen (H〇 mixing, or oxidation in a pure oxygen environment. Because of this embodiment The first metal layer 1 is a tungsten, and therefore the oxidized metal layer 120b formed by the plasma oxidation method is tungsten oxide. Referring to Figures 5A, 5B and 5C, first, as shown in step 1 〇〇g, The first conductive material layer 140 is coupled to the metal oxide layer i2〇b. Next, as shown in step 1010, a second patterned mask 2 is formed on the second conductive material layer 140. In this embodiment, step 1 First, a photoresist layer (not shown) may be formed on the second conductive material layer 14 , and then the photoresist layer is patterned into a second patterned mask, 2 〇. It can be seen from FIG. 5A 'The first patterned mask 20 has a plurality of second line patterns And the first line pattern of the first patterned mask 10 is substantially perpendicular to each other. Referring to FIGS. 6A, 6B and 6C, as shown in step mu, the second patterned mask 20 is cut to become the second patterning. Mask 2〇a. Steps 1〇11 have the same function as step 903, and a smaller line width can be defined to produce smaller components. Similarly, if the capability of the exposure machine is sufficient, it can be formed in step 1010. For the width, step 1011 can be omitted. 1358819

Sanda Number: TW3432PA Referring to Figures 7A, 7B and 7C, first, as shown in step 1012, the second conductive material layer 140 is etched to form a second signal line 140a, thereby forming the memory structure 125. The memory structure 125 includes a second signal line 140a, a memory unit 120c, and a first conductive layer 115a. The second conductive material layer 140 may be made of the same metal material as the first metal material layer 120, and etched using, for example, chlorine (Cl2), vaporized boron (BC13), or the like as an etching agent; in this embodiment, it is preferably employed. A chemical agent mainly composed of sulfur fluoride (SF6) is used to remove tungsten oxide of a portion of the memory material layer 120b, and a memory cell 120c and a second signal line 140b are defined. Next, as shown in step 1013, the second patterned mask 20a is removed, in the same manner as step 1005. Referring to Figures 8A, 8B and 8C, as shown in step 1014, depositing a second dielectric layer 150 over the memory structure 125 can be accomplished in the same manner as step 1006. At this point, the resistive memory 50 is completed. As shown in FIGS. 8A, 8B and 8C, the resistive memory 50 includes a substrate 100, a first signal line 115a, a memory unit 120c, a first dielectric layer 130a, a second signal line 140a, and a second dielectric layer 150. The first signal line 115a is disposed on the substrate 100 and has a first surface 117. In the present embodiment, the first signal line 115a is composed of a first barrier layer 110a and a first metal layer 120a, and titanium nitride and tungsten are used as source materials, respectively. The memory unit 120c has a second surface 122 coupled to the first signal line 115a by the second surface 122 contacting the first surface 117. The material of the memory unit 120c in this embodiment is tungsten oxide. The second signal line 140a is disposed on the memory unit 120c and coupled to the memory unit 120c. In this embodiment, the second signal line 140a 11 1358819

", Landa number: TW3432PA * is used as a bit line. The area of the second surface 122 is substantially equal to the area of the overlapping area of the first signal line 115a and the second signal line 140a. That is to say, the memory unit 120c is located at the intersection of the first signal line 115a and the second signal line 140a. Please refer to the figures 9A, 9B and 9C, which respectively show the top view of the conventional resistive memory, and along the 9A Section line AA, and BB, section view. The function and structure of the substrate 200, the first signal line 215, the second dielectric layer 230, the second signal line 240 and the second dielectric layer 250' of the resistive memory 5 and the corresponding components in the resistive memory 50 The first signal line 215 includes a first barrier layer 210 and a first metal layer 220. The difference between the resistive memory 5 and the resistive memory 50 is that the first signal line 215 and the second signal line 240 ′ are separated by the third dielectric layer 260 and coupled to the first signal line 215 by the contact hole 270 . And the second signal line 240, the memory unit 272 is located between the second signal line 240 and the metal layer of the contact hole 270. Since each contact hole is an independent island-like structure, each contact hole is not easily aligned with the first signal line 215 and the second signal line 240, and the misalignment occurs as shown in FIGS. 8B and 8C. . The above embodiment of the present invention can form a very small cross section by reducing the line width, and define the memory unit in a self-aligned manner on the intersection section. In addition to ensuring that the signal line and the memory unit are correctly aligned, the linear pattern can be reduced in size, which can effectively reduce the area of the memory unit. In addition to increasing component density, the reduction in the area of the memory cell increases the resistance value, which greatly reduces the programming voltage and reduces leakage current and power consumption. 12 1358819 » »

* Sanda number: TW3432PA In addition, steps 1002 and 1003 can be replaced by a hard mask mask. Next, a cross-sectional view along the section line bb in the diagram of the brothers 1A and 2A will be described as an example of the flow of another first patterned mask. Referring to FIG. 11A-11b, a cross-sectional view showing the formation process of another first patterned mask during the manufacturing process of the resistive memory of the present invention is shown. First, a layer of hard mask material (not shown) is formed on the first conductive material layer 115. Next, a layer of photoresist material (not shown in green) is formed on the layer of hard mask material. The patterned photoresist layer then becomes the first patterned mask 10 as shown in Figure 1C. Next, the hard mask material layer is etched to become the first patterned hard mask 30' as shown in Fig. 11A. Then, the first patterned photoresist layer 10 is removed. Next, the first patterned hard mask 3 〇 ' is cut to become the first patterned hard mask 30a as shown in Fig. 11B. The layer of hard mask material may be a nitride such as a nitride, or a mono-oxide such as hafnium oxide, which may be reduced by mixing RIE with CF4, CHF3, Ar, C4F8, C4F6, oxygen, or one or more chemical gases. Alternatively, when φ is used as the source material of the hard mask, dilute HF (DHF) or buffered HF (BHF) may be used for wet etching reduction; when nitrogen is used; When phlegm is used as a source material for a hard mask, hot phosphoric acid can be used for wet etching. However, regardless of the etchant used, care must be taken to ensure a high degree of selectivity for the underlying metal material to avoid damage to the metal source. The use of a hard mask increases the resistance to RIE, ensuring that subsequent etching can form a precise pattern. Then, step 1004 can be continued. 13 1358819

Sanda number: TW3432PA Similarly, (4) 1〇10 and 1〇11 can be replaced by a hard mask in the same way. Next, a flow chart for forming a fresh-patterned mask will be described, and a cross-sectional view along the section line aa in Figs. 5A and 6A will be described as an example. Please refer to the figure 12B for a cross-sectional view showing the formation process of the second patterned mask during the manufacturing process of the resistive memory of the present invention. A layer of hard mask material (not shown) is formed on the second layer of conductive material (10). Next, a photoresist layer (not shown) is formed on

The layer of the photoresist layer is made as the fifth layer ===the photoresist layer 2〇. Then the layer of the hard mask material becomes the ^ hard scale 40, as shown in Fig. 12A, and then the second = The photoresist layer 20 is then formed. Next, the second patterned hard mask 4 is cut into a j-patterned hard mask 4Ga, as shown in Fig. 12B. Then, step 1012 can be continued. Further, 'oxidation in step 1012 The metal layer 12〇1:) can be etched without etching, and the area of the second surface of the formed memory cell is larger than the area of the overlapping area of the first signal line φ115a and the second signal line. However, as long as the first signal line The overlapping area of 115a and the second signal line 14〇a is rotated through the oxidized metal layer 12〇b, and the memory unit that substantially functions as a memory is located in the overlapping area of the first singular line l15a and the second signal line 144a. The resistive memory and the manufacturing method thereof disclosed in the above embodiments of the present invention generate a separate memory structure in a line pattern, which can improve the miniaturization capability of the component and produce a high-density memory than the conventional use of the island pattern. Reduced resistance Memory means having a more stylized low voltage, low 1,358,819

Sanda number: TW3432PA Leakage current, low power consumption, etc., greatly increase the practicality and application range of resistive memory. In the above, the present invention has been disclosed in the above preferred embodiments, but it is not intended to limit the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. 15 1358819

Sanda number: TW3432PA [Simple description of the drawings] FIG. 1A-8A is a top view showing a manufacturing process of a resistive memory according to the present invention; and FIG. 1B-8B is a cross-sectional line AA' along the first A-8A drawing. FIG. 1C-8C is a cross-sectional view taken along line BB′ of FIG. 1A-8A; FIG. 9A is a top view of a conventional resistive memory; FIG. 9B is a view along line 9A; FIG. 9C is a cross-sectional view taken along line BB′ of FIG. 9A; FIG. 10A-10B is a flow chart showing a manufacturing step of a resistive memory according to the present invention; 11B is a cross-sectional view showing the formation process of another first patterned mask in the manufacturing process of the resistive memory of the present invention; and FIG. 12A-12B illustrates the manufacturing process of the resistive memory of the present invention. Another cross-sectional view of the formation of the second patterned mask. 16

Claims (1)

1358819 June 16th, 100th revised replacement page l〇6. 6. i 6 year month 曰 correction replacement page ten, patent application range 1r~- ^ A resistive memory, including · a substrate; a first signal line Provided on the substrate, the first signal line has a first surface; a memory unit having a second surface, the memory unit contacting the first surface and the first signal by the second surface a second signal line is disposed on the memory unit and is connected to the memory unit, wherein the second signal line has a third surface, an area of the surface of the three surfaces, and the second The area of the surface is substantially large; or the area of the area where the first signal line overlaps the second signal line. 2. The resistive memory of claim 4, wherein the first signal line comprises: a barrier layer; a metal layer disposed on the barrier layer. 3. The resistive memory according to item 2 of the scope of the patent application, wherein the material of the barrier layer is titanium nitride, and the material of the metal layer is crane. 4. The resistive memory according to the first aspect of the invention, wherein the material of the unit is oxidized scale. 5) A method of manufacturing a resistive memory, comprising: (a) forming a layer of a first conductive material on a substrate; wherein the layer of the first conductive material becomes - having a surface of the first surface (c) The second surface of the memory material layer of the memory material 1358819 rl β-- 曰 曰 correction replacement page - June 100] 6th correction replacement page ^ and by the first surface contact the second surface and the first - signal The wire is connected; and (4) is formed - the second conductive material layer is consumed by the memory material layer; (^ the second conductive material layer is formed to form - the second signal line, and the second signal line has - the first The surface of the third surface is larger than the area of the surface of the δ 弟 ,, and the area of the first surface is substantially larger than or larger than the area of the _-signal line and the area overlapping the second signal line. As described in claim 5, (a) further includes forming a first patterned mask having a first stomach: step-type pattern on the layer of conductive material 'this step (4) further includes forming - Having a first line pattern and the second line pattern The method of claim 5, wherein the step (4) deposits an electrically conductive first barrier material, depositing a first-metal material layer on the first barrier; and: forming the first conductive material Layer. 啊·^上'以形8. If the barrier material layer of item 7 of the patent application scope is titanium nitride. Eighth of the first 9. If the patent application scope includes: the method of the description, where step (8) = a mask material layer on the first conductive material layer; forming a photo-layer on the hard mask material layer; 1358819 June 16 曰 revised replacement page patterning the photoresist material layer becomes a a patterned photoresist layer; etching the hard mask material layer to form the first patterned mask, and removing the first patterned photoresist layer. 10. The method of claim 9 wherein the removing The step of the first patterned photoresist layer further comprises: trimming the first patterned mask. The method of claim 9, wherein the hard mask material layer Is a nitride or an oxide. 12. If applying The method of claim 5, wherein the step (b) comprises: forming a photoresist layer on the first conductive material layer; and patterning the photoresist material layer into the first patterned mask. 13. The method of claim 12, wherein the step of patterning the photoresist layer further comprises: reducing the first patterned mask. 14. As described in claim 5 The method, wherein the step (i) comprises: forming a hard mask material layer on the second conductive material layer; forming a photoresist material layer on the hard mask material layer; patterning the photoresist material layer into a second patterned photoresist layer; etching the hard mask material layer into the second patterned mask; and removing the second patterned photoresist layer. The method of claim 14, wherein the step of removing the second patterned photoresist layer further comprises: 20 L35 «819 lior^: 1 6- IO 6 6 6 6 6 Replace the page I year month date correction replacement page to cut the second patterned mask. The method of claim 5, wherein the step (i: a photoresist layer is on the second conductive material layer; and patterning the light layer layer to the second chemist layer) U. The method of claim 16, wherein the step of the 匕k photoresist layer further comprises: /, θ 〃 reducing the second patterned mask. (8) more = including / please patent scope The method of claim 5, wherein the step (8) further comprises depositing a layer of a first dielectric material and planarizing the first layer of the dielectric material to expose the first signal line. 19. claim 18 The method described, wherein the polishing, CMP) method. 2. The method of claim 18, wherein the step (f) uses an etching back method. The method of claim 5, wherein the step (g) includes oxidizing the far-signal line to form the memory material layer. 22. The method of claim 5, wherein the step (e) further comprises: depositing - a second dielectric layer overlying the memory structure.