100年12月02日修正替換頁 1358698 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係關於一種移位暫存器及採用該移位暫存器之液 晶顯示裝置。 【先前技術】 [0002] 目前薄膜電晶體（Thin Fi lm Transistor, TFT)液晶 顯示裝置已逐漸成為各種數位產品之標準輸出設備，然 ，其需要設計適當的驅動電路以保證其穩定工作。 [0003] 通常，液晶顯示裝置的驅動電路包括一資料驅動電路及 一掃描驅動電路。資料驅動電路用於控制每一像素單元 之顯示輝度，掃描驅動電路則用於控制薄膜電晶體之導 通與截止。二驅動電路均應用移位暫存器作為核心電路 單元。通常，移位暫存器係由複數移位暫存單元串聯而 成，且前一移位暫存單元之輸出訊號為後一移位暫存單 元之輸入訊號。 [0004] 請參閱圖1，係一種先前技術移位暫存器之移位暫存單元 之電路圖。該移位暫存單元100包括一第一時鐘反相電路 110、一換流電路120及一第二時鐘反相電路130。該移 位暫存單元100之各電路均由PMOS(P-channel Metal-Oxide Semiconductor, P溝道金屬氧化物半導體）型電 晶體組成，每一PM0S型電晶體均包括一閘極、一源極及 一汲極。 [0005] 該第一時鐘反相電路110包括一第一電晶體Ml、一第二電 晶體M2、一第三電晶體M3、一第四電晶體M4、一第一輸 出端V01及一第二輸出端V02。該第一電晶體Ml之閘極接 096104986 表單编號 A0101 第 4 頁/共 28 頁 1003447516-0 1358698 100年.12月0》日修正替換頁 收該移位暫存單元100之前一移位暫存單元之輸出訊號VS ，其源極接收來自外部電路之高電平訊號VDD，其汲極連 接至該第二電晶體M2之源極。該第二電晶體M2之閘極及 其汲極接收來自外部電路之低電平訊號VSS。該第三電晶 體M3及該第四電晶體M4之閘極均接收來自外部電路之反 相時鐘訊號^，二者之汲極分別作為該第一時鐘反相 電路110之第一輸出端V01及第二輸出端V02，且該第三 電晶體M3之源極連接至該第一電晶體Ml之汲極，該第四 電晶體Μ 4之源極連接至該第一電晶體Μ1之閘極。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a shift register and a liquid crystal display device using the shift register. [Prior Art] [0002] At present, Thin Film Transistor (TFT) liquid crystal display devices have gradually become standard output devices for various digital products. However, it is necessary to design an appropriate driving circuit to ensure stable operation. [0003] Generally, a driving circuit of a liquid crystal display device includes a data driving circuit and a scanning driving circuit. The data driving circuit is used to control the display luminance of each pixel unit, and the scan driving circuit is used to control the on and off of the thin film transistor. Both drive circuits use a shift register as a core circuit unit. Generally, the shift register is formed by connecting the plurality of shift register units in series, and the output signal of the previous shift register unit is the input signal of the latter shift register unit. Please refer to FIG. 1, which is a circuit diagram of a shift register unit of a prior art shift register. The shift register unit 100 includes a first clock inverting circuit 110, a commutation circuit 120, and a second clock inverting circuit 130. Each circuit of the shift register unit 100 is composed of a PMOS (P-channel Metal-Oxide Semiconductor) type transistor, and each PMOS transistor includes a gate and a source. And a bungee. The first clock inverting circuit 110 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a first output terminal V01, and a second Output V02. The gate of the first transistor M1 is connected to 096104986. Form No. A0101 Page 4 of 28 1003447516-0 1358698 100. December 0" Day Correction Replacement Page Receives a shift before the shift register unit 100 The output signal VS of the memory unit has a source receiving a high level signal VDD from an external circuit and a drain connected to a source of the second transistor M2. The gate of the second transistor M2 and its drain receive a low level signal VSS from an external circuit. The gates of the third transistor M3 and the fourth transistor M4 receive the inverted clock signal ^ from the external circuit, and the drains of the two are respectively used as the first output terminal V01 of the first clocked inverter circuit 110 and The second output terminal V02, and the source of the third transistor M3 is connected to the drain of the first transistor M1, and the source of the fourth transistor Μ 4 is connected to the gate of the first transistor Μ1.
[0006] 該換流電路120包括一第五電晶體Μ5、一第六電晶體Μ6及 一訊號輸出端V0。該第五電晶體Μ5之閘極連接至該第一 輸出端V01，其源極接收來自外部電路之高電平訊號VDD ，其汲極連接至該第六電晶體Μ6之源極。該第六電晶體 Μ6之閘極連接至該第二輸出端V02，其汲極接收來自外部 電路之低電平訊號VSS，其源極係該移位暫存單元100之 訊號輸出端V0。 [0007] 該第二時鐘反相電路130包括一第七電晶體Μ7、一第八電 晶體Μ8、一第九電晶體Μ9及一第十電晶體Μ10。該第七電 晶體Μ7之閘極連接至該訊號輸出端V0，其源極接收來自 外部電路之高電平訊號VDD，其汲極連接至該第八電晶體 Μ8之源極。該第八電晶體Μ8之閘極及其汲極均接收來自 外部電路之低電平訊號VSS。該第九電晶體Μ9之源極連接 至該第一輸出端V01，其閘極接收來自外部電路之時鐘訊 號CK，其汲極連接至該第七電晶體Μ7之汲極。該第十電 晶體之閘極接收外部電路之時鐘訊號CK，其源極連接至 096104986 表單編號Α0101 第5頁/共28頁 1003447516-0 1358698 [0008] 100年12月02日接正替換頁 該第二輸出端V02，其汲極連接至該訊號輸出端VO。 請一併參閱圖2，係該移位暫存單元100之工作時序圖。 在T1時間内，該前一移位暫存單元之輸出訊號VS由高電 平跳變為低電平，反相時鐘訊號^由低電平跳變為高 電平，則使該第三電晶體M3及該第四電晶體M4截止，進 而使該第一時鐘反相電路110斷開。而該時鐘訊號CK由高 電平跳變為低電平，使該第九電晶體M9及該第十電晶體 M10導通，進而使該第二時鐘反相電路130導通，而該訊 號輸出端VO初始狀態之南電平經該第十電晶體M10 ’使該 第六電晶體M6截止，而該第八電晶體M8輸出之低電平經 由該第九電晶體M9，使該第五電晶體M5導通，進而使其 源極之高電平訊號VDD輸出至該訊號輸出端VO，故該訊號 輸出端VO保持高電平輸出。 [0009] 在T2時間内，該反相時鐘訊號gg由高電平跳變為低電 平，則使該第三電晶體M3及該第四電晶體M4導通，進而 使該第一時鐘反相電路110導通。而該時鐘訊號CK由低電 平跳變為高電平，則使該第九電晶體M9及該第十電晶體 M10截止，進而使該第二時鐘反相電路130斷開。該輸入 訊號VS由高電平跳變為低電平，則使該第一電晶體Μ1導 通，其源極之高電平VDD經該第三電晶體M3截止該第五電 晶體Μ5，且該輸入訊號VS之低電平經該第四電晶體Μ4導 通該第六電晶體Μ6，使該訊號輸出端VO輸出低電平。 [0010] 在Τ3時間内，該反相時鐘訊號ck由低電平跳變為向電 096104986 表單编號Α0101 第6頁/共28頁 1003447516-0 1358,698 .100年.12月0乏日梭正替换頁 平，則使該第三電晶體M3及該第四電晶體M4截止，進而 使該第一時鐘反相電路110斷開。而該時鐘訊號CK由高電 平跳變為低電平，使該第九電晶體M9及該第十電晶體M10 導通，進而使該第二時鐘反相電路130導通。該訊號輸出 端V0之低電平導通該第七電晶體M7，其源極之高電平經 該第九電晶體M9截止該第五電晶體M5。同時，該訊號輸 出端V0之低電平亦經該第十電晶體Ml 0導通該第六電晶體 M6，該第六電晶體M6之汲極低電平使該訊號輸出端V0保 持低電平輸出。 [0011] 在T 4時間内’該反相時鐘訊號由向電平跳變為低電 平，則使該第三電晶體M3及該第四電晶體M4導通，進而 使該第一時鐘反相電路110導通。而該時鐘訊號CK由低電 平跳變為高電平，使該第九電晶體M9及該第十電晶體M10 截止，進而使該第二時鐘反相電路120斷開。輸入訊號VS 之面電平經該第四電晶體M4截止該第六電晶體M6，而該 第二電晶體M2之汲極低電平經該第三電晶體M3導通該第 五電晶體M5，使其源極之高電平輸出至該訊號輸出端V0 ，使該訊號輸出端V0之輸出由低電平跳變為高電平。 [0012] 該移位暫存器的各移位暫存單元100所用電晶體數量較多 ，且各訊號走線的繞線較複雜，故該移位暫存器的電路 結構較複雜。 [0013] 另外，該移位暫存器可應用於液晶顯示裝置以及其他數 位電子產品中。例如液晶顯示裝置的資料驅動電路或掃 描驅動電路需要該移位暫存貫現列掃描或行掃描的功 096104986 表單編號A0101 第7頁/共28頁 1003447516-0 1358698 100年12月02日修正呑換頁 能。然，該移位暫存器的電路結構較複雜，容易發生雜 訊干擾，故採用該移位暫存器作為資料驅動電路及掃描 驅動電路之液晶顯示裝置在進行列掃描或行掃描時，各 訊號間亦容易相互干擾。 【發明内容】 [0014] 有鑑於此，提供一種電路結構簡單之移位暫存器實為必 要。 [0015] 另，提供一種可避免訊號干擾之液晶顯示裝置亦為必要 〇 [0016] —種移位暫存器，其包括複數移位暫存單元，每一移位 暫存單元均受外部電路的時鐘訊號、反相時鐘訊號、前 一級移位暫存單元之輸出訊號及前一級移位暫存單元之 反相輸出訊號控制。每一移位暫存單元包括一時鐘訊號 輸入端、一反相時鐘訊號輸入端、一高電平輸入端、一 低電平輸入端、一第一輸入端、一第二輸入端、一輸出 端、一反相輸出端、一上拉電路、一下拉電路、一第一 輸出電路、一第二輸出電路及一反相電路，該時鐘訊號 輸入端接收外部電路之時鐘訊號，該反相時鐘訊號輸入 端接收外部電路之反相時鐘訊號，該高電平輸入端接收 外部電路之高電平訊號，該低電平輸入端接收外部電路 之低電平訊號，該第一輸入端電連接至前一級移位暫存 單元之輸出端，該第二輸入端電連接至前一級移位暫存 單元之反相輸出端，該輸出端電連接至後一級移位暫存 單元之第一輸入端，該反相輸出端電連接至後一級移位 暫存單元之第二輸入端，該上拉電路、下拉電路及該第 096104986 表單编號A0101 第8頁/共28頁 1003447516-0 1358698 •100'年.12月0·2日修正智換頁 一輸出電路具有一公共節點，該上拉電路受該第一輸入 端控制’該下拉電路受該第二輸入端及該公共節點控制 ’該上拉電路為該公共節點提供高電平訊號，該下拉電 路為該公共節點提供低電平訊號。該第一輸出電路在該 公共節點的控制下輸出時鐘訊號，該第二輸出電路在該 反相時鐘訊號的控制下輸出低電平訊號，該反相電路將 第一或第二輸出電路的輸出訊號反相後輸出，其中，該 下拉電路包括一第二電晶體、一第三電晶體及—第四電 晶體，該第二電晶體的閘極電連接該第二輸入端，其源._ 極電連接該公共節點，其汲極電連接該第三電晶體的源 極，該第三電晶體的閘極電連接該第四電晶體的源極， 其没極電連接該低電平輸入端，該第四電晶體的閘極電 連接該公共節點’其汲極電連接該反相時鐘訊號輸入端 〇 [0017] 一種液晶顯示裝置，其包括一液晶顯示面板、一資料驅 動電路及一掃描驅動電路，該資料驅動電路為該液晶顯 示面板提供資料訊號，該掃描驅動電路為該液晶顯示面 板提供掃描訊號，該資料驅動電路及該掃描驅動電路分 別包括-移位暫存器以控制資料訊號與掃描訊號之輸出 時序。該移位暫存包括複數移位暫存單元，每一移位 暫存單it均文外部電路的時鐘訊號、反相時鐘訊號、前 -級移位暫存單元之輸出訊號及前—級移位暫存單元之 反相輸出轉控制，每—移位暫存單元包括—時鐘訊號 輸入端、一反相時鐘訊號輸入端、一高電平輸入端、一 低電平輸入端、—第一輸入端、一第二輸入端、一輸出 096104986 表單编號A0101 第9頁/共28頁 1003447516-0 1358698 100年12月02日修正替換頁 端、一反相輸出端、一上拉電路、一下拉電路、一第一 輸出電路、一第二輸出電路及一反相電路。該時鐘訊號 輸入端接收外部電路之時鐘訊號，該反相時鐘訊號輸入 端接收外部電路之反相時鐘訊號，該高電平輸入端接收 外部電路之高電平訊號，該低電平輸入端接收外部電路 之低電平訊號，該第一輸入端電連接至前一級移位暫存 單元之輸出端，該第二輸入端電連接至前一級移位暫存 單元之反相輸出端，該輸出端電連接至後一級移位暫存 單元之第一輸入端，該反相輸出端電連接至後一級移位 暫存單元之第二輸入端。該上拉電路、下拉電路及該第 一輸出電路具有一公共節點，該上拉電路受該第一輸入 端控制，該下拉電路受該第.二輸入端及該公共節點控制 ，該上拉電路為該公共節點提供高電平訊號，該下拉電 路為該公共節點提供低電平訊號，該第一輸出電路在該 公共節點的控制下輸出時鐘訊號，該第二輸出電路在該 反相時鐘訊號的控制下輸出低電平訊號，該反相電路將 第一或第二輸出電路的輸出訊號反相後輸出，其中，該 下拉電路包括一第二電晶體、一第三電晶體及一第四電 晶體，該第二電晶體的閘極電連接該第二輸入端，其源 極電連接該公共節點，其汲極電連接該第三電晶體的源 極，該第三電晶體的閘極電連接該第四電晶體的源極， 其汲極電連接該低電平輸入端，該第四電晶體的閘極電 連接該公共節點，其汲極電連接該反相時鐘訊號輸入端 〇 [0018] 與先前技術相比，本發明移位暫存器的每一移位暫存單 096104986 表單编號A0101 第10頁/共28頁 1003447516-0 1358698 100年.12月日修正替换頁 元由六顆電晶體構成，且沒有複雜的繞線，故該移位暫 存器的電路結構簡單，從而可避免不必要雜訊干擾發生 。同時，因電晶體數量較少，在生産中的錯誤機率也相 應較低，從而可以提高產品的良率。 [0019] 由於該移位暫存器的電路結構較簡單，因此可避免不必 要雜訊干擾發生。使用該移位暫存器之掃描驅動電路及 資料驅動電路在進行行掃描或列掃描時，其各輸出訊號 間亦不會產生訊號干擾，從而提高了該液晶顯示裝置的 顯示效果。 【實施方式】 [0020] 請參閱圖3，其係本發明移位暫存器較佳實施方式之結構 示意圖。該移位暫存器20包括複數結構相同之移位暫存 單元2G0，該複數移位暫存單元200依次串聯。每一移位 暫存單元200包括一時鐘訊號輸入端TS、一反相時鐘訊號 輸入端TSB、一第一輸入端VIN1、一第二輸入端VIN2、 一輸出端V0UT、一反相輸出端V0UTB、一高電平輸入端 VH及一低電平輸入端VL。每一移位暫存單元200之時鐘訊 號輸入端TS接收外部電路（圖未示）之時鐘輸入訊號CK， 其反相時鐘訊號輸入端TSB接收外部電路（圖未示）之反相 時鐘輸入訊號CKB，其高電平輸入端VH接收外部電路（圖 未示）之高電平訊號VDD，其低電平輸入端VL接收外部電 路（圖未示）之低電平訊號VSS。其第一輸入端VIN1電連 接至前一級移位暫存單元200之輸出端V0UT，其第二輸入 端VIN2電連接前一級移位暫存單元200之反相輸出端 V0UTB，其輸出端V0UT箪連接至後一級移位暫存單元200 096104986 表單編號A0101 第11頁/共28頁 1003447516-0 1358698 100年12月02日接正替換頁 之第一輸入端VIN1 ,其反相輸出端V0UTB電連接至後一 級移位暫存單元200之第二輪入端VIN2。即前一級移位暫 存單兀200之輸出訊號為後—級移位暫存單元2〇〇之第一 輸入訊號，前一級移位暫存單元2〇〇之反相輸出訊號為後 一級移位暫存單元200之第二輸入訊號，且每一移位暫存 單兀200同時由外部電路的時鐘訊號CK、反相時鐘訊號 CKB、鬲電平訊號vdd及低電平訊號vSS控制。 [0〇21]明參閱圖4，其係圖3之移位暫存單元之電路示意圖。該 移位暫存單元200包括一上拉電路31 ' —下拉電路32、一 第一輸出電路33、一第二輸出電路34、一緩衝器35及一 反相器36 ’該緩衝器35係由二反相器串接而成，主要用 於保持該移位暫存單元2〇〇之輸出波形，避免輸出波形失 真。該上拉電路31、下拉電路32及該第一輸出電路33具 有一公共節點P ’該上拉電路31為該公共節點p提供高電 平訊號’該下拉電路32為該公共節點p提供低電平訊號。 該上拉電路31受該第一輸入端viNl控制，該下拉電路32 受該第二輸入端VIN2及該公共節點P控制》該第一輸出電 路33在該公共節點P的控制下輸出時鐘訊號CK至該缓衝器 35 ’該第二輸出電路34在該反相時鐘訊號CKB的控制下輸 出低電平訊號VSS至該緩衝器，該緩衝器將接收的時鐘訊 號CK或低電平訊號vss傳送至該輸出端νουτ。該反相器 36將輸出端V0UT的訊號反相後輸入至該反相輸出端 V0UTB 。 [0022]該上拉電路31包括一第一電晶體Ml，該第一電晶體Ml係 NM0S型電晶體。該第一電晶體Ml的閘極電連接該第一輸 096104986 表單編號A0101 第12頁/共28頁 1003447516-0 1358698 入端VINl，其源極電連接該高電 連接該公共節點P。 100年.12月0乏日核正脊換頁 平輸入端VH，其汲極電 [0023] [0024] [0025] ’ 路32包括-第二電晶體M2、一第三電晶體及 一第四電晶魏，該第二、第三、第四電晶體H M4均係麵S型電晶體。該第二電編2的閘極電連接該 第二輸入端VIN2 ’其源極電連接該公共節點P，其没極電 連接該第三電晶細的源極。該第三電晶體_間極電 連接該第四電晶魏的源極，纽極電連接該低電平輸 入端VL。該第四電晶體M4的閘極電連接該公共節點p，其 汲極電連接該反相時鐘訊號輸入端TSB。 該第一輸出電路33包括一第五電晶體M5,該第五電晶體 M5係_S型電晶體。該第五電晶體M5的閘極電連接該公 共節點p ’其源極電連接該時鐘訊號輸人端ts，其汲極電 連接該緩衝器35。 該第二輸出電路34包括一第六電晶細，該卜電曰體 M__S型電晶體。該第六電晶體㈣的閉極電連接:反 相時鐘訊號輸人端TSB ’其源極電連接該緩衝器， 電連接該低電平輸入端VL。 八4 [0026] 請一併參閱圖5，其係圖3中移位暫存 。用η表示某一級移位暫存單元2〇〇， 示。 器20之時序示意圖 則其前—級用η-1表 [0027] 在Τ1時間内，對於第η級移位暫存單开9ηη & 仔早兀200，第—輸入端 VIN1接收第η-1級輸出訊號V01為高雷半，目^ 兄丁 第一電晶體 Μ1導通，該公共節點Ρ被上拉為高電平。 卞忒第二輪入端 096104986 表單编號Α0101 第13頁/共28頁 1003447516-0 1358698 _:_ 100年12月咗日梭正替換頁 VIN2接收第n-1級反相輸出訊號专^·為低電平，則該第 二電晶體M2截止。因該公共節點P為高電平，則第五電晶 體M5導通。此時該反相時鐘訊號為南電平，則第六電晶 體M6導通。此時該時鐘訊號CK為低電平，故該緩衝器35 接收到的訊號為低電平，該輸出端V0UT的輸出訊號V02為 低·電平。 · [0028] 在T2時間内’對於第^級移位暫存單元200，第一輸入端 VIN1接收第n-1級輸出訊號V01為低電平，則第一電晶體 Ml截止，該公共節點p繼續保持為高電平。第二輸入端 VIN2接收第n-1級反相輸出訊號.胃p為高電平，則該第 二電晶體M2導通。因該公共節點p為高電平，則第五電晶 體M5導通。因該公共節點p為高電平，則第四電晶體M4導 通，反相時鐘訊號CKB通過該第四電晶體M4控制該第三電 晶體M3，此時該反相時鐘訊號CKB為低電平，則第三電晶 體M3截止，該第六電晶體M6也截止《時鐘訊號CK分別通 過該第五電晶體Μ 5輪入至該緩衝器3 5，此時該時鐘訊號 CK為高電平’故輸出端VOUT的輸出訊號V02為高電平。 [0029] 在Τ3時間内，對於第η級移位暫存單元200，第一輸入端 VIN1接收第n-1級輸出訊號V01為低電平，則第一電晶體 Ml截止，該公共節點P繼續保持為高電平。第二輸入端 VIN2接收第η-I級反相輸出訊號為高電平，則該第 二電晶體M2導通。因該公共節點P為高電平，則第四電晶 體M4導通，反相時鐘訊號CKB通過該第四電晶體M4控制該 第三電晶體M3 ’此時該反相時鐘訊號CKB為高電平，則第 096104986 表單编號A0101 第14頁/共28頁 1003447516-0 1358.698 [0030] [0031] [0032] 100年.12月02日修正眷換頁 三電晶體M3導通，公共節點p被下拉為低電平，則第五電 晶體M5截止。因爲此時該反相時鐘訊號CKB為高電平，則 第六電晶體M6導通，低電平訊號通過該第六電晶體M6輪 入至該緩衝器35，故輸出端ν〇ϋΤ的輸出訊號v〇2為低電 平。 在T4時間内，對於第η級移位暫存單元200，第一輸入端 VIN1接收第η_1級輸出訊號V01為低電平，則第_一電晶體 Μ1截止，該公共節點P繼續保持為低電平，則第四電晶體 Μ4截止、第五電晶體Μ5截止。此時該反相時鐘訊號ckb為 低電平，則第六電晶體Μ6截止’故輪出端ν〇υτ的輸出訊 號V02保持為低電平。 與先前技術相比，本發明移位暫存器20的每一移位暫存 單元200由六顆電晶體構成，且沒有複雜的繞線’故該移 位暫存器20的電路結構簡單，從而可避免不必要雜訊干 擾發生。同時，因電晶體數量較少，在生産中的錯誤機 率也相應較低，從而可以提高產品的良率。 每-移位暫存單元200的反相器36也可用一反相電路代替 〇 [0033] 該移位暫存器2()可用於液晶顯示裝置以 產品中。請參關6,其係—採用上述移位暫存器之^ 顯不裝置之結構示意圖。該液晶顯示裝置2包括一液晶顯 ^面板21、-資料驅動電路22及—掃#驅動電物，該 資料驅動電路22及該掃描驅動電路23分別藉由複數數據X 線與複數掃描線與該液晶顯示面板21連接。該液晶顯示 096104986 表單編號Α0101 第15頁/共28頁 1003447516-0 1358698 1 anm ι ? b n? η 由 vv ι r\ 面板21包括一上基板（圖未示）、一下基板（圖未示）及一 夾持於上基板與下基板間之液晶層（圖未示），且於該下 基板鄰近液晶層一側設置有一用於控制液晶分子扭轉狀 態之薄膜電晶體陣列（圖未示）。該資料驅動電路22及該 掃描驅動電路23分別包括一上述移位暫存器20。該掃描 驅動電路23在該移位暫存器20的控制下依序輸出高電平 訊號至該複數掃描線，以逐列控制該薄膜電晶體矩陣之 導通與關斷狀態。該資料驅動電路22依序輸出資料訊號 至該液晶顯示面板21，以控制其顯示畫面變化。該掃描 驅動電路23及該資料驅動電路22皆利用該移位暫存器20 控制掃描訊號與資料訊號之輸出時序，從而實現晝面顯 示。 [0034] 由於該移位暫存器20的電路結構較簡單，因此可避免不 必要雜訊干擾發生。使用該移位暫存器20之掃描驅動電 路23及資料驅動電路22在進行行掃描或列掃描時，其各 輸出訊號間亦不會產生訊號干擾，從而提高了該液晶顯 示裝置2的顯示效果。 [0035] 綜上所述，本創作確已符合發明專利之要件，爰依法提 出申請專利。惟，以上所述者僅係本發明之較佳實施方 .式，本發明之範圍並不以上述實施方式爲限，舉凡熟習 本案技藝之人士援依本發明之精神所作之等效修飾或變 化，皆應涵蓋於以下申請專利範圍内。 【圖式簡單說明】 [0036] 圖1係一種先前技術移位暫存單元之電路示意圖。 [0037] 圖2係圖1中移位暫存單元所在移位暫存器之時序示意圖 096104986 表單编號 A0101 ' 第 16 頁/共 28 頁 1003447516-0 1358698 100年.12月02日梭正替換頁 [0038] 圖3係本發明移位暫存器較佳實施方式之結構示意圖。 [0039] 圖4係圖3之移位暫存單元之電路示意圖。 [0040] 圖5係圖1中移位暫存器之時序示意圖。 [0041] 圖6係本發明液晶顯示裝置較佳實施方式之結構示意圖。 【主要元件符號說明】 [0042] 液晶顯示裝置：2 [0043] 移位暫存器：20 [0044] 液晶顯示面板：21 [0045] 資料驅動電路：22 [0046] 掃描驅動電路：23 [0047] 上拉電路：31 [0048] 下拉電路：32 [0049] 第一輸出電路：33 [0050] 第二輸出電路：34 [0051] 緩衝器：35 [0052] 反相器：36 [0053] 移位暫存單元：200 096104986 表單編號A0101 第17頁/共28頁 1003447516-0The commutation circuit 120 includes a fifth transistor Μ5, a sixth transistor Μ6, and a signal output terminal V0. The gate of the fifth transistor Μ5 is connected to the first output terminal V01, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the sixth transistor Μ6. The gate of the sixth transistor Μ6 is connected to the second output terminal V02, and the drain thereof receives the low level signal VSS from the external circuit, and the source thereof is the signal output terminal V0 of the shift register unit 100. The second clocked inverter circuit 130 includes a seventh transistor Μ7, an eighth transistor Μ8, a ninth transistor Μ9, and a tenth transistor Μ10. The gate of the seventh transistor Μ7 is connected to the signal output terminal V0, the source thereof receives the high level signal VDD from the external circuit, and the drain thereof is connected to the source of the eighth transistor Μ8. The gate of the eighth transistor 汲8 and its drain receive a low level signal VSS from an external circuit. The source of the ninth transistor Μ9 is connected to the first output terminal V01, the gate thereof receives the clock signal CK from the external circuit, and the drain thereof is connected to the drain of the seventh transistor Μ7. The gate of the tenth transistor receives the clock signal CK of the external circuit, and the source thereof is connected to 096104986. Form number Α0101 Page 5/28 pages 1003447516-0 1358698 [0008] December 02, 100, the replacement page The second output terminal V02 has its drain connected to the signal output terminal VO. Please refer to FIG. 2 together, which is a working sequence diagram of the shift register unit 100. During the time T1, the output signal VS of the previous shift register unit is changed from a high level to a low level, and the inverted clock signal ^ is changed from a low level to a high level to make the third power The crystal M3 and the fourth transistor M4 are turned off, and the first clock inverting circuit 110 is turned off. The clock signal CK is changed from a high level to a low level, so that the ninth transistor M9 and the tenth transistor M10 are turned on, thereby turning on the second clock inverting circuit 130, and the signal output terminal VO The south level of the initial state is turned off by the tenth transistor M10 ′, and the low level of the output of the eighth transistor M8 is passed through the ninth transistor M9 to make the fifth transistor M5 After being turned on, the source high level signal VDD is output to the signal output terminal VO, so the signal output terminal VO maintains a high level output. [0009] During the T2 time, the inverted clock signal gg is changed from a high level to a low level, and the third transistor M3 and the fourth transistor M4 are turned on, thereby inverting the first clock. Circuit 110 is turned on. When the clock signal CK is changed from a low level to a high level, the ninth transistor M9 and the tenth transistor M10 are turned off, and the second clocked inverter circuit 130 is turned off. When the input signal VS is changed from a high level to a low level, the first transistor Μ1 is turned on, and the high level VDD of the source is turned off by the third transistor M3 to the fifth transistor Μ5, and the The low level of the input signal VS is turned on by the fourth transistor Μ4 to turn on the sixth transistor Μ6, so that the signal output terminal VO outputs a low level. [0010] During the Τ3 time, the inverted clock signal ck is changed from a low level to a power 096104986 Form No. 1010101 Page 6 / Total 28 Page 1003447516-0 1358, 698 .100. December 0 When the shuttle is replacing the page level, the third transistor M3 and the fourth transistor M4 are turned off, and the first clocked inverter circuit 110 is turned off. The clock signal CK is changed from a high level to a low level, and the ninth transistor M9 and the tenth transistor M10 are turned on, thereby turning on the second clock inverting circuit 130. The low level of the signal output terminal V0 turns on the seventh transistor M7, and the high level of the source thereof is turned off by the ninth transistor M9 to the fifth transistor M5. At the same time, the low level of the signal output terminal V0 is also turned on by the tenth transistor M10 to turn on the sixth transistor M6, and the drain level of the sixth transistor M6 keeps the signal output terminal V0 low. Output. [0011] In the T4 time, the inverted clock signal changes from a level to a low level, and the third transistor M3 and the fourth transistor M4 are turned on, thereby inverting the first clock. Circuit 110 is turned on. The clock signal CK is changed from a low level to a high level to turn off the ninth transistor M9 and the tenth transistor M10, thereby turning off the second clock inverting circuit 120. The surface level of the input signal VS is turned off by the fourth transistor M4, and the second low level of the second transistor M2 is turned on by the third transistor M3. The high level of the source is output to the signal output terminal V0, so that the output of the signal output terminal V0 is changed from a low level to a high level. [0012] The shift register unit 100 of the shift register has a large number of transistors, and the winding of each signal trace is complicated, so the circuit structure of the shift register is complicated. [0013] In addition, the shift register can be applied to liquid crystal display devices and other digital electronic products. For example, the data driving circuit or the scanning driving circuit of the liquid crystal display device needs to perform the shifting of the column scanning or the line scanning function 096104986 Form No. A0101 Page 7 / Total 28 Page 1003447516-0 1358698 Revised December 02, 100 Change page can. However, the circuit structure of the shift register is relatively complicated, and noise interference is likely to occur. Therefore, when the liquid crystal display device using the shift register as the data driving circuit and the scan driving circuit performs column scanning or line scanning, each Signals are also easy to interfere with each other. SUMMARY OF THE INVENTION [0014] In view of the above, it is necessary to provide a shift register having a simple circuit structure. [0015] In addition, it is also necessary to provide a liquid crystal display device capable of avoiding signal interference. [0016] A shift register includes a plurality of shift register units, each of which is subjected to an external circuit. The clock signal, the inverted clock signal, the output signal of the previous stage shift register unit, and the inverted output signal control of the previous stage shift register unit. Each shift register unit includes a clock signal input terminal, an inverted clock signal input terminal, a high level input terminal, a low level input terminal, a first input terminal, a second input terminal, and an output. a terminal, an inverting output terminal, a pull-up circuit, a pull-down circuit, a first output circuit, a second output circuit and an inverting circuit, wherein the clock signal input end receives a clock signal of the external circuit, and the inverted clock The signal input end receives an inverted clock signal of the external circuit, and the high level input end receives a high level signal of the external circuit, and the low level input end receives a low level signal of the external circuit, and the first input end is electrically connected to the An output end of the previous stage shift register unit, the second input end is electrically connected to an inverting output end of the shift register unit of the previous stage, and the output end is electrically connected to the first input end of the shift register unit of the second stage The inverting output terminal is electrically connected to the second input end of the rear stage shift register unit, the pull-up circuit, the pull-down circuit, and the 096104986 form number A0101 page 8 / 28 pages 1003447516-0 1358698 • 100 'Year.1 On February 2:00, the modified page-changing output circuit has a common node, and the pull-up circuit is controlled by the first input terminal. The pull-down circuit is controlled by the second input terminal and the common node. The common node provides a high level signal, and the pull down circuit provides a low level signal to the common node. The first output circuit outputs a clock signal under the control of the common node, and the second output circuit outputs a low level signal under the control of the inverted clock signal, and the inverter circuit outputs the output of the first or second output circuit After the signal is inverted, the pull-down circuit includes a second transistor, a third transistor, and a fourth transistor. The gate of the second transistor is electrically connected to the second input terminal, and the source thereof. The pole is electrically connected to the common node, and the drain is electrically connected to the source of the third transistor, and the gate of the third transistor is electrically connected to the source of the fourth transistor, and the pole is electrically connected to the low level input The gate of the fourth transistor is electrically connected to the common node, and the drain electrode is electrically connected to the inverted clock signal input terminal. [0017] A liquid crystal display device includes a liquid crystal display panel, a data driving circuit and a a scan driving circuit, the data driving circuit provides a data signal for the liquid crystal display panel, the scan driving circuit provides a scanning signal for the liquid crystal display panel, and the data driving circuit and the scan driving circuit respectively include - The shift register is used to control the output timing of the data signal and the scan signal. The shift temporary storage comprises a plurality of shift temporary storage units, each shift registering a single-bit external circuit clock signal, an inverted clock signal, a pre-stage shift register unit output signal and a pre-stage shift Inverting output rotation control of the temporary storage unit, each shift register unit includes a clock signal input end, an inverted clock signal input end, a high level input end, a low level input end, and a first input End, a second input, an output 096104986 Form No. A0101 Page 9 / Total 28 Page 1003447516-0 1358698 Correction of the replacement page end, an inverting output, a pull-up circuit, a pull a circuit, a first output circuit, a second output circuit, and an inverting circuit. The clock signal input end receives a clock signal of an external circuit, and the inverted clock signal input end receives an inverted clock signal of an external circuit, and the high level input end receives a high level signal of an external circuit, and the low level input end receives the signal a low level signal of the external circuit, the first input end is electrically connected to the output end of the previous stage shift register unit, and the second input end is electrically connected to the inverting output end of the previous stage shift register unit, the output The terminal is electrically connected to the first input end of the rear stage shift register unit, and the inverted output end is electrically connected to the second input end of the rear stage shift register unit. The pull-up circuit, the pull-down circuit and the first output circuit have a common node, and the pull-up circuit is controlled by the first input terminal, and the pull-down circuit is controlled by the second input terminal and the common node, and the pull-up circuit Providing a high level signal for the common node, the pull-down circuit provides a low level signal to the common node, the first output circuit outputs a clock signal under the control of the common node, and the second output circuit is in the inverted clock signal Outputting a low level signal, the inverting circuit inverting an output signal of the first or second output circuit, wherein the pull down circuit comprises a second transistor, a third transistor and a fourth a transistor, the gate of the second transistor is electrically connected to the second input end, the source of the second transistor is electrically connected to the common node, the drain of the second transistor is electrically connected to the source of the third transistor, and the gate of the third transistor Electrically connecting the source of the fourth transistor, the drain of the fourth transistor is electrically connected to the low-level input terminal, the gate of the fourth transistor is electrically connected to the common node, and the drain of the fourth transistor is electrically connected to the inverted clock signal input terminal. [0018] Compared with the prior art, each shift register of the shift register of the present invention is 096104986 Form No. A0101 Page 10 / Total 28 Page 1003447516-0 1358698 100. December Date Correction Replacement Page Element by Six Electric The crystal is formed without complicated winding, so the circuit structure of the shift register is simple, so that unnecessary noise interference can be avoided. At the same time, due to the small number of transistors, the probability of error in production is also relatively low, which can improve the yield of the product. [0019] Since the circuit structure of the shift register is relatively simple, it is possible to avoid unnecessary noise interference. When the scan driving circuit and the data driving circuit of the shift register are used for row scanning or column scanning, signal interference is not generated between the output signals, thereby improving the display effect of the liquid crystal display device. [Embodiment] [0020] Please refer to FIG. 3, which is a schematic structural diagram of a preferred embodiment of a shift register of the present invention. The shift register 20 includes a shift register unit 2G0 having the same complex structure, and the plurality of shift register units 200 are sequentially connected in series. Each shift register unit 200 includes a clock signal input terminal TS, an inverted clock signal input terminal TSB, a first input terminal VIN1, a second input terminal VIN2, an output terminal V0UT, and an inverting output terminal V0UTB. A high level input terminal VH and a low level input terminal VL. The clock signal input terminal TS of each shift register unit 200 receives the clock input signal CK of an external circuit (not shown), and the inverted clock signal input terminal TSB receives the inverted clock input signal of an external circuit (not shown). CKB, its high-level input terminal VH receives the high-level signal VDD of an external circuit (not shown), and its low-level input terminal VL receives the low-level signal VSS of an external circuit (not shown). The first input terminal VIN1 is electrically connected to the output terminal VOUT of the previous stage shift register unit 200, and the second input terminal VIN2 is electrically connected to the inverting output terminal V0UTB of the previous stage shift register unit 200, and its output terminal V0UT箪Connected to the next stage shift register unit 200 096104986 Form No. A0101 Page 11 / Total 28 Page 1003447516-0 1358698 On December 2, 100, the first input terminal VIN1 of the replacement page is connected, and the inverting output terminal VOUTB is electrically connected. The second round-in terminal VIN2 of the temporary storage unit 200 is shifted to the next stage. That is, the output signal of the previous stage shift temporary storage unit 200 is the first input signal of the post-stage shift temporary storage unit 2, and the inverted output signal of the previous stage shift temporary storage unit 2 is the latter stage shift. The second input signal of the temporary storage unit 200, and each shift temporary storage unit 200 is simultaneously controlled by the external circuit clock signal CK, the inverted clock signal CKB, the 鬲 level signal vdd and the low level signal vSS. [0〇21] Referring to FIG. 4, it is a circuit diagram of the shift register unit of FIG. The shift register unit 200 includes a pull-up circuit 31'-down pull circuit 32, a first output circuit 33, a second output circuit 34, a buffer 35, and an inverter 36. The two inverters are connected in series, and are mainly used to maintain the output waveform of the shift register unit 2 to avoid distortion of the output waveform. The pull-up circuit 31, the pull-down circuit 32, and the first output circuit 33 have a common node P'. The pull-up circuit 31 provides a high-level signal to the common node p. The pull-down circuit 32 provides low power to the common node p. Ping signal. The pull-up circuit 31 is controlled by the first input terminal viN1, and the pull-down circuit 32 is controlled by the second input terminal VIN2 and the common node P. The first output circuit 33 outputs a clock signal CK under the control of the common node P. Up to the buffer 35', the second output circuit 34 outputs a low level signal VSS to the buffer under the control of the inverted clock signal CKB, and the buffer transmits the received clock signal CK or low level signal vss. To the output νουτ. The inverter 36 inverts the signal of the output terminal VOUT and inputs it to the inverting output terminal V0UTB. [0022] The pull-up circuit 31 includes a first transistor M1, which is an NM0S type transistor. The gate of the first transistor M1 is electrically connected to the first input 096104986, Form No. A0101, Page 12 of 28, 1003447516-0 1358698, the input terminal VIN1, the source of which is electrically connected to the common node P. 100 years. December 0 days of zero-day nuclear ridge-changing flat input terminal VH, its 汲 pole electric [0023] [0024] [0032] Road 32 includes - second transistor M2, a third transistor and a fourth The second crystal, the third and the fourth transistor H M4 are both S-type transistors. The gate of the second circuit 2 is electrically connected to the second input terminal VIN2', and its source is electrically connected to the common node P, which is not electrically connected to the source of the third transistor. The third transistor _ is electrically connected to the source of the fourth transistor, and the button is electrically connected to the low level input terminal VL. The gate of the fourth transistor M4 is electrically connected to the common node p, and the drain is electrically connected to the inverted clock signal input terminal TSB. The first output circuit 33 includes a fifth transistor M5, which is an _S type transistor. The gate of the fifth transistor M5 is electrically connected to the common node p', and its source is electrically connected to the clock signal input terminal ts, and its drain is electrically connected to the buffer 35. The second output circuit 34 includes a sixth transistor, which is a M__S type transistor. The closed-pole electrical connection of the sixth transistor (4): the inverting clock signal input terminal TSB' has its source electrically connected to the buffer, and is electrically connected to the low-level input terminal VL. 8 4 [0026] Please refer to FIG. 5 together, which is the shift temporary storage in FIG. Use η to indicate a certain level of shift register unit 2, shown. The timing diagram of the device 20 is as follows: η-1 table [0027] In the Τ1 time, for the n-th stage shift temporary storage single open 9ηη & 早早兀200, the first input terminal VIN1 receives the n-1 The level output signal V01 is a high-definition half, and the first transistor Μ1 is turned on, and the common node 上 is pulled up to a high level.卞忒Second round entry 096104986 Form number Α0101 Page 13/28 page 1003447516-0 1358698 _:_ December 100 咗 梭 替换 replacement page VIN2 receives the n-1th stage inverting output signal ^· When it is low, the second transistor M2 is turned off. Since the common node P is at a high level, the fifth transistor M5 is turned on. At this time, the inverted clock signal is at the south level, and the sixth transistor M6 is turned on. At this time, the clock signal CK is low, so the signal received by the buffer 35 is low level, and the output signal V02 of the output terminal VOUT is low level. [0028] In the T2 time, for the first stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be low level, then the first transistor M1 is turned off, the common node p continues to remain high. The second input terminal VIN2 receives the n-1th stage inverted output signal. When the stomach p is at a high level, the second transistor M2 is turned on. Since the common node p is at a high level, the fifth transistor M5 is turned on. Because the common node p is at a high level, the fourth transistor M4 is turned on, and the inverted clock signal CKB controls the third transistor M3 through the fourth transistor M4, and the inverted clock signal CKB is at a low level. The third transistor M3 is turned off, and the sixth transistor M6 is also turned off. "The clock signal CK is respectively polled into the buffer 35 through the fifth transistor , 5, and the clock signal CK is at a high level." Therefore, the output signal V02 of the output terminal VOUT is at a high level. [0029] In the Τ3 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n-1th stage output signal V01 to be low level, then the first transistor M1 is turned off, the common node P Continue to stay high. The second input terminal VIN2 receives the n-th phase inverting output signal to be high level, and the second transistor M2 is turned on. Because the common node P is at a high level, the fourth transistor M4 is turned on, and the inverted clock signal CKB controls the third transistor M3 through the fourth transistor M4. At this time, the inverted clock signal CKB is at a high level. , 096104986 Form No. A0101 Page 14 / Total 28 Page 1003447516-0 1358.698 [0031] [0032] 100 years. December 02 revision 眷 page change three transistor M3 is turned on, the common node p is pulled down When the level is low, the fifth transistor M5 is turned off. Because the inverted clock signal CKB is at a high level, the sixth transistor M6 is turned on, and the low level signal is turned into the buffer 35 through the sixth transistor M6, so the output signal of the output terminal ν〇ϋΤ V〇2 is low. During the T4 time, for the nth stage shift register unit 200, the first input terminal VIN1 receives the n_1th stage output signal V01 to be low level, then the first transistor Μ1 is turned off, and the common node P continues to remain low. At the level, the fourth transistor Μ4 is turned off and the fifth transistor Μ5 is turned off. At this time, the inverted clock signal ckb is at a low level, and the sixth transistor Μ6 is turned off, so that the output signal V02 of the round-trip terminal ν〇υτ is kept at a low level. Compared with the prior art, each shift register unit 200 of the shift register 20 of the present invention is composed of six transistors, and has no complicated windings. Therefore, the circuit structure of the shift register 20 is simple. This avoids unnecessary noise interference. At the same time, due to the small number of transistors, the probability of error in production is also relatively low, which can improve the yield of the product. The inverter 36 of each shift register unit 200 can also be replaced by an inverter circuit. [0033] The shift register 2 () can be used in a liquid crystal display device. Please refer to section 6, which is a schematic diagram of the structure of the display device using the above shift register. The liquid crystal display device 2 includes a liquid crystal display panel 21, a data driving circuit 22, and a scan driving device. The data driving circuit 22 and the scan driving circuit 23 respectively use a plurality of data X lines and a plurality of scanning lines. The liquid crystal display panel 21 is connected. The liquid crystal display 096104986 Form No. 101 0101 Page 15 / Total 28 Page 1003447516-0 1358698 1 anm ι ? bn? η by vv ι r\ Panel 21 includes an upper substrate (not shown), a lower substrate (not shown) and A liquid crystal layer (not shown) is sandwiched between the upper substrate and the lower substrate, and a thin film transistor array (not shown) for controlling the twist state of the liquid crystal molecules is disposed on a side of the lower substrate adjacent to the liquid crystal layer. The data driving circuit 22 and the scan driving circuit 23 respectively include a shift register 20 as described above. The scan driving circuit 23 sequentially outputs a high level signal to the complex scan line under the control of the shift register 20 to control the on and off states of the thin film transistor matrix column by column. The data driving circuit 22 sequentially outputs data signals to the liquid crystal display panel 21 to control display screen changes. The scan driving circuit 23 and the data driving circuit 22 use the shift register 20 to control the output timing of the scanning signal and the data signal, thereby realizing the display. [0034] Since the circuit structure of the shift register 20 is relatively simple, unnecessary noise interference can be avoided. When the scan driving circuit 23 and the data driving circuit 22 of the shift register 20 are used for row scanning or column scanning, signal interference is not generated between the output signals, thereby improving the display effect of the liquid crystal display device 2. . [0035] In summary, the creation has indeed met the requirements of the invention patent, and the patent application is filed according to law. However, the above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and those skilled in the art will be able to make equivalent modifications or variations in accordance with the spirit of the present invention. All should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0036] FIG. 1 is a circuit diagram of a prior art shift register unit. 2 is a timing diagram of a shift register in which the shift register unit of FIG. 1 is located. 096104986 Form No. A0101 'Page 16 of 28 1003447516-0 1358698 100. December 02 [0038] FIG. 3 is a schematic structural view of a preferred embodiment of a shift register of the present invention. 4 is a circuit diagram of the shift register unit of FIG. 3. 5 is a timing diagram of the shift register of FIG. 1. 6 is a schematic structural view of a preferred embodiment of a liquid crystal display device of the present invention. [Main component symbol description] [0042] Liquid crystal display device: 2 [0043] Shift register: 20 [0044] Liquid crystal display panel: 21 [0045] Data drive circuit: 22 [0046] Scan drive circuit: 23 [0047] Pull-up circuit: 31 [0048] Pull-down circuit: 32 [0049] First output circuit: 33 [0050] Second output circuit: 34 [0051] Buffer: 35 [0052] Inverter: 36 [0053] Shift Bit buffer unit: 200 096104986 Form number A0101 Page 17 / Total 28 pages 1003447516-0