TWI357142B - Inverted leadframe on substrate - Google Patents

Description

IX. INSTRUCTIONS OF THE INVENTION: TECHNICAL FIELD The present invention relates to a semiconductor package and a method of fabricating a semiconductor package having a plurality of dies, wherein one die is attached to one inverted lead frame and the other die is attached To a substrate. The lead frame is then attached to the substrate. The present application claims the benefit of U.S. Provisional Application Serial No. 60/871,509, the entire disclosure of which is incorporated herein by reference. [Prior Art] Based on current packaging trends, a stacked die package typically includes a plurality of packages packaged in a vertical stack. The conventional method of assembling the stacked die package involves placing a smaller die. The top of the larger die is (four) formed into a pyramid structure such that each die does not land on the periphery of the die immediately below it, where the placement wires are joined. It is necessary to use a die stack, w 'call, W, ie, 耵 (l·j) and - a larger die (for example, a dedicated integrated circuit (Asic) die), and the smaller crystal A problem arises when the grain has a conductor or resistance limit. In such packages, it is preferred to connect the RF die to a substrate. Wire bonding should be kept as short as possible. However, conventional die stacking method 2 requires smaller RF die stacking in larger ASI (: grain

The grain is relative to the top of the ASICH.卩上. Therefore, the RF, in the ASICa day, will have a longer line junction away from the substrate. Forming a stacked die seals and dressing seals # & Zhuang + . Nai Ling T is time consuming because of the need for continuous real, ^, the process steps involved in the installation. Figure just shows - used for planting. A conventional method of semiconductor packaging at 127888.doc 1357142

In step ci, the first die (i.e., ASIC grain) is attached to a substrate using a die attach epoxy. Next, in step C2f, the _th grain line is bonded to the substrate. Then, in step C3, the second die (i.e., RF die) is attached to the first die using a die attach epoxy. Next, a second die line is bonded to the substrate in step C4. Then, in step C5, the substrate and the warp-bonded crystal grains are molded. After molding, the solder balls are attached to the semiconductor package in step C6. The package is singulated in step 〇. As mentioned above, conventional methods involve process steps that occur in sequential order. Therefore, there is a need to improve such processes to enable certain steps to be performed simultaneously so that manufacturing time can be reduced. SUMMARY OF THE INVENTION Exemplary embodiments of the present invention overcome the above disadvantages and other disadvantages of the above. Also, the present invention is not necessarily required to overcome the disadvantages described above, and the exemplary embodiments of the present invention may not overcome any of the above problems.

A semiconductor package according to an embodiment of the invention includes: a substrate having a top surface and a bottom surface; a lead frame having a top die pad surface, a bottom die pad surface, and a plurality of wires Wherein the lead frame is attached to a top surface of the substrate; a first die having a top surface and a bottom surface 'where the bottom surface is attached to a top surface of the substrate and the first die is electrically connected to a second die having a top surface and a bottom surface 'where the top surface is attached to the bottom die pad surface of the lead frame and the second die is electrically connected to the lead frame; An encapsulant covering at least a portion of the leadframe and the substrate. The semiconductor package can also include a third die having a top surface and a bottom surface, the bottom surface being attached to a top surface of the substrate and the third crystal grain being electrically connected to the substrate. The semiconductor package can also include a fourth die having a top surface and a bottom surface, wherein the top surface is attached to a top and bottom surface of the second die and the fourth die is electrically connected to the leadframe. The semiconductor package also includes a third die having a top surface and a bottom surface, wherein the bottom surface is attached to a top surface of the first die and the second die is electrically connected to the substrate. The semiconductor package may further include a fourth germanium having a top surface and a bottom surface, the top surface being attached to the bottom surface of the second die and the fourth die electrically connected to the lead frame . The semiconductor package may further include: a third die having a top surface and a bottom surface 'where the top surface is attached to a bottom surface of the second die; and a plurality of bonding wires 'connected to the third The bottom surface of the die is between the wire on the leadframe. The semiconductor package also includes a masking agent covering the entire top die fill surface of the leadframe. The semiconductor package can also include an entire top die pad surface that allows the encapsulant to cover the leadframe except for a plurality of regions. The #semiconductor n package can also include a second semiconductor package connected to the leadframe via the plurality of regions. The semiconductor package may also include a surface of the top lining of the lead frame having a region of the lining, and the encapsulant covering the etched region without covering the surface of the top die pad. 127888.doc 1357142 - A semiconductor package according to a second embodiment of the present invention includes: a lead frame having a top grain pad surface, a bottom grain surface, and a plurality of wires, a substrate Having a top surface '_ bottom surface and a cavity, wherein the lead frame is attached to a top surface of the substrate; a first die having a top surface and a bottom surface, wherein the bottom surface is attached to An empty space and a cavity of the substrate are electrically connected to the substrate; a second die having a top surface and a bottom surface, wherein the top surface is attached to the bottom crystal of the lead frame a surface of the crucible and the second die electrically connected to the lead frame; an encapsulant covering at least a portion of the lead frame and the substrate. The semiconductor package according to the second embodiment of the present invention may further comprise a top surface and a third die of a bottom surface, wherein the The bottom surface is attached to the cavity of the substrate and the third die is electrically connected to the substrate. The semiconductor package according to the second embodiment of the present invention may further comprise a fourth die having a top surface and a bottom surface The top surface is attached to the bottom surface of the second die and the fourth die is electrically connected to the lead frame. The semiconductor package according to the second embodiment of the present invention may further comprise a top surface and a third die of a bottom surface, wherein the bottom surface is attached to a top surface of the first die and the third die is electrically connected to the substrate. The semiconductor package according to the second embodiment of the present invention may also include a fourth die having a top surface and a bottom surface, wherein the top surface is attached to a bottom surface of the second die and the fourth die is electrically connected to the lead frame. According to the second aspect of the present invention The semiconductor package of an embodiment may further include a third die having a top surface and a bottom surface, wherein the top surface is attached to a bottom surface of the second die and the third die is electrically connected to the lead frame 127888.doc -10- 1357142 according to the invention The second embodiment of the present invention may also include an encapsulating agent covering the entire top die pad surface of the lead frame. The semiconductor package according to the second embodiment of the present invention may also comprise an encapsulation The coating covers the entire top grain lining surface of the lead frame except for a plurality of regions. The semiconductor package according to the second embodiment of the present invention may further include a second semiconductor connected to the lead frame via the plurality of regions Package: The semiconductor package according to the second embodiment of the present invention may further comprise: the top die padding surface of the wire = containing the half (four) area of the encapsulant covering the half-cut area without covering A portion of the surface of the top die pad. A method of fabricating a semiconductor package in accordance with an embodiment of the present invention includes (a) providing a substrate having a top surface and a bottom surface; b) providing a top a die pad surface, a bottom die pad surface, and a plurality of wire lead frames; (C) attaching a first die having a top surface and a bottom surface to the substrate, wherein the first crystal Bottom surface of the grain Connecting to a top surface of the substrate and electrically connecting the first die to the substrate; (d) attaching a second die having a top surface and a bottom surface to the lead frame, wherein the second die a top surface attached to a bottom die pad surface of the leadframe and the second die electrically connected to the leadframe; (e) attaching the leadframe to a top surface of the substrate; and (f) a bladder至少 at least a portion of the lead frame and the substrate. The method of fabricating the semiconductor package can also include attaching solder balls to the substrate and singulating the semiconductor packages into individual semiconductor packages. The method of fabricating the semiconductor package may also include the steps ((^ and (d) occurring simultaneously. A method of fabricating a plurality of semiconductor packages I27888.doc-II-1357142 according to a second embodiment of the present invention may include (a) providing a substrate strip having a top surface and a bottom surface, b) providing a lead frame strip having a top die pad surface, a bottom die pad surface, and a plurality of lead edges; a plurality of first dies having a top surface and a bottom surface attached to the substrate strip, wherein bottom surfaces of the first dies are attached to a top surface of the substrate strip and the first dies are electrically connected to the a substrate strip; (d) attaching a plurality of second dies having a top surface and a bottom surface to the lead frame, wherein a top surface of the second dies is attached to a bottom die pad of the lead frame strip And the second die is electrically connected to the leadframe strip; (e) attaching the leadframe strip to a top surface of the substrate strip; and (1) encapsulating the leadframe strip and at least a portion of the substrate strip. The second method of the semiconductor package can also include attaching a solder ball to the substrate And singulating the semiconductor packages into individual semiconductor packages. The second method of fabricating the semiconductor package may also include the step (4) occurring simultaneously. [Embodiment] The present invention will be explained in detail below by way of example embodiments with reference to the drawings. The exemplified embodiments are intended to be illustrative of the invention and are not intended to limit the scope of the invention in any way. In all the drawings for explaining the exemplary embodiments, the components having the same function carry the same The reference package will omit repeated explanation of the components. The semiconductor package of the present invention comprises an inverted frame attached to a substrate. Each of the inverted lead frame and the substrate holds one or more dies, When the inverted lead frame is attached to the substrate, a - (four) domain is formed between the inverted lead frame (four) substrate and the substrate is on the wire frame and the substrate is 127888.doc 1357142 one or more crystal grains are facing each other The lead frame and the substrate are connected by solder existing on the substrate or the lead of the lead frame. The solder may be pre-printed onto the substrate or on the substrate The molding material encapsulating the leadframe and at least a portion of the substrate may also hold the two structures in place. Figures 2A and 2B show an example of an embodiment of the semiconductor package 1 of the present invention. The package includes: The substrate 100 has a top surface 1 & and a bottom surface 100b, a lead frame 200 having a die pad portion 201 and a plurality of wires 220; a first semiconductor die 3? It has a top surface 300a and a bottom surface 300b, wherein the bottom surface 3〇〇b is attached to the top surface 100a of the substrate 100; and a second semiconductor die 4〇〇 having a top surface 400a and a bottom surface 400b, wherein the top surface 4A is attached to the bottom die pad surface 201b of the leadframe 200. The package 1 can also include a third semiconductor die 5A having a top surface 500a and a bottom surface 500b, wherein the bottom surface 500b is attached to the top surface 3A of the first semiconductor die 3A. The lead frame 200 has a grain lining portion 2 〇 1, a first inclined portion 2 〇 2, an intermediate portion 203, a second inclined portion 204, and a bottom portion 205. The first inclined portion 202 abuts the die pad portion 201 to the intermediate portion 2〇3, and the second inclined portion 204 abuts the intermediate portion 203 to the bottom portion 205 to form a double unframed frame, as shown in FIGS. 2A and 2B. Shown. The grain lining portion 2〇1 has a top grain lining portion 201a and a bottom grain lining portion 2〇1b. The intermediate portion 203, the second inclined portion 204, and the bottom portion 205 form a guide wire of the lead frame 2''. It will be appreciated that although the leadframe illustrated in this embodiment has a double lower frame', it is also possible to use leadframes with more than two lower members. The first semiconductor die 300 is attached to the substrate 1 by means of an adhesive 7〇〇 with its bottom surface 300b facing the top surface 1 of the substrate 100 with 127888.doc • 13-1357142. The first semiconductor die 300 is electrically connected to the substrate 1 via a wire bond 310 extending from the top surface 3〇〇3 of the first semiconductor die 3〇〇 to the top surface 10a of the substrate 100. The second semiconductor die 400 is attached to the bottom die pad portion 201a of the lead frame 2 by an adhesive 700. The second semiconductor die 400 is electrically connected to the intermediate portion 203 of the lead frame 2 by a wire bond 410 extending from the bottom surface 400b of the second semiconductor wafer 400 to the intermediate portion 203 of the lead frame 200. The third semiconductor φ die 500 is attached to the top surface 300a of the first semiconductor die 300 by an adhesive 700. The wire bonding 5 1 电 electrically connects the third semiconductor die 5 〇 0 to the substrate 100. The solder ball 800 is attached to the bottom surface i〇〇b of the substrate 100. The lead frame 200 is encapsulated by the molding compound 900 in addition to the top grain lining surface 201a exposed to the outside. Since the top die pad surface 2〇la of the lead frame 200 is exposed to the outside, heat dissipation is enhanced. It should be understood that although in this embodiment wire bonding is illustrated as a means for forming an electrical connection between a die and its respective substrate or leadframe, other forms of electrical connections (eg, the overlay shown in Figure 5) Crystal connection) is also possible. In this particular embodiment, the largest of the three semiconductor dies 400 is attached to the leadframe 200. Since the two smaller semiconductor dies 300, 500 - are attached to the substrate 100 instead of the lead frame, compared to the case where the three dies 300, 400, 500 are stacked vertically in a conventional semiconductor package, The bond wires associated with the die 300, 500 can be shorter. Figure 1B is an enlarged view of an alternate embodiment of a corner portion 201c of a leadframe 200. In the embodiment of Fig. 1B, a notch 240 is etched (e.g., half etched) in the corner portion 201c of the leadframe 200. The notch 240 can be modified to engage the lead frame 200 and thus better secure the lead frame 2 to the substrate 100. It will be appreciated that although the notch 24 is etched at the corner portion 201c in this alternative embodiment, the notch 24 can be formed in any other portion of the wire guide 200 that facilitates engagement of the molding material 9〇〇 with it. Fig. 4 shows an example of a second embodiment of a semiconductor package 1 of the present invention. Elements having the same number are the same as those of the previous figures. In this embodiment, the substrate 1 has a cavity 11(). Another difference is that the first die 300 is attached to the bottom of the substrate cavity 11 by an adhesive 7〇〇. Fig. 5 shows an example of a third embodiment of a semiconductor package 1 of the present invention. Elements having the same number are the same as those of the previous figures. Similar to the second embodiment, this embodiment also has a cavity 110 in the substrate 1〇〇. Another difference is that the first die 3 is attached to the bottom of the substrate cavity 11 by solder bumps 320. Fig. 6 shows an example of a fourth embodiment of a semiconductor package 1 of the present invention. Elements having the same number are the same as those of the previous figures. This embodiment is similar to the first embodiment except that it has an additional semiconductor die 6 which is attached to the bottom surface 400b of the second semiconductor die 400 by an adhesive 7?. In addition, there is also a wire bond 61 〇〇 electrically connecting the fourth semiconductor die 6 〇〇 to the intermediate portion 203 of the lead frame 200. Fig. 7 shows an example of a fifth embodiment of a semiconductor package 1 of the present invention. Elements having the same number are the same as those of the previous figures. This embodiment is similar to the first embodiment except that only the first and second semiconductor dies 3A and 4〇〇 127888.doc •15-1357142 are shown. The additional semiconductor die can be a semiconductor package 1 〇 = part. In addition, the top die pad surface 201a of the lead frame 200 is not exposed to the outside, but the molding compound 900 completely covers the entire lead frame 2', and FIG. 8 shows a sixth implementation of the semiconductor package 1 of the present invention. An example of an example. The elements having the same number are the same as those of the previous figures. This embodiment is in addition to the second semiconductor die 500 being bonded to the substrate 100 by the adhesive 7〇〇 instead of the top surface of the first semiconductor die 300. It is similar to the first embodiment except for 30 〇a. 9A, 9B and 9C show an example of a seventh embodiment of a semiconductor package of the present invention. Components with the same number are the same as those in the previous figure

The same components. In this embodiment, the molding compound 9 encapsulates the entire top die pad surface 201a of the package leadframe 2 except for the plurality of regions 26 shown in the top view of Fig. 9A. Zone 26〇 exposes a plurality of wires. As shown in circle 9c, a quad flat pack (QFp) 2 can be attached to the plurality of exposed wires 260 by wires 22. Similarly, a quad flat no-wire package (QFN) (not shown) can be attached to the exposed plurality of wires 260 by solder connections. Next, the inventive semiconductor package can be assembled in conjunction with FIG. method. In step S1A, the second semiconductor die 4 is attached to the bottom die pad surface 201b of the lead frame 2, and at the same time, in step sib, the first semiconductor die 300 is attached to the substrate 100. The top surface 1〇〇a; next, in step S2A, the second die 4 is wire bonded to the lead frame 2〇〇, and at the same time in 127888.doc 1357142 step S2B 'the first die 300 The wire is bonded to the substrate loo; then, in step S3, the lead frame 200 is inverted and attached to the substrate 100 at the bottom portion 205 using solder, and thereafter the lead frame 200 and the substrate 1 are placed in a model. The molding material 900 encapsulates at least a portion of the substrate 1 and the lead frame 2A; after molding, the solder ball 800 is attached to the bottom surface 10b of the substrate 100 in step S4. In step S5, the package is singulated.

Since the two die attaching steps (s t A and S 1B) for the semiconductor die and the two wire bonding steps (S2A and S2B) have been combined, the assembly time is reduced and the unit time (UPH) rate is increased. The assembly method can also be implemented for a plurality of semiconductor packages. See, for example, Figures 3A, 3B, and 3C. Figure 3A shows a cross-sectional view of a leadframe strip 200 comprising a plurality of leadframes 2''. 3A also shows a substrate strip 1 包含 (Γ 。 。 包含 包含 在 在 在 在 在 在 在 在 在 在 在 在 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板 基板A top view of a lead frame strip of a matrix. Figure 3C shows a top view of a substrate strip 1 〇〇. of a substrate. During the manufacturing process, a plurality of semiconductor dies can be simultaneously attached to the lead frame strip 2 〇°' and the substrate strip 1 〇〇 both. Next, a wire bonding step is performed for all the semiconductor dies. Then, the lead frame strip 2 及 and the substrate strip 1 〇 0· are attached to each other and placed in a - model , in which the lead frame strips and the substrate strips (10) are encapsulated. After the encapsulation, the individual semiconductor packages are formed by singulation. 10° The semiconductor package is assembled into a form to increase the unit time rate and the quasi-I27888.doc -17· 1357142 Authenticity Both. The present invention provides several advantages over conventional packages and methods, for example, when a smaller die with conductor/resistance limitations and a larger die phase semiconductor package are used, Smaller die attached to the substrate The wire bonding for smaller dies in semiconductor packages of the time is kept as short as possible. In conventional semiconductor packages, the 'small die at the top will have a longer length. # In the present invention, when stacking more than two For a die, the "pyramid" pattern stack on the leadframe and on the substrate can be maintained while keeping the wire bond for the smaller die with conductor/resistance limits as short as possible. Smaller dies with conductor/resistance limitations are stacked on a substrate as a tower, and the structure is achieved by stacking larger die stacks on the leadframe in the same manner. In the conventional method of die stacking, The shortest possible wire bonding of smaller dies requires stacking the dies on the substrate in an inverted pyramid. As will be appreciated by those skilled in the art, stacking dies with "inverted pyramid" So that the larger top die does not land on the bond pads of the smaller bottom die. These other processing steps can include the use of spacers or insertions between the die that can cause potential package reliability issues. As described above, when the top grain pad surface of the lead frame is exposed to the outside, the lead frame can serve as an increase in both Θ Ja (junction to surrounding) and θ (junction to housing). A heat sink that can also act as a shield (ie, EMI shield) when the package is assembled onto a printed circuit board (PCB). Finally, although various embodiments show only two stacked together The crystal can be added to the package while maintaining the package height by using the inverted lead frame and the substrate. The inverted lead frame can be coupled to the cavity in the substrate. To further improve the thinness of the package, the present invention has been particularly shown and described with reference to the exemplary embodiments of the present invention, but those skilled in the art will understand that, without departing from the scope of the following claims Various changes may be made in the form and details of the invention. BRIEF DESCRIPTION OF THE DRAWINGS A number of aspects of the present invention can be better understood with reference to the T-pattern. The components in the drawings are not necessarily to scale, and the emphasis is on a clear understanding of the principles of the invention. In addition, in all the several views in the drawings, the same reference numerals indicate corresponding parts. Fig. 1A shows a cross-sectional view of a first embodiment of the invention. Figure 1B is a cross-sectional view showing a modification of a pair of lead frames of the present invention. 2A and 2B show a cross-sectional view and a perspective view of an embodiment of a method of the present invention. 3A, 3B and 3C show a cross-sectional view and a plan view of an embodiment of a lead frame and a substrate of the present invention. Figure 4 shows a cross-sectional view of a second embodiment of one of the inventions. Figure 5 shows a cross-sectional view of a third embodiment of the present invention. Figure 6 is a cross-sectional view showing a fourth embodiment of the present invention. Fig. 7 shows a representative view of a fifth embodiment of the present invention. Figure 8 shows a cross-sectional view of a sixth embodiment of the present invention. 9A, 9A and 9C are plan views showing a seventh embodiment of the present invention and a cross-sectional view of 127888.doc-19-1357142. Figure 10A shows an embodiment of a method of the present invention. Figure 10B shows an embodiment of a conventional method of assembling a package. [Main component symbol description] 10 Semiconductor package 20 Quad flat package (QFP) 22 wire

100 substrate 100' substrate strip 100a top surface 100b bottom surface 110 cavity 200 lead frame 200' lead frame strip 201 die pad portion

201a top die pad portion 201b bottom die pad portion 201c corner portion 202 first inclined portion 203 intermediate portion 204 second inclined portion 205 bottom portion 220 wire 240 notch 127888.doc • 20- 1357142

260 region 300 first semiconductor die 300a top surface 300b bottom surface 310 wire bond 320 solder bump 400 second semiconductor die 400a top surface 400b bottom surface 410 wire bond 500 third semiconductor die 500a top surface 500b bottom surface 510 line Bonding 600 Additional Semiconductor Die 610 Wire Bonding 700 Adhesive 800 Solder Ball 900 Molding Compound 127888.doc -21 -

Claims (1)

Patent Application No. 096149606 (Recording of Patent Application No. 096149606) This is a semiconductor package comprising: a substrate having a top surface and a bottom surface; a lead frame having a top die surface, a bottom die surface, and a plurality of wires, wherein the lead frame is attached to the top surface of the substrate; a first die having a top a surface and a bottom surface, wherein the bottom surface is attached to the top surface of the substrate and the first die is electrically connected to the substrate; a first die having a top surface and a bottom surface, wherein the top surface A surface is attached to the bottom die pad surface of the lead frame and the second die is electrically connected to the lead frame; and an encapsulant 'covers at least a portion of the lead frame and the substrate. 2. The package of claim 1 further comprising: a second die having a top surface and a bottom surface, wherein the bottom surface is attached to the top surface of the substrate and the third die is electrically connected To the substrate. 3. The package of claim 2, further comprising: a fourth die having a top surface and a bottom surface, wherein the top surface is attached to the top surface of the second die and the fourth The die is electrically connected to the leadframe. 4. The package of claim 1, further comprising: a third die having a top surface and a bottom surface, wherein the bottom surface is attached. The top surface of the first die of the primary child and the third die are electrically connected to the substrate by 127888-1001028.doc 1357142. 5. The package of claim 4, further comprising: a fourth die having a top surface and a bottom surface, wherein the top surface is attached to the bottom surface of the second die and the fourth The die is electrically connected to the leadframe. 6. The package of claim 1, further comprising: a third die having a top surface and a bottom surface, wherein the top surface is attached to the bottom surface of the second die; and a plurality of bonds a wire connected between the bottom surface of the third die and the wires on the lead frame. 7. The package of claim 1, wherein the encapsulant covers the entire top grain lining surface of the leadframe. 8. The package of claim 1, wherein the encapsulant covers the entire top die pad surface of the "Hail lead frame except for a plurality of regions. The package of claim 8, further comprising a second semiconductor package connected to the leadframe via the plurality of regions. 1. The package of claim 1 wherein the top die pad surface of the leadframe comprises 30 etched regions, and wherein the encapsulant covers the etched region rather than the remaining surface of the top die pad section. U. The package of claim 1, wherein a top surface of the second die is attached to the bottom die pad surface of the die pad portion of the lead frame. 12. The package of claim 1, wherein the second die is t-connected to the leadframe by wire bonding extending from the bottom surface of the second die. 13. The crack of claim 1, wherein the first die is electrically connected to the substrate by a wire bond extending from the top surface of the first die 127888-1001028.doc 13)7142. 14. The package of claim 1, wherein the encapsulant covers the leadframe and a top surface of the substrate in addition to the top die pad surface of the leadframe. 15. The package of claim 1, further comprising a solder ball disposed on the bottom surface of the substrate. 16. A semiconductor package, comprising: a leadframe having a top surface, a bottom grain surface, and a plurality of wires; a substrate having a top surface, a bottom surface, and a cavity Wherein the lead frame is attached to the top surface of the substrate; the first die has a top surface and a bottom surface, wherein the bottom surface is attached to the cavity of the substrate and the first die is electrically connected To the substrate; a second die having a top surface and a bottom surface, wherein the top surface is attached to the bottom die pad surface of the lead frame and the second die is electrically connected to the lead frame And an encapsulant that covers at least a portion of the leadframe and the substrate. 17. The package of claim 16, further comprising: a first die having a top surface and a bottom surface, wherein the bottom surface is attached to the cavity of the substrate and the third die is electrically connected To the substrate. 18. The package of claim π, further comprising: a fourth die having a top surface and a bottom surface, wherein the top surface is attached to the bottom surface of the second die and the fourth crystal The pellet is electrically connected to 127888-1001028.doc 1357142 to the lead frame. 19. The package of claim 16, further comprising: a second die having a top surface and a bottom surface, wherein the bottom surface is attached to the top surface of the first die and the third crystal The pellets are electrically connected to the substrate. 2. The package of claim 19, further comprising: a fourth die having a top surface and a bottom surface, wherein the top surface is attached to the bottom surface of the second die and the fourth The die is electrically connected to the leadframe. 21. The package of claim 16, further comprising: a third die having a top surface and a bottom surface, wherein the top surface is attached to the bottom surface of the second die and the third crystal The pellets are electrically connected to the lead frame. 22. The package of claim 16, wherein the encapsulant covers the entire top grain lining surface of the leadframe. 23. The package of claim 16, wherein the encapsulant covers the entire top die pad surface of the leadframe except for a plurality of regions. 24. The package of claim 23, further comprising a second semiconductor package connected to the leadframe via the plurality of regions. 25. The package of claim 16, wherein the top die pad surface of the leadframe comprises a semi-etched region, and wherein the encapsulant covers the semi-etched region rather than the top die pad surface The rest. 26. A method of fabricating a semiconductor package, comprising: (a) providing a substrate having a top surface and a bottom surface; 127888-1001028.doc 1357142 (b) providing a leadframe having a top die a pad surface, a bottom die pad surface, and a plurality of wires; (c) attaching a first die having a top surface and a bottom surface to the substrate 'where the bottom surface of the first die is attached To the top surface of the substrate and the first die is electrically connected to the substrate; (d) attaching a second die having a top surface and a bottom surface to the lead frame, wherein the second die The top surface is attached to the bottom die pad surface of the lead frame and the second die is electrically connected to the lead frame; (e) attaching the lead frame to the top surface of the substrate; and 0. The method of claim 26, further comprising: attaching solder balls to the substrate; and singulating the semiconductor packages into individual semiconductor packages. The method of claim 26, wherein the steps (〇) and ((1) are the same A method of fabricating a plurality of semiconductor packages, comprising: (a) providing a substrate strip having a top surface and a bottom surface; (b) providing a leadframe strip having a top die pad surface a bottom lining surface and a plurality of wires; (c) attaching a plurality of first dies having a top surface and a bottom surface to the substrate strip, wherein the bottom surfaces of the first dies are attached Connecting to the top surface of the substrate strip and the first die are electrically connected to the substrate strip; (d) attaching a plurality of second crystal grains having a top surface and a bottom surface to the lead frame, wherein The top surfaces of the second die are attached to the bottom die pad surface of the leadframe strip and the second die are electrically connected to 127888-1001028.doc 1357142 the leadframe strip; Attaching the leadframe strip to the top surface of the substrate strip; and (f) encapsulating the leadframe strip and at least a portion of the substrate strip. 30. The method of claim 29, further comprising: placing the solder ball Attached to the substrate and singulated the semiconductor packages into individual semiconductor packages 31. The method of claim 29, wherein steps (c) and (d) occur simultaneously. 127888-1001028.doc 6-