CN-200704002 24317twf.doc/n 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種封裝結構及其製作方法，且特別 是有關於一種晶圓級封裝結構及其製作方法。 ’ 【先前技術】 近幾年來’隨著攜帶式（portable)電子產品、手持 通訊以及及消費性電子產品之成長性已凌駕於傳統個人^ 腦（PC)產品之上，電子元件不斷地朝向高容量、窄線寬 的高密度化、高頻、低耗能、多功能整合方向發展。而在 積體電路（integrated circuiUC )封裝技術方面，為配合高 輸入/輸出（I/O)數、高散熱以及封裝尺寸縮小化的要= 下，使得晶粒級封裝（chip scale package，CSP)、晶圓級 封裝（wafer level package )等高階封裝技術需求不斷升高。 ,有別於傳統以單一晶片（die)為加工標的的封技 術，晶圓級封裝以晶圓（wafer)為封裝處理的對象，其主 要目的在簡化晶片之封裝製程，以節省時間及成本。在曰 圓上之積體電路製作完成以後，便可直接對整片晶圓進^ 封裝裝程’其後再進行晶圓切割（wafer saw )的動作，£ 分別形成多個晶片封裝體。製作完成之晶片封裝體忠^ 於载板上。 文裝 在使晶片封裝體與載板接合時，習知技術是在晶片 焊墊上形成金屬凸塊，並以導電膠填充於晶片封裝體之$ 塊與載板之接墊之間。然而，金屬凸塊之彈性較差，在 CN-200704002 24317twf.doc/n 在本發明之-實施例中，上述 基於上述，本發明採用彈性較佳之聚合物凸塊取代習 ^凸塊’因此，在聚合物凸塊與載板之接墊間的電性 接受到應力時，聚合物凸塊可產生形變以吸收應力。如 、可減合物凸塊與接墊間之電性連接所受到之應 力’進而提高之可靠度。 為讓本發明之上述特徵和優點能更_易懂，下文特 舉實施例’並配合所_式，作詳細“明如下。 【實施方式】 圖1A至圖ij為本發明一實施例之晶圓級封裝結構的 2方法流關。請參照® ^至® U，本發明之晶圓級 L、、”。構的製作方法包括下列步驟。首先，請參照圖ia， ，供-包括多個晶片職（圖中僅繪示一晶片馳）之晶 恩100 ’其中各晶片100a具有多個焊塾110a以及一保護 « 120a，且保護層12〇a具有多個第一開口 12%，而第一 開口 122a暴露—部分的焊墊u〇a。 接下來，請參照圖1B，在各焊墊ll〇a上形成一球底 ’’屬層130(見圖u及圖⑴。上述形成球底金屬層 之方法，可在晶圓1〇〇表面以電鍍之方式形成一全面覆蓋 之金屬層130, ’而在後續步驟中再將金屬層13〇，圖案化以 形成球底金屬層130。 之後喷參照圖1C至圖1G ’在各球底金屬層丨3〇(見 及圖1J)上形成一聚合物凸塊14〇，其中各聚合物凸 1356461 CN-200704002 24317twf.doc/n 塊140包括一聚合物層142、至少一導電柱144以及—接 合層146。[Technical Field] The present invention relates to a package structure and a method of fabricating the same, and more particularly to a wafer level package structure and a method of fabricating the same. '[Prior Art] In recent years, as the growth of portable electronic products, handheld communications, and consumer electronics has surpassed traditional personal brain (PC) products, electronic components are constantly moving toward high Capacity, narrow line width, high density, high frequency, low energy consumption, multi-functional integration direction. In the integrated circuit (integrated circuiUC) package technology, in order to match the high input/output (I/O) number, high heat dissipation, and package size reduction, the chip scale package (CSP) is required. Demand for high-end packaging technologies such as wafer level packages is increasing. Different from the traditional sealing technology that uses a single die as the processing target, the wafer-level packaging is wafer-wrapped, and its main purpose is to simplify the packaging process of the wafer to save time and cost. After the integrated circuit on the 曰 circle is completed, the entire wafer can be directly packaged and then subjected to a wafer saw operation to form a plurality of chip packages. The finished chip package is faithful to the carrier board. When the chip package is bonded to the carrier, the conventional technique is to form a metal bump on the wafer pad and fill it with a conductive paste between the block of the chip package and the pad of the carrier. However, the elasticity of the metal bumps is poor, and in the embodiment of the present invention, in the above-described embodiments, the present invention uses a polymer bump having better elasticity instead of the bumps. When the electrical contact between the polymer bump and the pad of the carrier is stressed, the polymer bump can be deformed to absorb the stress. For example, the stress on the electrical connection between the bump and the pad can be reduced, thereby improving the reliability. In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following detailed description of the embodiments of the present invention will be described in detail below. [Embodiment] FIG. 1A to FIG. The method of the circular package structure is 2, please refer to ® ^ to ® U, the wafer level L, "" of the present invention. The manufacturing method includes the following steps. First, please refer to FIG. ia, for a plurality of wafer jobs (only one wafer is shown in the figure), wherein each wafer 100a has a plurality of pads 110a and a protection «120a, and the protective layer 12 〇a has a plurality of first openings 12%, and the first opening 122a exposes a portion of the pads u〇a. Next, referring to FIG. 1B, a ball bottom dysfunction layer 130 is formed on each of the pads 〇a (see FIG. 9 and FIG. 1). The above method for forming the ball bottom metal layer can be performed on the wafer 1 surface. A fully covered metal layer 130 is formed by electroplating, and the metal layer 13 is further patterned in a subsequent step to form a ball-bottom metal layer 130. After that, reference is made to FIG. 1C to FIG. A polymer bump 14 is formed on the layer 3 (see FIG. 1J), wherein each polymer bump 1356461 CN-200704002 24317twf.doc/n block 140 includes a polymer layer 142, at least one conductive pillar 144, and Bonding layer 146.
在本實施例中’形成聚合物凸塊140之方法可包括下 列步驟。首先，請參照圖1C，在焊墊ll〇a上方之金屬層 130’上形成一聚合物層142 ’其中各聚合物層142具有I 少一貫孔142a，而上述聚合物層142之材質為聚醯亞胺或 其他聚合物。The method of forming the polymer bumps 140 in this embodiment may include the following steps. First, referring to FIG. 1C, a polymer layer 142' is formed on the metal layer 130' above the pad 11a, wherein each polymer layer 142 has a relatively small number of holes 142a, and the polymer layer 142 is made of a polymer. Yttrium or other polymers.
然後，請參照圖1D至圖1E，在各貫孔i42a中形成 一導電柱144。形成導電柱144的方法例如包括下列步驟。 首先，請參照圖1D，在金屬層130,以及聚合物層142上 幵y成圖案化罩幕50，而圖案化罩幕5〇具有多個第一 口 52，以使貫孔142a由第二開口 52中暴露出來。之後 請參照圖1E，藉由圖案化罩幕5〇電鍍貫孔14仏以在各貝 孔142a中形成一導電柱144。在本實施例中，上述導電柱 144之材質例如為鈦鎢合金。Then, referring to Figs. 1D to 1E, a conductive post 144 is formed in each of the through holes i42a. The method of forming the conductive pillars 144 includes, for example, the following steps. First, referring to FIG. 1D, the metal layer 130 and the polymer layer 142 are patterned into a mask 50, and the patterned mask 5 has a plurality of first openings 52, so that the through holes 142a are second. The opening 52 is exposed. Referring to FIG. 1E, a conductive via 144 is formed in each of the via holes 142a by patterning the mask 5 〇 through the via holes 14 。. In the present embodiment, the material of the conductive pillar 144 is, for example, a titanium-tungsten alloy.
,接下來，請參照圖1F至圖1J，在各聚合物層142上 ^成-接合層146’其中接合層146覆蓋導電柱144，並使 ^接合層！46透過導電柱144與對應之焊塾_電性連 丁^本實施例中’上述形成接合層146的方法可包括以 /首先’請參照圖1F，利用圖案化罩幕50，在由 弟7開口 52中暴露出來的導電柱144上形成—接合材料層 電性連接使2材料層146’透過導電柱144與焊塾偷 ,,'、、、'後，凊參照圖1G，移除圖案化罩幕50。之 ”月 > 照圖1H至圖丨！，圖案化接合材料層146，以形成 9 丄力6461 CN-200704002 24317twf.doc/n 接合層146。 在本實拖例中，可以—微影_製程將接合材料層 M6圖案化。詳細來說’圖案化接合材料層⑷’可包括下 歹步驟。首先’請參關1H，在各貫孔142a上方之接人 材料層H6,上形成-罩幕60。接下來，請參照圖u，對^ 被罩幕6〇钱刻之部分接合材料層Μ6,進行餘刻以形成接 合層146’朗時關金屬層13()，，以形成球底金屬層 • 130。之後，請參照圖1J，移除罩幕60。至此，大致完丄 晶圓級封裝結構200之製作。 睛參照圖2 ’在完成上述步驟之後，可再對晶圓級封 裝結構200進行切割’以使晶圓級封裝結構細形成多個 晶片封裝體200a，並將晶片封裝體2〇〇a安裝至一 上，且在載板70之接墊72與聚合物凸塊14〇之間填入導 電膠80 ’使晶片封裝體2〇〇a與載板7〇電性連接。 由於本發明使用聚合物凸塊140取代習知技術中之金 屬凸塊因此’在日曰片封裝體與載板％間之電性連 接文到應力時，聚合物凸塊14〇可產生形變以吸收應力。 如此，聚合物凸塊140可作為晶片封裝體2〇〇a之焊墊丨1〇& 與載板70之輕72間的緩衝，進而提高晶片封裝體施 與載板70之間電性連接的可靠度。 除此之外，在本實施例中，上述聚合物層140之厚产 大於導電权144之高度，而使位於導電柱144上方之接ς 層146具有一凹陷。如此，聚合物凸塊14〇在與接墊π 接合時’可固定導電膠8〇 +之導電粒子82，進一步提高 1356461 CN-2007〇4〇〇2 24317twf.doc/n 晶片封裝體200a與載板7〇之間電性連接的可靠度。 點：综上所述，本發明與習知技術相較之下具有以下優 屈由於本發明使用聚合物凸塊取代f知技術中之金 力睥2此’在^塊财触H㈣接受到應 物凸塊可產生形變以吸收應力。如此，聚合物 曰片封之焊墊與载板之接㈣的緩衝，進而提高 曰曰片封裝體與載板之間電性連接的可靠度。 導雷i可使聚合物層之厚度大於導電柱之高度，而使位於 接墊桩土：之接合層具有一凹陷。如此，聚合物凸塊在與 時，可固定導電谬中之導電粒子，進一步提高晶 月封裝體與載板之間電性連接的可靠度。 雖然本發明已以實施例揭露如上，然其並 本發明’任何所屬技術領域巾具有通常知識者，在不^離 ί發明之精神和範圍内，當可作些許之更動與潤飾，因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準0 【圖式簡單說明】 圖1Α至圖1J為本發明一實施例之晶圓級封裝結構的 製作方法流程圖。 、 圖2為圖1J之實施例中晶片封裝體與載板連接示音 圖。 11 1356461 CN-200704002 24317twf.doc/n 【主要元件符號說明】 50 :圖案化罩幕 52 :第二開口 60 :罩幕 70 :載板 72 :接墊 80 :導電膠 82 :導電粒子 100 :晶圓 100a .晶片 110a :焊墊 120a ··保護層 122a :第一開口 130 :球底金屬層 130’ ：金屬層 140 :聚合物凸塊 Φ 142 :聚合物層 142a :貫孔 144 :導電柱 146 :接合層 146’ ：接合材料層 200 :晶圓級封裝結構 200a :晶片封裝體 12Next, referring to FIG. 1F to FIG. 1J, a bonding layer 146' is formed on each of the polymer layers 142, wherein the bonding layer 146 covers the conductive pillars 144, and the bonding layer is made! 46 through the conductive post 144 and the corresponding soldering iron _ electrical connection □ in the present embodiment 'the above method of forming the bonding layer 146 may include / first 'please refer to FIG. 1F, using the patterned mask 50, in the brother 7 The conductive pillar 144 exposed in the opening 52 is formed on the conductive pillar 144. The bonding material layer is electrically connected, so that the 2 material layer 146' is smashed through the conductive pillar 144 and the soldering iron, after ',,, ', after removing the patterning, referring to FIG. 1G Cover 50. "Month", according to FIG. 1H to FIG., patterning the bonding material layer 146 to form a 9 CN force 6461 CN-200704002 24317 twf.doc/n bonding layer 146. In this example, it can be - lithography _ The process patterning the bonding material layer M6. In detail, the 'patterned bonding material layer (4)' may include a squeezing step. First, please refer to 1H, and a material layer H6 is formed on each of the through holes 142a. Curtain 60. Next, referring to FIG. u, a portion of the bonding material layer 6 is etched by the mask 6 to make a bonding layer 146' to turn off the metal layer 13 () to form a ball-bottom metal. Layer 130. Thereafter, referring to FIG. 1J, the mask 60 is removed. At this point, the fabrication of the wafer level package structure 200 is substantially completed. The eye can be re-processed after the above steps. 200 is diced 'to make the wafer level package structure finely form a plurality of chip packages 200a, and the chip package 2A is mounted on one, and the pads 72 of the carrier 70 and the polymer bumps 14 The conductive paste 80 ′ is filled between the chip package 2 〇〇 a and the carrier 7 〇 electrically connected. The invention uses the polymer bumps 140 to replace the metal bumps in the prior art. Therefore, when the electrical connection between the niobium chip package and the carrier sheet is applied to the stress, the polymer bumps 14 can be deformed to absorb the stress. Thus, the polymer bumps 140 can serve as a buffer between the pad 丨1〇& of the chip package 2〇〇a and the light 72 of the carrier 70, thereby improving the electrical property between the chip package and the carrier 70. In addition, in the present embodiment, the thickness of the polymer layer 140 is greater than the height of the conductive member 144, and the interface layer 146 above the conductive post 144 has a recess. Thus, polymerization When the bump 14 is bonded to the pad π, the conductive particles 82 of the conductive paste 8 can be fixed, and the electrode package 82 can be further increased by 1354661 CN-2007〇4〇〇2 24317twf.doc/n chip package 200a and carrier 7〇 The reliability of the electrical connection between them. Point: In summary, the present invention has the following advantages compared with the prior art. Since the present invention uses the polymer bump instead of the gold force 2 in the technology. At the block of the H (four), the accepting of the bumps can be deformed to absorb the stress. Therefore, the buffer of the polymer chip seal pad and the carrier plate (four) buffer, thereby improving the reliability of the electrical connection between the chip package and the carrier plate. The guide i can make the thickness of the polymer layer larger than the conductive The height of the column is such that the bonding layer on the pad pile soil has a depression. Thus, the polymer bumps can fix the conductive particles in the conductive crucible at the same time, further improving the electricity between the crystal matrix package and the carrier plate. Reliability of the sexual connection. Although the present invention has been disclosed above by way of example, and the invention of the present invention has a general knowledge, it is possible to make some changes in the spirit and scope of the invention. And the scope of the present invention is defined by the scope of the appended claims. [FIG. 1A to FIG. 1J is a flow chart of a method for fabricating a wafer level package structure according to an embodiment of the present invention. Figure. FIG. 2 is a schematic diagram showing the connection of the chip package and the carrier in the embodiment of FIG. 1J. 11 1356461 CN-200704002 24317twf.doc/n [Main component symbol description] 50: patterned mask 52: second opening 60: mask 70: carrier 72: pad 80: conductive paste 82: conductive particles 100: crystal Circle 100a. Wafer 110a: pad 120a · · protective layer 122a: first opening 130: ball bottom metal layer 130': metal layer 140: polymer bump Φ 142: polymer layer 142a: through hole 144: conductive column 146 : bonding layer 146 ′: bonding material layer 200 : wafer level package structure 200 a : chip package 12