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TWI346999B - Wafer level chip scale package and method for fabricating the same - Google Patents

Wafer level chip scale package and method for fabricating the same

Info

Publication number
TWI346999B
TWI346999B TW096145989A TW96145989A TWI346999B TW I346999 B TWI346999 B TW I346999B TW 096145989 A TW096145989 A TW 096145989A TW 96145989 A TW96145989 A TW 96145989A TW I346999 B TWI346999 B TW I346999B
Authority
TW
Taiwan
Prior art keywords
fabricating
same
wafer level
chip scale
scale package
Prior art date
Application number
TW096145989A
Other languages
Chinese (zh)
Other versions
TW200926365A (en
Inventor
Chih Wei Wu
Hung Hsin Hsu
Original Assignee
Powertech Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Powertech Technology Inc filed Critical Powertech Technology Inc
Priority to TW096145989A priority Critical patent/TWI346999B/en
Publication of TW200926365A publication Critical patent/TW200926365A/en
Application granted granted Critical
Publication of TWI346999B publication Critical patent/TWI346999B/en

Links

Classifications

    • H10W72/0198—
    • H10W74/15—
    • H10W90/724—
    • H10W90/734—
TW096145989A 2007-12-03 2007-12-03 Wafer level chip scale package and method for fabricating the same TWI346999B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
TW096145989A TWI346999B (en) 2007-12-03 2007-12-03 Wafer level chip scale package and method for fabricating the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW096145989A TWI346999B (en) 2007-12-03 2007-12-03 Wafer level chip scale package and method for fabricating the same

Publications (2)

Publication Number Publication Date
TW200926365A TW200926365A (en) 2009-06-16
TWI346999B true TWI346999B (en) 2011-08-11

Family

ID=44729672

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096145989A TWI346999B (en) 2007-12-03 2007-12-03 Wafer level chip scale package and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI346999B (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI509759B (en) * 2013-08-19 2015-11-21 力成科技股份有限公司 Substrate-free package structure of dicing fin in heat sink and manufacturing method thereof

Also Published As

Publication number Publication date
TW200926365A (en) 2009-06-16

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Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees