TWI344753B - Decimation filter - Google Patents

Description

</ RTI> </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> <RTIgt; </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> <RTIgt; The entire content of this priority application is incorporated into this case for reference. BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a down-conversion filter that converts a signal frequency to a lower frequency at a predetermined ratio. • [Prior Art] In signal processing, it is sometimes necessary to change the sampling rate of the signal sampled at a predetermined sampling frequency. - A system that raises the frequency is called an interpolator. The system that reduces the frequency is called a decimator. The invention is related to a frequency reducer. In the down-converter, filtering and wave processing are performed on the data, and then the data is down-converted to achieve the desired processing. In the case of reducing the sampling (d〇wn_sampi squeaking) to the lower frequency, when the component is higher than 1/2 (Nyquist freqUenCy) of the lower frequency, overlapping distortion occurs ( Foldover distortion) (aliasing component). Therefore, filtering processing is performed to limit the bandwidth to the Nyquist frequency or lower. The filter used for the filtering process is called a decimation filter. When the downconverter is down-converted according to this principle, the sampling rate can be converted without using an analog signal. However, there is a problem such as an increase in the processing load, because the slit processing must be performed at a high sampling rate before the sampling is reduced 319700 5 1344753, and the ideal filter cannot be used. Therefore, the calculation process is performed, and the transfer function (transfer functi〇n) H(z) is divided into a plurality of filter coefficient groups corresponding to the frequency ratio Μ. This filter and waver structure is called a polyphase fabric (p〇lyphase c〇nfigurati〇n), and the filter having this structure is called a polyphase fiiter. The filter coefficients in the polyphase fabric are obtained by decimation of the coefficients from each of the M coefficients of the original filter coefficients. When the input data is applied to the filter to reduce the sampling, the filter can operate at the low operating speed caused by the reduced sampling. Therefore, an effective filter can be constructed. Figure 4 is a diagram showing an example of a downconverter implemented by a polyphase fabric. Referring to the drawing, the signal input from the input side at the higher sampling frequency Fs is output from the output side 51 at the lower sampling frequency Fd. The delay element 52 is a shift register that delays the signal by a period of 1/Fs (corresponding to a frequency). The down-sampler 53 (indicated by "n&gt;" in the figure) is to reduce the sampling and call the input signal to the down-conversion ratio Μ. Do (z)...Dd(z) of the polyphase filter 54 is obtained by causing the transfer function Η(ζ) to undergo polyphase decomposition, and the Do(z)...Dh of the polyphase filter 54 is obtained. (z) constitutes a group of filters in which the filter coefficients are selected for each μ number. The adder 55 adds the filtered signals to each other. For example, a transfer function η ( ζ ) of a filter whose filter is assumed to have a tap number of η and is down-converted by 1:3 is represented by the following formula ("* indicates a multiplication symbol,"): 6 319700 1344753 H(z) = h0.+ h,z-1 + h2*z,2 + h3*z-3 + h4*z-&lt; + ...+ hn-2*zn-2 +

Wz11-1 (a) then 'forms three polyphase filters 54 or is formed as j) D ( Z ) to 〇 2 ( Z ) and is represented by the following formula (in this case, the number of taps is a multiple of 3) : D〇(z) = h〇+ h3*z_l + h6*z'2 +...+ h„-3*z'n/3+1 (b)

Di(z) = hi + h4*z_1 + h7*z'2 +...+ hn-2*z'n/3+1 (c) d2(z) = h2 + hs^z-*1 + hB *z'2 +...+ hft_i*z&quot;n/3+1 (d) In this manner, the polyphase filter 54 can perform the filtering calculation at the learned processing rate after the sampling is reduced. Therefore, the processing load can be reduced. The outputs are added together by an adder 55, and the last downsampled signal is output from the output side 51. In the calculation of the polyphase filter 54, a ρ IR filter (Finite Impulse Response er), 11R, and a filter (infinite impulse response filter (I n ^ ini te) can be used. impulseResponseFilter)), or FFT (Fast Fourier Transform) calculation. • [Non-patent reference multi-rate signal processing (Multi rate signal

Processing),,(SH0K0D0 Co., Ltd., ΚΙγΑ,, especially Chapter 4. However, in the downconverter having the above-mentioned related art fabric, when performing a frequency reduction ratio greater than 100, it is necessary to be proportional to the drop. Increasing the circuit size (when the frequency ratio is 3 as in the above example), the number of delay elements required is 3). Again = the calculated size of the phase chopper 54. It is a method of performing frequency reduction while dividing the frequency reducer into several stages. 319700 7 In contrast, in applications where the instrument does not have a 4~ state, there is a large frequency reduction ratio. There is a situation in advance. The organization of this is not always appropriate. Because &amp;,: It is difficult to achieve multiple levels of what is expected. Material supply - seed material (four) real [invention content]

Instead of the exemplary embodiment, a down-converting filter is provided that converts the input down: to a lower frequency and has a filter fabric that can easily handle any down-conversion ratio without adding hardware. In accordance with one or more embodiments of the present invention, the down-converting filter includes: a plurality of computing devices each having a multiplier and an accumulator (aCCUD1Ulat〇r); a plurality of coefficient memories 'its And storing the filter coefficients respectively corresponding to the computing device; and the selector 'selectively outputs the output of the plurality of computing devices in synchronization with the clock signal; wherein, when the down-conversion ratio is η, the sequence is sequentially The money coefficient of shifting up to n filters and wave coefficients is recovered from the plurality of coefficients

The body is read and multiplied by the signal in the multiplier of the computing device, and multiplied, and the result is accumulated in the accumulator for output. According to this configuration, it is possible to provide a chopper configuration that can easily handle an arbitrary down-conversion ratio without adding hardware. The plurality of coefficient memories may have: a memory (memory) storing all previously calculated filter coefficients, and sequentially reading the loop memory from the loop memory in synchronization with the clock signal Filter coefficients; and a plurality of shift registers whose steps are connected to reascade-connected) to the ring memory; and, the shift registers 319700 8 丄• Γ, can be stored when the down-conversion ratio is 11. The chopper coefficients of the n-th filter coefficients are stored in the plurality of registers and read from the plurality of shift registers, and the filter is sequentially , wave coefficient. According to this configuration, the required storage capacity in the 4-factor memory can be largely reduced. The case of ^ is that the number of computing devices is equal to or greater than the value obtained by dividing the number of 遽^ coefficients by the down-conversion ratio. Or preferably, the number of chopper coefficients stored in the coefficient memory is equal to or less than the value obtained by multiplying the number of computing devices by the down-conversion ratio. According to this configuration, the calculation can be performed approximately efficiently using the number of computing devices provided. The present invention is capable of providing a down-waveform that converts the frequency of the input signal to a lower frequency and has a filter fabric that can easily handle an arbitrary down-conversion ratio without adding hardware. The features and advantages of the invention are apparent from the following detailed description, appended claims and claims. [Embodiment] An embodiment of the falling (four) wave device of the present invention will now be described. silk! The figure shows an illustration of the configuration of an embodiment of the reduced down filter, and Fig. 2 is a diagram showing the relationship between the sampled signal and the filter coefficients. The down-converting filter of the present invention is not a polyphase filter. The figures, the division numbers, the other specific numbers, and the like, which are represented in the following examples, are merely intended to be illustrative of the present invention and are not intended to limit the invention unless otherwise specified. 319700 9 丄JH·pieces/:):) In the down-converter filter of Figure 1 in Figure 1, from the input side 10 to the south sampling frequency Fs Lang·&amp;λ a φ The signal input to the hall is rotated from the output side 11 at a lower sampling frequency Fd. The germination, grinding, and taste of the wave include: a plurality of computing devices 20, each of which is multiplier 21 and accumulates 51 99. α, 斋 22 ν and constructed; ring memory 3〇, which is an example of a system = body; a plurality of shift registers 3 are coefficient memory • ^ 歹, and selector 13 ' The output of the computing device 2 is sequentially selected to output it. The %-type memory 30 is capable of storing all of the previously calculated choppers, &gt; and the coefficients can be sequentially cyclically read out in synchronization with the clock signal. The shift register 31 is stepped. The (caseade) mode (hierarchy) is connected to the ring memory 30, and the 俾 will be read from the ring memory 30, 'the skin coefficient is stored in the plurality of shift registers, and the temporary number is temporarily stored. It is read out and the filter coefficients are shifted sequentially. The operation of the ring memory 30 and the shift register 31 will be described in detail below. The filter coefficients are read from the % memory 30 and the corresponding calculation is input. The data of the time filter benefit coefficient is simultaneously sent to the first shift register 3:1. In the ring memory 30 towel, the next chopper coefficient to be read ^ address is shifted. The filter coefficients sent out are stored in each shift temporary storage 31 and are sequentially shifted at the same time, and when the capacity of the shift register 31 is filled, the shift from the shift is performed. The device 31 reads the processing to the computing device 20. Simultaneously with this reading, the data of the filter coefficients is sent to the two shift registers 3 to repeat the procedure, so that the data of the filter coefficients are shifted in the temporary #|| Moved in a way that is pushed forward. 319700 10 In the case where the down-conversion ratio is n, the ring memory 30 stores n * k in filter coefficients. This shift register μ has a capacity (depth) capable of chopper coefficients. The coefficient k represents the calculation means 2 〇 , , , ' and the coefficient of the filter tap length and is, for example, a value of about 24. The coefficient is an integer, which is not less than ◦', and in order to prevent the generation of the excess multiplier 21, preferably not more than 〇2, the number of computing devices 20 is equal to or greater than

The number of filter coefficients divided by the value obtained by the down-conversion ratio. In other words, it is preferable that the number of filter coefficients in the to-be-stored memory 3G is smaller or smaller than the value obtained by multiplying the number of the calculations X 20 by the down-conversion ratio. According to this configuration, the calculation can be performed efficiently using the number provided by the computing device. y. The signal input to the input side 10 is supplied to one of the plurality of multiplications 11 21 of the plurality of computing devices 2». The output of the ring memory cassette 30 and the shift register 31 are respectively connected to the other input of the multiplier 21, and the execution is performed by multiplying the input signal by each filter coefficient. The multiplication result is calculated by the sum of each of W 2 until the tapping length of the elementary filter is calculated, and when the selector 13 is connected, it is output to the output side u. An example of the operation of the down-converting filter and the waver will be described with reference to FIG. Example: Words assume that the down-conversion ratio is 3, the coefficient k is 24, and the coefficient! „为〇.”Ί/wave filter tap length is 72. Therefore, the ring memory 3A has a capacity for storing 72 tapped chopper coefficients, and the shift register 31 has a capacity for storing 3 tapped filter coefficients. In the figure, the ten-opening device 20 is represented by 2〇_ι, 2〇-2, 319700 11 1344753 20-3, ..., 20-24 in order from the left. In Fig. 2, the 72 tap coefficients of the filter coefficients are represented by h0, hi, h2, ..., h71, and the input signals at the sampling points are represented by d0, dl, h2, .... Under the above conditions, the computing devices 20-1, 20-2, 20-3, and 20-24 respectively perform calculations represented by the following formulas (e), (f), (g), and (h): (20) -1) d〇*h〇+ dx*hi + d2*h2 + d3*h3 +...+ d69*h6? + d7〇*h7fr + dn*h71 (e) φ (20-2) d3*h 〇+ d4*hi + d5*h2 + d«*h3 +...+ d72*h69 + d73*h7〇+ d74*h7i (f) (20-3) d6*h〇+ d7*hi + d8* H2 + d9*h3 +...+ d75*h69 + d76*h7〇+ dr?*h7i (g) (20-4) d69*h〇+ d7〇*hi + d7i*h2 + d72*h3 +. ..+d138*h69 + di39*h7〇+ di4〇*h?i (h) After n calculations (three clocks in this embodiment) from the start of calculation by the computing device 20-1, Computing device 20-2 begins the calculation. Similarly, computing device 20 begins operation every n clock cycles. * In the computing device 20-1, when the calculation represented by the formula (e) is completed, the accumulator 22 is reset, and then the filter calculation represented by the formula (i) is successively started at the timing d72. Similarly, in the computing devices 20-2 to 20-24, the connected data is processed, whereby continuous frequency down-conversion can be performed. ^2〇-1) d72*li〇+ ^73*hi + d74*h2 + d75*h3 +...+ d14a*h69 + di42*h7〇+ di43*hn (1) At the end of the computing device 20_1, 72 points The time of the calculation is hot, the selector! 3 is connected to the computing device 2G-1. Then, the ratio of 1/3 sampling 12 319700 ^^4/53 'calculated &amp; 2G is sequentially switched to the output of the tube output. That is to say, at the time point of the formula (4): :: beam time 'select the output of the computing device 2 (M.) After the temperature has passed 3 hours, the remote computing device 2〇2 Output, and select the remaining computing devices sequentially until the calculation of i 2 (four) is

After that, the output of the computing device 20-1 is selected. The next calculation of the time point 20-1 after the passage of 3 clocks after the end of the juice calculation (h) of the computing device 20-24. In the down-converting filter thus constructed, it is possible to construct a filter having an arbitrary down-conversion ratio by adjusting only the depth (capacity) of the coefficient memory type memory 30 and the shift register 31). In the related art example, the number of delay elements 52 and polyphase filters 54 must be changed, and this change is a large-scale modification of the circuit. Therefore, it is difficult to achieve arbitrary down-conversion filtering. According to the present invention, it is possible to provide a filter structure which can easily handle the tolerable down-conversion ratio without adding hardware. In particular, the coefficient memory system is constructed by a ring memory 3〇 and a plurality of shift registers 31, and the filter coefficient data is stored into the coefficient memory while being sequentially shifted. Enter to the next level (=tage). Therefore, each coefficient memory does not need to have all of the filter coefficient negatives correspond to the juice calculation device, and can greatly reduce the required storage capacity in the coefficient memories. For example, the down-converting filter described above can be constructed by Fpga. In recent years, FPGAs have included one or more such multipliers 21 and memories (the § 己 体 30 and the shift register 31), and thus are suitable for real 13 319700 1344753. Fabrication. When the filter is constructed by using an FPGA, the number of computing devices 2 and the capacity (depth) of the memory can be appropriately set in a dynamic manner. The number of computing devices 20 corresponds to the filter tap length. The required filter characteristics can be adjusted by increasing or decreasing the number of computing devices 20. In the case where the cut-off frequency region requires a transient characteristic of the steep mountain, the number of computing devices 20 increases. In contrast, in the case where the filter state can be relaxed to the allowable level, it can be reduced. With the number of 10 nose devices, 俾 can construct a down-converting filter that can be economically realized. /', 'The computing device 20 always operates in a manner that does not generate a wasted time period, and can calculate the processing speed at a higher processing speed than a computer having a general multi-core configuration. Implement calculation processing. In the instrument such as the 1C tester or the memory tester, the input signal must be down-converted according to the target to be measured at different ratios. In particular, the filter is constructed in the above manner. High speed and highly accurate filter for instant operation. [Other Embodiments] In the above embodiment, the coefficient memory system is constructed by a ring memory and a plurality of shift registers 11 31 . Alternatively, all of the parameters - the hidden bodies can be constructed from % memory, thereby implementing the present invention. Fig. 3 is a diagram showing another configuration example of the down-converting filter. In the figure, the shift register 31 is not provided, and all the coefficient records are constructed by the magnetic type. Each ring type·% is stored ^ 14 lion. ; 1344753 All filter coefficients calculated. In the case where the down-conversion ratio is η, the filter coefficients which are shifted by n filter coefficients are sequentially read from the respective ring-shaped memories 30. In each of the computing devices 2, the filter coefficients and signals read by the 丄1 开 甲 甲 are multiplied by the multiplier 21 and accumulate in the accumulator 22, and then output, thereby being able to perform The same calculation process in the above embodiment. When the down-conversion ratio is 1, the down-converter chopper of the present invention functions as a general-purpose FIR filter, and thus can be used as a high-speed and highly accurate FIR filter for immediate operation. The invention has been described with reference to the preferred embodiments thereof, but the invention is of course not limited by the embodiments. It is obvious that those skilled in the art can make various modifications and changes within the scope of the appended claims, and such modifications and variations will fall within the technical scope of the present invention. The present invention can be used as a down-converting filter that converts the frequency of the signal to a lower frequency at a certain ratio. BRIEF DESCRIPTION OF THE DRAWINGS # Fig. 1 is a diagram showing the configuration of an embodiment of a down-converting filter. Figure 2 is a diagram showing the relationship between the sampling signal and the filter coefficients. Figure 3 is a diagram showing another example of the configuration of the down-converting filter. - 4th is a diagram showing an example of a downconverter implemented by a polyphase fabric. [Main component symbol description] Input side output side - 319700 15 11 1344753 13 Selector 20 Calculation device calculation device 20-1, 20 -2, 20-3, ..., 20-24 21 Multiplier 22 Accumulator 30 Ring Memory 31 Shift Register 50 Input Side 51 Output Side 52 Delay Element 53 Sample Reducer 54 Polyphase Filter 55 Adder H0, hi, h2.....h71 tap dO, dl, h2, ... input signal Fs sampling frequency

Fd sampling frequency 16 319700

Claims (1)

Ten, the scope of application for patents: L - a type of down-conversion filter, comprising: a plurality of computing devices, each having a multiplier and an accumulator; 2 a plurality of coefficient memories 'the coefficient memory system stores the filter stealing coefficients, and respectively corresponding to The computing device; and the selection device, the selector selectively and selectively outputs the output of the plurality of computing devices in synchronization with the clock signal; wherein 'when the down-conversion ratio is n, the sequence is shifted by n The 波 遽 器 器 器 器 器 器 器 器 器 器 it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it it Waiting for output. 2. The down-conversion filter of claim i, wherein the plurality of coefficient memories have: a ring memory, the ring memory system stores all chopper coefficients that have been previously calculated, and from The ring Z recalls 2 to continuously read the filter coefficients in synchronization with the clock signal; and a plurality of shift registers connected to the ring memory; wherein the shifts are temporarily The buffer has a capacity capable of storing n chopper coefficients when the down-conversion ratio is 4, and the filter coefficients read from the ring memory are stored in the plurality of shift registers and from the plurality of The shift register reads out and sequentially shifts the filter coefficients. The down-conversion filter of claim 1, wherein the number of the computing devices is equal to or greater than a value obtained by dividing the number of filter coefficients by 319700 17 1344753 at the down-conversion ratio. 4. The down-conversion filter of claim 1, wherein the number of the filter coefficients stored in the coefficient memory is equal to or less than the number of the computing devices multiplied by the down-conversion ratio The value obtained. 18 319700