1343626 93103 21747lwf.doc/t 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種積體 是有關於一種半導體元件與其製造^法方法，且特別 【先前技術】 ^ 以符步薄電:元_造必須提高積集度， 的方法，除了縮小半導體元件提高積集度 導體元件其本身的尺寸，或是J二；論是縮小半 都會發生-些製程上的問題，件間的距離， 寬縮小後’位元線接觸窗在形 ；，：:所： 臨的一些問題作為說明。 τ在I私上所面 圖1是習知的記憶轉之上視圖；圖2是圖】中沿㈣ 剖面圖；圖3是圖1中沿ΠΙ·ΙΠ剖面的剖面圖。 丨與圖2，f知的記憶體元件之製程，是在 基底200上形成隔離結構2〇3，界定出主動區1〇1之後， 在基底200上形成彼此相互平行的字元線1〇5，之後再於 基底200上沉積介電層1〇7，並在介電層】〇7之中形成位 元線，觸窗開σ靡，以露出主動區un，最後再於位元線 接觸窗開口 109中填入複晶矽層以形成位元線接觸窗111。 由於元件的尺寸製作日漸縮小，因此不論是字元線 1〇t本身的寬度，或是字元線105彼此間的間隙(Space) 113 之寬度都必須縮小，以達成高度積集化之目標。但是，字 5 93103 21747twf.doc/t 元線105其彼此間的間隙113寬度縮小後，將使得間隙的 高寬比(Aspect ratio)增加。當介電層川7填入此具有增加 尚寬比的間隙113時，將非常容易產生有如隧道般的空孔 (Key Hole)115。此種隧道般之空孔115的形成，會使後續 所形成之位元線接觸窗開口 1〇9彼此之間，透過空孔j ^ 而相互連通，如圖3所示。 另外，請參照圖3，線寬縮小之後，將使位元線接觸 窗開口 109白勺高寬比也跟著增加。為了使土真充於位元線接 觸®開口 109中的複晶矽層具有良好的階梯覆蓋能力，往 往採用化學氣相沉積的方式來形成複^層。然而，具有 良好階梯覆魏力之複砂層1U亦將獻與位元線接觸 窗開口 109相互導通的空孔115巾，因而導致兩相鄰的位 兀線接觸窗m透過純115之巾的導體層而發生短路。 因此，如何在不改變原有的線寬及接觸窗開口大小的 ，件下，避免空孔的形成，便成為一項亟待解決的重要課 題0 【發明内容】 本發_目的就是提供半導體元件的製造方法，利用 二介於接觸窗間的字元線之寬度，使字元線彼此之間隙 目曰^達到避練觸窗之間因空孔彼此連通而發生短路的 短路再—目暇提供—義免位元線接觸窗之間 部之—&體讀’辭導體元件包括本身具有寬部與窄 。子几線，使介於接觸窗之間的字元線彼此之間的間隙 93103 21747twf.doc/t 増大美連通使位元線接觸窗之間發生短路。 造方i 目的，树顺^料導體元件的製 方法T先方；基底上定義多數個主動區 成第-字元線與第二字元線，第 立方、基底上升/ 主動區相互交錯，且分別具有多數互對 其中這些相互對應== 相互對應的寬部之間為窄間隙；接著於這些窄 丄开ί 的中，多數個源極/沒極區;再於基底 位丄線^觸:門妾者於技些窄間隙之介電層中形成多數個 位：：中:：ίΓ及極區;最後於這些 接觸窗。 體㈣成錄個位元線 ^另-觀點來看，本發明提出—種半導體元件，此半導 =ϊ:位於基底上之第一字元線與第二字元線，第-字 數徊Γ第—子兀線與基底的主動區相互交錯，且分別具有多 :=間為寬間隙’相互對應的寬部之心 ^個源極/汲極區位於這些窄間隙之主動區的基底中，·以及介 位於基底上且覆蓋第-字元線與第二字元線；以及多數 :立，線接_，位概鮮_之介f層中，電性連接源 極/>及極區。 依照本發明的較佳實施例所述之避免位元線接觸窗之 =路之半導體元件’其中位於寬間隙之介電層中不包含 93103 21747twf.doc/t ㈣利用5肖整子元線本身介於接觸窗間的 =來，字元，字元線之間的間隙宽度，可以避免習知技 何中因子7G線與字①線間，關隙過小導致 ^洞的問題，故可達成避免位元線接_之_生』二 為讓本發明之上，和其他目的、特徵和優點能更明顯 k ’下文轉較佳實施例，並配合所_式，作詳細說 明如下。 【實施方式】 圖4所繪示為依照本發明較佳實施例之一種且有深溝 渠式電容之動態隨機存取記憶體之上視圖。圖5、圖6與 圖7係分別緣示圖4中沿v_v剖面、νι νι剖面以及抓— 剖面之剖面圖。 請同時參照目4、圖5與圊6，基底4〇〇中的隔離結構 401 ’用以在基底4〇〇上界定出主動區4〇3。隔離結構4〇1 的形成方法例如可以是淺溝渠隔離法(ST1)。基底4⑻中形 成溝渠式電容器405。溝渠式電容器4〇5可以採用已知的 各種方式來製作之。 卜在基底4〇〇上形成—層閘介電層407，其材質例如為 氧化矽，形成的方法例如為熱氧化法。接著，在基底4〇〇 上形成一層導體層，並圖案化此導體層，以形成字元線4〇9 與411。字兀線409與411中，跨越主動區4〇3以及主動 區403周圍的部分’其字元線寬度413均維持原佈局之線 寬，而在兩主動區403之間的部分，其字元線寬度4]5則 略小於原佈局之線寬(即字元線寬度413)❶換句話說，字元 93103 2l747twf.doc/t 線409與字元線411具有相互對稱的寬部417與窄部4]9, 其中，寬部417為字元線409、4〗1跨越主動區403以及主 動區403周緣的部分；窄部4】9則是較遠離字元線409、 411中跨越主動區4〇3的部分。因此，窄部419之間間隙 423的寬度較大於寬部417之間的間隙421的寬度。 上述字元線409與字元線411之導體層的材質例如為 複晶矽，其形成的方法例如為化學氣相沉積法。字元線 409、411的圖案，可透過光罩上直接設計(Lay〇ut)出，然 後經由微影與餘刻製程加以完成。 之後，在基底400的主動區403中形成源極/汲極區 430。然後，在基底400上形成一層介電層425，以覆蓋字 元線409、411以及字元線4〇9與字元線411之間的間隙 421與423。介電層425之材質例如是硼磷矽玻璃或介電常 數低於4之介電材料’形成的方法可以採用化學氣相沉積 法。由於寬部417之間的間隙421其寬度較小於窄部419 之間之間隙423的寬度，間隙423的高寬比較小於間隙42ι 的高寬比，因此，當介電層425覆蓋間隙423時，其覆蓋 的效果較好，不易形成空孔，如圖5所示；而介電層4乃 覆蓋於間隙421時，即便其覆蓋的欵果較差，而形成如圖 6 t的空孔427時，亦可透過間隙423之中所形成的介電 層425加以阻隔，使兩相鄰之寬部4丨7之間之間隙421中 所形成的空孔427不會相立導通，因此，其製程空間 (Process Window)遠大於習知者。 之後’請參照圖4與圖7，在寬部417之間的介電層 1343626 93103 21747twf.doc/t 425中形成位元線接觸窗開口 429，以裸露出主動區4的 之基底400表面。位元線接觸窗開口 429可能會與間隙421 之介電層425中的空孔427相互導通，但是，由於窄部419 之間所形成之介電層425並無空孔，因此兩相鄰之位元線 接觸窗開口 429並不會透過空孔425而相互導通。 接著，在位元線接觸窗開口 429之中填入導體材料 431，以形成與基底400中之源極/汲極區43〇電性連接之 位元線接觸窗431。為了增加導體材料的階梯覆蓋能力， 較佳的導體材料的形成方法例如採用化學氣相沉積法，而 $質例如是複㈣。值得注意的是，本實施射的字元線 ^度縮小的部分位於溝渠式電容醜段，然並非用以限定 务明，子7L線的寬度縮小的位置可視實際需要加以調整。 相^體而言，本發明奴義字7^圖案時，利用減少兩 相^过線接觸窗之間之字元線的寬度，以增加兩相鄰字 =彼低其高寬比，使位元線接觸窗開 彼此間，可以透過無空孔連通之介電層來加以阻隔。 觸窗之=條件T，解決習知 ，然本發明已以較佳實施例揭露如上，缺直並以 <疋本勒明，任何所屬技中 替 脫離本發明之一句璁吊知識者，在不 -發二者 1343626 93103 21747twf.d〇c/t 為準。 【圖式簡單說明】 圖1繪示為習知中一種記憶元件之上視圖。 圖2繪示為圖]之IMI剖面的剖面圖。 圖3繪示為圖1之m_nI剖面的剖面圖。 圖4所繪示為依照本發明較佳實施例之一種具有溝渠 式電容之動態隨機存取記憶體之上視圖。 圖5所繪示為圖4之v_v剖面的剖面圖。 圖6所綠示為圖4之VI-VI剖面的剖面圖。 圖7所繪不為圖4之VII-VII剖面的剖面圖。 【主要元件符號說明】 101 :主動區 105、409、411 :字元線 107 :介電層 109 :位元線接觸窗開口 111、431 :位元線接觸窗 113 :間隙 115 :空孔 200、400]基底 203、401 :隔離結構 403 :主動區 4〇5 :溝渠式電容器 407 :閘介電層 413、415 :字元線寬度 1343626 93103 2l747twf.doc/t 417 :寬部 419 :窄部 421、423 :間隙 425 :介電層 427 :空孔 429 :位元線接觸窗開口 430 :源極/汲極區1343626 93103 21747lwf.doc/t IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to an integrated body relating to a semiconductor device and a method of manufacturing the same, and in particular [Prior Art] ^ Electricity: the method of making the degree of integration must be improved, in addition to reducing the size of the semiconductor component to improve the integration of the conductor component itself, or J two; on the reduction of half will occur - some process problems, between the pieces Distance, after the width is reduced, the 'bit line contact window is in shape;, :::: Some questions about Pro. τ is in private view of Fig. 1 is a view of a conventional memory turn; Fig. 2 is a cross-sectional view of the middle edge of Fig. 1; Fig. 3 is a cross-sectional view taken along line ΠΙ·ΙΠ of Fig. 1.丨 and FIG. 2, the process of the memory device is formed by forming an isolation structure 2〇3 on the substrate 200, and after defining the active region 1〇1, forming word lines 1〇5 parallel to each other on the substrate 200. Then, a dielectric layer 1〇7 is deposited on the substrate 200, and a bit line is formed in the dielectric layer 〇7, and the touch window is opened σ靡 to expose the active region un, and finally to the bit line contact window. The opening 109 is filled with a polysilicon layer to form a bit line contact window 111. Since the size of the component is gradually reduced, the width of the word line 1〇t itself or the width of the space 113 between the word lines 105 must be reduced to achieve the goal of high integration. However, the word line 5 93103 21747 twf.doc/t element line 105, when the width of the gap 113 between them is reduced, will increase the aspect ratio of the gap. When the dielectric layer 7 is filled with the gap 113 having an increased aspect ratio, it is very easy to generate a tunnel-like key hole 115. The formation of such a tunnel-like void 115 causes the subsequently formed bit line contact opening 1〇9 to communicate with each other through the aperture j^, as shown in FIG. In addition, referring to Fig. 3, after the line width is reduced, the aspect ratio of the bit line contact window opening 109 is also increased. In order to make the polysilicon layer in the bit line contact opening 109 have good step coverage, chemical vapor deposition is often used to form the layer. However, the composite sand layer 1U having a good stepped Wei force will also provide a hole 115 which is electrically connected to the bit line contact opening 109, thereby causing two adjacent bit line contact windows m to pass through the conductor layer of the pure 115 towel. A short circuit has occurred. Therefore, how to avoid the formation of voids without changing the original line width and the size of the contact window opening has become an important issue to be solved. [Invention] The present invention is to provide a semiconductor component. The manufacturing method utilizes the width of the word line between the contact windows to make the gap between the word lines 曰 ^ to reach the short circuit between the evasive contact windows due to the communication of the holes, and then provide a short circuit. The "& body read" conductor element between the contact line of the sense line includes itself having a wide portion and a narrow portion. Sub-line, so that the gap between the word lines between the contact windows 93103 21747twf.doc / t 増 大美连接 causes a short circuit between the bit line contact windows. For the purpose of making the i, the method of manufacturing the conductor elements of the tree is T-first; the plurality of active areas are defined on the substrate into the first-character line and the second word line, and the cubic, base rising/active areas are interlaced, and respectively There are a large number of inter-pairs in which the mutual correspondences == correspond to a narrow gap between the wide portions; then in these narrow-openings, a plurality of source/no-polar regions; and then at the base position, the line touches: the gate The latter formed a plurality of bits in the dielectric layer of the narrow gap:: medium:: Γ and polar regions; and finally at these contact windows. The body (4) is recorded as a bit line ^ another - point of view, the present invention proposes a semiconductor component, the semiconductor = ϊ: the first word line and the second word line on the substrate, the first word number 徊The first-sub-twist line and the active area of the substrate are interlaced with each other, and each has a plurality of: = a wide gap 'the center of the wide portion corresponding to each other ^ a source/drain region is located in the base of the active regions of the narrow gaps , and is located on the substrate and covers the first-character line and the second word line; and the majority: the vertical, the line is connected to the _, the bit is fresh, the layer is electrically connected to the source/> Area. According to a preferred embodiment of the present invention, the semiconductor element of the pixel line contact window is avoided. The dielectric layer in the wide gap does not include 93103 21747 twf.doc/t (4) using the 5 xiao sub-elements themselves. Between the contact window, the width of the gap between the word and the word line can avoid the problem that the conventional technique is between the 7G line and the word line, and the gap is too small to cause the hole, so it can be avoided. The bit line is connected to the other, and other objects, features and advantages can be more apparent. The following is a detailed description of the preferred embodiment and the following description. [Embodiment] FIG. 4 is a top view of a dynamic random access memory with a deep trench capacitor according to a preferred embodiment of the present invention. 5, 6 and 7 are cross-sectional views taken along line v_v, νι νι, and grab-section, respectively, of Fig. 4. Referring also to item 4, Fig. 5 and Fig. 6, the isolation structure 401' in the substrate 4'' is used to define the active region 4?3 on the substrate 4. The formation method of the isolation structure 4〇1 may be, for example, a shallow trench isolation method (ST1). A trench capacitor 405 is formed in the substrate 4 (8). The trench capacitor 4〇5 can be fabricated in various known ways. A layer of gate dielectric layer 407 is formed on the substrate 4, and the material thereof is, for example, hafnium oxide. The method of formation is, for example, thermal oxidation. Next, a conductor layer is formed on the substrate 4A, and the conductor layer is patterned to form word lines 4〇9 and 411. In the word lines 409 and 411, the portion around the active area 4〇3 and the active area 403 whose word line width 413 maintains the line width of the original layout, and the portion between the two active areas 403, the characters thereof The line width 4]5 is slightly smaller than the line width of the original layout (i.e., the word line width 413). In other words, the character 93103 2l747twf.doc/t line 409 and the word line 411 have mutually wide 417 and narrow sides. The portion 4]9, wherein the wide portion 417 is a portion of the word line 409, 4 〗 1 spanning the active area 403 and the periphery of the active area 403; the narrow portion 4] 9 is farther away from the character line 409, 411 across the active area 4〇3 part. Therefore, the width of the gap 423 between the narrow portions 419 is larger than the width of the gap 421 between the wide portions 417. The material of the conductor layer of the word line 409 and the word line 411 is, for example, a polysilicon, and the method of forming the film is, for example, a chemical vapor deposition method. The pattern of the word lines 409, 411 can be directly designed through the reticle and then completed by the lithography and the engraving process. Thereafter, a source/drain region 430 is formed in the active region 403 of the substrate 400. A dielectric layer 425 is then formed over the substrate 400 to cover the word lines 409, 411 and the gaps 421 and 423 between the word lines 4 〇 9 and the word lines 411. The method of forming the dielectric layer 425, such as a borophosphon glass or a dielectric material having a dielectric constant of less than 4, may employ a chemical vapor deposition method. Since the gap 421 between the wide portions 417 has a width smaller than the width of the gap 423 between the narrow portions 419, the height and width of the gap 423 are smaller than the aspect ratio of the gap 42ι, and therefore, when the dielectric layer 425 covers the gap 423 The covering effect is better, and it is difficult to form voids, as shown in FIG. 5; and when the dielectric layer 4 covers the gap 421, even if the covering effect is poor, the void 427 as shown in FIG. 6 t is formed. The dielectric layer 425 formed in the gap 423 can also be blocked, so that the holes 427 formed in the gap 421 between the two adjacent wide portions 4丨7 are not turned on. Therefore, the process is performed. The Process Window is much larger than the Learner. Thereafter, referring to Figures 4 and 7, a bit line contact opening 429 is formed in the dielectric layer 1343626 93103 21747twf.doc/t 425 between the wide portions 417 to expose the surface of the substrate 400 of the active region 4. The bit line contact opening 429 may be in conduction with the via 427 in the dielectric layer 425 of the gap 421, but since the dielectric layer 425 formed between the narrow portions 419 has no voids, the two adjacent The bit line contact window openings 429 do not pass through each other through the holes 425. Next, a conductor material 431 is filled in the bit line contact opening 429 to form a bit line contact 431 electrically connected to the source/drain region 43 in the substrate 400. In order to increase the step coverage of the conductor material, a preferred method of forming the conductor material is, for example, chemical vapor deposition, and the mass is, for example, a complex (four). It is worth noting that the portion of the character line that is reduced in this implementation is located in the ugly section of the trench capacitor. However, it is not intended to limit the problem. The position where the width of the sub 7L line is reduced can be adjusted according to actual needs. In terms of the body, when the slavish word 7^ pattern of the present invention is used, the width of the word line between the two-phase and the line contact window is reduced to increase the two adjacent words=the lower the aspect ratio thereof. The contact openings of the wires are opened to each other and can be blocked by a dielectric layer that is connected without voids. Touching the window = condition T, the conventional solution has been disclosed. However, the present invention has been disclosed in the preferred embodiment as above, and is in the form of a singularity of the present invention. No - both 1343626 93103 21747twf.d〇c/t shall prevail. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a top view of a conventional memory element. 2 is a cross-sectional view of the IMI section of FIG. 3 is a cross-sectional view of the m_nI section of FIG. 1. 4 is a top view of a dynamic random access memory having a trench capacitor in accordance with a preferred embodiment of the present invention. FIG. 5 is a cross-sectional view showing the v_v section of FIG. 4. Green of Fig. 6 is a cross-sectional view taken along line VI-VI of Fig. 4. Figure 7 is a cross-sectional view taken along line VII-VII of Figure 4 . [Main component symbol description] 101: active region 105, 409, 411: word line 107: dielectric layer 109: bit line contact window opening 111, 431: bit line contact window 113: gap 115: hole 200, 400] Substrate 203, 401: isolation structure 403: active region 4〇5: trench capacitor 407: gate dielectric layer 413, 415: word line width 1343626 93103 2l747twf.doc / t 417: wide portion 419: narrow portion 421 423: gap 425: dielectric layer 427: void 429: bit line contact window opening 430: source/drain region