[go: up one dir, main page]

TWI342594B - Semiconductor chip and method for fabricating the same - Google Patents

Semiconductor chip and method for fabricating the same Download PDF

Info

Publication number
TWI342594B
TWI342594B TW096133089A TW96133089A TWI342594B TW I342594 B TWI342594 B TW I342594B TW 096133089 A TW096133089 A TW 096133089A TW 96133089 A TW96133089 A TW 96133089A TW I342594 B TWI342594 B TW I342594B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
layer
wafer structure
forming
metal
Prior art date
Application number
TW096133089A
Other languages
Chinese (zh)
Other versions
TW200814212A (en
Inventor
Mou Shiung Lin
Chiu Ming Chou
Original Assignee
Megica Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Megica Corp filed Critical Megica Corp
Publication of TW200814212A publication Critical patent/TW200814212A/en
Application granted granted Critical
Publication of TWI342594B publication Critical patent/TWI342594B/en

Links

Classifications

    • H10W72/012—
    • H10W74/15—
    • H10W90/724—
    • H10W90/734—

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

1342594 ' 九、發明說明： . 【發明所屬之技術領域】 ^ 本發明係關於一種本發明係為半導體晶片元件結構及 其製程，特別是關於一種具有聚合物凸塊的半導體晶片結 構及其製程。 【先前技術】 % 一般而言，習知技術使用金作為導電凸塊。然而，使 用金作為導電凸塊之缺點則係當半導體基板和玻璃基板使 用異方向性導電膠接合時，在加熱固化異方向性導電膠的 ， 製程中’容易因為半導體基板和玻璃基板的熱膨脹係數之 , 不同，在固化冷卻後產生相當大的收縮應力。而金屬材質 之導電凸塊之彈性緩衝力不佳，也因此造成半導體基板和 玻璃基板的變形，形成光折射不均勻的現象。另外使用金 作為導電凸塊還的物料價格昂貴之缺點，使得製造之成本 _ 無法降低。 另外當電極之間距愈來愈小時，導電凸塊和電極間之 構裝技術亦向小間隔（fine pitch)的構裝技術發展》為增加 • 導電凸塊之導電粒子之捕捉數，需使用更多導電粒子數目 之異方向性導電膠（ACF)，用來做垂直方向的導通，但在 小間隔的情況時，兩相鄰的導電凸塊容易因為導電粒子之 聚集’而產生導電凸塊間的短路。 有鑑於此，本發明係針對上述之問題，提出一種晶片 6 1342594 元件之製程及其結構，有效克服習知技術之困擾。 - 【發明内容】 .· 本發明之主要目的，係在提供一種半導體晶片元件結 構及其製程，利用聚合物凸塊取代現有之金屬凸塊，以大 幅減少材料成本。 本發明之另一目的，係在提供一種半導體晶片元件結 構及其製程，改善兩相鄰的導電凸塊因導電粒子之聚集， # 而產生導電凸塊間的短路之缺點。 為了本發明上述之目的’提出一種半導體晶片元件結 構，一半導體基底，該半導體基底上包括至少一主動元件； ，一細連線結構，位在該半導體基底及該主動元件上，該細 . 連線結構包括複數個厚度小於3微米之介電層及複數個厚 度小於3微米之細線路層位於該半導體基底上，且該些介 電層具有多數個通道孔，該些細線路層係位於該些介電層 其中之一上’其中該些細線路層藉由該些通道孔彼此電性 ® 連接，該些細線路層包括至少一金屬接墊；一保護層，位 在該半導體基底上，該保護層具有至少一開口曝露出該金 屬接墊；一聚合物凸塊，位在該保護層上及該主動元件上 ， 方；一黏著阻障層，位在該保護層、該聚合物凸塊及該金 • 屬接墊上’該黏著阻障層包覆該聚合物凸塊之至少二表 面；一種子層’位在該黏著阻障層上；一金屬層，位在該 種子層上’該金屬層與該種子層相同材質，且經由位在該 聚合物凸塊頂面上之該金屬層可連接至一外界電路。1342594' IX. Description of the Invention: 1. Field of the Invention The present invention relates to a semiconductor wafer element structure and a process thereof, and more particularly to a semiconductor wafer structure having polymer bumps and a process therefor. [Prior Art] % In general, conventional techniques use gold as a conductive bump. However, the disadvantage of using gold as a conductive bump is that when the semiconductor substrate and the glass substrate are bonded using an anisotropic conductive paste, in the process of heating and curing the anisotropic conductive paste, it is easy to be because of the thermal expansion coefficient of the semiconductor substrate and the glass substrate. Differently, a considerable shrinkage stress is generated after solidification cooling. On the other hand, the conductive bumps of the metal material have poor elastic buffering force, and thus the semiconductor substrate and the glass substrate are deformed to form uneven light refraction. In addition, the use of gold as a conductive bump is also a disadvantage of expensive materials, so that the cost of manufacturing cannot be lowered. In addition, when the distance between the electrodes is getting smaller and smaller, the mounting technology between the conductive bumps and the electrodes is also developed to the fine pitch structure technology to increase the number of conductive particles of the conductive bumps. The number of conductive particles (ACF) of the number of conductive particles is used to conduct conduction in the vertical direction, but in the case of small intervals, two adjacent conductive bumps are likely to be formed between the conductive bumps due to the accumulation of conductive particles. Short circuit. In view of the above, the present invention is directed to the above problems, and proposes a process for fabricating the components of the wafer 6 1342594 and its structure, effectively overcoming the problems of the prior art. - SUMMARY OF THE INVENTION The main object of the present invention is to provide a semiconductor wafer component structure and a process thereof, which use polymer bumps instead of existing metal bumps to substantially reduce material cost. Another object of the present invention is to provide a semiconductor wafer device structure and a process thereof for improving the shortcomings of conductive bumps between two adjacent conductive bumps due to the accumulation of conductive particles. In order to achieve the above object of the present invention, a semiconductor wafer device structure is proposed, a semiconductor substrate including at least one active component, and a thin wiring structure on the semiconductor substrate and the active component. The wire structure includes a plurality of dielectric layers having a thickness of less than 3 micrometers and a plurality of thin circuit layers having a thickness of less than 3 micrometers on the semiconductor substrate, and the dielectric layers have a plurality of via holes, wherein the thin circuit layers are located On one of the dielectric layers, wherein the thin circuit layers are electrically connected to each other by the via holes, the fine circuit layers include at least one metal pad; a protective layer is disposed on the semiconductor substrate, the protective layer Having at least one opening exposing the metal pad; a polymer bump on the protective layer and the active component; an adhesive barrier layer positioned on the protective layer, the polymer bump, and the On the gold susceptor pad, the adhesive barrier layer covers at least two surfaces of the polymer bump; a sub-layer is positioned on the adhesive barrier layer; and a metal layer is located on the seed The metal layer on the layer is the same material as the seed layer and is connectable to an external circuit via the metal layer on the top surface of the polymer bump.

J 7 1342594 為了本發明上述之目的，提出一種半導體晶片元件結 構’一半導體基底，該半導體基底上包括至少一主動元件； 一細連線結構，位在該半導體基底及該主動元件上，該細 連線結構包括複數個厚度小於3微米之介電層及複數個厚 度小於3微米之細線路層位於該半導體基底上，且該些介 電層具有多數個通道孔，該些細線路層係位於該些介電層 其中之一上，其令該些細線路層藉由該些通道孔彼此電性 連接，該些細線路層包括至少一金屬接墊；一保護層，位 在該半導體基底上，該保護層具有至少一開口曝露出該金 屬接墊；一聚合物凸塊，位在該保護層及該金屬接墊上， 並暴露出該金屬接塾表面之一導電區域；一黏著阻障層， 位在該保護層、該聚合物凸塊及該導電區域上，該黏著阻 障層包覆該聚合物凸塊之至少二表面；一種子層，位在該 黏著阻障層上；一金屬層，位在該種子層上，該金屬層與 該種子層相同材質，且經由位在該聚合物凸塊頂面上之該 金屬層可連接至一外界電路。 為了本發明上述之目的，提出一種半導體晶片元件製 程，其製程包括提供一半導體基底，該半導體基底包括至 少一金屬接墊、一細連線結構及一保護層，該保護層位在 該半導體基底上，該保護層具有至少一開口曝露出該細連 線結構之一金屬接墊；形成圖案化之一聚合物凸塊在該保 護層及該金屬接墊上，暴露出該金屬接墊表面之一導電區 域，形成一黏著阻障層在該導電區域、該聚合物凸塊及該 保護層上；形成一種子層在該黏著阻障層上；形成一圖案 8 1342594 化光阻層在該種子層上，該圖案化光阻層之m露出 部分該聚合物凸塊及該導電區域上之該種子層；形成一金 層層在該開σ内之該種子層及該圖案化光阻層上；以研磨 方式移除位在該圖案化光阻層上之該金屬層；移除該圖案 化光阻層；移除未在該金屬層下方之該種子層及該黏著阻 障層。 底下藉由具體實施例配合所附的圖式詳加說明，當更 谷易瞭解本發明之目的、技術内容、特點及其所達成之功 效。 【實施方式】 本發明係為半導體晶片元件結構及其製程，其中在 此發明之中揭露數種不同類型的半導體晶片元件結構及 其製程’所揭露的每一種方法及結構皆是建構在一半導 體基底上，且在此半導體基底上更設有一細連線結構及 一保護層，因此首先解說此半導體基底、細連線結構及 保護層之結構及形成方法後，再進行本發明各種實施例 的解說’另外在解說之前先定義「上方」—詞在本發明 中是表示位在某物上面並與之接觸，或是表示位在某物 上面但未與之接觸，而「上」一字在本發明中是表示位 在某物上面並與之接觸。 半導體基t: 請參閱第la圖所示’提供一基底（substrate)lO，基底 1342594 10通常是為一石夕基底（silicon substrate)，此石夕基底可以是 一本質（intrinsic)i夕基底、一 p型石夕基底或是一 η型>6夕基 底。對於高性能的晶片，則是使用矽鍺（SiGe)或絕緣層上 覆石夕（Silicon-On-Insulator，SOI)基底。其中，石夕錯基底包 括一石夕錯附生層（epitaxial layer)在石夕基底的表面上，另絕 緣層上覆矽基底則包括一絕緣層（較佳為氧化矽）在一矽基 底上，且一矽或矽鍺附生層形成在絕緣層上。 接者清參閱第lb圖所不，在此基底10上形成一元件 層（device layer) 12，此元件層12通常包括至少一半導體元 件（semiconductor device)，此半導體元件包括至少一主動 元件，且此元件層12是在基底10的表面内以及/或是表面 上。其中，半導體元件可以是一金氧半電晶體（MOS transistor)14，例如 N 型金氧半電晶體（NMOS transistor， n-channel MOS transistor)或 P 型金氧半電晶體（PMOS transistor，p-channel MOS transistor)，且此金氧半電晶體 14包括一源極16、一汲極18與一閘極20，而閘極20通 常是為一多晶矽（poly silicon)、一複晶金屬石夕化鎢（tungsten polycide)、一矽化鎢（tungsten silicide)、一石夕化鈦（titanium silicide)、一钻化石夕（cobalt silicide)或一石夕化物閘極 (salicide gate)。另，半導體元件亦可以是雙載子電晶體 (bipolar transistor)、擴散金屬氧化物半導體（Diffused MOS，DMOS)、橫向擴散金屬氧化物半導體（Lateral Diffused MOS，LDMOS)、電荷耦合元件（Charged-Coupled Device，CCD)、互補式金屬氧化物半導體（CMOS)感測元 10 1342594 件、光敏二極體（photo-sensitive diode)、電阻元件（由在石夕 基底内之多晶矽層或擴散區所形成）。利用這些半導體元件 可以形成各種電路，例如互補式金屬氧化物半導體（CMOS) 電路、N型金氧半導體電路、P型金氧半導體電路、雙載 子互補式金屬氧化物半導體(BiCMOS)電路、互補式金屬氧 化物半導體感測器電路、擴散金屬氧化物半導體電源電 路、橫向擴散金屬氧化物半導體電路等。此外，元件層12 也包括一反或閘（NOR gate)或一反及閘（NAND gate)之 外，亦可以是一反相器（inverter)、一且閘（AND gate)、一 或閘（OR gate)、一靜態隨機存取記憶體單元（SRAM cell)、 一動態隨機存取記憶體單元（DRAM cell)、一非揮發性記憶 體單元（non-volatile memory cell)、一快閃記憶體單元 (flash memory cell)、一可消除可程式唯讀記憶體單元 (EPROM cell)、一唯讀記憶體單元(ROM cell)、一磁性隨 機存取記憶體（magnetic RAM，MRAM)單元、一感測放大 器（sense amplifier)、一運放算大器（operational amplifier， Op Amp、OPA)、一 加法器（adder)、一 多工器（multiplexer)、 一雙工器（diplexer)、一乘法器（multiplier)、一類比/數位轉 換器（A/D converter)、一數位 /類比轉換器（D/A converter)、 一互補式金屬氧化物半導體感測元件單元（CMOS sensor cell)、一光敏二極體（photo-sensitive diode)、一互補式金屬 氧化物半導體、一雙載子互補式金氧半導體、一雙載子電 路（bipolar circuit)或類比電路（analog circuit)。 細連線結構. 11 1342594 請參閱第lc圖所示，在基底10及元件層12上形成一 細線路結構22，此細線路結構22包括複數細線路層 (fine-line conductivity layer)24、複數細線路介電層 (fine-line dielectric layer)26以及複數在細線路介電層26 之開口 28、及開口 28内的導電栓塞（fine-line via piug)30’ 此外在最頂部之細線路層24可至少一或複數區域，這些區 域定義為接墊32。 細線路層24在此實施例中係選自鋁金屬材質、銅金屬 材質，或更具體來說，可以是以濺鍍方式形成的鋁層、或 以鑲嵌方式形成的銅層。所以，細線路層24可以是：（1) 所有的細線路層24均為鋁層；（2)所有的細線路層24均為 銅層；（3)底層的細線路層24為鋁層，而頂層的細線路層 24為銅層；或是（4)底層的細線路層24為銅層，而頂層的 細線路層24為鋁層。 此外，每一細線路層24的厚度係介於0.05微米（μιη) 至2微米之間，而以介於0.2微米至1微米之間的厚度為 較佳者，另細線路層24若為線路，則其橫向設計標準（寬 度）係介於20奈米（nano-meter)至15微米之間，並以介於 20奈米至2微米之間為較佳者。 首先解說細線路層24為鋁層，細線路層24之鋁層通 常是利用物理氣相沉積（Physical Vapor Deposition，PVD) 的方式來形成，例如利用減鍵（sputtering)的方式來形成， 接著透過沈積厚度介於0.1微米至4微米之間（較佳為介於 0.3微米至2微米之間）的一光阻層對此鋁層進行圖案化， 12 1342594 再來對此銘層進行一渔姓刻（wet etching)或一乾餘刻（dry etching)，較佳的方式是為乾式電聚（dry plasma)钮刻（通常 包含氟電漿）。另，在鋁層下可選擇性形成一黏著/阻障層 (adhesion/barrier layer)，其中此黏著/阻障層可以是鈦、欽 鎢合金、氮化鈦或者是上述材料所形成之複合層；而在鋁 層上亦可選擇性形成一抗反射層（例如氮化鈦P此外，開 口 28可選擇性以化學氣相沉積（chemical vapor deposition，CVD)鎢金屬的方式填滿，接著再以化學機械 研磨（chemical mechanical polish，CMP)的方式研磨鶴金屬 層，以形成導電栓塞30。 接著解說細線路層24為銅層，細線路層24之銅層通 常是利用電鑛與鑲嵌製程（damascene process)的方式來形 成，其敘述如下：（1)沈積一銅擴散阻障層（例如厚度介於 0.05微米至0.25微米之間的氮氧化合物層或氮化物層）； (2)利用電製辅助化學氣相沈積（plasma enhanced CVD， PEC VD)、旋轉塗佈（Spin_on coating)或高密度電漿化學氣 相沉積（High Density Plasma CVD，HDPCVD)的方式沈積 厚度介於〇·1微米至2.5微米之間的一細線路介電層26， 其中此細線路介電層26是以介於0.3微米至1.5微米之間 的厚度為較佳者；（3)利用沈積厚度介於〇.1微米至4微米 之間的一光阻層來圖案化細線路介電層26,其中光阻層的 厚度又以介於0.3微米至2微米之間為較佳者，接著對此 光阻層進行曝光與顯影，使光阻層形成複數開口以及/或是 複數溝渠’再來去除此光阻層；（4)利用濺鍍或化學氣相沈 13 1342594 積的方式，沈積一黏著/阻障層與一種子層（seedlayer)。其 中，此黏著/阻障層包括钽、氮化钽、氮化鈦、鈦或鈦鎢合 金，或者是由上述材料所形成之一複合層。另外，此種子 層通常是一銅層，而此銅層可以是利用濺鍍銅金屬、化學 氣相沈積銅金屬，或者是先以化學氣相沈積一銅金屬，然 後再濺鍍一銅金屬的方式形成；（5)電鍍厚度介於〇〇5微 米至2微米之間的一銅層在此種子層上，其中又以電鍍銅 層厚度介於0.2微米至1微米之間的一銅層為較佳者；（6) 以研磨（較佳的方式為化學機械研磨）晶圓的方式去除未在 細線路介電層26之開口或溝渠内的銅層、種子層以及黏著 /阻障層，直至暴露出位在黏著/阻障層下之細線路介電層 26為止。在經過化學機械研磨之後，僅剩下位在開口或溝 渠内的金屬，而剩下的金屬則用來作為金屬導體（線路或是 平面）或導電栓塞30(連接兩相鄰的細線路層24)0另外’ 亦可利用一雙鑲嵌（double-damascene)製程，於一次電鍵製 程與一次化學機械研磨中同時形成導電栓塞3〇以及金屬 線路或金屬平面。兩次微影（photolithography)製程及兩次 電鍍製程係適用於雙鑲嵌製程上。雙鑲嵌製程在上述單次 鑲嵌製程中的圖案化一介電層之步驟與沈積金屬層之 步驟（4)間，增加更多沈積與圖案化另一介電層的製程步 驟。 接著說明細線路介電層26，細線路介電層26係利用 化學氣相沈積、電漿輔助化學氣相沈積、高密度電漿化學 氣相沉積或旋塗（spin_on)的方式形成。細線路介電層26的 14 1342594 材質包括氧化石夕（silicon oxide)、氮化石夕（silicon nitride)、 氮氧化碎（silicon oxynitride)、以電漿輔助化學氣相沈積形 成之四乙氧基矽烷（PECVD TEOS)、旋塗玻璃（SOG，矽氧 化物或石夕氧烧基）、敦石夕玻璃（Fluorinated Silicate Glass， FSG)或一低介電常數（low-K)材質，例如黑鑽石薄膜（Black Diamond，其係為Applied Materials之產品，公司譯名為 應用材料公司）、ULK CORAL(為Novellus公司之產品）或 SiLK(IBM公司）之低介電常數的介電材質。以電聚輔助化 學氣相沈積形成的氧化矽、以電漿輔助化學氣相沈積形成 的四乙氡基矽烷或以高密度電漿形成的氡化物具有介於 3.5至4.5之間的介電常數K;以電漿輔助化學氣相沈積形 成的氟矽玻璃或以高密度電漿形成的氟矽玻璃具有介於 3.0至3.5之間的介電常數值，而低介電常數介電材料則具 有介於1.5至3,5之間的介電常數值。低介電常數介電材 料，例如黑鑽石薄膜，其係為多孔性，並包括有氫、碳、 矽與氧，其分子式為HwCxSiyOz。此細線路介電層26通常 包括無機材料（inorganic material)。每一細線路介電層26 的厚度係介於0.05微米至2微米之間。另，細線路介電層 26内的開口 28是利用溼蝕刻或乾蝕刻的方式蝕刻圖案化 光阻層形成，其中較佳的蝕刻方式係為乾蝕刻。乾蝕刻種 類包括氟電楽_ (fluorine plasma)。 保謨層: 請參閱第lc圖所示，形成一保護層34在細線路結構 22上，此保護層34在本發明中扮演著非常重要的角色。 15 1342594 保護層34在積體電路產業中是為一個重要的組成部分，如 1990 年由 S. Wolf 著，並由 Lattice Press 所發行之“Silicon Processing in the VLSI era”第2冊所述，保護層34在積體 電路製程中是被定義作為最終層，並沈積在晶圓的整體上 表面上。保護層34係為一絕緣、保護層，可以防止在組裝 與封裝期間所造成的機械與化學傷害。除了防止機械刮痕 之外，保護層34也可以防止移動離子（mobile ion)，比如 是納（sodium)離子，以及過渡金屬（transition metal)，比如 是金、銅，穿透進入至下方的積體電路元件。另外，保護 層34也可以保護下方的元件與連接線路（細線路金屬結構 與細線路介電層）免於受到水氣（moisture)的侵入。 保護層34通常包括一氮化石夕（silicon nitride)層以及/ 或是一氮氧化矽（sUicon oxynitride)層，且其厚度是介於〇·2 微米至1.5微米之間，並以介於0.3微米至1.0微米之間的 厚度為較佳者。其它使用在保護層300的材料則有以電漿 輔助化學氣相沈積形成的氧化矽、電漿加強型二氧化四乙 基正石夕酸鹽（plasma-enhanced tetraethyl orthosilicate， PETEOS)之氧化物、碟石夕玻璃（phosphosilicate glass， PSG)、硼填矽玻璃（borophospho silicate glass，BPSG)、以 高密度電漿（HDP)形成的氧化物。接著，敘述保護層34由 複合層組成的一些範例，其底部至頂部的順序是為： 厚度介於0.1微米至1.0微米之間（較佳厚度則介於〇 3微 米至0.7微米之間）的氧化物/厚度介於〇 25微米至12微 米之間（較佳厚度則介於0.35微米至1.〇微米之間）的氮化 16 1342594 矽，這種型式的保護層34通常是覆蓋在以鋁形成之金屬連 接線路上，其中以鋁形成之金屬連接線路通常包括濺鍍鋁 及蝕刻鋁的製程；（2)厚度介於〇 〇5微米至〇 35微米（較佳 厚度則介於0.1微米至〇.2微米之間）的氮氧化合物/厚度介 於〇.2微米至1.2微米（較佳厚度則介於〇‘1微米至〇 2微 米之間）的氧化物/厚度介於〇2微米至12微米（較佳厚度 則介於0.3微米至0.5微米之間）的氮化物/厚度介於〇2微 米至1.2微米（較佳厚度則介於〇 3微米至〇 6微米之間）的 氧化物’這種型式的保護層34通常是覆蓋在以銅形成之金 屬連接線路上，其中以銅形成之金屬連接線路通常包括電 鍍、化學機械研磨與鑲嵌製程。另，上述兩範例中的氧化 物層可以是利用電漿輔助化學氣相沈積形成的氧化矽、電 漿加強型二氧化四乙基正矽酸鹽（plasmaenhanced tetraethyl orthosilicate ’ PETE〇s)之氧化物、利用高密度電 漿形成的氧化物。以上的内容係適用於本發明的所有實施 例中。 請參閲第id圖所示，在此保護層34形成至少一開口 此保”蔓層34之開口 36是利用渔飯刻或乾飯刻的方式 七成/、中又以乾敍刻為較佳方式。此外，開口 36的尺寸 係介於0.1微米至200微米之間，並以介於i微米至_ 微求之間或5微米至30微米之間為較佳者，另開口刊的 形狀可以疋圓形、正方形、長方形或多邊形所以上述開 口 36的尺寸是指圓形的直徑尺寸、正方形的邊長尺寸、多 邊形的最長對角線尺寸或長方形的寬度尺寸，其中長方形 17 1342594 的長度尺寸則是介於1微米至i釐米，並以介於5微米至 200微米為較佳者。 其中保護層34之開口 36對於元件層12所設置元件不 同也有不同的大小，一般而言保護層34之開口 36的尺寸 疋介於0.1微米至1〇〇微米之間’並以介於〇 3微米至3〇 微米之間為較佳者；若是元件層丨2中係設置穩壓器、變壓 器及靜電放電防護電路而言，此開口 36的尺寸較大，其範 圍係介於1微米至150微米之間，並以介於5微米至1〇〇 微米之間為較佳者。另外，開口 36暴露出細線路層24最 上層之接墊（metal pad)32，用以電性連接保護層％上方 (over-passivation)的線路或平面。 以上所述之結構定義為晶圓（wafer)，例如石夕晶圓 (silicon wafer)，係使用不同世代的積體電路製程技術來製 造’例如1微米、0.8微米、〇.6微米、〇·5微米、0.35微 米、0.25微米、0.18微米、0.25微米、0.13微米、90奈米 (nm)、65奈米、45奈米、35奈米、25奈米技術，而這些 積體電路製程技術的世代是以金氧半電晶體14之閘極長 度（gate length)或有效通道長度（Channei iength)來定義。 晶圓的尺寸大小比如是5吋、6吋、8对、12忖或18 吋等。基底10係使用微影製程來製作，此微影製程包含塗 佈（coating)、曝光（exposing)以及顯影（devei〇ping)光阻。用 於製作基底10的光阻，其厚度是介於〇1微米至〇4微米 之間，並以五倍（5X)步進曝光機（stepper)或掃描機（scanner) 曝光此光阻。其中，步進曝光機的倍數是指當光束從一光 18 1342594 罩（通常是以石英構成）投影至晶圓上時，光罩上之圖形縮 小在晶圓上的比例，而五倍（5X)即是指光罩上之圖案比例 是為晶圓上之圖案比例的五倍。使用在先進世代的積體電 路製程技術上的掃描機，通常是以四倍（4X)尺寸比例縮小 來改善解析度。步進曝光機或掃描機所使用的光束波長係 為436奈米（g-nne)、365奈米（i-line)、248奈米（深紫外光， DUV)、193 奈米（DUV)、157 奈米（DUV^ 13.5 奈米（極短 紫外光，EUV)。另，高索引侵潤式（high_index immersi〇n) 微影技術亦可用以完成晶圓上的細線路層24。 此外’晶圓是在具有等級l〇(class 1〇)或更佳（例如等 級1)的無塵室（clean room)中製作。等級10的無塵室允許 每立方英呎之最大灰塵粒子數目係為：含有大於或等於i 微米之灰塵粒子不超過1顆、含有大於或等於〇 5微米之 灰塵粒子不超過1〇顆、含有大於或等於〇 3微米之灰塵粒 子不超過30顆、含有大於或等於〇2微米之灰塵粒子不超 過75顆、含有大於或等於〇1微米之灰塵粒子不超過 顆，而等級1的無塵室則允許每立方英呎之最大灰塵粒子 數目是為：含有大於或等於〇5微米之灰塵粒子不超過1 顆3有大於或等於0.3微米之灰塵粒子不超過3顆、含 有大於或等於0.2微米之灰塵粒子不超過7顆、含有大於 或等於0.1微米之灰塵粒子不超過35顆。 其中當使用銅作為細線路層24時，則需要使用一金屬 頂層（metal cap)(圖中未示）來保護保護層34開口 ％所暴露 出銅質之接墊32’使此接墊32免於受到氧化而侵蝕損壞， 1342594 並可作為後續晶片的打線接合。此金屬頂層包括一鋁 (aluminum)層、一金（gold)層、一鈦（Ti)層、一鈦鎢合金層' 一鈕（Ta)層、一氮化鈕（TaN)層或一鎳（Ni)層。其中，當金 屬頂層是為一鋁層時，則在銅接墊與金屬頂層之間形成有 一阻障層（barrier layer)，而此阻障層包括鈦、鈦鎢合金、 氮化鈦、钽、氮化钽、鉻（Cr)或鎳。 上述為本發明半導體基底10、細連線結構22及保護 層34的解說，以下解說本發明數種不同類型之實施例，本 發明之實施例係為製造一保護層上之結構 (over-passivation scheme)及製程，在本發明中保護層上之 結構包括有堆疊式的封裝、聚合物凸塊的貼帶自動接合 (tape automated bonded,TAB) 、 C0G(chip on glass)、捲 帶式晶粒接合（Tape Carrier Package，TCP)、C0F(chip on film)的封裝方式，以及利用聚合物凸塊以覆晶（FI ip Chip, FC )技術接合至另一外界基板上，以下分別解說各個 實施例之結構及製程。 另外以下所解說之實施例有許多部分之材質 及製程相同，因此以下各實施例及態樣中的相同元件之 材質及製程就不加以重覆說明，例如以下之實施例中的 接墊32係為鋁材質之接墊作為說明，但是接墊32 之材質也可以係為銅，差別在於當接墊32的材質包 括有銅金屬時，須使用一金屬頂層（例如鋁層）來保護層 34開口 36所暴露出之含有銅金屬的接墊32,讓含有銅金 屬的接墊32免於受到氧化而侵蝕損壞。而當金屬頂層為一 20 1342594 銘層時’在接塾32與铭層之間形成有-阻障層(barrier layer)’此阻障層包括鈦、欽鶴合金、氮化鈦、纽、氣化 组、絡（Cr)或錄。底下内容係以沒有金屬頂層的情沉進行 說明，然熟習該技術者當可藉由下列實施例的說明，以加 入金屬頂層的方式據以實施。 第1實施例之笫1能样： 此實施例之結構中基底1()、元件層12、金氧半電晶雜 14、源極16、汲極18、閘極2〇、細線路結構22、細線路 介電層26、導電栓塞3〇等以積體電路1〇〇代替，且積體 電路100中的各結構及製程在上述實施已完整說明，因此 實施例中的積體電路1〇〇中的各結構及製程就不加以重覆 說明。 請參閱第2a圖所示，形成一聚合物層112在整個積體 電路100上的保護層34及接墊32上。 請參閱第2b圖所示，並透過曝光（exp〇sure)、顯影 (development)製程及蝕刻製程圖案化此聚合物層112，使 此聚合物層112形成複數聚合物凸塊（p〇lymer bump) 114(圖示中僅顯示出1個），而保護層34及接塾32 暴露於外，接著進行加熱硬化，使此聚合物凸塊114硬化， 此硬化過程的溫度係介於150度（°C )至300度（〇C )之間， 且此聚合物凸塊114之材質可選自聚酿亞胺（poiyimide， PI)、苯基環丁稀（benzocyclobutene，BCB)、聚對二甲苯 (parylene) ' 環氧基材料（epoxy-based material)其中之 21 1342594 一 ’例如環氧樹脂或是由位於瑞士之Renens的SotecJ 7 1342594 for the above purpose of the present invention, a semiconductor wafer device structure 'a semiconductor substrate comprising at least one active component; a thin wiring structure on the semiconductor substrate and the active component, the fine The wiring structure includes a plurality of dielectric layers having a thickness of less than 3 micrometers and a plurality of thin circuit layers having a thickness of less than 3 micrometers on the semiconductor substrate, and the dielectric layers have a plurality of via holes, wherein the thin circuit layers are located And one of the dielectric layers, wherein the thin circuit layers are electrically connected to each other by the via holes, the fine circuit layers comprise at least one metal pad; and a protective layer is disposed on the semiconductor substrate, the protection The layer has at least one opening exposing the metal pad; a polymer bump located on the protective layer and the metal pad, and exposing a conductive region of the metal interface surface; an adhesive barrier layer, located at The protective layer, the polymer bump and the conductive region, the adhesive barrier layer covers at least two surfaces of the polymer bump; a sub-layer is located at the adhesive layer A barrier layer; a metal layer disposed on the seed layer, the metal layer is the same material as the seed layer and the metal layer via a bit in a top surface of the polymer bumps may be connected to a external circuit. For the above object of the present invention, a semiconductor wafer device process is provided, the process comprising: providing a semiconductor substrate comprising at least one metal pad, a thin wiring structure and a protective layer on the semiconductor substrate The protective layer has at least one opening exposing one of the metal wiring pads of the thin wiring structure; forming a patterned polymer bump on the protective layer and the metal pad to expose one of the metal pad surfaces a conductive region forming an adhesive barrier layer on the conductive region, the polymer bump and the protective layer; forming a sub-layer on the adhesive barrier layer; forming a pattern 8 1342594 photoresist layer in the seed layer The m of the patterned photoresist layer exposes a portion of the polymer bump and the seed layer on the conductive region; forming a gold layer on the seed layer and the patterned photoresist layer in the opening σ; Removing the metal layer on the patterned photoresist layer by grinding; removing the patterned photoresist layer; removing the seed layer and the adhesion barrier layer not under the metal layer. The details, technical contents, features, and effects achieved by the present invention will be apparent from the detailed description of the embodiments and the accompanying drawings. [Embodiment] The present invention is a semiconductor wafer device structure and a process thereof, wherein each of the methods and structures disclosed in the disclosure of several different types of semiconductor wafer device structures and processes are constructed in a semiconductor A thin wiring structure and a protective layer are further disposed on the substrate, and therefore, the structure and the forming method of the semiconductor substrate, the thin wiring structure and the protective layer are first explained, and then various embodiments of the present invention are performed. Explain 'Before defining the "above" before the explanation - the word in the present invention means that it is on or in contact with something, or that it is on something but not in contact with it, and the word "up" is in In the present invention, it is meant to be placed on and in contact with something. Semiconductor base t: Please refer to the figure la to provide a substrate 10, the substrate 1342594 10 is usually a silicon substrate, which can be an intrinsic i-base, a The p-type Shi Xi base or an n-type > 6 eve substrate. For high performance wafers, a germanium (SiGe) or a silicon-on-insulator (SOI) substrate is used. Wherein, the core substrate comprises an epitaxial layer on the surface of the base of the stone, and the base of the insulating layer comprises an insulating layer (preferably yttrium oxide) on a substrate. And an epiphytic layer is formed on the insulating layer. Referring to FIG. 1b, a device layer 12 is formed on the substrate 10. The device layer 12 generally includes at least one semiconductor device including at least one active device. This element layer 12 is in the surface of the substrate 10 and/or on the surface. The semiconductor component may be a MOS transistor 14, such as an NMOS transistor (n-channel MOS transistor) or a P-type MOS transistor (p-type). Channel MOS transistor), and the MOS transistor 14 includes a source 16, a drain 18 and a gate 20, and the gate 20 is usually a poly silicon, a polycrystalline metal Tungsten polycide, tungsten silicide, titanium silicide, a cobalt silicide or a salicide gate. In addition, the semiconductor device may also be a bipolar transistor, a diffused metal oxide semiconductor (DMOS), a laterally diffused metal oxide semiconductor (LDMOS), and a charge coupled device (Charged-Coupled). Device, CCD), Complementary Metal Oxide Semiconductor (CMOS) sensing element 10 1342594, photo-sensitive diode, resistive element (formed by a polysilicon layer or diffusion region in the base of the Shixi) . Various semiconductor circuits can be used to form various circuits such as a complementary metal oxide semiconductor (CMOS) circuit, an N-type MOS circuit, a P-type MOS circuit, a bi-carrier complementary metal-oxide-semiconductor (BiCMOS) circuit, and a complementary circuit. Metal oxide semiconductor sensor circuit, diffusion metal oxide semiconductor power supply circuit, laterally diffused metal oxide semiconductor circuit, and the like. In addition, the component layer 12 also includes a NOR gate or a NAND gate, and may also be an inverter, an AND gate, or a gate (an AND gate). OR gate), a static random access memory cell (SRAM cell), a dynamic random access memory cell (DRAM cell), a non-volatile memory cell, a flash memory Flash memory cell, an erasable read only memory cell (EPROM cell), a read only memory cell (ROM cell), a magnetic random access memory (MRAM) cell, a sense A sense amplifier, an operational amplifier (Op AOP, an OPA), an adder, a multiplexer, a diplexer, a multiplier ( Multiplier), a class of analog/digital converter (A/D converter), a digital/analog converter (D/A converter), a complementary MOS sensor cell, a photodiode Photo-sensitive diode, a complementary gold An oxide semiconductor, a pair of carriers complementary metal oxide semiconductor, a pair of carrier circuits (bipolar circuit) or the analog circuit (analog circuit). Thin wiring structure. 11 1342594 Referring to FIG. 1c, a thin circuit structure 22 is formed on the substrate 10 and the element layer 12. The thin circuit structure 22 includes a fine-line conductivity layer 24, a plurality a fine-line dielectric layer 26 and a plurality of openings 28 in the fine-line dielectric layer 26 and a fine-line via piug 30' in the opening 28 24 may be at least one or a plurality of regions defined as pads 32. The thin wiring layer 24 is selected from the group consisting of an aluminum metal material, a copper metal material, or more specifically, an aluminum layer formed by sputtering or a copper layer formed in a damascene manner in this embodiment. Therefore, the fine circuit layer 24 may be: (1) all of the fine circuit layers 24 are aluminum layers; (2) all of the fine circuit layers 24 are copper layers; and (3) the fine circuit layer 24 of the bottom layer is an aluminum layer. The fine circuit layer 24 of the top layer is a copper layer; or (4) the fine circuit layer 24 of the bottom layer is a copper layer, and the fine circuit layer 24 of the top layer is an aluminum layer. In addition, each thin circuit layer 24 has a thickness of between 0.05 micrometers (μm) and 2 micrometers, and a thickness of between 0.2 micrometers and 1 micrometer is preferred, and the thinner wiring layer 24 is a circuit. The lateral design standard (width) is between 20 nanometers and 15 micrometers, and preferably between 20 nanometers and 2 micrometers. First, the thin circuit layer 24 is an aluminum layer, and the aluminum layer of the thin circuit layer 24 is usually formed by physical Vapor Deposition (PVD), for example, by means of sputtering, and then transmitted. Depositing a layer of aluminum with a photoresist layer having a thickness between 0.1 micrometers and 4 micrometers (preferably between 0.3 micrometers and 2 micrometers), 12 1342594 Wet etching or dry etching, preferably in the form of a dry plasma (commonly containing fluorine plasma). In addition, an adhesion/barrier layer may be selectively formed under the aluminum layer, wherein the adhesion/barrier layer may be titanium, a tungsten alloy, titanium nitride or a composite layer formed by the above materials. An anti-reflective layer may also be selectively formed on the aluminum layer (for example, titanium nitride P. Further, the opening 28 may be selectively filled with a chemical vapor deposition (CVD) tungsten metal, and then A chemical mechanical polish (CMP) is used to polish the metal layer to form a conductive plug 30. Next, the thin circuit layer 24 is a copper layer, and the copper layer of the fine circuit layer 24 is usually made of an electric ore and damascene process (damascene). The process is formed as follows: (1) depositing a copper diffusion barrier layer (for example, an oxynitride layer or a nitride layer having a thickness of between 0.05 μm and 0.25 μm); (2) utilizing electricity Auxiliary chemical vapor deposition (PEC VD), spin coating (Spin_on coating) or high-density plasma chemical vapor deposition (HDPCVD) deposition thickness is 〇· a fine-line dielectric layer 26 between 1 micrometer and 2.5 micrometers, wherein the thin-line dielectric layer 26 is preferably between 0.3 micrometers and 1.5 micrometers thick; (3) using a deposition thickness between Between 1 micron and 4 micrometers of a photoresist layer to pattern the fine-line dielectric layer 26, wherein the thickness of the photoresist layer is preferably between 0.3 micrometers and 2 micrometers, followed by the light The resist layer is exposed and developed to form a plurality of openings in the photoresist layer and/or a plurality of trenches to remove the photoresist layer; (4) depositing an adhesion by sputtering or chemical vapor deposition 13 1342594 product a barrier layer and a seed layer, wherein the adhesion/barrier layer comprises tantalum, tantalum nitride, titanium nitride, titanium or titanium tungsten alloy, or a composite layer formed of the above materials. The seed layer is usually a copper layer, and the copper layer may be formed by sputtering copper metal, chemical vapor deposition of copper metal, or first depositing a copper metal by chemical vapor deposition, and then sputtering a copper metal. (5) a copper layer having a plating thickness between 〇〇5 μm and 2 μm Preferably, a copper layer having an electroplated copper layer thickness between 0.2 μm and 1 μm is preferred on the seed layer; (6) removing the wafer by grinding (preferably chemical mechanical polishing) The copper layer, the seed layer, and the adhesion/barrier layer in the opening or trench of the fine-line dielectric layer 26 until exposed to the fine-line dielectric layer 26 under the adhesion/barrier layer. After that, only the metal in the opening or trench is left, and the remaining metal is used as a metal conductor (line or plane) or a conductive plug 30 (connecting two adjacent thin circuit layers 24). A double-damascene process is used to simultaneously form conductive plugs 3 and metal lines or metal planes in a single key process and a chemical mechanical polishing process. Two photolithography processes and two electroplating processes are available for the dual damascene process. The dual damascene process adds more steps to deposit and pattern another dielectric layer between the step of patterning a dielectric layer in the single damascene process and the step (4) of depositing a metal layer. Next, the fine-line dielectric layer 26 will be described. The thin-line dielectric layer 26 is formed by chemical vapor deposition, plasma-assisted chemical vapor deposition, high-density plasma chemical vapor deposition, or spin-on. The 14 1342594 material of the fine-line dielectric layer 26 includes silicon oxide, silicon nitride, silicon oxynitride, tetraethoxy decane formed by plasma-assisted chemical vapor deposition. (PECVD TEOS), spin-on glass (SOG, yttrium oxide or yttrium oxide), Fluorinated Silicate Glass (FSG) or a low dielectric constant (low-K) material, such as black diamond film (Black Diamond, which is a product of Applied Materials, the company's name is Applied Materials), ULK CORAL (product of Novellus) or SiLK (IBM) low dielectric constant dielectric material. Cerium oxide formed by electropolymerization-assisted chemical vapor deposition, tetraethylphosphonium decane formed by plasma-assisted chemical vapor deposition, or telluride formed by high-density plasma having a dielectric constant between 3.5 and 4.5 K; fluorocarbon glass formed by plasma-assisted chemical vapor deposition or fluorocarbon glass formed by high-density plasma having a dielectric constant value between 3.0 and 3.5, and low-k dielectric material having A dielectric constant value between 1.5 and 3,5. Low dielectric constant dielectric materials, such as black diamond films, are porous and include hydrogen, carbon, helium and oxygen in the formula HwCxSiyOz. This thin line dielectric layer 26 typically comprises an inorganic material. The thickness of each thin line dielectric layer 26 is between 0.05 microns and 2 microns. In addition, the opening 28 in the thin wiring dielectric layer 26 is formed by etching the patterned photoresist layer by wet etching or dry etching, wherein the preferred etching method is dry etching. Dry etching species include fluorine plasma. The protective layer: Referring to Figure lc, a protective layer 34 is formed on the thin wiring structure 22, which plays a very important role in the present invention. 15 1342594 Protective layer 34 is an important component of the integrated circuit industry, as described in 1990 by S. Wolf and published in the book "Silicon Processing in the VLSI era" by Lattice Press. Layer 34 is defined as the final layer in the integrated circuit process and is deposited on the overall upper surface of the wafer. The protective layer 34 is an insulating and protective layer that prevents mechanical and chemical damage during assembly and packaging. In addition to preventing mechanical scratches, the protective layer 34 also prevents mobile ions, such as sodium ions, and transition metals, such as gold and copper, penetrating into the product below. Body circuit components. In addition, the protective layer 34 can also protect the underlying components and connection lines (fine line metal structure and fine line dielectric layer) from moisture intrusion. The protective layer 34 typically comprises a silicon nitride layer and/or a sUicon oxynitride layer and has a thickness between 〇2 μm and 1.5 μm and is between 0.3 μm. A thickness of between 1.0 microns is preferred. Other materials used in the protective layer 300 are oxides of plasma-enhanced tetraethyl orthosilicate (PETEOS) formed by plasma-assisted chemical vapor deposition. Phosphorus silicate glass (PSG), borophospho silicate glass (BPSG), oxide formed by high density plasma (HDP). Next, some examples of the protective layer 34 composed of a composite layer will be described. The bottom to top order is: a thickness between 0.1 micrometers and 1.0 micrometers (preferably a thickness of between 3 micrometers and 0.7 micrometers). Nitride 16 1342594 矽 having an oxide/thickness between 〇25 μm and 12 μm (preferably between 0.35 μm and 1.〇 microns), this type of protective layer 34 is typically covered by A metal connection line formed by aluminum, wherein the metal connection line formed of aluminum generally comprises a process of sputtering aluminum and etching aluminum; (2) a thickness of between 〇〇5 μm and 〇35 μm (preferably, thickness is 0.1 μm)氮2 μm) NOx / thickness between 〇. 2 microns to 1.2 microns (preferably thickness between 〇 '1 micron to 〇 2 microns) oxide / thickness between 〇 2 A nitride/thickness from micron to 12 microns (preferably between 0.3 microns and 0.5 microns) is between 〇2 microns and 1.2 microns (preferably between 〇3 microns and 〇6 microns) Oxide 'this type of protective layer 34 is usually covered in a copper shape The metal on the connecting line, wherein the metal connection lines to form the copper plating generally includes chemical mechanical polishing the damascene process. In addition, the oxide layers in the above two examples may be oxides of plasma-enhanced tetraethyl orthosilicate 'PETE〇s' formed by plasma-assisted chemical vapor deposition. An oxide formed using a high density plasma. The above is applicable to all embodiments of the present invention. Referring to the id diagram, the protective layer 34 forms at least one opening. The opening 36 of the vine layer 34 is made by means of a fishing or dry meal, and is preferably dried in the middle. In addition, the size of the opening 36 is between 0.1 micrometers and 200 micrometers, and preferably between i micrometers to _ micro-finals or between 5 micrometers and 30 micrometers.疋 round, square, rectangular or polygonal, so the size of the opening 36 refers to the diameter of the circle, the length of the square, the longest diagonal of the polygon or the width of the rectangle, wherein the length of the rectangle 17 1342594 It is preferably between 1 micrometer and i centimeter, and preferably between 5 micrometers and 200 micrometers. The opening 36 of the protective layer 34 also has different sizes for the components of the component layer 12, generally the protective layer 34 The opening 36 has a size 疋 between 0.1 μm and 1 μm and is preferably between 〇3 μm and 3 μm; if the component layer 丨2 is provided with a voltage regulator, a transformer and an electrostatic For the discharge protection circuit, The opening 36 has a relatively large size ranging from 1 micrometer to 150 micrometers and preferably between 5 micrometers and 1 micrometer micrometer. In addition, the opening 36 exposes the uppermost layer of the fine wiring layer 24. a metal pad 32 for electrically connecting an over-passivation line or plane. The structure described above is defined as a wafer, such as a silicon wafer. , using different generations of integrated circuit process technology to produce 'eg 1 micron, 0.8 micron, 〇. 6 micron, 〇 · 5 micron, 0.35 micron, 0.25 micron, 0.18 micron, 0.25 micron, 0.13 micron, 90 nanometer ( Nm), 65 nm, 45 nm, 35 nm, 25 nm technology, and the generation of these integrated circuit process technologies is the gate length or effective channel length of the gold oxide half transistor 14 ( According to Channei iength), the size of the wafer is 5吋, 6吋, 8 pairs, 12忖 or 18吋, etc. The substrate 10 is fabricated using a lithography process, and the lithography process includes coating, Exposure and development (devei〇ping) photoresist. The photoresist of the bottom 10 has a thickness between 〇1 μm and 〇4 μm and is exposed by a five-times (5X) stepper or scanner. The multiple of the exposure machine refers to the ratio of the pattern on the reticle on the wafer when the light beam is projected onto the wafer from a light 18 1342594 cover (usually composed of quartz), and five times (5X) means The pattern on the reticle is five times the proportion of the pattern on the wafer. Scanners that use the advanced generation of integrated circuit process technology are usually scaled down by a factor of four (4X) to improve resolution. The beam wavelength used by the stepper or scanner is 436 nm (g-nne), 365 nm (i-line), 248 nm (deep ultraviolet, DUV), 193 nm (DUV), 157 nm (DUV^ 13.5 nm (very short UV, EUV). In addition, high index immersion (high_index immersi〇n) lithography can also be used to complete the fine circuit layer 24 on the wafer. The circle is made in a clean room with class l〇 (class 1〇) or better (eg class 1). The clean room of class 10 allows the maximum number of dust particles per cubic inch to be: No more than one dust particle containing greater than or equal to i micrometers, no more than one dust particle containing greater than or equal to 〇5 micrometers, no more than 30 dust particles containing greater than or equal to 〇3 micrometers, containing greater than or equal to 〇 2 micron dust particles no more than 75, containing more than or equal to 〇 1 micron of dust particles no more than 1, and level 1 clean room allows the maximum number of dust particles per cubic inch is: contains greater than or equal to 〇 5 micron dust particles no more than 1 3 have greater than or equal to 0.3 No more than 3 micron dust particles, no more than 7 dust particles containing 0.2 micron or more, and no more than 35 dust particles containing 0.1 micron or more. When copper is used as the fine circuit layer 24, it is required. A metal cap (not shown) is used to protect the copper pad 32' from the opening % of the protective layer 34. This pad 32 is protected from oxidation and damage, 1342594 and can be used as a subsequent wafer. The metal top layer comprises an aluminum layer, a gold layer, a titanium (Ti) layer, a titanium-tungsten alloy layer, a button (Ta) layer, and a nitride button (TaN) layer. Or a nickel (Ni) layer, wherein when the metal top layer is an aluminum layer, a barrier layer is formed between the copper pad and the metal top layer, and the barrier layer comprises titanium, titanium tungsten Alloy, titanium nitride, tantalum, tantalum nitride, chromium (Cr) or nickel. The above is an illustration of the semiconductor substrate 10, the thin wiring structure 22 and the protective layer 34 of the present invention, and several different types of embodiments of the present invention are explained below. An embodiment of the present invention is for manufacturing a protective layer The over-passivation scheme and the process, the structure on the protective layer in the present invention includes a stacked package, a tape bump bonded (TAB) of a polymer bump, a C0G (chip on glass), Tape carrier code (TCP), C0F (chip on film) package, and bonding to another external substrate using polymer bumps by FI ip Chip (FC) technology, The structure and process of each embodiment are explained separately. In the following embodiments, the materials and processes of the same parts are the same. Therefore, the materials and processes of the same components in the following embodiments and aspects are not repeatedly described. For example, the pads 32 in the following embodiments are not limited. The aluminum material is used as a description, but the material of the pad 32 may also be copper. The difference is that when the material of the pad 32 includes copper metal, a metal top layer (for example, an aluminum layer) is used to protect the opening of the layer 34. The exposed copper-containing pads 32 of 36 allow the copper-containing pads 32 to be protected from oxidation and damage. When the top layer of the metal is a 20 1342594 layer, 'a barrier layer is formed between the interface 32 and the layer. The barrier layer includes titanium, zihe alloy, titanium nitride, neon, gas. Group, network (Cr) or recorded. The bottom content is described in terms of the absence of a metal top layer, but those skilled in the art can implement it by adding a metal top layer by the following examples. The structure of the first embodiment is as follows: in the structure of this embodiment, the substrate 1 (), the element layer 12, the gold oxide semi-electric crystal 14, the source 16, the drain 18, the gate 2, and the thin wiring structure 22 The fine-line dielectric layer 26, the conductive plug 3, and the like are replaced by the integrated circuit 1A, and the structures and processes in the integrated circuit 100 have been fully described in the above embodiment, so the integrated circuit 1 in the embodiment The structures and processes in 〇 will not be repeated. Referring to Figure 2a, a polymer layer 112 is formed over the protective layer 34 and pads 32 of the integrated circuit 100. Referring to FIG. 2b, the polymer layer 112 is patterned by an exposure process, a development process, and an etching process to form the polymer layer 112 into a plurality of polymer bumps. 114 (only one is shown in the drawing), and the protective layer 34 and the interface 32 are exposed to the outside, followed by heat hardening to harden the polymer bump 114, and the temperature of the hardening process is 150 degrees ( Between °C and 300 degrees (〇C), and the material of the polymer bump 114 may be selected from the group consisting of poiyimide (PI), benzocyclobutene (BCB), and parylene. (parylene) 'epoxy-based material of which 21 1342594 a 'e.g. epoxy resin or Sotec from Renens, Switzerland

Microsystems 所提供之 ph〇t〇ep〇xy SU-8、彈性材料 (elastomer) ’例如矽酮（silicone)。其中此聚合物層U2 是為感光性材質時，可以僅利用微影製程（無須蝕刻製程） 來圖案化此聚合物層112,且此聚合物凸塊114厚度介於5 微米至50微米，聚合物凸塊丨丨4最大橫向尺寸介於1〇微 米至60微米，此聚合物凸塊114由俯視圖觀之係為圓形、 正方形、四邊形或多邊形等，另外在此實施例之中聚合物 凸塊114位在積體電路1〇〇内之主動元件上方。 清參閱第2c圖所示，形成一黏著阻障層 (adhesion/bairier layer)116在整個積體電路10〇上的保護 層34、接墊32及聚合物凸塊114上，黏著/阻障層116包 括鈦、鈦鎢合金、氮化鈦、鈕、氮化钽、鉻（Cr)或鎳。另， 黏著/阻障層116可以利用電鑛（electr〇piating)、無電電鑛 (electroless plating)、化學氣相沈積或物理氣相沉積（例如 濺鍍）的方式形成》其中又以物理氣相沉積為較佳的形成方 式，例如金屬濺鍍製程。另外此黏著阻障層116的厚度係 介於0.02微米至0.8微米之間，並以介於〇 〇5微米至〇 2 微米之間的厚度為較佳者。 請參閱第2d圖所示，接著形成厚度介於〇〇〇5微米至 2微米之間（較佳厚度係介於〇.丨微米至〇7微米之間）的 一種子層（seed layer)118在黏著/阻障層116上，而形成 種子層118的方式比如是賤鍵、7純、物理氣相沉積、電 錢或者是無電電鍵（electroless plating)的方式。此種子 22 1342594 層118有利於後續金屬線路的設置，因此種子層118的材 質會隨後續金屬線路的材質而有所變化。例如，當種子層 118上電鍍形成銅材質之金屬層時，種子層118之材質係 以銅為佳；當種子層118上電鍍形成金材質之金屬層時， 種子層118之材質係以金為佳；當種子層118上電鍍形成 鈀材質之金屬層時’種子層118之材質係以鈀為佳；當種 子層118上電鍍形成鉑材質之金屬層時，種子層ι18之材 質係以鉑為佳；當種子層118上電鍍形成铑材質之金屬層 時，種子層118之材質係以铑為佳；當種子層ns上電鑛 形成釕材質之金屬層時’種子層118之材質以釕為佳；當 種子層118上電鍍形成銶材質之金屬層時，種子層118之 材質係以銖為佳；當種子層118上電鍍形成鎳材質之金屬 層時，種子層118之材質係以錄為佳。 請參閱第2e圖所示’形成一光阻層120在種子層118 上，並透過曝光（exposure)與顯影（development)製程圖案化 此光阻層120’以形成複數光阻層開口 12如在光阻層12〇 内並暴露出位在接墊32及聚合物凸塊114上方的種子層 118上，而在形成光阻層開口 12〇a的過程中比如是以一倍 (1X)之曝光機（steppers)或掃描機（scanners)進行曝光顯影。 其中此光阻層120有兩種型式，其係為：（1)濕膜光阻 (liquid photoresist) ’其係利用單一或多重的旋轉塗佈方式 或者是印刷（printing)方式形成。此濕膜光阻的厚度係介於 3微米至60微米之間，而以介於5微米至4〇微米之間為 較佳者；以及（2)乾膜光阻（dry film Photoresist)，其係利用 23 1342594 貼合方式（laminating method)形成。此乾膜光阻的厚度係介 於30微米至300微米之間，而以介於50微米至150微米 之間為較佳者。另外，光阻可以是正型（positive-type)或負 型（negative-type)，而在獲得更好解析度上，則以正型厚光 阻(positive-type thick photoresist)為較佳者 ° 利用一對準機 (aligner)或一倍（IX)步進曝光機曝光此光阻。此一倍（1χ) 係指當光束從一光罩（通常係以石英或玻璃構成）投影至晶 圓上時，光罩上之圖形縮小在晶圓上的比例，且在光罩上 之圖案比例係與在晶圓上之圖案比例相同。對準機或一倍 步進曝光機所使用的光束波長係為436奈米（g-line)、397 奈米（h-line)、365 奈米（i-line)、g/h line(結合 g-line 與 h-line) 或 g/h/i line(結合 g-line、h-line 與 i-line)。使用光束波長 為g/h line或g/h/i line的一倍步進曝光機（或一倍對準機） 可在厚光阻或厚感光性聚合物（photosenstive polymer)的 曝光上’提供較大的光強度（light intensity);此外，此圖 案化光阻層120之開口 120a之形狀也可包括線圈形狀、方 形、圓形、多邊形或不規則形狀。 請參閱第2f圖所示，以電鍍方式形成_金屬層122在 開口 120a内的種子層118上，此金屬層m至少包覆聚合 物凸塊114二表面上方的種子層118，而此金屬層122比 如是金、銅、銀、鈀、鉑、铑、釕、銖或鎳之單層金屬層 結構或是複合式金屬層結構，此金屬層丨22之厚度介於j 微米至20微米，較佳之厚度可介於15微米至15微米之 間，而複合式金屬層結構之組合包括銅/鎳/金 、銅/金、銅 24 1342594 /鎳/鈀及銅/鎳/鉑等組合，在此實施例中此金屬層122係 為單層’而金屬層122之材質係為金，位在聚合物凸塊 上之金屬層122表面定義一區域為接合接墊124，此接合 接塾124可用於連接外界電路，此外界電路包括印刷電路 板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基板 其中之一。 請參閱第2g圖所示’去除圖案化光阻層12〇及去除未 在金屬層122下方的種子層118、黏著阻障層116。 請參閱第2h圖所示’將積體電路1〇〇進行切割步驟， 產生複數半導體晶片（chip) 126,半導體晶片126上的接合 接墊124可經由貼帶自動接合（tape aUt〇mated bonded’TAB)、COG(chip on glass)、捲帶式晶粒接合（Tape Carrier Package，TCP)或 COF(chip on film)的方式連接至 一外界電路128上，此128具有至少一接合金屬層129， 接合接墊124連接至接合金屬層〗29。 如第2i圖所示，本實施態樣以c〇G方式連接至外界 電路〗28,利用異方性導電膠13〇將半導體晶片126上的 接合接墊124接合至外界電路128之接合金屬層129上。 請參閱第2j圖所示，本實施態樣若以c〇F方式連接至 外界電路128，則同樣利用異方性導電膠〗3〇將半導體晶 片126上的接合接墊124接合至外界電路128之接合金屬 層129上另一種c〇F接合的方式，請參閲第以圖所示， 此方式係利用熱壓合的方式將半導體晶片126上的接合接 塾124接合至含踢之外界電路128上，藉由熱麼合使接合 25 1342594 接墊124上的金與接合金屬層129上之錫層132產生錫金 合金層134而穩固接合，此種藉由熱壓合接合的方式也可 應用到貼帶自動接合（tape automated bonded，TAB)及捲帶 式晶粒接合（Tape Carrier Package, TCP)上。 第l實施例之m 2態後： 此第2態樣之結構及製作方法與第1態樣之結構及製 作方法相當類似’因此以下各實施例及態樣中的相同元件 之材質及製程就不加以重覆說明。 請參閱第3a圖所示’第2態樣與第1態樣差異點在於 第2態樣的積體電路1〇〇具有二個接墊32、32,，同樣形 成聚合物層112在整個積體電路1〇〇上的保護層34及接墊 32、32,上。 請參閱第3b圖所示，並透過曝光（exp〇sure)、顯影 (development)製程及蝕刻製程圖案化此聚合物層112，使 此聚合物層112形成複數聚合物凸塊（p〇lymer burap)114(圖示中僅顯示出1個），開口 112a暴露出保護層 34及接墊32、32’，接著進行加熱硬化，使此聚合物凸塊 114硬化。其中此聚合物凸塊114是為感光性材質時，可 以僅利用微影製程（無須蝕刻製程）來圖案化此聚合物凸塊 114，且此聚合物凸塊114厚度介於5微米至5〇微米，聚 合物凸塊114最大橫向尺寸介於1〇微米至6〇微米。 請參閱第3c圖所示，形成黏著阻障層（adhesi〇n/barrier layer)116在整個積體電路10〇上的保護層34、接墊32、 26 1342594 32’及聚合物凸塊114上’黏著/阻障層n6包括欽、欽鎢 合金、氮化鈦、钽、氮化鈕、鉻（Cr)或鎳，此黏著阻障層 116的厚度係介於〇.02微米至〇.8微米之間，並以介於〇 〇5 微米至0.2微米之間的厚度為較佳者。 請參閱第3d圓所示’接著形成厚度介於〇.〇〇5微米至 2微米之間（較佳厚度係介於〇丨微米至〇 7微米之間）的 種子層（seed layer) 118在黏著/阻障層116上。 請參閱第3e圖所示，形成光阻層12〇在種子層118 上，並透過曝光（exposure)與顯影（devel〇pment)製程圖案化 此光阻層120，以形成複數光阻層開口 12〇a、12〇b在光阻 層120内並分別暴露出位在接墊32、32’及聚合物凸塊114 上方的種子層118。 請參閱第3f圖所示，以電鍍方式形成金屬層122在開 口 120a、120b内的種子層118上，此金屬層122至少包覆 聚合物凸塊114二表面上方的種子層118,而金屬層ι22 比如是金、銅、銀、鈀、鉑、铑、釕、銖或鎳之單層金屬 層結構或是複合式金屬層結構，此金屬層122之厚度介於 1微米至20微米，較佳之厚度可介於l 5微米至15微米 之間，而複合式金屬層結構之組合包括銅/鎳/金、銅/金、 銅/鎳/鈀及銅/鎳/鉑等組合，在此實施例中此金屬層122 係為單層，而金屬層122之材質係為金，位在金屬層丨22 表面定義二區域分別為接合接墊124及一打線接墊136， 接合接塾124係位在聚合物凸塊114上，而打線接塾136 位在接墊32’上’此接合接墊124及打線接塾136可用於 27 1342594 連接外界電路，此外界電路包括印刷電路板、金屬基板、 玻璃基板、軟性基板、陶瓷基板及矽基板其中之一。 請參閱第3g圖所示，去除圖案化光阻層〗2〇及去除未 在金屬層122下方的種子層ι18、黏著阻障層116。 明參閱第3h圖及第3i圖所示，將積體電路1〇〇進行 切割步驟，產生複數半導體晶片（chip)126，半導體晶片 126上的接合接墊124可經由覆晶（Flip Chip，Fc)技術 接合至另一外界基板138上，此外界基板138比如是半導 體晶片，此外界基板138為半導體晶片時，此外界基板138 具有複數接合接塾140，在接合接墊140上具有一接合金 屬層142’此接合金屬層142之材質包括金、銅、銀、鈀、 鉑、铑、釕、铼、錫或鎳之單層金屬層結構或是複合式金 屬層結構，此接合金屬層142會隨著金屬層122之材質而 有所改變，例如金屬層122之材質為金時，接合金屬層142 之材質係為金或含錫之金屬層，接著利用覆晶（F1 ip chip， FC)技術將外界基板138疊設在半導體晶片126上，其中 接合的方式可採用熱壓合的方式，使接合金屬層142與金 屬層122產生融合或合金（金/金接合或金_錫合金）接合，並 且在外界基板138與半導體晶片126之間形成一封裝層 144將其包覆，此封裝層144之材質係為聚合物材質，比 如是環氧樹脂。另外打線接墊136則經由打線製程形成一 導線146連接至另一外界電路（圖中未示）上，此外界電路 包括印刷電路板、金屬基板、玻璃基板、軟性基板、陶瓷 基板及石夕基板其中之一。 28 1342594 請參閱第3j圖及第3k圖所示，此外打線接墊】36除 了可以利用打線製程所形成之導線】46連接至另一外界電 路，此外界電路包括印刷電路板、金屬基板、玻璃基板、 軟性基板、陶瓷基板及矽基板其令之一，也可以連接至外 界電路之錫球147上，如第3k圖所示，此錫球147之厚度 係介於50微来至3〇〇微米之間，此連接方式可利用熱壓合 的方式接合。 舅1實施例之第3钹描： 此第3態樣之結構及製作方法與第2態樣及第丨態樣 之結構及製作方法相當類似，因此以下各實施例及態樣中 的相同元件之材質及製程就不加以重覆說明。 請參閱第4a圖及第4b圖所示，第3態樣與第2態樣 差異點僅在於打線接墊136的位置不同，第3態樣的打線 接墊136的位置從俯視透視圖（第讣圖）觀之，打線接墊ι36 位置係不同於接墊32,之位置，此打線接墊136可提供一 打線導線接合’經由此打線導線連接至外界電路上，此外 界電路包括印刷電路板、金屬基板、玻璃基板、軟性基板、 陶瓷基板及矽基板其t之一，其中打線接墊136下方的積 體電路100内之基底1〇上可以設有至少一主動元件，此主 動元件包括二極體、電晶體等，主動元件己在上述元件層 12中己有詳盡介紹，在此就不加以重覆論述。 請參閱第4c圖所示，將積體電路100進行切割步驟， 產生複數半導體晶片（chip)126,半導體晶片126上的接合 29 1342594 接墊124可經由覆晶（Flip Chip，FC)技術接合至另一外 界基板138上，此外界基板138比如是半導體晶片，此外 界基板138為半導體晶片時，此外界基板138具有複數接 合接墊140,在接合接墊14〇上具有一接合金屬層142，此 接合金屬層142之材質包括金、銅、銀、纪、始、姥、釕、 銖、錫或鎳之單層金屬層結構或是複合式金屬層結構，此 接合金屬層142會隨著金屬層122之材質而有所改變，例 如金屬層122之材質為金時，接合金屬層142之材質係為 金或含錫之金屬層，接著利用覆晶（Flip Chip，FC)技術 將外界基板138疊設在半導體晶片126上，其中接合的方 式可採用熱壓合的方式’使接合金屬層142與金屬層ι22 產生融合或合金（金/金接合或金-錫合金）接合，並且在外界 基板138與半導體晶片126之間形成一封裝層144將其包 覆，此封裝層144之材質係為聚合物材質，比如是環氧樹 脂。另外打線接墊136則經由打線製程形成一導線！46連 接至另一外界電路（圖中未示）上，此外界電路包括印刷電 路板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基 板其中之一。 -第1實施例之第4 _枰： 此第4態樣之結構及製作方法與第3態樣及第1態樣 之結構及製作方法相當類似，因此以下各實施例及態樣中 的相同元件之材質及製程就不加以重覆說明。 請參閱第5a圖所示，同樣形成聚合物層n2在整個積 30 1342594 體電路100上的保護層34及接墊32及接墊32’上。 請參閱第5b圖所示，並透過曝光（exposure)、顯影 (deve lopment)製程及钱刻製程圖案化此聚合物層112,使 此聚合物層112形成複數開口 112a及複數聚合物塊 (polymer is land )142，開口 112a暴露出保護層34、接塾 32及接墊32’，接著進行加熱硬化，使聚合物塊148硬化， 此硬化過程的溫度係介於150度（°C)至300度（°C)之間， 且此聚合物塊148之材質可選自聚醯亞胺（polyimide， PI)、苯基環丁稀（benzocyclobutene ’ BCB)、聚對二甲苯 (parylene)、環氧基材料（epoxy-based material)其中之 一，例如環氧樹脂或是由位於瑞士之Renens的Sotec Microsystems 所提供之 photoepoxy SU-8、彈性材料 (elastomer)，例如石夕明（si 1 icone)。其中此聚合物層112 為感光性材質時，可以僅利用微影製程（無須蝕刻製程）來 圖案化此聚合物層112,且此聚合物塊148厚度介於5檄 米至50微米。 請參閱第5c圖及第5d圖所示，接著形成另一聚合物 層150在聚合物塊148及開口 112a内，此聚合物層150 之材質與聚合物層112相同，並透過曝光（exposure)、顯 影（development)製程及钱刻製程圖案化此聚合物層150 形成複數聚合物凸塊（polymer bump) 152(圖示中僅顯示出 1個），其中此聚合物層150為感光性材質時，可以僅利用 微影製程（無須蝕刻製程）來圖案化此聚合物層150,且此 聚合物凸塊厚度介於5微米至50微米，聚合物凸塊152 31 最大橫向尺寸介於10微米至60微米。 叫參閱第5e圖所示，形成黏著阻障層（adhesi〇n/barrier layer)116在整個積體電路1〇〇上的接墊32、接墊32，、聚 合物凸塊152及聚合物塊148上。 請參閱第5f圖所示，接著形成厚度介於0.005微米至 2微米之間（較佳厚度係介於〇1微米至〇 7微米之間）的 種子層（seed layer) 118在黏著/阻障層116上。 *月參閱第5g圖所示，形成光阻層12〇在種子層118 上，並透過曝光（exposure)與顯影（devd〇pment)製程圖案化 此光阻層I20,以形成複數光阻層開口 120a在光阻層120 内並暴露出位在接墊32、接墊32,、聚合物凸塊152及聚 合物塊148上方的種子層118，而在形成光阻層開口 l2〇a 的過程中比如是以一倍（1乂）之曝光機（steppers)或掃描機 (scanners)進行曝光顯影。 請參閱第5h圖所示，以電鍍方式形成金屬層122在開 口 120a内的種子層118上，此金屬層122至少包覆聚合物 凸塊152二表面上方的種子層118，而金屬層122比如是 金、銅、銀 '鈀 '鉑、铑、釕、銖或鎳之單層金屬層結構 或是複合式金屬層結構，此金屬層122之厚度介於丨微米 至20微米，較佳之厚度可介於15微米至15微米之間’ 而複合式金屬層結構之組合包括銅/鎳/金、銅/金、銅/鎳/ 把及銅/錄/鉑等組合，在此實施例中此金屬層i 22係為單 層，而金屬層122之材質係為金，位在聚合物凸塊152上 之金屬層122表面定義一區域為接合接墊124，此接合接 32 1342594 墊124可用於連接外界電路，此外界電路包括印刷電路 板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基板 其中之一，而位在聚合物塊148上之金屬層122表面定義 一區域為打線接墊136，此打線接墊136經由打線製程於 連接外界電路，其中位在打線接墊136下的聚合物塊ι48 在打線製程時可緩衝打線所產生的應力，對於厚度較薄的 基底10有足夠的緩衝效應，可以防止積體電路1〇〇之基底 10、元件層12之主動元件在打線製程時損壞，此外此實施 例態樣由上視透視圖觀之打線接塾148與接塾32’之位置 不同’但是打線接墊136也可以位在接墊32,上方，在此 就不加重覆論述。 請參閱第5i圖所示’去除圖案化光阻層120及去除未 在金屬層122下方的種子層118、黏著阻障層116。 請參閱第5j圖所示，將積體電路1〇〇進行切割步驟， 產生複數半導體晶片（chip) 126。 請參閱第5k圖所示’此第5k圖與上述第3i圖相似， 係將半導體晶片126經由覆晶（FlipChip，FC)技術接合 至另一外界基板138上，其中接合之說明如上述第3i圖說 明一樣，所以在此就不加以重覆論述。 ϋ-L宜施例之笛5鲅樣： 第5態樣之結構及製作方法與第4態樣之結構及製作 方法相當類似，此第4態樣之結構為第1態樣的變化，因 此以下各實施例及態樣中的相同元件之材質及製程就不加 33 1342594 以重覆說明。 請參閱第6a圖所示，第5態樣與第4態樣差異在於曝 光（exposure)、顯影（development)製程及蝕刻製程圖案化 此聚合物層112及加熱硬化之步驟，在第5態樣在此二步 驟係同時形成聚合物塊148及聚合物凸塊114,也就聚合 物塊148及聚合物凸塊114之厚度相同，且此聚合物塊148 與聚合物凸塊114厚度介於5微米至50微米之間。 請參閱第6b圖所示，依序形成黏著阻障層 (adhesion/barrier layer)116 及厚度介於 0.005 微米至 2 微 米之間（較佳厚度係介於〇. 1微米至〇 7微米之間）的種子 層（seed layer)l 18在整個積體電路1〇〇上的接墊32、接 墊32’、聚合物凸塊Π4及聚合物塊丨48上。 請參閱第6c圖所示’形成光阻層12〇在種子層n8 上’並透過曝光（exposure)與顯影（development)製程圖案化 此光阻層120’以形成複數光阻層開口 i2〇a在光阻層120 内並暴露出位在接墊32、接墊32’、聚合物凸塊114及聚 合物塊148上方的種子層118，而在形成光阻層開口〗2〇a 的過程中比如疋以一倍（IX)之曝光機（steppers)或掃描機 (scanners)進行曝光顯影。 請參閱第6d圖所示，以電鍍方式形成金屬層122在開 口 120a内的種子層118上，此金屬層122至少包覆聚合物 凸塊114二表面上方的種子層118,金屬層丨22比如是金、 銅、銀、鈀、鉑、铑、釕、銖或鎳之單層金屬層結構或是 複合式金屬層結構，此金屬層122之厚度介於丨微米至2〇 34 1342594 微米’較佳之厚度可介於丨_ 5微米至15微米之間，而複合 式金屬層結構之組合包括銅/鎳/金、銅/金、銅/鎳/鈀及銅 /鎳/鉑等組合，在此實施例中此金屬層122係為單層，而 金屬層122之材質係為金’位在聚合物凸塊〖Μ上之金屬 層122表面定義一區域為接合接墊124 ’此接合接墊ι24 可用於連接外界電路，此外界電路包括印刷電路板、金屬 基板、玻璃基板、軟性基板、陶瓷基板及矽基板其中之一， 而位在聚合物塊148上之金屬層122表面定義一區域為打 線接墊136，此打線接墊136經由打線製程於連接外界電 路’其中位在打線接墊136下的聚合物塊148在打線製程 時可緩衝打線所產生的應力，對於厚度較薄的基底1〇有足 夠的緩衝效應’可以防止積體電路1〇〇之基底1〇、元件層 12之主動元件在打線製程時損壞，此外此實施例態樣由上 視透視圖觀之打線接塾136與接墊32’之位置不同，但是 打線接塾136也可以位在接塾32,上方，在此就不加重覆 論述。 請參閱第6e圖所示，去除圖案化光阻層12〇及去除未 在金屬層122下方的種子層118、黏著阻障層116。 請參閱第6f圖所示’將積體電路1〇〇進行切割步驟， 產生複數半導體晶片（chip) 126。 請參閱第6g圖所示，此第6g圖與上述第3 i圖相似， 係將半導體晶片126經由覆晶（FlipChip，FC)技術接合 至另一外界基板138上，其中接合之說明如上述第3i圖說 明一樣，所以在此就不加以重覆論述。 35 1342594 農2實施例之第1雉槎： 此實施例之結構中基底1〇、元件層12、金氧半電晶體 14、源極16、汲極18 '閘極2〇、細線路結構22、細線路 介電層26、導電栓塞30等以積體電路1〇〇代替，且積體 電路100中的各結構及製程在上述實施已完整說明，因此 實施例中的積體電路1〇〇中的各結構及製程就不加以重覆 說明。 明參閱第7a圖所示，形成一聚合物層I〗]在整個積體 電路100上的保護層34及接塾32上。 明參閱第7b圖所示，並透過曝光（eXp〇sure)、顯影 (development)製程及蝕刻製程圖案化此聚合物層112，使 此聚合物層112形成複數聚合物凸塊（p〇lymer bump) 114(圖示中僅顯示出1個），而保護層34及接塾32 暴露於外，接著進行加熱硬化，使此聚合物凸塊U4硬化， 此硬化過程的溫度係介於150度（。(：）至300度（。(：）之間， 且此聚合物凸塊114之材質可選自聚醯亞胺（p〇iy imide， PI)、苯基環丁稀（benzocyclobutene，BCB)、聚對二甲苯 (parylene)、環氧基材料（ep〇xy-based material)其中之 一 ’例如環氧樹脂或是由位於瑞士之Renens的Sotec Microsystems 所提供之 photoepoxy SU-8、彈性材料 (elastomer) ’例如石夕酮（si 1 i cone)。其中此聚合物層112 是為感光性材質時，可以僅利用微影製程（無須蝕刻製程） 來圖案化此聚合物層112,且此聚合物凸塊114厚度介於5 36 1342594 微米至50微米，取合物凸塊114最大橫向尺寸介於1〇微 米至60微米，此聚合物凸塊114由俯視圖觀之係為圓形、 正方开v四邊形或多邊形等。另外聚合物凸塊114覆蓋住 接整32-部分之區域，而接塾32所暴露出之區域在此實 施例定義為導電區域154’此導電區域154的寛度係介於3 微米至20微米或2微米至15微米之間β 請參閱第7c圖所示’其中聚合物凸塊114在此實施例 中係將接# 32之-侧覆蓋，因此由俯視圖觀之，此導電區 域154係為四邊形或多邊形等，而所暴出之導電區域154 面積與金屬接墊表面面積之比率係為〇丨至〇 g或〇 〇5 至〇. 5之間。 凊參閱第7d圖所示，形成一黏著阻障層 (adhesi〇n/baiTier layer)U6在整個積體電路1〇〇上的保護 層34、導電區域154及聚合物凸塊114上黏著/阻障層 116包括鈦、鈦鎢合金、氮化鈦鈕氮化鈕鉻π。或 鎳。另’黏著/阻障層116可以利用電鍍（electr〇pUting)、 無電電鑛（eleetn)less plating)、化學氣相沈積或物理氣相沉 積（例如濺鍍）的方式形成，其中又以物理氣相沉積為較佳 的形成方式，例如金屬濺鍍製程，另外此黏著阻障層ιΐ6 的厚度係；|於微米至Q 8微米之間並以介於〇 微 米至0.2微米之間的厚度為較佳者。 凊參閱第7e圖所示，接著形成厚度介於0_ 005微米至 2微米之間（較佳厚度係介於〇j微米至〇 7微米之間）的 一種子層（seed Uyer)U8在黏著/阻障層ιΐ6上而形成 37 丄342594 種子層118的方式比如是濺鍍、蒸鍍、物理氣相沉積、電 鍍或者是無電電鍍（electroless plating)的方式。此種子 層118有利於後續金屬線路的設置，因此種子層118的材 質會隨後續金屬線路的材質而有所變化。例如，當種子層 118上電鍍形成銅材質之金屬層時，種子層118之材質係 以銅為佳；當種子層118上電鍍形成金材質之金屬層時， 種子層118之材質係以金為佳；當種子層118上電鍍形成 鈀材質之金屬層時，種子層118之材質係以鈀為佳；當種 子層118上電鍍形成鉑材質之金屬層時，種子層118之材 質係以鉑為佳；當種子層118上電鍍形成铑材質之金屬層 時’種子層118之材質係以铑為佳；當種子層U8上電鍍 形成釕材質之金屬層時，種子層118之材質以釕為佳；當 種子層118上電鍍形成銖材質之金屬層時，種子層118之 材質係以銖為佳；當種子層118上電鍍形成鎳材質之金屬 層時’種子層118之材質係以鎳為佳。 請參閱第7f圖所示，形成一光阻層12〇在種子層U8 上’並透過曝光（exposure)與顯影（development)製程圖案化 此光阻層120’以形成複數光阻層開口 12〇a在光阻層12〇 内並暴露出位在接墊32及聚合物凸塊114上方的種子層 118上’而在形成光阻層開口 i2〇a的過程中比如是以—倍 (IX)之曝光機（steppers)或掃描機（scanners)進行曝光顯影。 其中此光阻層120有兩種型式，其係為：（1)濕膜光阻 (liquid photoresist)，其係利用單一或多重的旋轉塗佈方式 或者是印刷（printing)方式形成。此濕膜光阻的厚度係介於 38 1342594 3微米至60微米之間’而以介於5微米至40微米之間為 較佳者；以及（2)乾膜光阻（dry film Photoresist)，其係利用 貼合方式（laminating method)形成。此乾膜光阻的厚度係介 於30微米至300微米之間，而以介於50微米至150微米 之間為較佳者。另外’光阻可以是正型（p0sitive-type)或負 型（negative-type) ’而在獲得更好解析度上，則以正型厚光 阻（positive-type thick photoresist)為較佳者。利用一對準機 (aligner)或一倍（IX)步進曝光機曝光此光阻。此一倍（ιχ) 係指當光束從一光罩（通常係以石英或玻璃構成）投影至晶 圓上時，光罩上之圖形縮小在晶圓上的比例，且在光罩上 之圖案比例係與在晶圓上之圖案比例相同。對準機或一倍 步進曝光機所使用的光束波長係為436奈米（g_line)、397 奈米（h-line)、365 奈米（i-line)、g/h iine(結合 g_丨ine 與 h_line) 或 g/h/i line(結合 g-line、h-line 與 i-line)。使用光束波長 為g/h line或g/h/i line的一倍步進曝光機（或一倍對準機） 可在厚光阻或厚感光性聚合物（ph〇t〇senstive polymer)的 曝光上’ it供較大的光強度（Hght jntensity);此外，此圖 案化光阻層120之開口 i2〇a之形狀也可包括線圈形狀、方 形、圓形、多邊形或不規則形狀。 請參閱第7g圖所示，以電鍍方式形成一金屬層122 在開口 120a内的種子層118上，此金屬層122至少包覆聚 合物凸塊114二表面上方的種子層118，而此金屬層122 比如是金、銅、銀、鈀、鉑、铑、釕、銖或鎳之單層金屬 層結構或是複合式金屬層結構，此金屬層122之厚度介於 39 1342594 1微米至20微米，較佳之厚度可介於15微米至15微米 之間，而複合式金屬層結構之組合包括銅/鎳/金、銅/金、 銅/鎳/鈀及銅/鎳/鉑等組合，在此實施例中此金屬層122 係為單層，而金屬層122之材質係為金，位在聚合物凸塊 114上之金屬層122表面定義一區域為接合接墊124，此接 合接墊124可用於連接外界電路，此外界電路包括印刷電 路板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基 板其中之一。 請參閱第7h圖所示’去除圖案化光阻層12〇及去除未 在金屬層122下方的種子層us、黏著阻障層 請參閱第7i圖所示，將積體電路丨〇〇進行切割步驟， 產生複數半導體晶片（chip)l26,半導體晶片126上的接合 接塾124可經由貼帶自動接合（Upe aut〇mated bonded’TAB)、COG(chip on glass)、捲帶式晶粒接合（Tape Carrier Package，TCP)或 COF(chip on film)的方式連接至 一外界電路128上，此外界電路i28包括印刷電路板、金 屬基板、玻璃基板、軟性基板、陶瓷基板及矽基板其中之 一，此外界電路128具有至少一接合金屬層129，接合接 墊124連接至接合金屬層129。 如第7j圖所示’本實施態樣以c〇G方式連接至外界 電路128，利用異方性導電膠130將半導體晶片ι26上的 接合接墊124接合至外界電路128之接合金屬層129上。 請參閲第7k圖所示，本實施態樣若以c〇F方式連接至 外界電路128 ’則同樣利用異方性導電膠130將半導體晶 40 1342594 片126上的接合接墊124接合至外界電路128之接合金屬 層129上，另一種c〇F接合的方式，請參閱第71圖所示， 此方式係利用熱壓合的方式將半導體晶片126上的接合接 墊124接合至含錫之外界電路128上，藉由熱壓合使接合 接墊124上的金與接合金屬層129上之錫層132產生錫金 合金層134而穩固接合，此種藉由熱壓合接合的方式也可 應用到貼帶自動接合（tape aut〇mated b〇nded TAB)及捲帶 式晶粒接合（Tape Carrier Package，TCP)上。 第2實施例之笫2能样: 此第2態樣之結構及製作方法與第丨態樣之結構及製 作方法相當類似，因此以下各實施例及態樣中的相同元件 之材質及製程就不加以重覆說明。 請參閱第8a圖所示，第2態樣與第1態樣差異點在於 第2態樣的積體電路1〇〇具有二個接塾32、32’ ’同樣形 成聚合物層112在整個積體電路100上的保護層34及接墊 32 ' 32,上。 請參閲第8b圖所示’並透過曝光（exp〇sure)、顯影 (development)製程及蝕刻製程圖案化此聚合物層112，使 • 此聚合物層112形成複數聚合物凸塊（p〇lymer • ^^"11>)114(圖示中僅顯示出1個）’開口1123暴露出保護層 34及接墊32、32，，接著進行加熱硬化，使此聚合物凸塊 114硬化。其中此聚合物凸塊1H是為感光性材質時，可 以僅利用微影製程（無須蝕刻製程）來圖案化此聚合物凸塊 41 1342594 114,且此聚合物凸塊ι14厚度介於5微米至5〇微米，聚 合物凸塊114最大橫向尺寸介於1〇微米至6〇微米。另外 聚合物凸塊114覆蓋住接墊32 一部分之區域，而接墊32 所暴露出之區域在此實施例定義為導電區域154，此導電 區域154的寛度係介於3微米至2〇微米或2微米至"微 米之間。 請參閱第8c圖所示’其中聚合物凸塊114在此實施例 中係將接塾32之一側覆蓋，因此由俯視圖觀之，此導電區 域154係為四邊形或多邊形等，而所暴出之導電區域154 面積與金屬接墊表面面積之比率係為〇丨至〇·9或〇 〇5 至0. 5之間。 請參閱第8d圖所示，形成黏著阻障層（adhesi〇n/barrier layer)116在整個積體電路1〇〇上的保護層34、導電區域 154、接墊32’及聚合物凸塊114上，黏著/阻障層ιΐ6包括 欽、鈦鶴合金、氮化鈦、、氮化纽 '路（⑺或錄，此黏 著阻障層116的厚度係介於〇.〇2微卡至〇8#米之間並 以介於0.05微米至〇·2微米之間的厚度為較佳者。 請參閱第8e圖所示，接著形成厚度介於〇 〇〇5微米至 2微米之間（較佳厚度係介於〇1微米至〇 7微米之間）的 種子層（seed layer)118在黏著/阻障層ία上。 請參閱第8f圖所示，形成光阻層12〇在種子層ιΐ8 上，並透過曝光（exposure)與顯影（devel〇pment)製程圖案化 此光阻層120,以形成複數光阻層開口 12如、12肋在光阻 層120内並分別暴露出位在接塾32、32,及聚合物凸塊ιΐ4 42 1342594 上方的種子層118。 請參閱第8g圖所示，以電鑛方式形成金屬層122在開 口 120a、120b内的種子層118上，此金屬層122至少包覆 聚合物凸14二表面上方的種子層118，而金屬層122 比如疋金、銅、銀、鈀、鉑、铑、釕、銖或鎳之單層金屬 層結構或是複合式金屬層結構，此金屬層122之厚度介於 1微米至20微米，較佳之厚度可介於15微米至15微米 之間，而複合式金屬層結構之組合包括銅/鎳/金、銅/金、 銅/鎳/鈀及銅/鎳/鉑等組合，在此實施例中此金屬層122 係為單層，而金屬層122之材質係為金，位在金屬層122 表面定義二區域分別為接合接墊124及一打線接墊136, 接合接墊124係位在聚合物凸塊114上，而打線接墊136 位在接墊32’上，此接合接墊124及打線接墊136可用於 連接外界電路，此外界電路包括印刷電路板、金屬基板、 玻璃基板、軟性基板、陶瓷基板及矽基板其中之一。 請參閱第8h圖所示，去除圖案化光阻層12〇及去除未 在金屬層122下方的種子層118、黏著阻障層116。 凊參閱第8i圖及第8 j圖所示，將積體電路1〇〇進行 切割步驟’產生複數半導體晶片（chip)i26，半導體晶片 126上的接合接墊124可經由覆晶（Flip Chip, FC)技術 接合至另一外界基板138上，此外界基板138比如是半導 體晶片’此外界基板138為半導體晶片時，此外界基板138 具有複數接合接墊140’在接合接墊140上具有一接合金 屬層142 ’此接合金屬層142之材質包括金、銅、銀、鈀、 43 1342594 麵、鍺、釕、銖、錫或鎳之單層金屬層結構或是複合式金 屬層結構’此接合金屬層142會隨著金屬層122之材質而 有所改變’例如金屬層！22之材質為金時，接合金屬層142 之材質係為金或含錫之金屬層，接著利用覆晶（FUpChip， 吖）技術將外界基板138疊設在半導體晶片126上其中 接合的方式可採用熱壓合的方式，使接合金屬層142與金 屬層122產生融合或合金（金/金接合或金_錫合金）接合並 且在外界基板138與半導體晶片126之間形成一封裝層 144將其包覆，此封裝層144之材質係為聚合物材質比 如疋％氧樹脂。另外打線接墊丨36則經由打線製程形成一 導線146 14接至另一外界電路（圖中未示）上，此外界電路 包括印刷電路板、金屬基板、玻璃基板、軟性基板、陶究 基板及碎基板其中之一。 请參閱第8k圖所示，此外打線接墊136除了可以利用 打線製程所形成之導線146連接至另一外界電路，也可以 連接至外界電路之錫球147 1，如第8k圖所示此錫球 147之厚度係介於50微米至300微米之間，此連接方式可 利用熱壓合的方式接合。 第1戈施魁態樣. 此第3態樣之結構及製作方法與第3態樣及第2態樣 之、構及製作方法相當類似，因此以下各實施例及態樣中 的相同元件之材質及製程就不加以重覆說明。 請參閱第9a圖及第9b圖所示，第3態樣與第2態樣 1342594 差異點僅在於打線接墊136的位置不同，第3態樣的打線 接塾136的位置從俯視透視圖（第9b圖）觀之’打線接整136 位置係不同於接墊32’之位置，此打線接墊136可提供一 打線導線接合’經由此打線導線連接至外界電路上，此外 界電路包括印刷電路板、金屬基板、玻璃基板、軟性基板、 陶瓷基板及矽基板其中之一’其中打線接墊136下方的積 體電路100内之基底1〇上可以設有至少一主動元件，此主 動元件包括一極體、電晶體等’主動元件己在上述元件層 12中己有詳盡介紹’在此就不加以重覆論述。 請參閱第9c圖所示’將積體電路1〇〇進行切割步驟， 產生複數半導體晶片（chip)l26,半導體晶片126上的接合 接塾124可經由覆晶（fi ip chip，FC)技術接合至另一外 界基板138上’此外界基板ι38比如是半導體晶片，此外 界基板138為半導體晶片時，此外界基板138具有複數接 合接墊140,在接合接墊14〇上具有一接合金屬層142，此 接合金屬層142之材質包括金、銅、銀、鈀、鉑、铑、钌、 鍊、錫或銻之單層金屬層結構或是複合式金屬層結構，此 接合金屬層142會隨著金屬層122之材質而有所改變，例 如金屬層122之材質為金時，接合金屬層142之材質係為 金或含錫之金屬層，接著利用覆晶（FlipChip，FC)技術 將外界基板138疊設在半導體晶片126上，其中接合的方 式可採用熱壓合的方式，使接合金屬们42與金屬層122 產生融合或合金（金/金接合或金錫合金）接合，並且在外界 基板138與半導體晶片126之間形成-封裝㉟144將其包 45 1342594 覆’此封裝層144之材質係為聚合物材質，比如是環氧樹 脂。另外打線接墊136則經由打線製程形成一導線146連 接至另一外界電路（圖中未示）上，此外界電路包括印刷電 路板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基 板其中之一。 JL2實施例之第4熊樺: 此第4態樣之結構及製作方法與第3態樣及第1態樣 之結構及製作方法相當類似，因此以下各實施例及態樣中 的相同元件之材質及製程就不加以重覆說明。 請參閱第10a圖所示，同樣形成聚合物層112在整個 積體電路100上的保護層34及接墊32及接墊32，上。 請參閱第10b圖及第i〇c圖所示，並透過曝光 (exposure)、顯影（development)製程及蝕刻製程圖案化此 聚合物層112 ’使此聚合物層η?形成複數開口 112a、複 數聚合物塊（polymer island) 148及聚合物凸塊114,開口 112a暴露出保護層34、接墊32及接墊32,，另外聚合物 凸塊114覆蓋住接墊32 —部分之區域，而接墊32所暴露 出之區域在此實施例定義為導電區域154，此導電區域154 的寬度係介於3微米至20微米或2微米至15微米之間。 由第l〇c圖所示聚合物凸塊114在此實施例中係將接墊32 之一側覆蓋，因此由俯視圖觀之，此導電區域154係為四 邊形或多邊形等，而所暴出之導電區域154面積與金屬接 墊表面面積之比率係為〇1至〇 9或〇 〇5至〇 5之間。 46 1342594 接著進行加熱硬化，使聚合物塊148及聚合物凸塊114 硬化，此硬化過程的溫度係介於150度（°c )至300度) 之間，且此聚合物塊148及聚合物凸塊114之材質可選自 聚醯亞胺（polyimide ， PI)、苯基環丁婦 (benzocyclobutene，BCB)、聚對二甲苯（paryiene)、環氧 基材料（epoxy-based material)其中之一，例如環氧樹脂 或是由位於瑞士之Renens的Sotec Microsystems所提供 之photoepoxy SU-8、彈性材料（elastomer)，例如石夕網 (silicone)。其中此聚合物層112為感光性材質時，可以 僅利用微影製程（無須蝕刻製程）來圖案化此聚合物層 112’且此聚合物塊148厚度介於5微米至50微米。 請參閱第10d圖所示，依序形成黏著阻障層 (adhesion/barrier layer)116 及厚度介於 Ο, 〇〇5 微米至 2 微 米之間（較佳厚度係介於0.1微米至0.7微米之間）的種子 層（seed layer)118在整個積體電路1〇〇上的導電區域 154、接墊32’、聚合物凸塊Π4及聚合物塊148上。 請參閱第10e圖所示，形成光阻層120在種子層118 上’並透過曝光（exposure)與顯影（development)製程圖案化 此光阻層120，以形成複數光阻層開口 120a在光阻層120 内並暴露出位在導電區域154、接墊32，、聚合物凸塊114 及聚合物塊148上方的種子層118，而在形成光阻層開口 120a的過程中比如是以一倍〇χ)之曝光機（steppers)或掃 描機（scanners)進行曝光顯影。 請參閱第1 Of圖所示，以電鍵方式形成金屬層122在 47 1342594 開口 120a内的種子層118上，此金屬層122至少包覆聚合 物凸塊114二表面上方的種子層118，金屬層122比如是 金、銅、銀、鈀、鉑、鍺、釕、銖或鎳之單層金屬層結構 或是複合式金屬層結構，此金屬層122之厚度介於1微米 至20微米，較佳之厚度可介於1. 5微米至丨5微米之間， 而複合式金屬層結構之組合包括銅/鎳/金、銅/金、銅/錄/ 把及銅/鎳/鉑等組合’在此實施例中此金屬層122係為單 層’而金屬層122之材質係為金，位在聚合物凸塊114上 之金屬層122表面定義一區域為接合接墊〗24，此接合接 塾124可用於連接外界電路，此外界電路包括印刷電路 板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基板 其中之一，而位在聚合物塊148上之金屬層122表面定義 一區域為打線接墊136，此打線接墊136經由打線製程於 連接外界電路，其中位在打線接墊136下的聚合物塊148 在打線製程時可緩衝打線所產生的應力，對於厚度較薄的 基底10有足夠的緩衝效應，可以防止積體電路1〇〇之基底 10、元件層12之主動元件在打線製程時損壞，此外此實施 例態樣由上視透視圖觀之打線接塾136與接塾32’之位置 不同，但是打線接墊136也可以位在接墊32,上方，在此 就不加重覆論述。 請參閱第10g圖所示’去除圖案化光阻層12〇及去除 未在金屬層122下方的種子層118、黏著阻障層116。 請參閱第1 Oh圖所示’將積體電路1〇〇進行切割步驟， 產生複數半導體晶片（chip)126。 48 1342594 請參閱S ηη圖所示，將半導體晶片126經由覆晶 (FlipChip，FC)技術接合至另一外界基板138上其中 接合的方式可採肖鐘合时式，使外界基板138上之接 合金屬層142與接合接#124上之金制122|生融合或 合金（金/金接合或金-錫合金）接合，並且在外界基板138 與半導體晶片126之間形成—封裝層144將其包覆，此封 裝層144之材質係為聚合物材質，比如是環氧樹脂。另外 打線接墊136則經由打線製程形成一導線146連接至另一 外界電路（圖巾未示）上，此外界電路包括印刷電路板金 屬基板、玻螭基板、軟性基板、陶瓷基板及矽基板其中之 笼3實施例之篦1能蛘： 此實施例之結構中基底10、元件層12、金氧半電晶體 14、源極16、汲極18、閘極2〇、細線路結構22、細線路 介電層26、導電栓塞30等以積體電路1〇〇代替，且積體 電路100中的各結構及製程在上述實施已完整說明，因此 實施例中的積體電路100中的各結構及製程就不加以重覆 說明。 請參閱第na圖所示’形成一聚合物層112在整個積 體電路100上的保護層34及接墊32上。 請參閱第lib圖所示，並透過曝光（exposure)、顯影 (development)製程及蝕刻製程圖案化此聚合物層112,使 此聚合物層112形成複數聚合物凸塊（p〇iymer 49 1342594 bump) 114(圖示中僅顯示出1個），而保護層34及接墊32 暴露於外，接著進行加熱硬化，使此聚合物凸塊114硬化， 此硬化過程的溫度係介於150度（°C)至300度（。〇之間， 且此聚合物凸塊114之材質可選自聚醯亞胺（polyimide， PI)、苯基環丁稀（benzocyclobutene，BCB)、聚對二甲笨 (parylene)、環氧基材料（epoxy-based material)其中之 一 ’例如環氧樹脂或是由位於瑞士之Renens的s〇tecMicrosystems offers ph〇t〇ep〇xy SU-8, an elastomer (elastomer) such as silicone. When the polymer layer U2 is a photosensitive material, the polymer layer 112 can be patterned by using only a lithography process (without an etching process), and the polymer bump 114 has a thickness of 5 micrometers to 50 micrometers, and is polymerized. The maximum lateral dimension of the bumps 4 is between 1 μm and 60 μm, and the polymer bumps 114 are circular, square, quadrangular or polygonal, etc. from a top view, and in this embodiment, the polymer bumps Block 114 is located above the active component within the integrated circuit 1〇〇. Referring to FIG. 2c, an adhesion/bairier layer 116 is formed on the protective layer 34, the pads 32 and the polymer bumps 114 on the entire integrated circuit 10, and the adhesion/barrier layer is formed. 116 includes titanium, titanium tungsten alloy, titanium nitride, button, tantalum nitride, chromium (Cr) or nickel. In addition, the adhesion/barrier layer 116 can be formed by means of electrification, electroless plating, chemical vapor deposition or physical vapor deposition (for example, sputtering). Deposition is a preferred form of formation, such as a metal sputtering process. In addition, the thickness of the adhesive barrier layer 116 is 0. 02 microns to 0. A thickness of between 8 microns and between 〇 5 microns and 〇 2 microns is preferred. Please refer to Figure 2d, and then form a thickness between 〇〇〇5 μm and 2 μm (preferably thickness is between 〇. A seed layer 118 between 丨 microns and 〇 7 microns) is on the adhesion/barrier layer 116, and the seed layer 118 is formed by, for example, 贱 bond, 7 pure, physical vapor deposition, electricity or It is a way of electroless plating. This seed 22 1342594 layer 118 facilitates the placement of subsequent metal lines, so the material of the seed layer 118 will vary with the material of the subsequent metal line. For example, when the seed layer 118 is plated to form a metal layer of copper, the material of the seed layer 118 is preferably copper; when the seed layer 118 is plated with a metal layer of gold, the material of the seed layer 118 is made of gold. Preferably, when the seed layer 118 is plated to form a metal layer of palladium material, the material of the seed layer 118 is preferably palladium; when the seed layer 118 is plated with a metal layer of platinum, the material of the seed layer ι18 is platinum. Preferably, when the seed layer 118 is plated to form a metal layer of tantalum material, the material of the seed layer 118 is preferably 铑; when the seed layer ns is charged with a metal layer of tantalum material, the material of the seed layer 118 is Preferably, when the seed layer 118 is plated to form a metal layer of tantalum material, the material of the seed layer 118 is preferably 铢; when the seed layer 118 is plated with a metal layer of nickel, the material of the seed layer 118 is recorded as good. Referring to FIG. 2e, 'forming a photoresist layer 120 on the seed layer 118 and patterning the photoresist layer 120' through an exposure and development process to form a plurality of photoresist layers 12 as in The photoresist layer 12 is exposed to the seed layer 118 above the pad 32 and the polymer bumps 114, and is exposed by a factor of 1 (1X) during the formation of the photoresist layer opening 12A. Exposure development is performed by steppers or scanners. There are two types of the photoresist layer 120, which are: (1) a liquid photoresist ‘which is formed by a single or multiple spin coating method or a printing method. The thickness of the wet film photoresist is between 3 microns and 60 microns, and preferably between 5 microns and 4 microns; and (2) dry film photoresist, It is formed by a 23 1342594 laminating method. The thickness of the dry film photoresist is between 30 micrometers and 300 micrometers, and preferably between 50 micrometers and 150 micrometers. In addition, the photoresist may be positive-type or negative-type, and in order to obtain better resolution, a positive-type thick photoresist is preferred. This photoresist is exposed by an aligner or a double (IX) stepper. This double (1χ) refers to the ratio of the pattern on the reticle to the wafer when the light beam is projected onto the wafer from a reticle (usually composed of quartz or glass), and the pattern on the reticle The ratio is the same as the pattern on the wafer. The beam wavelength used by the aligner or double stepper is 436 g-line, 397-h (line), 365 nm (i-line), g/h line (combined G-line and h-line) or g/h/i line (combined with g-line, h-line and i-line). Use a double stepper (or double aligner) with a beam wavelength of g/h line or g/h/i line to provide 'on exposure to thick photoresist or thick photosensitive polymer' (photosenstive polymer) A larger light intensity; in addition, the shape of the opening 120a of the patterned photoresist layer 120 may also include a coil shape, a square shape, a circular shape, a polygonal shape, or an irregular shape. Referring to FIG. 2f, a metal layer 122 is formed by electroplating on the seed layer 118 in the opening 120a. The metal layer m covers at least the seed layer 118 above the two surfaces of the polymer bump 114, and the metal layer 122 is a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure. The thickness of the metal layer 丨22 is between j micrometers and 20 micrometers. The thickness can range from 15 microns to 15 microns, and the combination of composite metal layer structures includes copper/nickel/gold, copper/gold, copper 24 1342594/nickel/palladium, and copper/nickel/platinum combinations. In the embodiment, the metal layer 122 is a single layer 'the metal layer 122 is made of gold, and the surface of the metal layer 122 on the polymer bump defines a region as a bonding pad 124. The bonding interface 124 can be used for The external circuit is connected, and the external circuit includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. Referring to Fig. 2g, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 116 which are not under the metal layer 122 are removed. Referring to FIG. 2h, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 126. The bonding pads 124 on the semiconductor wafer 126 can be automatically bonded via tape bonding (tape a Ut〇mated bonded' TAB), COG (chip on glass), tape carrier (TCP) or COF (chip on film) is connected to an external circuit 128 having at least one bonding metal layer 129. The bond pads 124 are connected to the bond metal layer -29. As shown in FIG. 2i, the present embodiment is connected to the external circuit 28 in a c〇G manner, and the bonding pads 124 on the semiconductor wafer 126 are bonded to the bonding metal layer of the external circuit 128 by the anisotropic conductive paste 13〇. 129. Referring to FIG. 2j, if the embodiment is connected to the external circuit 128 in the c〇F manner, the bonding pads 124 on the semiconductor wafer 126 are also bonded to the external circuit 128 by using the anisotropic conductive adhesive. Another way of bonding the bonding metal layer 129 to the metal layer 129 is shown in the figure, which is to bond the bonding interface 124 on the semiconductor wafer 126 to the circuit containing the kick boundary by thermocompression bonding. 128, the bonding between the gold on the bonding pad 125 and the tin layer 132 on the bonding metal layer 129 to form a tin-gold alloy layer 134 is formed by thermal bonding, and the bonding by thermocompression bonding is also applicable. To tape automated bonded (TAB) and Tape Carrier Package (TCP). After the m 2 state of the first embodiment: the structure and manufacturing method of the second aspect are quite similar to those of the first aspect. Therefore, the materials and processes of the same components in the following embodiments and aspects are Do not repeat the instructions. Referring to Fig. 3a, the difference between the second aspect and the first aspect is that the integrated circuit 1 of the second aspect has two pads 32, 32, and the polymer layer 112 is formed in the same product. The protective layer 34 and the pads 32, 32 on the body circuit 1 are on top. Referring to FIG. 3b, the polymer layer 112 is patterned by an exposure process, a development process, and an etching process to form the polymer layer 112 into a plurality of polymer bumps (p〇lymer burap). 114 (only one is shown in the drawing), the opening 112a exposes the protective layer 34 and the pads 32, 32', and then heat hardens to harden the polymer bumps 114. When the polymer bump 114 is a photosensitive material, the polymer bump 114 can be patterned by using only a lithography process (without an etching process), and the polymer bump 114 has a thickness of 5 micrometers to 5 Å. The micron, polymer bumps 114 have a maximum lateral dimension of from 1 micron to 6 microns. Referring to FIG. 3c, an adhesive barrier layer 116 is formed on the entire protective layer 34, the pads 32, 26 1342594 32', and the polymer bumps 114. The adhesion/barrier layer n6 comprises a zirconia, a tungsten alloy, a titanium nitride, a tantalum, a nitride button, a chromium (Cr) or a nickel. The thickness of the adhesion barrier layer 116 is between 〇. 02 micron to 〇. Between 8 microns and between 〇 5 microns to 0. A thickness between 2 microns is preferred. Please refer to the 3d circle as shown below. A seed layer 118 between 5 microns and 2 microns (preferably between 〇丨 microns and 〇 7 microns) is on the adhesion/barrier layer 116. Referring to FIG. 3e, the photoresist layer 12 is formed on the seed layer 118, and the photoresist layer 120 is patterned by an exposure and development process to form a plurality of photoresist layer openings 12. 〇a, 12〇b are in the photoresist layer 120 and expose the seed layer 118 over the pads 32, 32' and the polymer bumps 114, respectively. Referring to FIG. 3f, the metal layer 122 is formed by electroplating on the seed layer 118 in the openings 120a, 120b. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bumps 114, and the metal layer. The ι 22 is, for example, a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure, and the thickness of the metal layer 122 is between 1 micrometer and 20 micrometers, preferably. The thickness may range from 15 microns to 15 microns, and the combination of composite metal layer structures includes combinations of copper/nickel/gold, copper/gold, copper/nickel/palladium, and copper/nickel/platinum, in this embodiment. The metal layer 122 is a single layer, and the metal layer 122 is made of gold. The two regions defined on the surface of the metal layer 22 are respectively a bonding pad 124 and a bonding pad 136. The bonding interface 124 is in the middle. The polymer bumps 114 are located on the pads 32'. The bonding pads 124 and the wire bonding pads 136 can be used to connect the external circuits including the printed circuit board, the metal substrate, and the glass. One of a substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. Referring to Fig. 3g, the patterned photoresist layer is removed and the seed layer ι18 and the adhesion barrier layer 116 which are not under the metal layer 122 are removed. Referring to FIGS. 3h and 3i, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 126, and the bonding pads 124 on the semiconductor wafer 126 can be flipped (Flip Chip, Fc). The technology is bonded to another external substrate 138, such as a semiconductor wafer. When the external substrate 138 is a semiconductor wafer, the external substrate 138 has a plurality of bonding pads 140 and a bonding metal on the bonding pads 140. The material of the bonding metal layer 142 includes a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium, tin or nickel or a composite metal layer structure, and the bonding metal layer 142 The material of the metal layer 122 is changed. For example, when the material of the metal layer 122 is gold, the material of the bonding metal layer 142 is a metal layer of gold or tin, and then F1 ip chip (FC) technology is used. The external substrate 138 is stacked on the semiconductor wafer 126, wherein the bonding is performed by thermal bonding, and the bonding metal layer 142 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy). And forming an encapsulation layer 144 is coated thereon, the encapsulation layer 144 made of a polymer-based material, an epoxy resin between the outside than the case of the substrate 138 and the semiconductor wafer 126. In addition, the wire bonding pad 136 is connected to another external circuit (not shown) via a wire bonding process, and the external circuit includes a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a stone substrate. one of them. 28 1342594 Please refer to Figures 3j and 3k. In addition, the wire bonding pad 36 can be connected to another external circuit by using a wire formed by a wire bonding process, which includes a printed circuit board, a metal substrate, and a glass. One of the substrate, the flexible substrate, the ceramic substrate and the germanium substrate may also be connected to the solder ball 147 of the external circuit. As shown in FIG. 3k, the thickness of the solder ball 147 is between 50 micrometers and 3 turns. Between the micrometers, this connection can be joined by thermocompression bonding.第1 Example 3: The structure and manufacturing method of the third aspect are quite similar to the structure and manufacturing method of the second aspect and the second aspect, so the same components in the following embodiments and aspects The materials and processes are not repeated. Referring to FIGS. 4a and 4b, the difference between the third aspect and the second aspect is only that the position of the wire bonding pad 136 is different, and the position of the wire bonding pad 136 of the third aspect is from a top perspective view. )图), the wire pad ι36 position is different from the position of the pad 32, the wire bonding pad 136 can provide a wire bonding wire via the wire bonding wire to the external circuit, the external circuit including the printed circuit board One of the metal substrate, the glass substrate, the flexible substrate, the ceramic substrate, and the germanium substrate, wherein at least one active component may be disposed on the substrate 1 in the integrated circuit 100 below the wire bonding pad 136, and the active component includes two The polar body, the transistor, etc., the active components have been described in detail in the above-mentioned component layer 12, and will not be repeatedly discussed here. Referring to FIG. 4c, the integrated circuit 100 is subjected to a dicing step to generate a plurality of semiconductor chips 126. The bonding on the semiconductor wafer 126 29 1342594 pads 124 can be bonded via Flip Chip (FC) technology to On the other external substrate 138, the external substrate 138 is, for example, a semiconductor wafer. When the external substrate 138 is a semiconductor wafer, the external substrate 138 has a plurality of bonding pads 140, and has a bonding metal layer 142 on the bonding pads 14? The material of the bonding metal layer 142 includes a single metal layer structure of gold, copper, silver, hexa, bismuth, lanthanum, cerium, lanthanum, tin or nickel or a composite metal layer structure, and the bonding metal layer 142 will follow the metal. The material of the layer 122 is changed. For example, when the material of the metal layer 122 is gold, the material of the bonding metal layer 142 is a metal layer of gold or tin, and then the external substrate 138 is formed by Flip Chip (FC) technology. Stacked on the semiconductor wafer 126, wherein the bonding can be performed in a thermal compression manner to cause the bonding metal layer 142 to be fused or alloyed (gold/gold bonding or gold-tin alloy) to the metal layer ι22, and Forming a cladding 144 which is outside the encapsulation layer between the substrate 138 and the semiconductor wafer 126, this material based encapsulation layer 144 of a polymer material, such as an epoxy resin. In addition, the wire bonding pad 136 forms a wire through the wire bonding process! 46 is connected to another external circuit (not shown) including one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a ruthenium substrate. - 4th _枰 of the first embodiment: The structure and manufacturing method of the fourth aspect are quite similar to those of the third aspect and the first aspect, and therefore the same in the following embodiments and aspects The material and process of the components are not repeated. Referring to Fig. 5a, the protective layer 34 and the pads 32 and pads 32' of the polymer layer n2 are formed over the entire body 1301. Referring to FIG. 5b, the polymer layer 112 is patterned by an exposure, development process, and a process to form the polymer layer 112 into a plurality of openings 112a and a plurality of polymer blocks. Is land 142, the opening 112a exposes the protective layer 34, the interface 32 and the pad 32', and then heat hardens to harden the polymer block 148. The temperature of the hardening process is between 150 degrees (° C.) and 300 Between degrees (°C), and the material of the polymer block 148 may be selected from the group consisting of polyimide (PI), benzocyclobutene 'BCB, parylene, epoxy. One of the epoxy-based materials, such as epoxy resin or photoepoxy SU-8, an elastomer (elastomer) provided by Sotec Microsystems, Renens, Switzerland, such as Si 1 icone. When the polymer layer 112 is a photosensitive material, the polymer layer 112 can be patterned using only a lithography process (without an etching process), and the polymer block 148 has a thickness of 5 to 50 μm. Referring to FIGS. 5c and 5d, another polymer layer 150 is formed in the polymer block 148 and the opening 112a. The polymer layer 150 is made of the same material as the polymer layer 112 and is exposed through an exposure. The development process and the engraving process pattern the polymer layer 150 to form a plurality of polymer bumps 152 (only one is shown in the drawing), wherein the polymer layer 150 is a photosensitive material. The polymer layer 150 can be patterned using only a lithography process (without an etch process), and the polymer bump thickness is between 5 micrometers and 50 micrometers, and the polymer bumps 152 31 have a maximum lateral dimension of 10 micrometers to 60 microns. Referring to FIG. 5e, a pad 32, a pad 32, a polymer bump 152, and a polymer block are formed on the entire integrated circuit 1A by an adhesive barrier layer 116. On 148. Please refer to Figure 5f, and then form a thickness of 0. A seed layer 118 between 005 microns and 2 microns (preferably having a thickness between 〇1 μm and 〇 7 μm) is on the adhesion/barrier layer 116. * Referring to FIG. 5g, a photoresist layer 12 is formed on the seed layer 118, and the photoresist layer I20 is patterned by an exposure and development process to form a plurality of photoresist layers. 120a is within the photoresist layer 120 and exposes the seed layer 118 over the pads 32, pads 32, polymer bumps 152 and polymer blocks 148, and in the process of forming the photoresist layer opening 12a For example, exposure and development are performed by one-time (1 inch) steppers or scanners. Referring to FIG. 5h, the metal layer 122 is formed by electroplating on the seed layer 118 in the opening 120a. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 152, and the metal layer 122 is It is a single-layer metal layer structure of gold, copper or silver 'palladium' platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure. The thickness of the metal layer 122 is from 丨 micrometer to 20 micrometers, and the thickness is preferably Between 15 microns and 15 microns' and the combination of composite metal layer structures includes copper/nickel/gold, copper/gold, copper/nickel/battery and copper/record/platinum combinations, in this embodiment the metal The layer i 22 is a single layer, and the metal layer 122 is made of gold. The surface of the metal layer 122 on the polymer bump 152 defines a region as a bonding pad 124. The bonding pad 32 1342594 pad 124 can be used for connection. The external circuit includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate, and a surface of the metal layer 122 on the polymer block 148 defines a region as a wire bonding pad 136. The wire bonding pad 136 is processed by a wire bonding process. The external circuit is connected, wherein the polymer block ι48 under the wire bonding pad 136 can buffer the stress generated by the wire bonding during the wire bonding process, and has sufficient buffering effect on the thin substrate 10 to prevent the integrated circuit 1〇〇. The active component of the substrate 10 and the component layer 12 is damaged during the wire bonding process. In addition, the position of the wire bonding interface 148 and the interface 32' is different from the top view. However, the wire bonding pad 136 can also be positioned. Above the pad 32, it will not be repeated here. Referring to Fig. 5i, the patterned photoresist layer 120 is removed and the seed layer 118 and the adhesion barrier layer 116 which are not under the metal layer 122 are removed. Referring to FIG. 5j, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 126. Referring to FIG. 5k, 'this FIG. 5k is similar to the above-mentioned 3i, and the semiconductor wafer 126 is bonded to another external substrate 138 via FlipChip (FC) technology, wherein the description of the bonding is as described above. The diagram is the same, so it will not be repeated here. ϋ-L is suitable for the flute 5 sample: The structure and manufacturing method of the fifth aspect is quite similar to the structure and manufacturing method of the fourth aspect, and the structure of the fourth aspect is the change of the first aspect, The materials and processes of the same components in the following embodiments and aspects are not repeated by 33 1342594. Referring to FIG. 6a, the difference between the fifth aspect and the fourth aspect is an exposure, a development process, and an etching process for patterning the polymer layer 112 and heat hardening, in the fifth aspect. In this two steps, the polymer block 148 and the polymer bump 114 are simultaneously formed, that is, the thickness of the polymer block 148 and the polymer bump 114 are the same, and the thickness of the polymer block 148 and the polymer bump 114 is between 5. Micron to 50 microns. Referring to Figure 6b, an adhesion/barrier layer 116 is formed in sequence and the thickness is between 0. Between 005 micrometers and 2 micrometers (the preferred thickness is between 〇.  A seed layer 18 of 1 micron to 〇 7 micrometers is placed on the pads 32, pads 32', polymer bumps 4, and polymer blocks 48 of the entire integrated circuit. Please refer to FIG. 6c to form a photoresist layer 12 on the seed layer n8 and pattern the photoresist layer 120' through an exposure and development process to form a complex photoresist layer opening i2〇a. Within the photoresist layer 120 and exposing the seed layer 118 over the pads 32, pads 32', polymer bumps 114 and polymer blocks 148, in the process of forming the photoresist layer opening 〇 2 〇 a For example, the exposure is developed by a double (IX) stepper or a scanner. Referring to FIG. 6d, the metal layer 122 is formed by electroplating on the seed layer 118 in the opening 120a. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bumps 114. Is a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure, the thickness of the metal layer 122 is between 丨 micron to 2〇34 1342594 micron' The thickness can range from 丨 5 μm to 15 μm, and the combination of composite metal layer structures includes copper/nickel/gold, copper/gold, copper/nickel/palladium, and copper/nickel/platinum combinations. In the embodiment, the metal layer 122 is a single layer, and the metal layer 122 is made of gold. The surface of the metal layer 122 on the polymer bump defines a region as a bonding pad 124. The external circuit includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate, and a surface of the metal layer 122 on the polymer block 148 defines a region as a wire. a pad 136, the wire bonding pad 136 is connected by a wire The polymer block 148, which is placed under the wire bonding pad 136, can buffer the stress generated by the wire bonding process during the wire bonding process, and has sufficient buffering effect for the thinner substrate 1 ' to prevent the integrated circuit. The active component of the substrate 1 and the component layer 12 is damaged during the wire bonding process. In addition, the position of the wire bonding device 136 and the pad 32' are different from the top view, but the wire is connected. 136 can also be located at the top of the interface 32, and will not be repeated here. Referring to Figure 6e, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 116 that are not under the metal layer 122 are removed. Referring to Fig. 6f, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 126. Referring to FIG. 6g, the 6g figure is similar to the above-mentioned 3th figure, and the semiconductor wafer 126 is bonded to another external substrate 138 via FlipChip (FC) technology, wherein the description of the bonding is as described above. The 3i diagram is the same, so it will not be repeated here. 35 1342594 1st embodiment of the agricultural 2 embodiment: the substrate 1 〇, the element layer 12, the MOS transistor 14, the source 16, the drain 18 'gate 2 〇, the fine line structure 22 in the structure of this embodiment The fine-line dielectric layer 26, the conductive plug 30, and the like are replaced by the integrated circuit 1〇〇, and the structures and processes in the integrated circuit 100 have been fully described in the above embodiment, so the integrated circuit 1 in the embodiment The structures and processes in the process are not repeated. Referring to Fig. 7a, a polymer layer I is formed on the protective layer 34 and the interface 32 on the entire integrated circuit 100. Referring to FIG. 7b, the polymer layer 112 is patterned by exposure (eXp〇sure), development process, and etching process to form the polymer layer 112 into a plurality of polymer bumps. 114 (only one is shown in the drawing), and the protective layer 34 and the interface 32 are exposed to the outside, followed by heat hardening to harden the polymer bump U4, and the temperature of the hardening process is 150 degrees ( (:) to 300 degrees (between (:)), and the material of the polymer bump 114 may be selected from the group consisting of p〇iy imide (PI), benzocyclobutene (BCB). , one of parylene, ep〇xy-based material such as epoxy resin or photoepoxy SU-8, elastic material supplied by Sotec Microsystems, Renens, Switzerland ( "elastomer", for example, si 1 i cone. When the polymer layer 112 is a photosensitive material, the polymer layer 112 can be patterned using only a lithography process (without an etching process), and the polymerization is performed. The bump 114 has a thickness of 5 36 1342594 micrometers to 50 micrometers. The maximum lateral dimension of the bumps 114 ranges from 1 μm to 60 μm, and the polymer bumps 114 are circular, square-opened, quadrangular or polygonal, etc. from the top view. In addition, the polymer bumps 114 cover the entire 32- a portion of the region, and the region exposed by the interface 32 is defined herein as a conductive region 154'. The conductive region 154 has a mobility of between 3 microns and 20 microns or between 2 microns and 15 microns. 7c shows that the polymer bump 114 is covered by the side of the #32 in this embodiment, so that the conductive region 154 is a quadrangle or a polygon, etc., from the top view, and the conductive region is exposed. 154 The ratio of the area to the surface area of the metal pad is from 〇丨g to 〇〇g or 〇〇5 to 〇.  Between 5 Referring to Fig. 7d, an adhesive barrier layer (adhesi〇n/baiTier layer) U6 is formed on the protective layer 34, the conductive region 154 and the polymer bump 114 on the entire integrated circuit 1 The barrier layer 116 includes titanium, titanium tungsten alloy, titanium nitride button nitride button π. Or nickel. Another 'adhesive/barrier layer 116 can be formed by electroplating, electroless deposition, chemical vapor deposition or physical vapor deposition (such as sputtering), in which physical gas Phase deposition is a preferred formation method, such as a metal sputtering process, and the thickness of the adhesion barrier layer ι 6 is; between micrometers and Q 8 micrometers and between 〇 micrometers to 0. A thickness between 2 microns is preferred. Referred to Figure 7e, a seed Uyer U8 with a thickness between 0-005 microns and 2 microns (preferably between 〇j microns and 〇7 microns) is formed. The formation of the 37 丄 342594 seed layer 118 on the barrier layer ι 6 is, for example, by sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. This seed layer 118 facilitates the placement of subsequent metal lines, so the material of the seed layer 118 will vary with the material of the subsequent metal lines. For example, when the seed layer 118 is plated to form a metal layer of copper, the material of the seed layer 118 is preferably copper; when the seed layer 118 is plated with a metal layer of gold, the material of the seed layer 118 is made of gold. Preferably, when the seed layer 118 is plated to form a metal layer of palladium, the seed layer 118 is preferably made of palladium; when the seed layer 118 is plated to form a metal layer of platinum, the seed layer 118 is made of platinum. Preferably, when the seed layer 118 is plated to form a metal layer of tantalum material, the material of the seed layer 118 is preferably ;; when the seed layer U8 is plated with a metal layer of tantalum material, the material of the seed layer 118 is preferably 钌. When the seed layer 118 is plated to form a metal layer of tantalum material, the material of the seed layer 118 is preferably 铢; when the seed layer 118 is plated to form a metal layer of nickel material, the material of the seed layer 118 is preferably nickel. . Referring to FIG. 7f, a photoresist layer 12 is formed on the seed layer U8 and the photoresist layer 120' is patterned by an exposure and development process to form a plurality of photoresist layer openings. a in the photoresist layer 12〇 and exposed on the seed layer 118 above the pad 32 and the polymer bumps 114', and in the process of forming the photoresist layer opening i2〇a, for example, is - (IX) Exposure development is performed by steppers or scanners. There are two types of the photoresist layer 120, which are: (1) a liquid photoresist which is formed by a single or multiple spin coating method or a printing method. The thickness of the wet film photoresist is between 38 1342594 3 microns and 60 microns 'and preferably between 5 microns and 40 microns; and (2) dry film photoresist, It is formed by a laminating method. The thickness of the dry film photoresist is between 30 micrometers and 300 micrometers, and preferably between 50 micrometers and 150 micrometers. Further, the photoresist may be a positive-type or a negative-type, and in order to obtain a better resolution, a positive-type thick photoresist is preferred. The photoresist is exposed using an aligner or a double (IX) stepper. This double (ιχ) refers to the ratio of the pattern on the reticle to the wafer when the light beam is projected onto the wafer from a reticle (usually composed of quartz or glass), and the pattern on the reticle The ratio is the same as the pattern on the wafer. The beam wavelength used by the aligner or double stepper is 436 nm (g_line), 397 nm (h-line), 365 nm (i-line), g/h iine (combined with g_)丨ine and h_line) or g/h/i line (combined with g-line, h-line and i-line). Use a double stepper (or double aligner) with a beam wavelength of g/h line or g/h/i line for thick photoresist or thick photosensitive polymer (ph〇t〇senstive polymer) The exposure is 'it' for a larger light intensity (Hght strength); in addition, the shape of the opening i2〇a of the patterned photoresist layer 120 may also include a coil shape, a square shape, a circular shape, a polygonal shape, or an irregular shape. Referring to FIG. 7g, a metal layer 122 is formed by electroplating on the seed layer 118 in the opening 120a. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 114, and the metal layer 122 such as a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure, the thickness of the metal layer 122 is between 39 1342594 1 micrometer and 20 micrometers. Preferably, the thickness can be between 15 micrometers and 15 micrometers, and the combination of composite metal layer structures comprises a combination of copper/nickel/gold, copper/gold, copper/nickel/palladium, and copper/nickel/platinum. In the example, the metal layer 122 is a single layer, and the metal layer 122 is made of gold. The surface of the metal layer 122 on the polymer bump 114 defines a region as a bonding pad 124. The bonding pad 124 can be used for The external circuit is connected, and the external circuit includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. Please refer to the figure 7h for 'removing the patterned photoresist layer 12 and removing the seed layer us below the metal layer 122. The adhesion barrier layer is shown in Fig. 7i, and the integrated circuit is cut. In the step of generating a plurality of semiconductor chips 114, the bonding pads 124 on the semiconductor wafer 126 can be bonded via tape bonding (TAB), COG (chip on glass), and tape-type die bonding ( a tape carrier package (TCP) or a COF (chip on film) is connected to an external circuit 128, which includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. The junction circuit 128 has at least one bonding metal layer 129 to which the bonding pads 124 are connected. As shown in FIG. 7j, the present embodiment is connected to the external circuit 128 in a c〇G manner, and the bonding pads 124 on the semiconductor wafer ι26 are bonded to the bonding metal layer 129 of the external circuit 128 by the anisotropic conductive paste 130. . Referring to FIG. 7k, if the embodiment is connected to the external circuit 128' by the c〇F method, the bonding pads 124 on the semiconductor wafer 40 1342594 126 are also bonded to the outside by the anisotropic conductive paste 130. The bonding of the metal layer 129 of the circuit 128, another way of bonding, please refer to Fig. 71, which is to bond the bonding pads 124 on the semiconductor wafer 126 to the tin-containing layer by thermocompression bonding. On the external circuit 128, the gold on the bonding pad 124 and the tin layer 132 on the bonding metal layer 129 are firmly bonded by the tin-bonding layer 134 on the bonding pad 124. This method can also be applied by thermocompression bonding. To tape aut〇mated b〇nded TAB and Tape Carrier Package (TCP). The second embodiment of the second embodiment can be similar to the structure and manufacturing method of the second aspect. Therefore, the materials and processes of the same components in the following embodiments and aspects are Do not repeat the instructions. Referring to FIG. 8a, the difference between the second aspect and the first aspect is that the integrated circuit 1 of the second aspect has two interfaces 32, 32'' which also form the polymer layer 112 in the entire product. The protective layer 34 and the pads 32'32 on the body circuit 100 are on. Referring to FIG. 8b' and patterning the polymer layer 112 by an exposure process, a development process, and an etching process, the polymer layer 112 forms a plurality of polymer bumps (p〇 Lymer • ^^"11>) 114 (only one is shown in the drawing) 'The opening 1123 exposes the protective layer 34 and the pads 32, 32, and then heat-hardens to harden the polymer bumps 114. When the polymer bump 1H is a photosensitive material, the polymer bump 41 1342594 114 can be patterned by using only a lithography process (without an etching process), and the polymer bump ι 14 has a thickness of 5 μm to The 5 Å micron, polymer bump 114 has a maximum lateral dimension of between 1 micron and 6 micron. In addition, the polymer bumps 114 cover a portion of the pad 32, and the exposed regions of the pads 32 are defined herein as conductive regions 154 having a twist of between 3 microns and 2 microns. Or between 2 microns and "micron. Please refer to FIG. 8c, where the polymer bump 114 covers one side of the interface 32 in this embodiment, so that the conductive region 154 is quadrilateral or polygonal, etc., from the top view. The ratio of the area of the conductive region 154 to the surface area of the metal pad is 〇丨·〇·9 or 〇〇5 to 0.  Between 5 Referring to FIG. 8d, a protective layer 34, a conductive region 154, a pad 32' and a polymer bump 114 are formed on the entire integrated circuit 1 by an adhesive barrier layer 116. Above, the adhesion/barrier layer ιΐ6 includes chin, titanium alloy, titanium nitride, and nitrided ruthenium ((7) or recorded, the thickness of the adhesion barrier layer 116 is between 〇. 〇 2 micro card to 〇 8# meters and between 0. A thickness between 05 micrometers and 2 micrometers is preferred. Referring to Figure 8e, a seed layer 118 having a thickness between 〇〇〇5 μm and 2 μm (preferably between 〇1 μm and 〇7 μm) is formed. / barrier layer ία. Referring to FIG. 8f, the photoresist layer 12 is formed on the seed layer ι8, and the photoresist layer 120 is patterned by an exposure and development process to form a plurality of photoresist layer openings 12. For example, the 12 ribs are within the photoresist layer 120 and expose the seed layer 118 over the pads 32, 32, and the polymer bumps ι 4 42 1342594, respectively. Referring to FIG. 8g, the metal layer 122 is formed by electroplating on the seed layer 118 in the openings 120a, 120b. The metal layer 122 covers at least the seed layer 118 above the surface of the polymer bump 14 and the metal layer. 122 such as a single layer metal layer structure of sheet metal, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure, the thickness of the metal layer 122 is between 1 micrometer and 20 micrometers, preferably The thickness can range from 15 microns to 15 microns, and the combination of composite metal layer structures includes combinations of copper/nickel/gold, copper/gold, copper/nickel/palladium, and copper/nickel/platinum, in this embodiment. The metal layer 122 is a single layer, and the metal layer 122 is made of gold. The two regions defined on the surface of the metal layer 122 are respectively a bonding pad 124 and a bonding pad 136. The bonding pads 124 are in the polymer. The bumps 114 are located on the pads 32'. The bonding pads 124 and the bonding pads 136 can be used to connect external circuits, including printed circuit boards, metal substrates, glass substrates, and flexible substrates. One of a ceramic substrate and a tantalum substrate. Referring to FIG. 8h, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 116 that are not under the metal layer 122 are removed. Referring to FIGS. 8i and 8j, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips i26, and the bonding pads 124 on the semiconductor wafer 126 can be flipped (Flip Chip, The FC technology is bonded to another external substrate 138, such as a semiconductor wafer. When the external substrate 138 is a semiconductor wafer, the external substrate 138 has a plurality of bonding pads 140' having a bond on the bonding pads 140. The metal layer 142 'the material of the bonding metal layer 142 includes a single metal layer structure of gold, copper, silver, palladium, 43 1342594 surface, tantalum, niobium, tantalum, tin or nickel or a composite metal layer structure 'this bonding metal Layer 142 will vary with the material of metal layer 122 'eg metal layer! When the material of 22 is gold, the material of the bonding metal layer 142 is a metal layer of gold or tin, and then the external substrate 138 is stacked on the semiconductor wafer 126 by using a flip chip technology (FUpChip) technology. In a thermocompression bonding manner, the bonding metal layer 142 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy) and an encapsulation layer 144 is formed between the external substrate 138 and the semiconductor wafer 126. The material of the encapsulation layer 144 is a polymer material such as 疋% oxygen resin. In addition, the wire bonding pad 36 is connected to another external circuit (not shown) via a wire bonding process, and the external circuit includes a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and One of the broken substrates. Referring to FIG. 8k, in addition, the wire bonding pad 136 can be connected to another external circuit by using a wire 146 formed by a wire bonding process, and can also be connected to the solder ball 147 of the external circuit, as shown in FIG. 8k. The thickness of the ball 147 is between 50 micrometers and 300 micrometers, and this connection can be joined by thermocompression bonding. The first Gosch Kui situation.  The structure and manufacturing method of the third aspect are similar to those of the third aspect and the second aspect, and therefore the materials and processes of the same components in the following embodiments and aspects are not repeated. Description. Referring to Figures 9a and 9b, the difference between the third aspect and the second aspect 1342594 is only that the position of the wire bonding pad 136 is different, and the position of the wire bonding terminal 136 of the third aspect is from a top perspective view ( Figure 9b) Viewing the 'wire alignment 136 position is different from the position of the pad 32', the wire bonding pad 136 can provide a wire bonding wire via the wire bonding wire to the external circuit, the external circuit including the printed circuit One of the board, the metal substrate, the glass substrate, the flexible substrate, the ceramic substrate, and the germanium substrate, wherein at least one active component is disposed on the substrate 1 in the integrated circuit 100 below the wire bonding pad 136, the active component includes a The 'active elements of polar bodies, transistors, etc. have been described in detail in the above-mentioned element layer 12' and will not be repeated here. Referring to Fig. 9c, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 114. The bonding pads 124 on the semiconductor wafer 126 can be bonded via flip chip (FC) technology. The external substrate 138 is a semiconductor wafer, and the external substrate 138 is a semiconductor wafer. The external substrate 138 has a plurality of bonding pads 140 and a bonding metal layer 142 on the bonding pads 14A. The material of the bonding metal layer 142 includes a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, iridium, chain, tin or tantalum or a composite metal layer structure, and the bonding metal layer 142 will follow The material of the metal layer 122 is changed. For example, when the material of the metal layer 122 is gold, the material of the bonding metal layer 142 is a metal layer of gold or tin, and then the external substrate 138 is formed by flip chip (FlipChip, FC) technology. The semiconductor wafer 126 is stacked on the semiconductor wafer 126 in a manner of bonding, such that the bonding metal 42 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy) and are externally bonded. Is formed between the plate 138 and the semiconductor wafer 126-- ㉟144 package which package covering 451,342,594 'This encapsulation layer 144 of a polymer material based material, such as an epoxy resin. In addition, the wire bonding pad 136 is connected to another external circuit (not shown) via a wire bonding process, and the external circuit includes a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. one. The fourth aspect of the JL2 embodiment: The structure and manufacturing method of the fourth aspect are similar to those of the third aspect and the first aspect, and therefore the same components in the following embodiments and aspects Materials and processes are not repeated. Referring to Fig. 10a, the protective layer 34 and the pads 32 and pads 32 of the polymer layer 112 over the integrated circuit 100 are also formed. Referring to FIG. 10b and FIG. 2c, the polymer layer 112' is patterned by an exposure, development process, and etching process to form the polymer layer η to form a plurality of openings 112a, plural A polymer island 148 and a polymer bump 114, the opening 112a exposes the protective layer 34, the pad 32 and the pad 32, and the polymer bump 114 covers a portion of the pad 32, and is connected The area exposed by pad 32 is defined herein as a conductive region 154 having a width between 3 microns and 20 microns or between 2 microns and 15 microns. The polymer bump 114 shown in FIG. 1C is covered on one side of the pad 32 in this embodiment, so that the conductive region 154 is quadrangular or polygonal, etc., from the top view, and the The ratio of the area of the conductive region 154 to the surface area of the metal pad is between 〇1 to 〇9 or 〇〇5 to 〇5. 46 1342594 followed by heat hardening to harden the polymer block 148 and the polymer bump 114, the temperature of the hardening process is between 150 degrees (°c) and 300 degrees), and the polymer block 148 and the polymer The material of the bump 114 may be selected from the group consisting of polyimide (PI), benzocyclobutene (BCB), paryiene, and epoxy-based material. For example, epoxy resin or photoepoxy SU-8, an elastomer (elastomer) supplied by Sotec Microsystems, Renens, Switzerland, such as silicone. Where the polymer layer 112 is a photosensitive material, the polymer layer 112' can be patterned using only a lithography process (without an etching process) and the polymer block 148 has a thickness of between 5 microns and 50 microns. Referring to Fig. 10d, an adhesion/barrier layer 116 is formed in sequence and has a thickness of between 5 μm and 2 μm (preferably a thickness of 0. 1 micron to 0. A seed layer 118 between the 7 micrometers is on the conductive region 154, the pads 32', the polymer bumps 4, and the polymer blocks 148 on the entire integrated circuit. Referring to FIG. 10e, the photoresist layer 120 is formed on the seed layer 118 and the photoresist layer 120 is patterned by an exposure and development process to form a plurality of photoresist layer openings 120a in the photoresist. The seed layer 118 is disposed in the layer 120 and over the conductive region 154, the pad 32, the polymer bump 114 and the polymer block 148, and is doubled in the process of forming the photoresist layer opening 120a. Exposure or development of the steppers or scanners. Referring to FIG. 1A, a metal layer 122 is formed on the seed layer 118 in the opening 120a of the 47 1342594 by a key layer. The metal layer 122 covers at least the seed layer 118 above the two surfaces of the polymer bump 114. 122 is a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, ruthenium, iridium or nickel or a composite metal layer structure. The thickness of the metal layer 122 is between 1 micrometer and 20 micrometers, preferably. The thickness can be between 1.  5 micrometers to 丨 5 micrometers, and the combination of composite metal layer structures includes copper/nickel/gold, copper/gold, copper/recorded/copper, and copper/nickel/platinum combinations, etc., in this embodiment, the metal layer The 122 is a single layer' and the metal layer 122 is made of gold. The surface of the metal layer 122 on the polymer bump 114 defines a region as a bonding pad 24, which can be used to connect external circuits. The boundary circuit includes one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate, and a surface of the metal layer 122 on the polymer block 148 defines a region as a wire bonding pad 136. The pad 136 is connected to the external circuit via a wire bonding process. The polymer block 148 located under the wire bonding pad 136 can buffer the stress generated by the wire bonding during the wire bonding process, and has sufficient buffering effect on the thin substrate 10 . The active component of the substrate 10 and the component layer 12 of the integrated circuit 1 is prevented from being damaged during the wire bonding process. Further, the embodiment of the embodiment is different from the position of the bonding wire 136 and the interface 32'. Wire mat 136 can also be placed on the top of the pad 32, and will not be repeated here. Referring to Fig. 10g, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 116 which are not under the metal layer 122 are removed. Referring to the first Oh diagram, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips 126. 48 1342594 Referring to the S ηη diagram, the semiconductor wafer 126 is bonded to another external substrate 138 via FlipChip (FC) technology, wherein the bonding is performed in a manner that allows bonding on the external substrate 138. The metal layer 142 is bonded to the gold 122|synthesis or alloy (gold/gold bond or gold-tin alloy) on the joint #124, and is formed between the outer substrate 138 and the semiconductor wafer 126 - the package layer 144 is packaged The material of the encapsulation layer 144 is a polymer material, such as an epoxy resin. In addition, the wire bonding pad 136 is connected to another external circuit (not shown) via a wire bonding process, and the external circuit includes a printed circuit board metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. The structure of the cage 3 can be: the substrate 10, the element layer 12, the MOS transistor 14, the source 16, the drain 18, the gate 2, the thin circuit structure 22, the thin line in the structure of this embodiment The dielectric layer 26, the conductive plug 30, and the like are replaced by the integrated circuit 1A, and the structures and processes in the integrated circuit 100 have been fully described in the above embodiments, so that the structures in the integrated circuit 100 in the embodiment are And the process will not be repeated. Referring to Figure na, a polymer layer 112 is formed over the protective layer 34 and pads 32 of the integrated circuit 100. Referring to the lib diagram, the polymer layer 112 is patterned by exposure, development, and etching processes to form the polymer layer 112 into a plurality of polymer bumps (p〇iymer 49 1342594). 114 (only one is shown in the drawing), and the protective layer 34 and the pad 32 are exposed to the outside, followed by heat hardening to harden the polymer bump 114, and the temperature of the hardening process is 150 degrees ( Between C) and 300 degrees (between 〇, and the material of the polymer bump 114 may be selected from polyimide (PI), benzocyclobutene (BCB), polyparaphenylene (parylene), one of the epoxy-based materials such as epoxy resin or s〇tec from Renens, Switzerland.

Microsystems 所提供之 photoepoxy SU-8、彈性材料 (elastomer) ’例如石夕嗣（si 1 icone) β其中此聚合物層112 是為感光性材質時，可以僅利用微影製程（無須蝕刻製程） 來圖案化此聚合物層112,且此聚合物凸塊114厚度介於5 微米至50微米，聚合物凸塊ι14最大橫向尺寸介於1〇微 米至60微米，此聚合物凸塊114由俯視圖觀之係為圓形、 正方形、四邊开> 或多邊形等。另外聚合物凸塊114覆蓋住 接墊32 —部分之區域，而接墊32所暴露出之區域在此實 施例定義為導電區域154,此導電區域154的寛度係介於3 微米至20微米或2微米至15微米之間。 請參閱第11c圖所示，其中聚合物凸塊114在此實施 例中係將接塾32之至少二侧覆蓋，因此由俯視圖觀之，此 導電區域154係為®形、四邊形或多邊形等，而所暴出之 導電區域154面積與金屬接純面面積之比率係為〇】至 〇· 9或〇. 〇5至〇. 5之間。 請參閱第Ud圖所示’形成一黏著阻障層 UdheSi〇n/barrier layer)116在整個積體電路ι〇〇上的保護 50 1342594 層34、導電區域ι54及聚合物凸塊114上，黏著/阻障層 116包括鈦、鈦鎢合金、氮化鈦、鈕、氮化鈕鉻（Cr)或 鎳。另，黏著/阻障層116可以利用電鍍（e丨ectr〇pUting)、 無電電鑛（electro丨ess plating)、化學氣相沈積或物理氣相沉 積（例如濺鍍）的方式形成，其中又以物理氣相沉積為較佳 的形成方式，例如金屬濺鍍製程。另外此黏著阻障層116 的厚度係介於0.02微米至〇.8微米之間，並以介於〇 〇5微 米至0.2微米之間的厚度為較佳者。 請參閱第lie圖所示，接著形成厚度介於〇 〇〇5微米 至2微米之間（較佳厚度係介於〇丨微米至〇 7微米之間） 的一種子層（seed layer)118在黏著/阻障層116上，而形 成種子層118的方式比如是濺鍍、蒸鍍、物理氣相沉積、 電鍍或者是無電電鍍（electrolessplating)的方式。此種 子層118有利於後續金屬線路的設置，因此種子層118的 材質會隨後續金屬線路的材質而有所變化。例如，當種子 層118上電鍍形成銅材質之金屬層時，種子層118之材質 係以銅為佳；當種子層118上電鍍形成金材質之金屬層 時，種子層118之材質係以金為佳；當種子層118上電鍍 形成鈀材質之金屬層時，種子層118之材質係以鈀為佳； 當種子層118上電鍍形成鉑材質之金屬層時，種子層118 之材質係以鉑為佳；當種子層118上電鍍形成铑材質之金 屬層時，種子層118之材質係以铑為佳；當種子層118上 電鍍形成釕材質之金屬層時，種子層118之材質以釕為 佳；當種子層118上電鍍形成銖材質之金屬層時，種子層 51 1342594 118之材質係以銖為佳；當種子層118上電鍍形成鎳材質 之金屬層時’種子層118之材質係以鎳為佳。 請參閱第Ilf圖所示’形成一光阻層12〇在種子層118 上’並透過曝光（exposure)與顯影（development)製程圖案化 此光阻層120,以形成複數光阻層開口丨2〇3在光阻層12〇 内並暴露出位在接墊32及聚合物凸塊114上方的種子層 118上，而在形成光阻層開口 12〇3的過程中比如是以一户 (IX)之曝光機（steppers)或掃描機（scanners)進行曝光顯影。 其中此光阻層120有兩種型式，其係為：（1)濕膜光阻 (liquid photoresist)，其係利用單一或多重的旋轉塗佈方式 或者是印刷（printing)方式形成。此濕膜光阻的厚度係介於 3微米至60微米之間，而以介於5微米至40微米之間為 較佳者；以及（2)乾膜光阻（dry film Photoresist)，其係利用 貼合方式（laminating method)形成。此乾膜光阻的厚度係介 於30微米至300微米之間’而以介於50微米至150微米 之間為較佳者。另外’光阻可以是正型（positive-type)或負 型（negative-type)，而在獲得更好解析度上，則以正型厚光 阻（positive-type thick photoresist)為較佳者。利用一對準機 (aligner)或一倍（IX)步進曝光機曝光此光阻。此一倍（ιχ) 係指當光束從一光罩（通常係以石英或玻璃構成）投影至晶 圓上時，光罩上之圖形縮小在晶圓上的比例，且在光罩上 之圖案比例係與在晶圓上之圖案比例相同。對準機或一倍 步進曝光機所使用的光束波長係為436奈米（g-line)、397 奈米（h-line)、365 奈米（i-line)' g/h line(結合 g-line 與 h-line) 52 1342594 或 g/h/i line(結合 g-line、h-line 與 i-line)。使用光束波長 為g/h line或g/h/i line的一倍步進曝光機（或一倍對準機） 可在厚光阻或厚感光性聚合物（photosenstive polymer)的 曝光上’提供較大的光強度（丨ight intensity);此外，此圖 案化光阻層120之開口 120a之形狀也可包括線圈形狀、方 形、圓形、多邊形或不規則形狀。 請參閱第llg圖所示，以電鑛方式形成一金屬層122 在開口 120a内的種子層118上，其中電鍵形成之金屬層 122超過光阻層120之開口 12〇a，使部分金屬層122位在 光阻層120上’此金屬層122至少包覆聚合物凸塊114頂 面上方的種子層118’而此金屬層122比如是金、銅、銀、 纪、始、铑、釕、銶或鎳之單層金屬層結構或是複合式金 屬層結構，此金屬層122之厚度介於1微米至20微米，較 佳之厚度可介於1.5微米至15微米之間，而複合式金屬層 結構之組合包括銅/鎳/金、銅/金、銅/鎳/把及銅/鎳/始等 組合’在此實施例中此金屬層122係為單層，而金屬層ι22 之材質係為金。 請參閱第llh圖所示，利用一研磨製程將位於光阻層 12〇上之金屬層122移除，使金屬層122之表面平坦化， 此研磨製程包括機械研磨及化學機械研磨（CMp)其中之 一，進行平坦化製程後，位在聚合物凸塊114上之金屬層 122表面定義一區域為接合接墊124,此接合接墊124可用 於連接外界電路，此外界電路包括印刷電路板、金屬基板、 玻璃基板、軟性基板、陶瓷基板及矽基板其中之_。 53 1342594 請參閱第lli圖所示，去除圖案化光阻層12〇及去除 未在金屬層122下方的種子層118、黏著阻障層116〇 請參閱第11 j所示，將積體電路1〇〇進行切割步驟’ 產生複數半導體晶片（chiP)126,半導體晶片126上的接合 接墊124可經由貼帶自動接合（tape am〇mated bonded’TAB)、COG(chip on glass)、捲帶式晶粒接合（Tape Carrier Package，TCP)或 c〇F(chip 〇n fUm)的方式連接至 一外界電路128上，此外界電路128具有至少一接合金屬 層129，接合接墊124連接至接合金屬層129。 如第Ilk圖所示，本實施態樣以c〇G方式連接至外界 電路128’利用異方性導電膠13〇將半導體晶片126上的 接合接墊124接合至外界電路128之接合金屬層129上。 請參閱第111圖所示，本實施態樣若以c〇F方式連接 至外界電路128，則同樣利用異方性導電膠13〇將半導體 曰曰片126上的接合接墊124接合至外界電路128之接合金 屬層I29上’另一種C0F接合的方式，請參閱第llm圖 所示，此方式係利用熱壓合的方式將半導體晶片126上的 接合接墊124接合至含錫之外界電路128上，藉由熱壓合 使接合接墊124上的金與接合金屬層129上之錫層132產 生錫金合金層134而穩固接合，此種藉由熱壓合接合的方 式也了應用到貼帶自動接合（tape aut〇mated bonded,TAB) 及捲帶式晶粒接合（丁ape Carrier Package，TCp)上。 54 1342594 此第2態樣之結構及製作方法與第1態樣之結構及製 作方法相當類似，因此以下各實施例及態樣中的相同元件 之材質及製程就不加以重覆說明。 請參閱第12a圖所示，第2態樣與第1態樣差異點在 於第2態樣的積體電路1〇〇具有二個接塾32、32’，同樣 形成聚合物層112在整個積體電路1〇〇上的保護層34及接 墊 32、32,上。Photoepoxy SU-8, elastic material (elastomer) provided by Microsystems, for example, Si 1 icone β, in which the polymer layer 112 is made of a photosensitive material, it can be processed by only the lithography process (without etching process). The polymer layer 112 is patterned, and the polymer bump 114 has a thickness of 5 μm to 50 μm, and the polymer bump ι 14 has a maximum lateral dimension of 1 μm to 60 μm. The polymer bump 114 is viewed from a top view. The system is round, square, four sides open > or polygon. In addition, the polymer bumps 114 cover portions of the pads 32, and the regions exposed by the pads 32 are defined herein as conductive regions 154 having a twist of between 3 microns and 20 microns. Or between 2 microns and 15 microns. Referring to FIG. 11c, wherein the polymer bumps 114 cover at least two sides of the interface 32 in this embodiment, the conductive region 154 is a TM, a quadrangle or a polygon, etc., as viewed from a top view. The ratio of the area of the electrically conductive region 154 and the area of the metal to the pure surface is 〇·〇·9 or 〇. 〇5 to 〇. Referring to the UdheSi〇n/barrier layer formed on the Ud diagram, the protection of the entire integrated circuit 510 is performed on the layer 50, the layer 34, the conductive region ι54 and the polymer bump 114. The barrier layer 116 includes titanium, titanium tungsten alloy, titanium nitride, button, nitride button chromium (Cr) or nickel. In addition, the adhesion/barrier layer 116 may be formed by electroplating, electro-electroplating, chemical vapor deposition, or physical vapor deposition (eg, sputtering), wherein Physical vapor deposition is a preferred form of formation, such as a metal sputtering process. Further, the thickness of the adhesive barrier layer 116 is between 0.02 μm and 〇.8 μm, and preferably between 〇 5 μm and 0.2 μm. Referring to the lie diagram, a seed layer 118 having a thickness between 〇〇〇5 μm and 2 μm (preferably between 〇丨μm and 〇7 μm) is formed. The adhesion/barrier layer 116 is formed by a method such as sputtering, evaporation, physical vapor deposition, electroplating or electroless plating. Such a sub-layer 118 facilitates the placement of subsequent metal lines, so the material of the seed layer 118 will vary with the material of the subsequent metal lines. For example, when the seed layer 118 is plated to form a metal layer of copper, the material of the seed layer 118 is preferably copper; when the seed layer 118 is plated with a metal layer of gold, the material of the seed layer 118 is made of gold. Preferably, when the seed layer 118 is plated to form a metal layer of palladium, the seed layer 118 is preferably made of palladium; when the seed layer 118 is plated to form a metal layer of platinum, the seed layer 118 is made of platinum. Preferably, when the seed layer 118 is plated to form a metal layer of tantalum material, the material of the seed layer 118 is preferably 铑; when the seed layer 118 is plated with a metal layer of tantalum material, the material of the seed layer 118 is preferably 钌. When the seed layer 118 is plated to form a metal layer of tantalum material, the material of the seed layer 51 1342594 118 is preferably 铢; when the seed layer 118 is plated to form a metal layer of nickel material, the material of the seed layer 118 is made of nickel. It is better. Please refer to the 'Forming a photoresist layer 12 on the seed layer 118' as shown in the figure Ilf and patterning the photoresist layer 120 through an exposure and development process to form a plurality of photoresist layers opening 丨2 〇3 is in the photoresist layer 12〇 and exposes the seed layer 118 above the pad 32 and the polymer bump 114, and in the process of forming the photoresist layer opening 12〇3, for example, a household (IX) Exposure or development is performed by a stepper or a scanner. There are two types of the photoresist layer 120, which are: (1) a liquid photoresist which is formed by a single or multiple spin coating method or a printing method. The thickness of the wet film photoresist is between 3 microns and 60 microns, and preferably between 5 microns and 40 microns; and (2) dry film photoresist, It is formed by a laminating method. The thickness of the dry film photoresist is between 30 microns and 300 microns' and preferably between 50 microns and 150 microns. Further, the photoresist may be positive-type or negative-type, and in order to obtain better resolution, a positive-type thick photoresist is preferred. The photoresist is exposed using an aligner or a double (IX) stepper. This double (ιχ) refers to the ratio of the pattern on the reticle to the wafer when the light beam is projected onto the wafer from a reticle (usually composed of quartz or glass), and the pattern on the reticle The ratio is the same as the pattern on the wafer. The beam wavelength used by the aligner or double stepper is 436 g-line, 397 h-line, 365 i-line 'g/h line (combination G-line and h-line) 52 1342594 or g/h/i line (combined with g-line, h-line and i-line). Use a double stepper (or double aligner) with a beam wavelength of g/h line or g/h/i line to provide 'on exposure to thick photoresist or thick photosensitive polymer' (photosenstive polymer) Further, the shape of the opening 120a of the patterned photoresist layer 120 may also include a coil shape, a square shape, a circular shape, a polygonal shape, or an irregular shape. Referring to FIG. 11g, a metal layer 122 is formed by electroplating on the seed layer 118 in the opening 120a, wherein the metal layer 122 formed by the electric bond exceeds the opening 12〇a of the photoresist layer 120, so that the partial metal layer 122 Positioned on the photoresist layer 120, the metal layer 122 covers at least the seed layer 118' above the top surface of the polymer bump 114. The metal layer 122 is, for example, gold, copper, silver, ki, kiln, kiln, yttrium, yttrium. Or a single metal layer structure of nickel or a composite metal layer structure, the metal layer 122 having a thickness of 1 micrometer to 20 micrometers, preferably a thickness of between 1.5 micrometers and 15 micrometers, and a composite metal layer structure The combination includes copper/nickel/gold, copper/gold, copper/nickel/copper, and copper/nickel/start combination. In this embodiment, the metal layer 122 is a single layer, and the metal layer ι22 is made of gold. . Referring to FIG. 11h, the metal layer 122 on the photoresist layer 12 is removed by a polishing process to planarize the surface of the metal layer 122. The polishing process includes mechanical polishing and chemical mechanical polishing (CMp). For example, after the planarization process, the surface of the metal layer 122 on the polymer bump 114 defines a region as a bonding pad 124. The bonding pad 124 can be used to connect an external circuit, and the external circuit includes a printed circuit board. Among the metal substrate, the glass substrate, the flexible substrate, the ceramic substrate, and the germanium substrate. 53 1342594 Referring to FIG. 11Li, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 116 not under the metal layer 122 are removed. Referring to FIG. 11 j, the integrated circuit 1 is omitted. 〇〇 performing a dicing step to generate a plurality of semiconductor wafers (chiP) 126, and the bonding pads 124 on the semiconductor wafer 126 can be tape-bonded (TAB), COG (chip on glass), tape-and-reel The die carrier package (TCP) or c〇F (chip fn fUm) is connected to an external circuit 128 having at least one bonding metal layer 129, and the bonding pad 124 is connected to the bonding metal. Layer 129. As shown in FIG. 1k, the present embodiment is connected to the external circuit 128' in a c〇G manner to bond the bonding pads 124 on the semiconductor wafer 126 to the bonding metal layer 129 of the external circuit 128 by using the anisotropic conductive paste 13A. on. Referring to FIG. 111, if the embodiment is connected to the external circuit 128 in a c〇F manner, the bonding pads 124 on the semiconductor die 126 are also bonded to the external circuit by using the anisotropic conductive paste 13〇. Referring to FIG. 11m, the bonding pad 124 on the semiconductor wafer 126 is bonded to the tin-containing outer boundary circuit 128 by thermal compression bonding. The gold on the bonding pad 124 and the tin layer 132 on the bonding metal layer 129 are firmly bonded by the tin-bonding layer 134 on the bonding metal layer 129 by thermocompression bonding, and the bonding is also applied to the tape by thermocompression bonding. Tape aut〇mated bonded (TAB) and tape-type die bonding (TCp). 54 1342594 The structure and manufacturing method of the second aspect are quite similar to those of the first aspect, and therefore the materials and processes of the same components in the following embodiments and aspects are not repeated. Referring to Fig. 12a, the difference between the second aspect and the first aspect is that the integrated circuit 1 of the second aspect has two interfaces 32, 32', and the polymer layer 112 is formed in the same product. The protective layer 34 and the pads 32, 32 on the body circuit 1 are on top.

s青參閱第12b圖所示，並透過曝光（eXp〇sure)、顯影 (development)製程及蝕刻製程圖案化此聚合物層112，使 此聚合物層Π2形成複數聚合物凸塊（p〇lymer bump)114(圖示中僅顯示出1個），開口 U2a暴露出保護層 34及接墊32、32’，接著進行加熱硬化，使此聚合物凸塊 114硬化。其中此聚合物凸塊114是為感光性材質時可 以僅利用微影製程（無須蝕刻製程）來圖案化此聚合物凸塊 114，且此聚合物凸塊114厚度介於5微米至5〇微米聚Referring to FIG. 12b, the polymer layer 112 is patterned by exposure (eXp〇sure), development process, and etching process to form the polymer layer Π2 to form a plurality of polymer bumps (p〇lymer). The bumps 114 (only one is shown in the drawing), the opening U2a exposes the protective layer 34 and the pads 32, 32', and then heat hardens to harden the polymer bumps 114. Wherein the polymer bump 114 is a photosensitive material, the polymer bump 114 can be patterned by using only a lithography process (without an etching process), and the polymer bump 114 has a thickness of 5 micrometers to 5 micrometers. Gather

合物凸塊114最大橫向尺寸介於1()微米至⑽微米。另外 聚合物凸塊114覆蓋住接墊32 一部分之區域，而接墊32 所暴露出之區域在此實施例定義為導電區域154,此導電 區域15 4的寬度係介於3微米至2 0微米或2微米至i 5微 米之間。 12C圖所示，其中聚合物凸塊114在此實施 請參閱第 例中係將接塾32之至少m，因此由俯_“，此 導電區域154係為圓形、四邊形或多邊形等’而所暴出之 導電區域154面積與金屬接塾表面面積之比率係為（M至 55 1342594 0.9或0.05至〇·5之間。 請參閱第12d圖所示，形成黏著阻障層 (adhesion/barrier layer)116在整個積體電路1〇〇上的保護 層34、導電區域154、接墊32’及聚合物凸塊U4上，黏 著/阻障層116包括鈦、鈦鎢合金、氮化鈦、钽、氮化鈕、 絡（Cr)或鎳，此黏著阻障層ι16的厚度係介於〇 〇2微米至 0.8微米之間，並以介於〇.〇5微米至〇2微米之間的厚度 為較佳者。 請參閱第12e圖所示，接著形成厚度介於〇 〇〇5微米 至2微米之間（較佳厚度係介於〇·丨微米至〇. 7微米之間） 的種子層（seed layer)118在黏著/阻障層116上。 請參閱第12f圖所示，形成光阻層12〇在種子層】18 上，並透過曝光（exposure)與顯影（devel〇pment)製程圖案化 此光阻層120,以形成複數光阻層開口 12〇a、12〇b在光阻 層120内並分別暴露出位在接墊32'32，及聚合物凸塊 上方的種子層1】8。 請參閱第12g圖所示，以電鍍方式形成金屬層122在 開口伽、12()6内的種子層m上’其中電鑛形成之金屬 層122超過光阻層〖20之開口 12〇a，使部分金屬層122位 在光阻層m上，此金屬層122至少包覆聚合物凸塊114 頂面上方的種子層118，而金屬層122比如是金銅、銀、 鈀鉑錄、訂、銖或鎳之單層金屬層結構或是複合式金 屬層、《。構’此金屬層i22之厚度介於i微米至2G微米，較 佳之厚度可介於15微米至15微米之間而複合式金屬層 56 1342594 結構之組合包括銅/鎳/金、銅/金、銅/鎳/鈀及銅/鎳/鉑等 組合，在此實施例中此金屬層122係為單層，而金屬層122 之材質係為金。 請參閱第12h圖所示，利用一研磨製程將位於光阻層 12〇上之金屬層122移除，使金屬層丨22之表面平坦化， 此研磨製程包括機械研磨及化學機械研磨（CMp)其中之 一，進行平坦化製程後，位在金屬層122表面定義二區域 分別為接合接墊124及一打線接墊136,接合接墊124係 位在聚合物凸塊114上，而打線接墊136位在接墊32,上， 此接合接墊124及打線接墊136可用於連接外界電路，此 外界電路包括印刷電路板、金屬基板、玻璃基板、軟性基 板、陶瓷基板及矽基板其中之一。 凊參閱第12i圖所示’去除圖案化光阻層12〇及去除 未在金屬層122下方的種子層118、黏著阻障層丨16。 凊參閱第12 j圖及第12k圖所示，將積體電路1〇〇進 行切割步驟，產生複數半導體晶片（chip)i26,半導體晶片 126上的接合接墊124可經由覆晶（FlipChip, Fc)技術 接合至另一外界基板138上，此外界基板138比如是半導 體晶片，此外界基板138為半導體晶片時，此外界基板138 具有複數接合接墊140，在接合接墊14〇上具有一接合金 屬層142,此接合金屬層142之材質包括金、銅、銀、把、 鉑、铑、釕、銖、錫或鎳之單層金屬層結構或是複合式金 屬層結構，此接合金屬層142會隨著金屬層U2之材質而 有所改變，例如金屬層122之材質為金時，接合金屬層142 57 1342594 之材質係為金或含錫之金屬層，接著利用復晶(Fiipchip， FC)技術將外界基板138疊設在半導體晶片126上其中 接合的方式可採用熱壓合的方式，使接合金屬層142與金 屬層122產生融合或合金（金/金接合或金錫合金)接合並 且在外界基板138與半導體晶片126之間形成—封裝層 144將其包覆’此封裝& 144之材質係為聚合物材質比 如是環氧樹脂。另外打線接墊136則經由打線製程形成一 導線146連接至另一外界電路（圖中未示）上，此外界電路 包括印刷電路板、金屬基板、玻璃基板、軟性基板、陶竞 基板及石夕基板其中之一 β 凊參閱第121圖所示，此外打線接墊136除了可以利 用打線製程所形成之導線〗46連接至另一外界電路，也可 以連接至外界電路之錫球丨47上，此錫球147之厚度係介 於50微米至300微米之間，此連接方式可利用熱壓合的方 式接合。 J 3實施例之第3能祥: 此第3態樣之結構及製作方法與第3態樣及第2態樣 之結構及製作方法相當類似，因此以下各實施例及態樣中 的相同元件之材質及製程就不加以重覆說明。 請參閱第I3a圖及第13b圖所示，第3態樣與第2態 樣差異點僅在於打線接墊136的位置不同，第3態樣的打 線接墊136的位置從俯視透視圖（第13b圖）觀之，打線接 墊136位置係不同於接墊32,之位置，此打線接墊136可 58 1342594 提供一打線導線接合，經由此打線導線連接至外界電路 上’此外界電路包括印刷電路板、金屬基板、玻璃基板、 軟性基板、陶究基板及石夕基板其中之一，其中打線接塾136 下方的積體電路100内之基底1〇上可以設有至少一主動元 件’此主動元件包括二極體、電晶體等，主動元件己在上 述π件層12中己有詳盡介紹，在此就不加以重覆論述。 請參閱第13c圖所示，將積體電路100進行切割步驟， 產生複數半導體晶片（Chip)l26,半導體晶片126上的接合 接墊124可經由覆晶（flip chip, FC)技術接合至另一外 界基板138上，此外界基板138比如是半導體晶片，此外 界基板138為半導體晶片時，此外界基板138具有複數接 合接墊140,在接合接墊140上具有一接合金屬層142，此 接合金屬層142之材質包括金、銅、銀、鈀、鉑、铑、釕、 銖、錫或鎳之單層金屬層結構或是複合式金屬層結構此 接合金屬層142會隨著金屬層122之材質而有所改變，例 如金屬層122之材質為金時，接合金屬層142之材質係為 金或含錫之金屬層，接著利用覆晶（FUpChip，Fc)技術 將外界基板丨38疊設在半導體晶片126上，其中接合的方 式可採用熱壓合的方式，使接合金屬I 142與金屬層122 產生融合或合金（金/金接合或金_錫合金）接合，並且在外界 基板138與半導體晶片126之間形成一封裝们44將其包 覆，此封裝層144之材質係為聚合物材質比如是環氧樹 月曰。另外打線接& 136則經由打線製程形成一導線146連 接至另夕卜界電路（圖中未示）上，此外界電路包括印刷電 59 1342594 路板、金屬基板、玻璃基板、軟性基板、陶瓷基板及矽基 板其中之一。 以上所述係藉由實施例說明本發明之特點，其目的在 使熟習該技術者能暸解本發明之内容並據以實施，而非限 定本發明之專職圍，&，凡其他未脫離本發明所揭示之 精神所完成之等效修飾或修改，仍應包含在以下所述之申 請專利範圍中。The bumps 114 have a maximum lateral dimension of between 1 () microns and (10) microns. In addition, the polymer bumps 114 cover a portion of the pad 32, and the exposed regions of the pads 32 are defined herein as conductive regions 154 having a width between 3 microns and 20 microns. Or between 2 microns and 5 microns. As shown in Fig. 12C, wherein the polymer bumps 114 are implemented here, please refer to the example in which at least m of the interface 32 is used, so that the conductive region 154 is circular, quadrangular or polygonal, etc. The ratio of the area of the exposed conductive region 154 to the surface area of the metal interface is (M to 55 1342594 0.9 or 0.05 to 〇·5. See Figure 12d for the formation of an adhesion/barrier layer. 116] On the entire protective layer 34, the conductive region 154, the pad 32' and the polymer bump U4, the adhesion/barrier layer 116 comprises titanium, titanium tungsten alloy, titanium nitride, tantalum , nitride button, complex (Cr) or nickel, the thickness of the adhesive barrier layer ι16 is between 〇〇 2 μm and 0.8 μm, and is between 〇 5 〇 and 〇 2 μm. Preferably, see Figure 12e, followed by a seed layer having a thickness between 〇〇〇5 μm and 2 μm (preferably between 〇·丨 microns and 〇. 7 μm) (seed layer) 118 on the adhesion/barrier layer 116. Referring to Figure 12f, the photoresist layer 12 is formed on the seed layer. And patterning the photoresist layer 120 through an exposure and development process to form a plurality of photoresist layer openings 12〇a, 12〇b in the photoresist layer 120 and respectively exposing the contacts Pad 32'32, and seed layer 1] above the polymer bump. Referring to Figure 12g, the metal layer 122 is formed by electroplating on the seed layer m in the opening gamma, 12 () 6 The metal layer 122 formed by the mineral exceeds the opening 12〇a of the photoresist layer 20 such that a portion of the metal layer 122 is positioned on the photoresist layer m, and the metal layer 122 covers at least the seed layer 118 above the top surface of the polymer bump 114. The metal layer 122 is, for example, a single-layer metal layer structure of gold, copper, silver, palladium platinum, platinum, nickel, or nickel, or a composite metal layer. The thickness of the metal layer i22 is between i micrometers and 2 micrometers. Preferably, the thickness can be between 15 microns and 15 microns and the composite metal layer 56 1342594 combination of structures comprises copper/nickel/gold, copper/gold, copper/nickel/palladium, and copper/nickel/platinum combinations. In this embodiment, the metal layer 122 is a single layer, and the material of the metal layer 122 is gold. Please refer to the figure 12h, A polishing process removes the metal layer 122 on the photoresist layer 12 to planarize the surface of the metal layer 22, and the polishing process includes one of mechanical polishing and chemical mechanical polishing (CMp), after the planarization process The two regions defined on the surface of the metal layer 122 are respectively a bonding pad 124 and a bonding pad 136. The bonding pads 124 are fastened on the polymer bumps 114, and the bonding pads 136 are located on the pads 32. The bonding pad 124 and the bonding pad 136 can be used to connect an external circuit including one of a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a germanium substrate. Referring to Fig. 12i, the patterned photoresist layer 12 is removed and the seed layer 118 and the adhesion barrier layer 16 which are not under the metal layer 122 are removed. Referring to FIGS. 12j and 12k, the integrated circuit 1 is subjected to a dicing step to generate a plurality of semiconductor chips i26, and the bonding pads 124 on the semiconductor wafer 126 can be flipped (FlipChip, Fc). The technology is bonded to another external substrate 138, such as a semiconductor wafer. When the external substrate 138 is a semiconductor wafer, the external substrate 138 has a plurality of bonding pads 140, and has a bonding on the bonding pads 14A. The metal layer 142, the material of the bonding metal layer 142 comprises a single metal layer structure of gold, copper, silver, platinum, rhodium, ruthenium, iridium, tin or nickel or a composite metal layer structure. It will change with the material of the metal layer U2. For example, when the material of the metal layer 122 is gold, the material of the bonding metal layer 142 57 1342594 is a metal layer of gold or tin, and then the polycrystalline (Fiipchip, FC) is used. The technique stacks the external substrate 138 on the semiconductor wafer 126, wherein the bonding is performed by thermocompression bonding, and the bonding metal layer 142 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy). The outside is formed between the substrate 138 and the semiconductor wafer 126-- encapsulation layer 144 which covers' this wrapper & 144-based material is a polymer material than the case of the epoxy resin. In addition, the wire bonding pad 136 is connected to another external circuit (not shown) via a wire bonding process, and the external circuit includes a printed circuit board, a metal substrate, a glass substrate, a flexible substrate, a ceramic substrate, and a stone eve. One of the substrates β 凊 is shown in FIG. 121 , and the wire bonding pad 136 can be connected to the external ball circuit 47 by using the wire 46 formed by the wire bonding process, and can also be connected to the solder ball 47 of the external circuit. The thickness of the solder balls 147 is between 50 micrometers and 300 micrometers, and this connection can be joined by thermocompression bonding. The third embodiment of the J 3 embodiment: The structure and manufacturing method of the third aspect are quite similar to the structure and manufacturing method of the third aspect and the second aspect, so the same components in the following embodiments and aspects The materials and processes are not repeated. Referring to FIG. 3a and FIG. 13b, the difference between the third aspect and the second aspect is only that the position of the wire bonding pad 136 is different, and the position of the wire bonding pad 136 of the third aspect is from a top perspective view. 13b)), the position of the wire bonding pad 136 is different from the position of the pad 32. The wire bonding pad 136 can provide a wire bonding of the wire through the wire, and the wire is connected to the external circuit through the wire. One of the circuit board, the metal substrate, the glass substrate, the flexible substrate, the ceramic substrate, and the Shixi substrate, wherein at least one active component can be disposed on the substrate 1 in the integrated circuit 100 below the wire bonding 136 The components include diodes, transistors, etc. The active components have been described in detail in the above π-layer 12 and will not be repeated here. Referring to FIG. 13c, the integrated circuit 100 is subjected to a dicing step to generate a plurality of semiconductor chips (126). The bonding pads 124 on the semiconductor wafer 126 can be bonded to another via flip chip (FC) technology. On the external substrate 138, the external substrate 138 is a semiconductor wafer. When the external substrate 138 is a semiconductor wafer, the external substrate 138 has a plurality of bonding pads 140. The bonding pads 140 have a bonding metal layer 142. The material of the layer 142 includes a single metal layer structure of gold, copper, silver, palladium, platinum, rhodium, iridium, iridium, tin or nickel or a composite metal layer structure. The bonding metal layer 142 will follow the material of the metal layer 122. When the material of the metal layer 122 is gold, the material of the bonding metal layer 142 is a metal layer of gold or tin, and then the external substrate 丨 38 is stacked on the semiconductor by flip chip (FupChip, Fc) technology. On the wafer 126, the bonding is performed by thermocompression bonding, and the bonding metal I 142 and the metal layer 122 are fused or alloyed (gold/gold bonding or gold-tin alloy) bonding, and on the external substrate 138. 126 is formed between the semiconductor wafer 44 to have a package cladding material of the encapsulation layer 144. This system is a polymer material such as epoxy resin is said month. In addition, the wire bonding & 136 is connected to a circuit (not shown) via a wire bonding process, and the external circuit includes a printed circuit 59 1342594, a metal substrate, a glass substrate, a flexible substrate, and a ceramic. One of the substrate and the substrate. The above description of the features of the present invention is intended to be understood by those skilled in the art, and is intended to be Equivalent modifications or modifications made by the spirit of the invention should still be included in the scope of the claims described below.

【圖式簡單說明] 圖式說明：[Simple description of the schema] Schematic description:

第la圖至第Id圖為本發明形成細連線結構及保護層 意圖。 第2a圖至第2k圖為本發明第一實施例之第1 圖。 第h圖至第3j圖為本發明第一 圖。 』^弟2態樣之示意 第4a圖至第4c圖為太森ΒηΛ* 圓為本發明第一實施例 圖。 〈第3態樣之示意 第5a圖至第圖兔太政ηη κ圖為本發明第一實施例 圖。 j之第4態樣之示意 第6a圖至第圖氣士找 g圖為本發明第一實施例 之示 態樣之示意 圖 第7a圖至第71 圖。 之第5態樣之示 圖 為本發明第二實施例之第1 態樣之示意 60 1342594 2態樣之示意 第8a圖至第8k圖為本發明第二實施例之第 圖。 3態樣之不意 第9a圖至第9c圖為本發明第二實施例之第 圖。 4態樣之示 第10a圖至第10i圓為本發明第二實施例之 意圖。 第 第Ua圖至第llm圖為本發明第三實施 意圖。 $ 1態樣之示 第12a圖至第121圖為本發明第三實 意圖。 &lt;第2態樣之示 第13a圖至第13C圖為本發明 意圖。 實施例之第3態樣之示 圖號說明： 10 基底 14 金氧半電晶體 18 汲極 22 細線路結構 26 細線路介電層 30 導電栓塞 34 保護層 100 積體電路 114 聚合物凸塊 12 元件層 16 源極 20 開極 24 細線路層 28 開口 32 接墊 36 開口 112 聚合物層 116 黏著/阻障層 1342594 118 種子層 120 光阻層 120a 光阻層開口 122 金屬層 124 接合接墊 126 半導體晶片 128 外界電路 129 接合金屬層 130 異方性導電膠 132 錫層 134 錫金合金層 325 接墊 120b 光阻層開口 136 打線接墊 138 外界基板 140 接合接墊 142 接合金屬層 144 封裝層 146 導線 147 錫球 148 聚合物塊 150 聚合物層 152 聚合物凸塊 154 導電區域 62The first to fourth figures are intended to form a thin wiring structure and a protective layer of the present invention. 2a to 2k are first views of the first embodiment of the present invention. Figures h through 3j are first views of the present invention. The schematic diagram of the second aspect of the present invention is shown in Fig. 4a to Fig. 4c as a first embodiment of the present invention. <Illustration of the third aspect Fig. 5a to Fig. 3 is a diagram showing the first embodiment of the present invention. Explanation of the fourth aspect of j. Fig. 6a to Fig. Fig. 3 shows a schematic view of the first embodiment of the present invention. Figs. 7a to 71. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic view showing a first aspect of a second embodiment of the present invention. 60 1342594. FIG. 8A to FIG. 8k are diagrams showing a second embodiment of the present invention. 3 is not intended. Figs. 9a to 9c are diagrams showing a second embodiment of the present invention. 4 Aspects The 10a to 10ith circles are the intention of the second embodiment of the present invention. The first Ua to the llm are the third embodiment of the present invention. Description of the $1 aspect The 12th to the 121th drawings are the third embodiment of the present invention. &lt;The second aspect is shown in Figs. 13a to 13C. DESCRIPTION OF THE EMBODIMENT OF THE THIRD EMBODIMENT OF THE EMBODIMENT: 10 Substrate 14 Gold Oxide Transistor 18 Deuterium 22 Fine Line Structure 26 Thin Line Dielectric Layer 30 Conductive Plug 34 Protective Layer 100 Integrated Circuit 114 Polymer Bump 12 Component layer 16 source 20 open electrode 24 thin circuit layer 28 opening 32 pad 36 opening 112 polymer layer 116 adhesion/barrier layer 1342594 118 seed layer 120 photoresist layer 120a photoresist layer opening 122 metal layer 124 bonding pad 126 Semiconductor wafer 128 external circuit 129 bonding metal layer 130 anisotropic conductive adhesive 132 tin layer 134 tin gold alloy layer 325 pad 120b photoresist layer opening 136 wire bonding pad 138 external substrate 140 bonding pad 142 bonding metal layer 144 encapsulation layer 146 wire 147 Tin Ball 148 Polymer Block 150 Polymer Layer 152 Polymer Bump 154 Conductive Area 62

Claims (1)

1342594 十、申請專利範圍 1. 一種半導體晶片結構，包括： 一半導體基底’該半導體基底上包括至少一主動元件; 一細連線結構’位在該半導體基底及該主動元件上， 該細連線結構包括複數個介電層及複數個細線路層位於該 半導链基底上’且該些介電層具有多數個通道孔，該些細 線路層係位於該些介電層其中之一上，其中該些細線路層 • 藉由該些通道孔彼此電性連接，該些細線路層包括至少一 金屬接墊； 一保護層，位在該半導體基底上’該保護層具有至少 一開口曝露出該金屬接墊； 一聚合物凸塊’位在該保護層上及該主動元件上方； ' 一黏著阻障層，位在該保護層、該聚合物凸塊及該金 屬接墊上，該黏著阻障層包覆該聚合物凸塊之至少二表面； 一種子層’位在該黏著阻障層上；以及 _ 一金屬層’位在該種子層上’該金屬層與該種子層相 同材質，且經由位在該聚合物凸塊頂面上之該金屬層可連 接至一外界電路。 2·如申請專利範圍第1項所述之半導體晶片結構，其中， 該半導體基底包括破。 3.如申請專利範圍第1項所述之半導體晶片結構，其中， 該細線路層包括厚度係介於〇 〇5微米至2微米之間的 一銘層。 63 •如申請專利範圍第1項所述之半導體晶片結構，其中， 該細線路層包括厚度齡於〇. 05微米至2微米之間的 一鋼層。 5·如申請專利範圍第i項所述之半導體晶片結構，其中， 該保護層之材質包括一氮矽化合物。 、 6.如申請專利範圍第i項所述之半導體晶片結構，其中， 該保護層之材質包括一磷矽玻璃（psG)。 φ 7.如申請專利範圍第1項所述之半導體晶片結構，其中， 該保護層之材質包括一氧矽化合物。 8.如申請專職㈣丨項所述之半導H结構，其中， 該保護層之材質包括一氮氧矽化合物。 • 9.如巾請專㈣㈣1項所述之半導m结構，其中， • 該保護層之材質包括一硼磷矽玻璃（BPSG)。 10·如申請專利範圍第i項所述之半導體晶片結構其 中’該金屬層之材質包括金。 • U.如申請專利範圍第1項所述之半導體晶片結構，其 中’該金屬層之材質包括銅。 12·如申請專利範圍第i項所述之半導體晶片結構其 中’該金屬層之材質包括銀。 ' 13.如申請專利範圍第1項所述之半導體晶片結構，其 中該金屬層之材質包括翻。 14·如申請專利範圍第i項所述之半導體晶片結構其 中’該金屬層之材質包括把。 15.如申請專利範圍第i項所述之半導體晶片結構，其 64 中’該金屬層之材質包括鎳。 16· 如申請專利範圍第1項所述之半導體晶片結構，其 中’該金屬層之厚度介於1微米至20微米。 17. 如申請專利範圍第1項所述之半導體晶片結構，其 中’該金屬層之厚度介於1.5微米至15微米。 1 〇 • 如申請專利範圍第1項所述之半導體晶片結構，其1342594 X. Patent Application Area 1. A semiconductor wafer structure comprising: a semiconductor substrate comprising at least one active component on the semiconductor substrate; a thin wiring structure disposed on the semiconductor substrate and the active component, the thin wiring The structure includes a plurality of dielectric layers and a plurality of thin circuit layers on the semi-conductive chain substrate' and the dielectric layers have a plurality of via holes, wherein the thin circuit layers are located on one of the dielectric layers, wherein The thin circuit layers are electrically connected to each other by the via holes, the fine circuit layers including at least one metal pad; a protective layer on the semiconductor substrate, the protective layer having at least one opening exposing the metal connection a pad; a polymer bump 'located on the protective layer and above the active component; 'an adhesive barrier layer on the protective layer, the polymer bump and the metal pad, the adhesive barrier layer package Covering at least two surfaces of the polymer bump; a sublayer 'position on the adhesive barrier layer; and a metal layer 'on the seed layer' the metal layer and the seed layer The same material, and the metal layer via a bit in a top surface of the polymer bumps can be connected to an external circuit. 2. The semiconductor wafer structure of claim 1, wherein the semiconductor substrate comprises a broken. 3. The semiconductor wafer structure of claim 1, wherein the thin circuit layer comprises a layer of a layer having a thickness between 5 microns and 2 microns. The semiconductor wafer structure of claim 1, wherein the fine circuit layer comprises a steel layer having a thickness of between 0.25 mm and 2 μm. 5. The semiconductor wafer structure of claim i, wherein the material of the protective layer comprises a nitrogen arsenide compound. 6. The semiconductor wafer structure of claim i, wherein the material of the protective layer comprises a phosphorous bismuth glass (psG). The semiconductor wafer structure of claim 1, wherein the material of the protective layer comprises an oxonium compound. 8. The semi-conductive H structure as claimed in the full-time (4) item, wherein the material of the protective layer comprises a oxynitride compound. • 9. For the towel, please use the semi-conductive m structure described in (4) (4), where the material of the protective layer includes borophosphorus bismuth glass (BPSG). 10. The semiconductor wafer structure of claim i, wherein the material of the metal layer comprises gold. U. The semiconductor wafer structure of claim 1, wherein the material of the metal layer comprises copper. 12. The semiconductor wafer structure of claim i, wherein the material of the metal layer comprises silver. 13. The semiconductor wafer structure of claim 1, wherein the material of the metal layer comprises a turn. 14. The semiconductor wafer structure of claim i, wherein the material of the metal layer comprises a handle. 15. The semiconductor wafer structure of claim i, wherein the material of the metal layer comprises nickel. The semiconductor wafer structure of claim 1, wherein the metal layer has a thickness of from 1 micrometer to 20 micrometers. 17. The semiconductor wafer structure of claim 1, wherein the metal layer has a thickness of between 1.5 microns and 15 microns. 1 〇 • The semiconductor wafer structure as described in claim 1 of the patent application, 中，由俯視透視圖觀之該聚合物凸塊與該金屬接墊不同 位置。 19.如申請專利範圍第1項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於002微米至08微米 之一鈦鎢合金層。 20 .如申請專利範圍第1項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於0 02微米至0.8微米 之—鈦金屬層。The polymer bump is viewed from a top view in a different position from the metal pad. 19. The semiconductor wafer structure of claim 1, wherein the adhesion/barrier layer comprises a titanium tungsten alloy layer having a thickness between 002 microns and 08 microns. 20. The semiconductor wafer structure of claim 1, wherein the adhesion/barrier layer comprises a titanium metal layer having a thickness between 0 02 microns and 0.8 microns. 21.如申請專利範圍第1項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇 〇2微米至〇 8微米 之一氮化鈦層0 、 22 .如申請專利範圍第1項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇 〇2微米至〇8伞 之—钽金屬層。 八 23 .如申請專利範圍第1項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇. 02微米至〇· 8微米 之—氡化钽層。 、 .如申請專利範圍第1項所述之半導體晶片結構，其 65 中’該黏著/阻障層包括厚度介於Ο 02微米至Ο 8微米 之—鉻金屬層。 25. 如申請專利範圍第1項所述之半導體晶片結構，其 中’該黏著/阻障層包括厚度介於0.02微米至〇.8微米 之—鉻銅合金層。 26. 如申請專利範圍第1項所述之半導體晶片結構，更 包括一種子層位在該黏著/阻障層與該金屬層之間。21. The semiconductor wafer structure of claim 1, wherein the adhesion/barrier layer comprises a titanium nitride layer 0, 22 having a thickness between 〇〇2 μm and 〇8 μm. The semiconductor wafer structure of item 1, wherein the adhesion/barrier layer comprises a ruthenium metal layer having a thickness of between 〇〇2 μm and 〇8. The semiconductor wafer structure of claim 1, wherein the adhesion/barrier layer comprises a germanium telluride layer having a thickness of between 2.0 and 10 μm. The semiconductor wafer structure of claim 1, wherein the adhesive/barrier layer comprises a chromium metal layer having a thickness of from Ο02 μm to Ο8 μm. 25. The semiconductor wafer structure of claim 1, wherein the adhesion/barrier layer comprises a chromium-copper alloy layer having a thickness of between 0.02 micrometers and 0.8 micrometers. 26. The semiconductor wafer structure of claim 1, further comprising a sub-layer between the adhesion/barrier layer and the metal layer. 27·如申請專利範圍第1項所述之半導體晶片結構，其 中’該主動元件包括二極體。 28.如申請專利範圍第1項所述之半導體晶片結構，其 中’該主動元件包括電晶體。 29·如申請專利範圍第1項所述之半導體晶片結構，其 中’該外界電路包括印刷電路板。 30 •如申請專利範圍第1項所述之半導體晶片結構，其 中’該外界電路包括金屬基板。27. The semiconductor wafer structure of claim 1, wherein the active component comprises a diode. 28. The semiconductor wafer structure of claim 1, wherein the active component comprises a transistor. The semiconductor wafer structure of claim 1, wherein the external circuit comprises a printed circuit board. 30. The semiconductor wafer structure of claim 1, wherein the external circuit comprises a metal substrate. 31.如申請專利範圍第1項所述之半導體晶片結構，其 中’該外界電路包括玻璃基板。 32 .如申請專利範圍第1項所述之半導體晶片結構，其 中’該外界電路包括軟性基板。 go 如申請專利範圍第1項所述之半導體晶片結構，其 中’該外界電路包括陶究基板。 34.如申請專利範圍第1項所述之半導體晶片結構，其 中’該聚合物凸塊包括聚醯亞胺化合物。 .如申請專利範圍第1項所述之半導體晶片結構，其 66 35 1342594 中’該聚合物凸塊包括苯基環丁烯化合物。 36· 如申請專利範圍第1項所述之半導體晶片結構，其 中’該聚合物凸塊包括聚對二甲苯類高分子化合物。 37* 如申請專利範圍第1項所述之半導體晶片結構，其 中’該聚合物凸塊包括環氧樹脂。 38· 如申請專利範圍第1項所述之半導體晶片結構，其 中’該聚合物凸塊厚度介於5微米至50微米之間。 39. 如申請專利範圍第1項所述之半導體晶片結構，其 中’該聚合物凸塊之一宽度介於5微米至60微米之間。 40. 如申請專利範圍第1項所述之半導體晶片結構，其 中’該些介電層之介電常數值介於1至3之間。 41 · 一種半導體晶片結構，包括： 一半導體基底’該半導體基底上包括至少一主動元件； 一細連線結構，位在該半導體基底及該主動元件上， 該細連線結構包括複數個介電層及複數個細線路層位於該 半導體基底上，且該些介電層具有多數個通道孔，該些細 線路層係位於該些介電層其中之一上，其中該些細線路層 藉由該些通道孔彼此電性連接，該些細線路層包括至少一 金屬接墊； 一保護層，位在該半導體基底上，該保護層具有至少 一開口曝露出該金屬接墊； 一聚合物凸塊，位在該保護層及該金屬接墊上，並暴 露出該金屬接整表面之一導電區域； 一黏著阻障層，位在該保護層、該聚合物凸塊及該導 67 1342594 電區域上，該黏著阻障層包覆該聚合物凸塊之至少二表面; 一種子層，位在該黏著阻障層上；以及 _ 金屬層，位在該種子層上，該金屬層與該種子層相 同材質，且經由位在該聚合物凸塊頂面上之該金屬層可連 接至一外界電路。 42_如申請專利範圍第41項所述之半導體晶片結構，其 中’該半導體基底包括矽。 43.如申凊專利範圍第41項所述之半導體晶片結構，其 中，該細線路層包括厚度係介於〇 〇5微米至2微米之 間的一鋁層。 44·如申請專利範圍第41項所述之半導體晶片結構，其 中，該細線路層包括厚度係介於〇 〇5微米至2微米之 間的一鋼層。 45. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該保護層之材質包括一氮矽化合物。 46. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該保護層之材質包括一鱗石夕玻璃（PSG)。 47. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該保護層之材質包括一氧矽化合物。 48. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該保護層之材質包括一氮氧矽化合物。 49_如申請專利範圍第41項所述之半導體晶片結構，其 中，該保護層之材質包括一爛填石夕玻璃（BPSG)。 50.如申請專利範圍第41項所述之半導體晶片結構，其 68 51. 中 中 52, 中 53. 中 54. 中 55. 中 56. 中 57. 中 58. 中 位置 該金屬層之材質包括金。 如申請專利範圍第41項所述之半導體晶片結構，其 該金屬層之材質包括銅。 如申請專利範圍第41項所述之半導體晶片結構其 該金屬層之材質包括銀。 如申請專利範圍第41項所述之半導體晶片結構，其 該金屬層之材質包括鉑。 如申請專利範圍第41項所述之半導體晶片結構其 該金屬層之材質包括鈀。 如申請專利範圍第41項所述之半導體晶片結構，其 該金屬層之材質包括鎳。 如申請專利範圍第41項所述之半導體晶片結構，其 該金屬層之厚度介於1微米至2〇微米。 如申請專利範圍第41項所述之半導體晶片結構，其 該金屬層之厚度介於1.5微米至15微米。 如申請專利範圍第41項所述之半導體晶片結構，其 由俯視透視圖觀之該聚合物凸塊與該金屬接墊不同 59.如申請專利範圍第41項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇 〇2微米至〇 8微米 之一鈦鎢合金層。 60·如申請專利範圍第41項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇〇2微米至〇8微米 之—鈦金屬層。 69 61中如申請專利範圍第41項所述之半導體晶片結構，其 該黏著/阻障層包括厚度介於0 02微米至〇 8微米 之一氮化鈦層。 如申請專利範圍第41項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於0 02微米至〇 8微米 之—钽金屬層。 63. *申請專利範圍第41項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇 〇2微米至〇 8微米 之一氮化鈕層。 64·如申請專利範圍第41項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於0 02微米至〇 8微米 之—鉻金屬層。 、 0C •如申請專利範圍第41項所述之半導體晶片結構，其 中，該黏著/阻障層包括厚度介於〇〇2微米至〇8微米 之—路銅合金層。 66&gt;如申請專利範圍第41項所述之半導體晶片結構，更 包括一種子層位在該黏著/阻障層與該金屬層之間。 67. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該主動元件包括二極體。 、 68. 如申請專利範圍第41項所述之半導體晶片結構其 令’該主動元件包括電晶體。 、 69. 如申請專利範圍第41項所述之半導體晶片結構其 中’該外界電路包括印刷電路板。 ' 70. 如申請專利範圍第41項所述之半導體晶片結構，其 中’該外界電路包括金屬基板。 71'如申請專利範圍第41項所述之半導體晶片結構，其 中’該外界電路包括玻璃基板。 72. 如申請專利範圍第41項所述之半導體晶片結構，其 中’該外界電路包括軟性基板。 73. 如申請專利範圍第41項所述之半導體晶片結構，其 中’該外界電路包括陶莞基板。 74. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該聚合物凸塊包括聚醯亞胺化合物。 75. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該聚合物凸塊包括笨基環丁烯化合物。 6.如申凊專利範圍第41項所述之半導體晶片結構其 中’該聚合物凸塊包括聚對二甲苯類高分子化合物。 77，如申請專利範圍第項所述之半導體晶片結構，其 中’該聚合物凸塊包括環氧樹脂。 78·如申請專利範圍第4i項所述之半導體晶片結構，其 中，該聚合物凸塊厚度介於5微米i5〇微米之間。、 79·如申請專利範圍第4i項所述之半導體晶片結構，其 中，該聚合物凸塊之一寛度介於5微米至6〇微米之間 80. 如申請專利範圍第41項所述之半導體晶片結構，其 中，該些介電層之介電常數值介於丨至3之間。 81. 如申請專利範圍第41項所述之半導體晶片結構，其 中’該導電區域面積與該金屬接塾表面面積之比率係為 0. 1至0. 9之間。 82. 如_請專利範®第4〗項所述之半導體^結構，其 該，電區域面積與該金屬接爸表面面積之比率係為 至0. 5之間。 ^如申料懸㈣41項料之半導體晶片結構其 令’該聚合物凸塊圍繞該導電區域。 84. 如申請專利範園第41項所述之半導體晶片結構其 中，該聚合物凸塊位在該導電區域之至少二侧。31. The semiconductor wafer structure of claim 1, wherein the external circuit comprises a glass substrate. 32. The semiconductor wafer structure of claim 1, wherein the external circuit comprises a flexible substrate. The semiconductor wafer structure of claim 1, wherein the external circuit comprises a ceramic substrate. 34. The semiconductor wafer structure of claim 1, wherein the polymer bump comprises a polyimine compound. The semiconductor wafer structure of claim 1, wherein the polymer bump comprises a phenylcyclobutene compound. 36. The semiconductor wafer structure of claim 1, wherein the polymer bump comprises a parylene polymer compound. 37* The semiconductor wafer structure of claim 1, wherein the polymer bump comprises an epoxy resin. 38. The semiconductor wafer structure of claim 1, wherein the polymer bump has a thickness between 5 microns and 50 microns. 39. The semiconductor wafer structure of claim 1, wherein one of the polymer bumps has a width between 5 microns and 60 microns. 40. The semiconductor wafer structure of claim 1, wherein the dielectric layers have a dielectric constant value between 1 and 3. 41. A semiconductor wafer structure comprising: a semiconductor substrate comprising: at least one active component; a thin wiring structure on the semiconductor substrate and the active component, the thin wiring structure comprising a plurality of dielectrics a layer and a plurality of thin circuit layers are disposed on the semiconductor substrate, and the dielectric layers have a plurality of via holes, wherein the thin circuit layers are located on one of the dielectric layers, wherein the thin circuit layers are The channel holes are electrically connected to each other, the fine circuit layers comprise at least one metal pad; a protective layer is disposed on the semiconductor substrate, the protective layer has at least one opening exposing the metal pad; a polymer bump, a bit On the protective layer and the metal pad, and exposing a conductive region of the metal bonding surface; an adhesive barrier layer is disposed on the protective layer, the polymer bump and the conductive region of the conductor 67 1342594, An adhesive barrier layer coating at least two surfaces of the polymer bump; a sub-layer on the adhesive barrier layer; and a _ metal layer on the seed layer, the gold The seed layer and the same material layer and the metal layer via a bit in a top surface of the polymer bumps can be connected to an external circuit. 42. The semiconductor wafer structure of claim 41, wherein the semiconductor substrate comprises germanium. 43. The semiconductor wafer structure of claim 41, wherein the thin circuit layer comprises an aluminum layer having a thickness between 5 microns and 2 microns. 44. The semiconductor wafer structure of claim 41, wherein the thin circuit layer comprises a steel layer having a thickness between 5 microns and 2 microns. 45. The semiconductor wafer structure of claim 41, wherein the material of the protective layer comprises a nitrogen arsenide compound. 46. The semiconductor wafer structure of claim 41, wherein the material of the protective layer comprises a scale glass (PSG). 47. The semiconductor wafer structure of claim 41, wherein the material of the protective layer comprises an oxonium compound. 48. The semiconductor wafer structure of claim 41, wherein the material of the protective layer comprises a oxynitride compound. 49. The semiconductor wafer structure of claim 41, wherein the material of the protective layer comprises a ruined stone glass (BPSG). 50. The semiconductor wafer structure as described in claim 41, wherein the material of the metal layer is included in the middle portion 52, the middle portion 54, the middle portion 54, the middle portion 55, the middle portion 56, the middle portion 57. gold. The semiconductor wafer structure of claim 41, wherein the material of the metal layer comprises copper. The semiconductor wafer structure of claim 41, wherein the material of the metal layer comprises silver. The semiconductor wafer structure of claim 41, wherein the material of the metal layer comprises platinum. The semiconductor wafer structure of claim 41, wherein the material of the metal layer comprises palladium. The semiconductor wafer structure of claim 41, wherein the material of the metal layer comprises nickel. The semiconductor wafer structure of claim 41, wherein the metal layer has a thickness of from 1 micrometer to 2 micrometers. The semiconductor wafer structure of claim 41, wherein the metal layer has a thickness of from 1.5 micrometers to 15 micrometers. The semiconductor wafer structure of claim 41, wherein the polymer bump is different from the metal pad in a top perspective view. The semiconductor wafer structure of claim 41, wherein The adhesion/barrier layer comprises a titanium-tungsten alloy layer having a thickness ranging from 〇〇2 μm to 〇8 μm. 60. The semiconductor wafer structure of claim 41, wherein the adhesion/barrier layer comprises a titanium metal layer having a thickness between 〇〇2 microns and 〇8 microns. The semiconductor wafer structure of claim 41, wherein the adhesion/barrier layer comprises a titanium nitride layer having a thickness between 0 02 μm and 〇 8 μm. The semiconductor wafer structure of claim 41, wherein the adhesion/barrier layer comprises a ruthenium metal layer having a thickness of from 0 02 μm to 〇 8 μm. 63. The semiconductor wafer structure of claim 41, wherein the adhesion/barrier layer comprises a nitride button layer having a thickness between 2 μm and 〇 8 μm. 64. The semiconductor wafer structure of claim 41, wherein the adhesion/barrier layer comprises a chromium metal layer having a thickness between 0 02 microns and 〇 8 microns. The semiconductor wafer structure of claim 41, wherein the adhesion/barrier layer comprises a copper alloy layer having a thickness of between 〇〇2 μm and 〇8 μm. 66. The semiconductor wafer structure of claim 41, further comprising a sub-layer between the adhesion/barrier layer and the metal layer. 67. The semiconductor wafer structure of claim 41, wherein the active device comprises a diode. 68. The semiconductor wafer structure of claim 41, wherein the active device comprises a transistor. 69. The semiconductor wafer structure of claim 41, wherein the external circuit comprises a printed circuit board. 70. The semiconductor wafer structure of claim 41, wherein the external circuit comprises a metal substrate. 71. The semiconductor wafer structure of claim 41, wherein the external circuit comprises a glass substrate. The semiconductor wafer structure of claim 41, wherein the external circuit comprises a flexible substrate. 73. The semiconductor wafer structure of claim 41, wherein the external circuit comprises a ceramic substrate. 74. The semiconductor wafer structure of claim 41, wherein the polymer bump comprises a polyamidene compound. 75. The semiconductor wafer structure of claim 41, wherein the polymer bump comprises a stupid cyclobutene compound. 6. The semiconductor wafer structure of claim 41, wherein the polymer bump comprises a parylene polymer compound. 77. The semiconductor wafer structure of claim 2, wherein the polymer bump comprises an epoxy resin. 78. The semiconductor wafer structure of claim 4, wherein the polymer bump has a thickness between 5 microns and 5 microns. The semiconductor wafer structure of claim 4, wherein one of the polymer bumps has a twist between 5 micrometers and 6 micrometers. 80. As described in claim 41. A semiconductor wafer structure in which the dielectric layers have a dielectric constant value between 丨 and 3. The ratio of the ratio of the area of the surface area of the surface of the metal to the surface area of the metal layer is between 0.1 and 0.9. The ratio of the area of the area of the metal to the surface area of the metal is between 0.5 and 0.5. ^ The semiconductor wafer structure of the 41 item of the material (4) is ordered to surround the conductive region. 84. The semiconductor wafer structure of claim 41, wherein the polymer bump is located on at least two sides of the conductive region. 85. 如申請專利範圍第41項所述之半導體晶片結構，其 申’該導電區域之形狀包括四邊形。 ' 86·如申請專利範圍第41項所述之半導體晶片結構其 令’該導電區域之形狀包括圓形。 87. 如申請專利範圍第41項所述之半導體晶片結構，其 中’該導電區域之形狀包括多邊形。 、 88. 一種半導體晶片結構之製作方法，包括： 提供一半導體基底，該半導體基底包括至少一金屬接85. The semiconductor wafer structure of claim 41, wherein the shape of the conductive region comprises a quadrilateral. The semiconductor wafer structure of claim 41, wherein the shape of the conductive region comprises a circular shape. 87. The semiconductor wafer structure of claim 41, wherein the shape of the conductive region comprises a polygon. 88. A method of fabricating a semiconductor wafer structure, comprising: providing a semiconductor substrate, the semiconductor substrate comprising at least one metal connection 中， 0. 05 墊、一細連線結構及一保護層，該保護層位在該半導體基 底上’該保護層具有至少一開口曝露出該細連線結構之一 金屬接墊； 形成圖案化之一聚合物凸塊在該保護層及該金屬接墊 上’暴露出該金屬接塾表面之一導電區域； 形成一黏著阻障層在該導電區域、該聚合物凸塊及該 保護層上； 形成一種子層在該黏著阻障層上； 形成圖案化光阻層在該種子層上，該圖案化光阻層 72 1342594 之—開口暴露出部分該聚合物凸塊及該導電區域上之該種 子層； 形成一金屬層在該開口内之該種子層及該圖案化光阻 層上； 以研磨方式移除位在該圖案化光阻層上之該金屬層； 移除該圖案化光阻層；以及 移除未在該金屬層下方之該種子層及該黏著阻障層。 89· 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該提供該半導體基底之步驟包括提供一 矽晶圓。 90· 如申請專利範圍第88項所述之半導體晶片結構之製 作方法’其中，該提供該半導體基底之步驟包括提供一 碎晶片。 91· 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該細連線結構包括： 複數個介電層，位於該半導體基底上，且該些介電層 具有多數個通道孔；以及 複數個細線路層，而該些細線路層係位於該些介電層 其中之一上，其中該些細線路層藉由該些通道孔彼此電性 連接。 92， 如申請專利範圍第91項所述之半導體晶片結構之製 作方法’其中，該細線路層包括厚度係介於〇 〇5微米 至2微米之間的一鋁層。 93. 如申請專利範圍第91項所述之半導體晶片結構之製 73 1342594 作方法，其中，該細線路層包括厚度係介於微米 至2微朱之間的一銅層。 4’如申凊專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該保護層之材質包括一氮矽化合物。 5.如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該保護層之材質包括一磷矽玻璃（psG)。 96.如申請專利範圍第88項所述之半導體晶片結構之製 方法其中，該保護層之材質包括一氧石夕化合物。 97·如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該保護層之材質包括一氮氧矽化合物。 98.如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該保護層之材質包括一硼碗矽玻璃 (BPSG)。 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該金屬層之步驟包括形成一金層。 1 〇〇.如申請專利範圍第88項所述之半導體晶片結構之製 作方法’其中，該形成該金屬層之步驟包括形成一銅層。 1 〇1 ·如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該金屬層之步驟包括形成一銀層。 1〇2.如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該金屬層之步驟包括形成一鉑層。 1〇3.如申請專利範圍第88項所述之半導體晶片結構之製 作方法’其中’該金屬層之材質包括把。 1〇4’如申請專利範圍第88項所述之半導體晶片結構之製 1342594 作方法’其中’該形成該金屬層之步驟包括形成一鎳層。 105. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法’其中，該形成該金屬層之步驟包括形成厚度介 於1微米至20微米之該金屬層。 106. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法’其中，該形成該金屬層之步驟包括形成厚度介 於丨.5微米至15微米之該金屬層。 107 •如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成一濺鑛 製程。 108 .如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成一化學 氣相沉積製程。 .如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成一無電 電鍍製程。 如申清專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成一電鍍 製程。 .如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成與該金 屬層相同材質之金屬層。 4如申请專利範圍第88項所述之半導體晶片、结構之製 作方法，其中’該形成該金屬層之步驟包括形成一無電 75 1342594 電鍍製程。 113 •如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該金屬層之步驟包括形成一電鍍 製程α 114’如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成一銅層。 115 ^ • 申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該種子層之步驟包括形成一金層。 6.如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該黏著/阻障層之步驟包括形成 厚度’丨於0.02微米至〇.8微米之一欽鎮合金層。 1 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該黏著/阻障層之步驟包括形成 厚度”於〇.〇2微米至0_8微米之一鈦金屬層。 118. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該黏著/阻障層之步驟包括形成 厚丨於〇.〇2微米至0.8微米之一氮化欽層。 119. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該黏著/阻障層之步驟包括形成 厚度&quot;於〇.〇2微米至〇.8微米之一组金屬層。 120. 如申請專利範圍第88項所述之半導體晶片結構之製 方法，其中，該形成該黏著/阻障層之步驟包括形成 厚度介於〇.〇2微米至0.8微米之一氬化组層。 121. 如申請專利範圍第88項所述之半導體晶片結構之製 76 1342594 作方法，其中，該形成該黏著/阻障層之步驟包括形成 尽度；丨於〇.〇2微米至0.8微米之一鉻金屬層。 122.如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該黏著/阻障層之步驟包括形成 厚度介於0.02微米至0.8微米之一鉻銅合金層。 123·如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該圖案化光阻層之步驟包括形成 一感光性光阻層在該種子層上。 124. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成一 聚酿亞胺化合物層。 125. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成一 苯基環丁烯化合物層。 126_如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成一 聚對二甲笨類高分子化合物層。 127_如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成一 環氧樹脂層。 128. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成一 厚度介於5微米至50微米之間的聚合物層。 129. 如申請專利範圍第88項所述之半導體晶片結構之製 77 1342594 作方法，其中，該形成該聚合物凸塊之步驟包括形成一 宽度介於5微米至60微米之間的聚合物層。 130. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括一旋塗 (spin-coating)步驟。 131. 如申請專利範圍第91項所述之半導體晶片結構之製 作方法，其中，該些介電層之介電常數值介於丨至3之 間。 132. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該導電區域面積與該金屬接墊表面面積 之比率係為〇. 1至〇. 9之間。 133. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該導電區域面積與該金屬接墊表面面積 之比率係為〇. 05至〇. 5之間。 134. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成圍 繞該導電區域之一聚合物層。 135. 如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成在 該導電區域之至少二側。 136_如申請專利範圍第88項所述之半導體晶片結構之製 作方法，其中，該形成該聚合物凸塊之步驟包括形成在 該導電區域之至少一側。 137.如申請專利範圍第88項所述之半導體晶片結構之製 78 1342^4 138方法’其中’該導電區域之形狀包括四邊形。 作方如中請專利範圍第88項所述之半導體晶片結構之製 ,qQ法其中，該導電區域之形狀包括圓形。 1 〇 y. 由 作方 4專利範圍第88項所述之半導體晶片結構之製 法，其中，該導電區域之形狀包括多邊形。a 0. 05 pad, a thin wiring structure and a protective layer on the semiconductor substrate. The protective layer has at least one opening exposing a metal pad of the thin wiring structure; forming a pattern a polymer bump on the protective layer and the metal pad to expose a conductive region of the metal interface surface; forming an adhesive barrier layer on the conductive region, the polymer bump and the protective layer; Forming a sub-layer on the adhesion barrier layer; forming a patterned photoresist layer on the seed layer, the opening of the patterned photoresist layer 72 1342594 exposing a portion of the polymer bump and the conductive region a seed layer; forming a metal layer on the seed layer and the patterned photoresist layer in the opening; removing the metal layer on the patterned photoresist layer by grinding; removing the patterned photoresist a layer; and removing the seed layer and the adhesion barrier layer that are not under the metal layer. 89. The method of fabricating a semiconductor wafer structure of claim 88, wherein the step of providing the semiconductor substrate comprises providing a germanium wafer. 90. A method of fabricating a semiconductor wafer structure as described in claim 88, wherein the step of providing the semiconductor substrate comprises providing a shredded wafer. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the thin wiring structure comprises: a plurality of dielectric layers on the semiconductor substrate, and the dielectric layers have a plurality of channels And a plurality of thin circuit layers, wherein the thin circuit layers are located on one of the dielectric layers, wherein the thin circuit layers are electrically connected to each other by the via holes. 92. The method of fabricating a semiconductor wafer structure according to claim 91, wherein the thin wiring layer comprises an aluminum layer having a thickness of between 5 micrometers and 2 micrometers. 93. The method of claim 1, wherein the thin circuit layer comprises a copper layer having a thickness ranging from micrometers to 2 microcubics. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the material of the protective layer comprises a nitrogen arsenide compound. 5. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the material of the protective layer comprises a phosphorous bismuth glass (psG). The method of fabricating a semiconductor wafer structure according to claim 88, wherein the material of the protective layer comprises a oxime compound. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the material of the protective layer comprises a oxynitride compound. 98. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the material of the protective layer comprises a boron bowl glass (BPSG). The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the metal layer comprises forming a gold layer. The method of fabricating a semiconductor wafer structure as described in claim 88, wherein the step of forming the metal layer comprises forming a copper layer. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the metal layer comprises forming a silver layer. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the metal layer comprises forming a platinum layer. 1) 3. A method of fabricating a semiconductor wafer structure as described in claim 88, wherein the material of the metal layer comprises a handle. 1 〇 4' is a method of forming a semiconductor wafer structure as described in claim 88, wherein the step of forming the metal layer comprises forming a nickel layer. 105. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the metal layer comprises forming the metal layer having a thickness of from 1 micrometer to 20 micrometers. 106. The method of fabricating a semiconductor wafer structure as described in claim 88, wherein the step of forming the metal layer comprises forming the metal layer having a thickness of from 0.5 μm to 15 μm. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the seed layer comprises forming a sputtering process. 108. The method of fabricating a semiconductor wafer structure of claim 88, wherein the step of forming the seed layer comprises forming a chemical vapor deposition process. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the seed layer comprises forming an electroless plating process. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the seed layer comprises forming an electroplating process. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the seed layer comprises forming a metal layer of the same material as the metal layer. 4. The method of fabricating a semiconductor wafer or structure according to claim 88, wherein the step of forming the metal layer comprises forming an electroless 75 1342594 electroplating process. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the metal layer comprises forming an electroplating process α 114 ′ as in the semiconductor wafer structure described in claim 88 The manufacturing method, wherein the step of forming the seed layer comprises forming a copper layer. 115. The method of fabricating a semiconductor wafer structure of claim 88, wherein the step of forming the seed layer comprises forming a gold layer. 6. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming an alloy layer having a thickness of from 0.02 micrometer to 〇.8 micrometer. . 1 . The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming a titanium metal layer having a thickness of from 2 μm to 0 −8 μm. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming a nitride layer having a thickness of from 2 μm to 0.8 μm. 119. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming a thickness &quot; 〇. 〇 2 μm to 〇. 8 μm The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming an argon having a thickness of between 〇2 μm and 0.8 μm. The method of forming a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming a fullness; To 0.8 The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the adhesion/barrier layer comprises forming one of a thickness of between 0.02 micrometers and 0.8 micrometers. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the patterned photoresist layer comprises forming a photosensitive photoresist layer on the seed layer. 124. The method of fabricating a semiconductor wafer structure according to claim 88, wherein the step of forming the polymer bump comprises forming a layer of a polyamidide compound. 125. The method for fabricating a semiconductor wafer structure, wherein the step of forming the polymer bump comprises forming a layer of a phenylcyclobutene compound. 126. The method for fabricating a semiconductor wafer structure according to claim 88, Wherein, the step of forming the polymer bump comprises forming a layer of a polyparaphenylene polymer compound. 127_ as described in claim 88 The method of fabricating a conductive wafer structure, wherein the step of forming the polymer bump comprises forming an epoxy resin layer. 128. The method for fabricating a semiconductor wafer structure according to claim 88, wherein the forming The step of forming a polymer bump comprises forming a polymer layer having a thickness of between 5 micrometers and 50 micrometers. 129. A method of fabricating a semiconductor wafer structure according to claim 88, wherein the formation is The polymer bump is formed by forming a polymer layer having a width between 5 and 60 micrometers. The method for fabricating a semiconductor wafer structure according to claim 88, wherein the polymer is formed. The step of bumping includes a spin-coating step. The method of fabricating a semiconductor wafer structure according to claim 91, wherein the dielectric layers have a dielectric constant value between 丨 and 3. The ratio of the area of the conductive area to the surface area of the metal pad is between 〇1 and 〇.9, as described in the above. 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。 。. 134. The method of fabricating a semiconductor wafer structure of claim 88, wherein the step of forming the polymer bump comprises forming a polymer layer surrounding the conductive region. 135. The method of fabricating a semiconductor wafer structure of claim 88, wherein the step of forming the polymer bumps comprises forming on at least two sides of the conductive region. 136. The method of fabricating a semiconductor wafer structure of claim 88, wherein the step of forming the polymer bump comprises forming on at least one side of the conductive region. 137. A method of fabricating a semiconductor wafer structure as described in claim 88, wherein the shape of the conductive region comprises a quadrilateral. The method of the semiconductor wafer structure described in claim 88, wherein the shape of the conductive region comprises a circular shape. The method of the semiconductor wafer structure of claim 88, wherein the shape of the conductive region comprises a polygon. 7979
TW096133089A 2006-09-06 2007-09-05 Semiconductor chip and method for fabricating the same TWI342594B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US82461406P 2006-09-06 2006-09-06

Publications (2)

Publication Number Publication Date
TW200814212A TW200814212A (en) 2008-03-16
TWI342594B true TWI342594B (en) 2011-05-21

Family

ID=44768492

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096133089A TWI342594B (en) 2006-09-06 2007-09-05 Semiconductor chip and method for fabricating the same

Country Status (1)

Country Link
TW (1) TWI342594B (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102008042382A1 (en) * 2008-09-26 2010-04-01 Robert Bosch Gmbh Contact arrangement for producing a spaced, electrically conductive connection between microstructured components
US10103095B2 (en) * 2016-10-06 2018-10-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US10923449B2 (en) 2016-10-06 2021-02-16 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect
US11069606B2 (en) 2016-10-06 2021-07-20 Compass Technology Company Limited Fabrication process and structure of fine pitch traces for a solid state diffusion bond on flip chip interconnect

Also Published As

Publication number Publication date
TW200814212A (en) 2008-03-16

Similar Documents

Publication Publication Date Title
US11664336B2 (en) Bonding structure and method of forming same
KR102366537B1 (en) Semiconductor interconnect structure and method
CN102074564B (en) Bonding process for CMOS image sensor
JP5186392B2 (en) Method for forming final level copper-C4 connection using interface cap structure
TWI325616B (en)
TWI520243B (en) Semiconductor device and method of manufacturing same
TW541657B (en) Semiconductor device and its fabrication method
US7777300B2 (en) Semiconductor device with capacitor
US10692828B2 (en) Package structure with protrusion structure
TW200945495A (en) Semiconductor integrated circuit device and manufacturing method of semiconductor integrated device
KR20090086550A (en) CMOS Imager Array with Recessed Dielectric Layer
WO2002021587A1 (en) Semiconductor device and method of manufacturing the semiconductor device
JP3548061B2 (en) Method for manufacturing semiconductor device
TWI792433B (en) Semiconductor device and method for manufacturing semiconductor device
JP2000243754A (en) Semiconductor device
TWI342594B (en) Semiconductor chip and method for fabricating the same
JP2000195862A (en) Semiconductor device and manufacturing method thereof
CN101312170B (en) Circuit assembly
TWI856523B (en) Semiconductor device and method of forming the same
TW200843076A (en) Circuit component structure
CN101312174B (en) Circuit assembly
TWI331788B (en) Chip structure and method for fabricating the same
TWI898604B (en) Semiconductor device
CN219226281U (en) Semiconductor structure
WO2005062367A1 (en) I/o sites for probe test and wire bond

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees