1342567 redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks. 七、指定代表圖： * (一)本案指定代表圖為：第5(a)圖。 ' (二)本代表圖之元件符號簡單說明： • 2半導體記憶體裝置 21正規晶胞陣列 22冗餘晶胞陣列 23頁緩衝器陣列 24冗餘頁緩衝器陣列 25行解碼器電路 26行冗餘選擇電路 鲁 八、本案若有化學式時，請揭示最能顯示發明特徵的化學 (無） 九、發明說明： 【發明所屬之技術領域】 本發明係關於一種冗餘位元線修復之選擇方法及其事 尤指一種具有彈性修復能力之冗餘位元線修復之 士’ 裝署。 、俾万法及其 1342567 » ·. 【先前技術】 於製造出半導體記憶體驗後，會進行多種的測試來判斷 其上=電路操作起來是否符合職之規袼，而每—測試中均會 用到若干參數來檢查電路之雖以及運作。#半導體記憶體； 某部份的正規記憶體晶胞被發現有缺陷，則此部分的記憶體晶 ，會被几餘記憶體晶胞取代，使半導體記憶體裝置能夠繼續正 *地運作。換句活說，為修復缺陷，包含有可藉由高能量光(如 • 雷射等）而熔斷之複數熔絲的冗餘電路於製造時係與半導體記 憶體裝置的記憶體晶胞以及其電路裝置形成為一體。 如第1圖所示，美國專利公開第2005/0207244號專利（後 稱’244號專利)係揭露一種具有冗餘修復功能之半導體記憶體 裝置1。該半導體記憶體裝置丨包含有一正規晶胞陣列丨丨、一冗 餘晶胞陣列12、一晶胞汲極選擇電路13、一行解碼器電路14、 一缺陷晶胞區塊之行冗餘選擇電路15、一鄰接晶胞區塊之行冗 餘選擇電路16以及一列解碼電路丨8。第2圖係為第丨圖中正規以 及几餘晶胞陣列之電路圖’如圖所示：正規晶胞陣列11具有16*8 個記憶體晶胞電晶體，而其中的16個(MLO, MRO, ML 1，MH1. ML7，MR7)係接收字元線選擇訊號WL1。電流係經由記憶體汲 極選擇電晶體MDSLO, MDSL1…MDSL7而提供給正規晶胞 Π ’資料訊號係經由行開關電晶體MBL〇, MBL1... MBL7而被 讀出。在正規晶胞陣列11中，正規晶胞ML2, MR2, ML3, MR3 以及其他位於同一行之正規晶胞組成一晶胞區塊110。同樣的， 正規晶胞MLO, MRO, ML1，MR1以及其他位於同一行之正規晶 胞組成另一晶胞區塊；正規晶胞ML4, MR4, ML5, MR5以及其 5 1342567 他位於同一行之正規晶胞组成又一晶胞區塊；正規晶胞厘]^6, MR6, ML7, MR7以及其他位於同一行之正規晶胞組成再一晶 胞區塊(圖未示包含晶胞]^5，^1115，]\4[6，河116，以及1^7的 行）。冗餘晶胞陣列12内具有8*8個冗餘晶胞，即冗餘記憶體晶 胞電晶體（冗餘晶胞）’且其中的8個(RMLO，RMRO，RML1， RMR1.·.，RML3, RMR3)係接收字元線選擇訊號肌卜電流係 經由記憶體没極選擇電晶體RMDSLO，RMDSL1... RMDSL4而 提供給冗餘晶胞陣列12，資料訊號係經由冗餘行開關電晶體 RMBLO, RMBL1…RMBL3而被讀出。在冗餘晶胞陣列12中， 冗餘晶胞RMLO, RMRO, RML1，RMR1以及其他位於同一冗餘 行之冗餘晶胞組成一第一冗餘晶胞區塊120,用以取代正規晶胞 陣列11中的缺陷晶胞區塊(如晶胞區塊11〇)。冗餘晶胞11^亿2, RMR2，RML3, RMR3以及其他位於同一冗餘行之冗餘晶胞組 成一第二冗餘晶胞區塊121，用以取代與缺陷晶胞區塊鄰接的無 缺陷晶胞區塊。舉例來說’若晶胞區塊110有缺陷，則冗餘晶胞 區塊121中之記憶體晶胞會被用來取代與其鄰接的半個區塊 111(位於晶胞區塊110之左侧）、與其鄰接的半個區塊112(位於晶 胞區塊110之右側)或與其鄰接的半個區塊111、112。 第3圖係為第1圖中行冗餘選擇電路15之電路圖，如圖所 示：該行冗餘選擇電路15產生行選擇訊號RY〇以及ryi並提供 給該第一冗餘晶胞區塊120。缺陷晶胞區塊之行冗餘選擇電路j 5 包含三組可程式化炼絲電路150-152、二組位址選擇電路153、 154以及一位址解碼電路155。可程式化炫絲電路15〇會產生一冗 餘致能訊號FMAIN ’當需要進行冗餘修復時，其會被程式化為 6 1342567 高邏輯位準’而不需要進行冗餘修復時，其會被程式化為低邏 輯位準。當需要進行冗餘修復時’可程式化熔絲電路151、152 會記錄缺陷晶胞區塊的位址。可程式化熔絲電路151、152係具 有相同的電路結構，均包含有一電阻以及一熔絲。在可程式化 熔絲電路150中’舉例來說’電阻R50之一端係與電源端Vcc連 接’另一端係與熔絲F50之一端連接，而熔絲F50之另一端則接 地。冗餘致能訊號FMAIN係自電阻R50與熔絲F50的連接端點而 輸出。可程式化炫絲位址訊號FY2係自可程式化炼絲電路151 之電阻(圖未示)與熔絲(圖未示)的連接端點而輸出；而另一可程 式化熔絲位址訊號FY3係自可程式化熔絲電路152之電阻(圖未 示)與炫絲(圖未示)的連接端點而輸出。位址選擇電路〗53、154 係為相同的電路結構，即互斥反或閘(EXN〇R)，均包含有一對 反相器150、151以及一對MOS開關M50、M51。各位址選擇電 路153(154)係將一位址位元ΑΥ2(ΑΥ3)以及一可程式化熔絲位 址訊號FY2(FY3)進行比較，並產生一冗餘行位址訊號 FA2(FA3)。若位址位元ΑΥ2(ΑΥ3)以及可程式化熔絲位址訊號 FY2(FY3)為相同之邏輯位準時’則冗餘行位址訊號以2(以3) 為高位準；反之’則為低位準。因此，只有在位址位元Αγ2(Αγ3) 以及可程式化熔絲位址訊號1^¥2(17¥3)為相同之邏輯位準時，行 選擇訊號RYG或RY1會被致動到高位準’關始進行位元線冗 餘修復。而冗餘致能訊係根據第3圖的缺陷晶胞區塊 之行几餘選擇電路15而成為高邏輯位準。 第4(a)圖係為第3圖缺陷晶胞區塊之行冗餘選擇電路15的 電路方塊®1，第4(_係為⑸Μ接晶艇塊之行冗餘選擇電 7 路16的電職要圖，如騎示：雜晶胞區塊之行冗餘選擇電 路16包3有可程式化溶絲電路I%、丨57、鄰接位址產生電路 160、161、162、163、164、165、位址選擇電路 166、167、168、 169、170、171以及位址解碼電路172、173。可程式化炫絲電路 156、鄰接位址產生電路16()、⑹、162、位址選擇電路I%、⑹、 168、以及健解碼電路172係組成一上部行冗餘選擇電路n 可程式化麟電路157、雜仙^生電路163、164、165、位 址，，電路169、17。、π卜以及位址解碼電路173係組成一下 部行几餘選擇電路175。上部與下部行冗餘聊電路174、175 係產生一上部冗餘行選擇訊號Ryu以及一下部冗餘行選擇訊 號RYD ’分_以選擇冗餘晶胞區塊之左半部或右半部來取代 正規鄰接半區塊112、111。 為達到取代缺陷晶胞區塊11〇及其相鄰二半區塊丨丨1、112 的目的’缺陷晶胞區塊之行冗餘選擇電路15及鄰接晶胞區塊之 行冗餘選擇電路16就是必要的。即，9條熔絲(缺陷晶胞區塊之 行几餘選擇電路15、上部行冗餘選擇電路174以及下部行冗餘選 擇電路175中各有3條皮用來實現位元線冗餘修復。故於半導體 裝置中，熔絲會佔據很大的面積，尤其是NAND(反及)型的快 閃s己憶體’需要更多的冗餘電路(大約1%〜2%的冗餘位元線)來 維持記憶體的良率。 有鑑於上述缺憾，本發明人有感其未至臻完善，遂竭盡心 智，悉心研究克服，憑從事該項產業多年之經驗累積，進而研 發出一種冗餘位元線修復之選擇方法及其裝置，以達到減少熔 絲佔用面積以及雷射修復操作時間之功效者。 1342567 【發明内容】 由是’本發明之一目的，即在於提供一種冗餘位元線修復 之選擇方法及其裝置，係利用數量較少的熔絲來產生一代碼， 用以選擇複數冗餘區塊來取代其對應之記憶體區塊，以達到減 少熔絲佔用面積以及雷射修復操作時間之功效者。 本發明之一目的，即在於提供一種冗餘位元線修復之選擇 方法及其裝置，係利用一由記憶體區塊之複數熔絲狀態以及邏 輯位址所產生的代碼來完成有彈性的位元線冗餘修復。 為達上述目的，本發明之技術實現如下： 一種冗餘位元線修復之選擇方法，該方法係包含下列步 驟：於正規晶胞陣列中提供複數記憶體區塊的邏輯位址；產生 複數附加熔絲訊號；根據該各熔絲訊號的狀態產生一代碼，且 該代碼係對應到該記憶體區塊之缺陷狀態；以及根據該代碼於 冗餘晶胞陣列中選擇出複數冗餘區塊來取代該記憶體區塊。該 裝置包含：一冗餘修復致能電路’用以根據該記憶體區塊之邏 輯位址產生一冗餘致能訊號；一控制熔絲電路，係用以傳送一 對應到S玄έ己憶體區塊缺陷狀態之代碼；以及一冗餘解碼琴電 路’係接收该几餘致能訊號以及根據該代碼來使冗餘區塊取代 該正規晶胞陣列中的記憶體區塊。 本發明亦揭露一種執行冗餘位元線修復選擇方法之裝置， 該裝置包含有一冗餘修復致能電路、一控制溶絲電路以及一冗 餘解碼電路。該冗餘修復致能電路係根據記憶體區塊之邏輯位 址產生一冗餘致能訊號，該控制熔絲電路係傳遞一對應記憶體 區塊之缺陷狀態的代碼，而冗餘解碼電路係接收該冗餘致能訊 9 1342567 號以及該代碼來產生複數冗餘選擇訊號，用以於冗餘晶胞陣列 中選出複數冗餘區塊來取代正規晶胞陣列中的複數記憶體區 塊。記憶體區塊之實際位址以及邏輯位址互為不相同。在位元 線冗餘修復期間，被取代的記憶體區塊係為正常的或是有缺陷 的0 為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 第5(a)圖係為本發明半導體記憶體裝置2執行冗餘位元線 修復之功能方塊圖，第5(b)圖係為第5(a)圖中半導體記憶體裝 置2之另一實施例圖。半導體記憶體裝置2(於本實施例中係為 一 NAND(反及)快閃記憶體裝置）包含有一正規晶胞陣列2卜一 冗餘晶胞陣列22、一頁緩衝器陣列23、一冗餘頁緩衝器陣列 24、一行解碼電路25以及一行冗餘選擇電路26。頁緩衝器陣 列23包含有複數頁緩衝器pb，用以作為正規晶胞陣列21中記 憶體區塊211-214的讀取/寫入介面，而記憶體區塊21U14内 係含有與正規晶胞陣列21中記憶體晶胞(圖未示)相關聯的記憶 體晶胞。冗餘頁緩衝器陣列24包含有複數冗餘頁緩衝器， 用以作為冗餘晶胞陣列22中記憶體區塊221-224的讀取/寫入 介面’而記憶體區塊221-224内係含有冗餘晶胞(圖未示）。行解 碼電路25會產生複數行選擇訊號γ[0]_Υ[Ν]，即非常類似第2 圖中的行選擇訊號RYO以及RY卜各行選擇訊號γ[〇]_γ[Ν]會 分別被對應傳送到複數位元開關電晶體BS丁的閘極端，即非常1342567 redundancy enable signal and the code to replace a plurality of memory blocks in the normal cell array with redundancy blocks. 7. Designation representative map: * (1) The representative representative figure of this case is: Figure 5(a). '(II) A brief description of the symbol of the representative figure: • 2 semiconductor memory device 21 regular cell array 22 redundant cell array 23 page buffer array 24 redundant page buffer array 25 row decoder circuit 26 line redundancy If you have a chemical formula, please disclose the chemical that best shows the characteristics of the invention. (None). Description of the Invention: [Technical Field of the Invention] The present invention relates to a method for selecting a redundant bit line repair. And it is especially a kind of redundant bit line repairing man with elastic repair ability.俾 法 法 and its 1342567 » ·. [Prior Art] After manufacturing the semiconductor memory experience, a variety of tests will be performed to determine whether the circuit is operational or not, and will be used in every test. Go to a number of parameters to check the circuit as well as the operation. #半导体记忆; A part of the normal memory cell is found to be defective, then this part of the memory crystal will be replaced by several memory cells, so that the semiconductor memory device can continue to operate. In other words, in order to repair defects, a redundant circuit including a plurality of fuses that can be blown by high-energy light (such as laser) is used in the memory cell of the semiconductor memory device and The circuit device is formed in one body. As shown in Fig. 1, U.S. Patent Publication No. 2005/0207244 (hereinafter referred to as the '244 patent) discloses a semiconductor memory device 1 having a redundancy repair function. The semiconductor memory device 丨 includes a normal cell array 丨丨, a redundant cell array 12, a cell drain selection circuit 13, a row decoder circuit 14, and a defective cell row redundancy selection circuit. 15. A row of redundant cell selection circuits 16 adjacent to the cell block and a column of decoding circuits 丨8. Figure 2 is a circuit diagram of the regular and several cell arrays in the figure. As shown in the figure: the regular cell array 11 has 16*8 memory cell transistors, and 16 of them (MLO, MRO) , ML 1, MH1. ML7, MR7) receives the word line selection signal WL1. The current is supplied to the normal cell 经由 ' data signal via the memory diode selection transistor MDSLO, MDSL1...MDSL7, and is read out via the row switch transistors MBL〇, MBL1...MBL7. In the regular cell array 11, the regular unit cells ML2, MR2, ML3, MR3 and other normal cells in the same row constitute a cell block 110. Similarly, the regular unit cells MLO, MRO, ML1, MR1 and other normal unit cells in the same row form another unit cell; the regular unit cells ML4, MR4, ML5, MR5 and its 5 1342567 are in the same line. The unit cell constitutes another unit cell; the normal crystal cell ]^^6, MR6, ML7, MR7 and other normal unit cells in the same row constitute a further unit cell (not shown to include a unit cell)^5, ^1115,]\4[6, River 116, and 1^7 lines). The redundant cell array 12 has 8*8 redundant cells, that is, redundant memory cell transistors (redundant cells)' and 8 of them (RMLO, RMRO, RML1, RMR1.., RML3, RMR3) is the receiving word line selection signal. The muscle current is supplied to the redundant cell array 12 via the memoryless selection transistor RMDSLO, RMDSL1... RMDSL4, and the data signal is via the redundant row switching transistor. Read out at RMBLO, RMBL1...RMBL3. In the redundant cell array 12, the redundant cells RMLO, RMRO, RML1, RMR1 and other redundant cells in the same redundant row constitute a first redundant cell block 120 for replacing the regular cell Defective cell blocks in array 11 (eg, cell block 11〇). Redundant unit cells 11.2 billion, RMR2, RML3, RMR3 and other redundant cells in the same redundant row form a second redundant cell block 121 for replacing the adjacent cells of the defective cell block Defective cell block. For example, if the cell block 110 is defective, the memory cell in the redundant cell block 121 is used to replace the half block 111 adjacent thereto (on the left side of the cell block 110). ), a half block 112 adjacent thereto (on the right side of the cell block 110) or a half block 111, 112 adjacent thereto. 3 is a circuit diagram of the row redundancy selection circuit 15 in FIG. 1, as shown in the figure: the row redundancy selection circuit 15 generates row selection signals RY and ryi and supplies them to the first redundant cell block 120. . The defective cell block row redundancy selection circuit j 5 includes three sets of programmable wire making circuits 150-152, two sets of address selecting circuits 153, 154, and a bit address decoding circuit 155. The programmable flash circuit 15〇 will generate a redundant enable signal FMAIN 'when it needs to be redundantly repaired, it will be programmed to 6 1342567 high logic level' without the need for redundancy repair, it will Stylized to a low logic level. When the redundancy repair is required, the programmable fuse circuits 151, 152 record the address of the defective cell block. The programmable fuse circuits 151, 152 have the same circuit structure and each include a resistor and a fuse. In the programmable fuse circuit 150, for example, one end of the resistor R50 is connected to the power supply terminal Vcc, and the other end is connected to one end of the fuse F50, and the other end of the fuse F50 is grounded. The redundant enable signal FMAIN is output from the connection end point of the resistor R50 and the fuse F50. The programmable flash address signal FY2 is output from the connection end of the resistor (not shown) of the programmable circuit 151 and the fuse (not shown); and another programmable fuse address The signal FY3 is output from the connection end point of the resistor (not shown) of the programmable fuse circuit 152 and the glare (not shown). The address selection circuits 535 and 154 have the same circuit configuration, that is, mutually exclusive OR gates (EXN 〇 R), and each includes a pair of inverters 150 and 151 and a pair of MOS switches M50 and M51. The address selection circuit 153 (154) compares the address bit ΑΥ 2 (ΑΥ 3) and a programmable fuse address signal FY2 (FY3) and generates a redundant row address signal FA2 (FA3). If the address bit ΑΥ2 (ΑΥ3) and the programmable fuse address signal FY2 (FY3) are the same logic level, then the redundant row address signal is 2 (to 3) as the high level; otherwise, ' Low level. Therefore, the row select signal RYG or RY1 will be activated to a high level only when the address bit Α γ2 (Α γ3) and the programmable fuse address signal 1^¥2 (17 ¥ 3) are the same logic level. 'Starting the bit line redundancy repair. The redundant enabling signal is a high logic level according to the selection circuit 15 of the defective cell block in Fig. 3. Figure 4(a) is the circuit block of the row row redundancy selection circuit 15 of the defect cell block diagram of Fig. 3, and the fourth block is the (5) row connection of the rowing block. Electric job map, such as riding display: line cell block redundancy selection circuit 16 package 3 with programmable melting circuit I%, 丨 57, adjacent address generation circuit 160, 161, 162, 163, 164 165, address selection circuits 166, 167, 168, 169, 170, 171 and address decoding circuits 172, 173. Programmable flash circuit 156, adjacent address generation circuit 16 (), (6), 162, address The selection circuits I%, (6), 168, and the health decoding circuit 172 form an upper row redundancy selection circuit n programmable logic circuit 157, heterogeneous circuit 163, 164, 165, address, circuit 169, 17 The π and the address decoding circuit 173 form a lower row selection circuit 175. The upper and lower row redundancy circuits 174, 175 generate an upper redundant row selection signal Ryu and a lower redundancy row selection signal. RYD 'minute_ replaces the normal adjacent half block 112, 111 by selecting the left or right half of the redundant cell block. The defective 'defective cell block 11' and its adjacent two half blocks 丨丨1, 112's destination 'defective cell block row redundancy selection circuit 15 and the adjacent cell block row redundancy selection circuit 16 are It is necessary that the nine fuses (the defective cell block row selection circuit 15, the upper row redundancy selection circuit 174, and the lower row redundancy selection circuit 175 each have three strips for realizing the bit line). Redundancy repair. Therefore, in semiconductor devices, the fuse will occupy a large area, especially the NAND (reverse) type of flash s replied 'requires more redundant circuits (about 1% to 2% Redundant bit line) to maintain the yield of memory. In view of the above shortcomings, the inventor felt that it was not perfect, exhausted his mind, carefully studied and overcome, and accumulated years of experience in the industry, and then developed A method for selecting a redundant bit line repair and a device thereof are provided to reduce the effective area of the fuse and the operation time of the laser repair operation. 1342567 [Invention] It is an object of the present invention to provide a Selection method of redundant bit line repair and its installation A lesser number of fuses are used to generate a code for selecting a plurality of redundant blocks to replace their corresponding memory blocks to achieve a reduction in fuse footprint and laser repair operation time. It is an object of the invention to provide a method and apparatus for selecting redundant bit line repairs by using a code generated by a complex fuse state of a memory block and a logical address to complete a flexible bit. Line redundancy repair. To achieve the above object, the technology of the present invention is implemented as follows: A method for selecting redundant bit line repair, the method comprising the steps of: providing logical bits of a plurality of memory blocks in a regular cell array; a plurality of additional fuse signals; generating a code according to the state of each fuse signal, and the code corresponds to a defect state of the memory block; and selecting a complex number in the redundant cell array according to the code Redundant blocks replace the memory block. The device comprises: a redundancy repair enabling circuit for generating a redundant enable signal according to the logical address of the memory block; and a control fuse circuit for transmitting a corresponding to the S Xuanji recall The code of the body block defect state; and a redundant decoding circuit 'receives the plurality of enable signals and replaces the memory blocks in the regular cell array according to the code. The present invention also discloses an apparatus for performing a redundant bit line repair selection method, the apparatus comprising a redundancy repair enabling circuit, a control silencing circuit, and a redundant decoding circuit. The redundancy repair enabling circuit generates a redundant enable signal according to the logical address of the memory block, and the control fuse circuit transmits a code corresponding to the defect state of the memory block, and the redundant decoding circuit is The redundant enable signal 9 1342567 and the code are received to generate a complex redundancy selection signal for selecting a plurality of redundant blocks in the redundant cell array to replace the complex memory blocks in the regular cell array. The actual address and logical address of the memory block are different from each other. The above and other objects, features and advantages of the present invention will be more apparent and understood during the bit line redundancy repair. The embodiments, in conjunction with the drawings, are described in detail below. [Embodiment] FIG. 5(a) is a functional block diagram of a semiconductor memory device 2 for performing redundant bit line repair, and FIG. 5(b) is a semiconductor memory device of FIG. 5(a). A diagram of another embodiment of 2. The semiconductor memory device 2 (in this embodiment, a NAND (inverse) flash memory device) includes a regular cell array 2, a redundant cell array 22, a page buffer array 23, and a redundancy. The remaining page buffer array 24, a row of decoding circuits 25, and a row of redundancy selection circuits 26. The page buffer array 23 includes a plurality of page buffers pb for reading/writing interfaces of the memory blocks 211-214 in the regular cell array 21, and the memory block 21U14 contains the normal cell A memory cell unit associated with a memory cell (not shown) in array 21. Redundant page buffer array 24 includes a plurality of redundant page buffers for use as read/write interfaces of memory blocks 221-224 in redundant cell array 22 and memory blocks 221-224. Contains redundant cells (not shown). The row decoding circuit 25 generates a complex row selection signal γ[0]_Υ[Ν], which is very similar to the row selection signal RYO and the RY row selection signal γ[〇]_γ[Ν] in FIG. To the gate terminal of the complex bit switch transistor BS, that is very
10 1342567 類似第2圖中的行開關電晶體MBL〇, MBL1…MBL7，用以在 几餘晶胞陣列22中選出對應的冗餘區塊來取代記憶體區塊 211-214。行冗餘選擇電路26會產生複數冗餘選擇訊號 RY[0]-RY[M] ’即非常類似第2 @巾的行選擇訊號RY0以及 RY卜並產生上部/下部冗餘行選擇訊號RYU、RYD，使之與冗 餘位元開關電晶體之閘極端連接，以開始進行位元線冗餘修 復。一資料線DL以及一冗餘資料線rdl係分別與位元開關電 晶體BST以及冗餘位元開關電晶體仙灯相連接，用以於位元 線冗餘修復期間傳遞資料。第5(b)圖中僅僅揭露4組記憶體區 塊211-214、4組冗餘區塊221-224、及其分別對應之頁緩衝器 PB與冗餘頁緩衝器rpb。在目前的實施例中，各記憶體區塊 包含有2條位元線BL(在NAND快閃記憶體裝置中，一條係為 遮蔽位元線’用以提供遮蔽的目的）。所有的位元線均具有從 BL[0]到BL[7]的實際位址以及2,〇，1，3的邏輯位址，其中一邏輯 位址即代表一記憶體區塊中的2條位元線。此外，冗餘區塊 221-224亦具有與記憶體區塊211-214相同的特徵。第5(c)圖係 為第5(a)圖中半導體記憶體裝置2之又一實施例圖，該半導體 記憶體裝置2’係非常類似半導體記憶體裝置2。半導體記憶體 裝置2’包含有一正規晶胞陣列21’、一冗餘晶胞陣列22,、一頁 緩衝器陣列(圖未示)以及一冗餘頁緩衝器陣列24(圖未示）。正 規晶胞陣列21’係接收行選擇訊號γ[〇]-γ[7]，用以於記憶體區 塊211’-218’中選出部分來被取代。該冗餘晶胞陣列22,係接收 冗餘選擇訊號RY[〇]-RY[3]，用以於冗餘晶胞陣列22’中選出部 分的冗餘記憶體區塊22Γ-224’來取代其對應之正規晶胞陣列 11 1342567 21’中的記憶體區塊。帛5(c)圖中僅僅揭露8組記憶體區塊 21Γ-218’以及4組冗餘區塊221，-224’，此外，第5(C)圖中的半 導體記憶體裝置2’係可被認定為第5(b)圖中半導體記憶體裝置 2的延伸。 第6圖係為第5(b)圖應用於本發明半導體記憶體裝置2之 行冗餘選擇電路26的第一實施例圖，如圖所示：行冗餘選擇電 路26包含有一冗餘修復致能電路26卜係跟據記憶體區塊之邏 # 輯位址ADD1來產生一冗餘致能訊號RED ; —控制熔絲電路 262 ’係傳遞一對應記憶體區塊之缺陷狀態的代碼；以及一冗餘 解碼電路263 ’係接收該冗餘致能訊號RgD、邏輯位址ADD2 以及該代碼來產生複數冗餘選擇訊號RY，用以於冗餘晶胞陣 列22中選出複數冗餘區塊來取代正規晶胞陣列21中的複數記 憶體區塊。於本實施例中，冗餘修復致能電路261包含有一冗 餘致能電路261a(參閱第7(a)圖）、一致能熔絲電路261b(參閱第 7(b)圖)以及3組熔絲狀態電路261c(參閱第7(c)圖）。致能熔絲 電路261b包含有串接之電阻R1與熔絲F1，且電阻R1與熔絲 • F1係配置於電源供應端Vcc與接地端之間，以產生一致能熔絲 訊號EN。熔絲狀態電路261c包含有串接之電阻R與熔絲F， 且電阻R與熔絲F係配置於電源供應端Vcc與接地端之間，以 產生一熔絲狀態訊號FA。因此，3組熔絲狀態電路261c產生3 組熔絲狀態訊號FA[2]-FA[4]。冗餘致能電路261a接收致能熔 絲訊號EN、3組熔絲狀態訊號FA[2]-FA[4]以及記憶體區塊中 邏輯位址(如第6圖中之ADD1)的3個位元A[2]-A[4]。當位元 A[2]等於熔絲狀態訊號A[2]、位元A[3]等於熔絲狀態訊號A[3] (S > 12 1342567 且位元A[4]等於熔絲狀態訊號a⑷時，邏輯閘E(^、eQ2與 EQ3均會輸出為邏輯1的訊號。此時若致能熔絲訊號£]^啟動’ 則冗餘致能訊號也會因此被產生出來。控制熔絲電路262包含 有如第8圖所示之3組熔絲指示電路262,，熔絲指示電路262’ 包含有串接之電阻FSR與熔絲FSF，且電阻FSR與熔絲FSF 係配置於電源供應端Vcc與接地端之間，以產生一附加溶絲訊 號FS。因此，3組熔絲指示電路262,產生3組附加熔絲訊號 FS[0]-FS[2]。冗餘解碼電路263包含6組第一編碼電路263a(如 第9(a)圖所示）、4組第二編碼電路263c(如第9(c)圖所示)以及 一第三編碼電路(如第9(d)圖所示）。該6組第一編碼電路263a 係根據3組附加熔絲訊號FS[0]-FS[2]以及由第9(b)圖中反相器 電路263b產生的3組反相附加熔絲訊號FS[0]N-FS[2]N來產生 6組第一訊號F[0]-F[5]。該4組第二編碼電路263c係根據3組 附加熔絲訊號FS[0]-FS[2]、冗餘致能訊號RED以及記憶體區 塊邏輯位址的二位元A[0]、A[l]來產生冗餘選擇訊號 RY[0]-RY[3]。該第三編碼電路263d係根據冗餘選擇訊號 RY[0]-RY[3]來產生一行失能訊號DISY。該冗餘解碼電路263 更包含5組反相器IN8-IN9以及IN21-IN23，用以將3組附加 熔絲訊號FS[0]-FS[2]以及第9(b)圖中記憶體區塊邏輯位址的二 位元A[0]、A[l]反相。 下方之表1揭露記憶體區塊的6種缺陷狀態DT1-DT6及其 對應之附加熔絲訊號FS[0]-FS[2](本發明第一實施例中行選擇 電路26之操作過程）。參閱第5(b)圖以及表1，以DT1的例子 來說，鄰接記憶體區塊211、212(即表1中被框起來的部份， 13 134256710 1342567 is similar to the row switch transistors MBL〇, MBL1...MBL7 in Fig. 2 for selecting corresponding redundant blocks in the plurality of cell arrays 22 in place of the memory blocks 211-214. The row redundancy selection circuit 26 generates a complex redundancy selection signal RY[0]-RY[M]' which is very similar to the row selection signals RY0 and RY of the second @巾 and generates an upper/lower redundancy row selection signal RYU, The RYD is connected to the gate terminal of the redundant bit switch transistor to begin bit line redundancy repair. A data line DL and a redundant data line rdl are respectively connected to the bit switch transistor BST and the redundant bit switch transistor lamp to transfer data during bit line redundancy repair. In Fig. 5(b), only four sets of memory blocks 211-214, four sets of redundant blocks 221-224, and their corresponding page buffers PB and redundant page buffers rpb are disclosed. In the current embodiment, each memory block contains two bit lines BL (in a NAND flash memory device, one is a mask bit line' for the purpose of providing shadowing). All bit lines have the actual address from BL[0] to BL[7] and the logical address of 2, 〇, 1, 3, where one logical address represents 2 in a memory block. Bit line. In addition, redundant blocks 221-224 also have the same features as memory blocks 211-214. Fig. 5(c) is a view showing still another embodiment of the semiconductor memory device 2 in Fig. 5(a), which is very similar to the semiconductor memory device 2. The semiconductor memory device 2' includes a regular cell array 21', a redundant cell array 22, a page buffer array (not shown), and a redundant page buffer array 24 (not shown). The regular cell array 21' receives the row selection signal γ[〇]-γ[7] for selecting a portion of the memory blocks 211'-218' to be replaced. The redundant cell array 22 receives the redundant selection signal RY[〇]-RY[3] for replacing a portion of the redundant memory block 22Γ-224' in the redundant cell array 22'. It corresponds to the memory block in the regular cell array 11 1342567 21'. In Fig. 5(c), only eight sets of memory blocks 21Γ-218' and four sets of redundant blocks 221, -224' are disclosed, and in addition, the semiconductor memory device 2' in Fig. 5(C) is It is considered to be an extension of the semiconductor memory device 2 in the fifth (b) diagram. Figure 6 is a diagram showing a first embodiment of the row redundancy selection circuit 26 applied to the semiconductor memory device 2 of the present invention as shown in Figure 5(b). As shown, the row redundancy selection circuit 26 includes a redundancy repair. The enabling circuit 26 generates a redundant enable signal RED according to the logical address ADD1 of the memory block; the control fuse circuit 262' transmits a code corresponding to the defect state of the memory block; And a redundant decoding circuit 263' receives the redundancy enable signal RgD, the logical address ADD2, and the code to generate a complex redundancy selection signal RY for selecting a plurality of redundant blocks in the redundant cell array 22. The complex memory block in the regular cell array 21 is replaced. In the present embodiment, the redundancy repair enabling circuit 261 includes a redundancy enabling circuit 261a (see FIG. 7(a)), a uniform energy fuse circuit 261b (see FIG. 7(b)), and three sets of melting. Wire state circuit 261c (see Figure 7(c)). The enable fuse circuit 261b includes a series connected resistor R1 and a fuse F1, and the resistor R1 and the fuse F1 are disposed between the power supply terminal Vcc and the ground to generate a uniform fuse signal EN. The fuse state circuit 261c includes a series connected resistor R and a fuse F, and the resistor R and the fuse F are disposed between the power supply terminal Vcc and the ground to generate a fuse state signal FA. Therefore, the three sets of fuse state circuits 261c generate three sets of fuse state signals FA[2]-FA[4]. The redundancy enabling circuit 261a receives the enable fuse signal EN, the three sets of fuse state signals FA[2]-FA[4], and the logical addresses in the memory block (such as ADD1 in FIG. 6). Bit A[2]-A[4]. When bit A[2] is equal to fuse state signal A[2], bit A[3] is equal to fuse state signal A[3] (S > 12 1342567 and bit A[4] is equal to fuse state signal When a(4), the logic gate E (^, eQ2 and EQ3 will output a signal of logic 1. If the fuse signal is enabled], then the redundancy enable signal will be generated. Control fuse The circuit 262 includes three sets of fuse indicating circuits 262 as shown in FIG. 8. The fuse indicating circuit 262' includes a series connected resistor FSR and a fuse FSF, and the resistor FSR and the fuse FSF are disposed at the power supply end. Between Vcc and the ground, an additional solutes signal FS is generated. Therefore, the three sets of fuse indicating circuits 262 generate three sets of additional fuse signals FS[0]-FS[2]. The redundant decoding circuit 263 includes 6 a group first encoding circuit 263a (as shown in Fig. 9(a)), four groups of second encoding circuits 263c (as shown in Fig. 9(c)), and a third encoding circuit (such as Fig. 9(d) The six sets of first encoding circuits 263a are based on three sets of additional fuse signals FS[0]-FS[2] and three sets of inverted additions generated by inverter circuit 263b in Figure 9(b). Fuse signal FS[0]N-FS[2]N to generate 6 groups Signals F[0]-F[5]. The four sets of second encoding circuits 263c are based on three sets of additional fuse signals FS[0]-FS[2], redundant enable signals RED, and memory block logic bits. The two bits A[0], A[l] of the address generate a redundancy selection signal RY[0]-RY[3]. The third encoding circuit 263d selects the signal RY[0]-RY[3 according to the redundancy. The redundancy decoding circuit 263 further includes five sets of inverters IN8-IN9 and IN21-IN23 for adding three sets of additional fuse signals FS[0]-FS[2] and 9(b) The two bits A[0], A[l] of the logical block of the memory block are inverted. Table 1 below reveals the six defect states DT1-DT6 of the memory block and their corresponding Additional fuse signal FS[0]-FS[2] (operation of row selection circuit 26 in the first embodiment of the present invention). Referring to FIG. 5(b) and Table 1, in the case of DT1, adjacent memory Blocks 211, 212 (ie, the framed part of Table 1, 13 1342567
其邏輯位址分別為2與0’其實際位址係分別為BL[0]與BL[2]) 會被其對應之冗餘區塊221、222所取代。於NAND快閃記憶 體的應用中’記憶體區塊(如記憶體區塊211)中的一條位元線通 常係被用來作為遮蔽位元線，且係由其對應之頁緩衝器所選 出，本發明實施例中之位元線BL[1]、BL[3]即為遮蔽位元線。 然’於其他半導體記憶體的應用中，一個記憶體區塊内可能僅 含有一條位元線’故於本發明之實施例中，記憶體區塊211與 212可被視為互相鄰接《以DT2的例子來說，鄰接記憶體區塊 213、214會被取代；以DT4的例子來說，鄰接記憶體區塊211、 213會被取代；以DT6的例子來說，鄰接記憶體區塊211-214 會被取代。行FS[n]係代表第一訊號F[0]-F[5]，其各顯示為高 邏輯位準，且係經由第9(a)圖中6組第一編碼電路263a的3組 附加熔絲訊號FS[0]-FS[2]來產生。The logical addresses of 2 and 0', respectively, whose actual address systems are BL[0] and BL[2], respectively, are replaced by their corresponding redundant blocks 221, 222. In the application of NAND flash memory, a bit line in a memory block (such as memory block 211) is typically used as a mask bit line and is selected by its corresponding page buffer. The bit lines BL[1], BL[3] in the embodiment of the present invention are the mask bit lines. However, in other semiconductor memory applications, a memory block may contain only one bit line. Thus, in embodiments of the present invention, memory blocks 211 and 212 may be considered to be adjacent to each other. For example, contiguous memory blocks 213, 214 will be replaced; in the case of DT4, contiguous memory blocks 211, 213 will be replaced; in the case of DT6, contiguous memory block 211- 214 will be replaced. The row FS[n] represents the first signals F[0]-F[5], each of which is shown as a high logic level, and is added via the three groups of the six sets of first encoding circuits 263a in the figure 9(a). The fuse signal FS[0]-FS[2] is generated.
缺陷 狀態 實際位址A[l:〇] 附加熔絲訊號 FS[n] A[l]-1 A[〇l=〇 Α[1]=0 Af〇l=0 A[l]=〇 A[〇l=l A[l]=l A[〇l=l FS[2] FS[1] FS[0] DT1 2 0 1 3 0 0 0 F[0] DT2 2 0 1 3 0 0 1 F[l] DT3 2 0 1 3 0 1 0 F[2] DT4 2 0 1 3 0 1 1 F[3] DT5 2 1°一 1 3 1 0 0 F[4] DT6 2 0 1丨3 1 0 1 F[5] 14 1342567 本發明第一實施例中的冗餘位元線修復之選擇方法，將於 下方伴隨著帛5(b)圖、第7⑻-7(c)®以及表1中的DT4加以詳 加描述，即記憶體區塊211-213會被取代。首先，於正規晶胞 陣列21中提供記憶體區塊211_213的3組邏輯位址(2,〇, ^，記 憶體區塊211之邏輯位址(即2)會提供A[〇]=〇與A[1]=1的位元 值’記憶體區塊212之邏輯位址(即〇)會提供a[〇]=〇與a[i]=〇 的位元值，而記憶體區塊213之邏輯位址(即1)會提供a[〇]=i 與A[l]=〇的位元值。其中，A[〇]與a⑴係為任一記憶體區塊中 邏輯位址的至少2個位元。其次，3組附加熔絲訊號fs[〇]-FS[2] 係藉由第8圖中的3組熔絲指示電路262’所產生；其中，3組 附加熔絲訊號FS[0]、FS[1]以及FS[2]係分別為1(高位準）、1(高 位準)以及〇(低位準)。再者，根據3組附加炼絲訊號fS[〇]_fs[2] 產生一代碼(明顯的，表1中3組附加熔絲訊號FS[0]_FS[2]的組 合會對應到一特定的代碼來區分缺陷狀態），且該代碼會對應到 記憶體區塊211-213的缺陷狀態(DT4)。最後，冗餘晶胞陣列 22中的3組冗餘區塊221-223會根據該代碼被選擇出來，用以 取代正規晶胞陣列21中的記憶體區塊211-213。此選擇冗餘區 塊221-223的過程將於下詳述。若第7(b)圖中的致能熔絲訊號 EN被設定為高邏輯位準且位元值a[2]-A[4]的邏輯狀態又分別 與3組熔絲狀態訊號FA[2]_FA[4]相同時，則第7⑻圖中的冗餘 致能訊號RED為高邏輯位準。記憶體區塊211具有”2”之邏輯 位址以及A[0]=0與A[l]=l的位元值。參閱第9(c)圖中具有冗 餘選擇§fL號RY[2]輸出的第二編碼電路263c，NOR(反或）閘 NOR4之輸出會因為第一訊號f[3](參閱表1與第9(a)圖)為高邏 輯位準的關係而成為低邏輯位準，且反相器IN14之輸出係為 高邏輯位準，更會令訊號RED=1(高邏輯位準）、A[1]=1(高邏輯 位準)以及A[0]N=1(高邏輯位準）。據此，冗餘選擇訊號RY[2] 會成為高邏輯位準，因此，冗餘區塊221會被冗餘選擇訊號 RY[2]選擇出來，用以取代記憶體區塊211。記憶體區塊212具 有”0”之邏輯位址以及A[0]=0與A[1]=0的位元值。具有冗餘選 擇訊號RY[0]輸出的第二編碼電路263c，NOR(反或)閘NOR2 之輸出會因為第一訊號F[3](參閱表1與第9(a)圖)為高邏輯位準 的關係而成為低邏輯位準，且反相器IN10之輸出係為高邏輯 位準，更會令訊號RED=1(高邏輯位準）、A[1]N=1(高邏輯位準) 以及A[0]N=1(高邏輯位準）。據此，冗餘選擇訊號ry[〇]會成為 高邏輯位準’因此’冗餘區塊222會被冗餘選擇訊號RY[〇]選 擇出來，用以取代記憶體區塊212。記憶體區塊213具有”1”之 邏輯位址以及A[0]=1與A[l]=〇的位元值。具有冗餘選擇訊號 RY[〇]輸出的第二編碼電路263c，NOR(反或)閘NOR3之輸出 會因為第一訊號F[3](參閱表1與第9(a)圖)為高邏輯位準與反相 器IN12之輸出係為高邏輯位準的關係而成為低邏輯位準，更 會令訊號RED=1(高邏輯位準）、a[1]N=1(高邏輯位準）以及 A[0]=1(高邏輯位準）。據此’冗餘選擇訊號RYR]會成為高邏輯 位準’因此’冗餘區塊223會被冗餘選擇訊號RY[i]選擇出來， 用以取代記憶體區塊213。然，記憶體區塊214具有”3”之邏輯 位址以及A[0]=1與A[l]=l的位元值。具有冗餘選擇訊號Ry[3] 輸出的第二編碼電路263c ’ NOR(反或)閘NOR5之輪出會因為 第一訊號F[l]、F[4]、F[5](參閱表1與第9⑻圖)為低邏輯位準 的關係而成為高邏輯位準，且反相器IN16之輸出係為低邏輯 位準。據此’冗餘選擇訊號RY[3]會成為低邏輯位準且冗餘區 塊224將不會被冗餘選擇訊號RY[3]選擇出來取代記憶體區塊 表1中DT6(記憶體區塊211-214被取代）的操作過程將於 下詳述。首先，於正規晶胞陣列中提供記憶體區塊211_214的 4組邏輯位址(2, 0, 1，3) ’記憶體區塊211之邏輯位址(即2)會提 供A[0]=〇與Α[ι]=1的位元值’記憶體區塊212之邏輯位址(即 〇)會提供A[0]=0與A[1]=0的位元值，記憶體區塊213之邏輯 位址(即1)會提供A[0]=1與A[1]=0的位元值，且記憶體區塊 214之邏輯位址(即3)會提供A[0]=1與A[l]=l的位元值。其次， 3組附加熔絲訊號FS[0]_FS[2]係藉由第8圖中的3組熔絲指示 電路262’所產生；其中，3組附加熔絲訊號FS[0]、FS[1]以及 FS[2]係分別為1(高位準）、〇(低位準)以及ι(高位準）。再者，根 據3組附加熔絲訊號FS[0]-FS[2]產生一代碼，且該代碼會對應 到記憶體區塊211-214的缺陷狀態(DT6)。最後，冗餘晶胞陣列 22中的3組冗餘區塊221-224會根據該代碼被選擇出來，用以 取代正規晶胞陣列21中的記憶體區塊211-214。此選擇冗餘區 塊221-223的過程將於下詳述。若第7(b)圖中的致能熔絲訊號 EN被設定為高邏輯位準且位元值a[2]-A[4]的邏輯狀態又分別 與3組熔絲狀態訊號FA[2]-FA[4]相同時，則第7(a)圖中的冗餘 致能訊號RED為高邏輯位準。記憶體區塊211具有”2”之邏輯 位址以及A[0]=0與A[l]=l的位元值。參閱第9(c)圖中具有冗 餘選擇訊號RY[2]輸出的第二編碼電路263c，NOR(反或）閘 1342567 N〇R4之輸出會因為第一訊號F[5](參閱表1與第9⑻圖)為高邏 輯位準的關係而成為低邏輯位準’且反相器！Ν14之輸出係為 高邏輯位準’更會令訊號RED=1(高邏輯位準）、Α[1]=1(高邏輯 位準)以及Α[0]Ν=1(高邏輯位準）。據此，冗餘選擇訊號RY[2] 會成為向邏輯位準，因此，冗餘區塊221會被冗餘選擇訊號 RY[2]選擇出來’用以取代記憶體區塊2U。記憶體區塊212具 有”0”之邏輯位址以及A[0]=0與A[1]=0的位元值。參閱第9(c) • 圖中具有冗餘選擇訊號RY[〇]輸出的第二編碼電路263c， NOR(反或)閘N0R2之輸出會因為第一訊號F风參閱表1與第 9⑻圖)為高邏輯位準的關係而成為低邏輯位準，且反相器以1〇 之輸出係為高邏輯位準，更會令訊號(高邏輯位準）、 A[1]N=1(高邏輯位準)以及AtojNi(高邏輯位準）。據此’冗餘 選擇訊號RY[0]會成為高邏輯位準，因此，冗餘區塊222會被 冗餘選擇訊號RY[0]選擇出來，用以取代記憶體區塊212。記憶 體區塊213具有，Τ’之邏輯位址以及A[〇]=1與八⑴屻的位元 值。參閱第9(c)圖中具有冗餘選擇訊號^[^輸出的第二編碼 _ 電路263c ’N0R(反或)閘N0R3之輸出會因為第一訊號F[5](參 閱表1與第9(a)圖)為高邏輯位準的關係而成為低邏輯位準，且 反相器IN12之輸出係為高邏輯位準’更會令訊號j^£d=1(高邏 輯位準）、A[1]N=1(高邏輯位準)以及A[〇]=1(高邏輯位準）。據 此’冗餘選擇訊號RY[1]會成為高邏輯位準，因此，冗餘區塊 223會被冗餘選擇訊號RYp]選擇出來，用以取代記憶體區塊 213。記憶體區塊214具有”3”之邏輯位址以及Α[〇]=ι與 的位元值。參閱第9(c)圖中具有冗餘選擇訊號RY[3]輸出的第 18 1342567 二編碼電路263c，NOR(反或)閘N〇R5之輪出會因為第一 F[5](參閱表1與第9⑻圖)為高邏輯位準的關係而成為低邏輯^ 準，且反相器IN16之輸出係為高邏輯位準，更會令訊 RED=1(高邏輯位準）、A⑴(高邏輯位準)以及Α[〇ϋ邏輯 位準）。據此，冗餘選擇訊號RY[3]會成為高邏輯位準，因此， 冗餘區塊224會被冗餘選擇訊號RY[3]選擇出來，用以取代記 憶體區塊214。對於表1中之其它例子①丁丨七乃與^^习來說， • 其操作過程均非常類似上述DT4與DT6的操作Ϊ故不再重複 贅述。 根據表1以及第5(b)圖所示，記憶體區塊存在著2個鄰接 缺陷記憶體區塊(如DT1-DT3)、3個鄰接缺陷記憶體區塊(如 DT4-DT5)或4個鄰接缺陷記憶體區塊(如DT6)時，都可以藉由 本發明第一實施例中具有少量熔絲的行冗餘選擇電路26來取 代之。參閱第7(a)圖，若EQ卜EQ2以及EQ3必須被使用到， 則冗餘會利用不同的A[2:4]來修復複數條位元線。因此，僅有 7組熔絲會被使用到（第7(b)圖中的4組熔絲以及第8圖中的3 • 組炼絲)，但’244號專利(參閱其第6A圖以及第6B圖)卻需要用 到9組熔絲。據此’本發明於修復表1中的6種缺陷狀態將非 常的具有彈性。 第6圖中的行冗餘選擇電路26’係為本發明之第二實施 例’其係可應用於第5(c)圖中的半導體記憶體裝置2’。冗餘修 復致能電路261’包含有261包含有一冗餘致能電路261a’(參閱 第10圖）、一致能熔絲電路261b’(參閱第7(b)圖）以及3組熔絲 狀態電路261c，(參閱第7(c)圖）。冗餘致能電路261a，接收致能 1342567Defect status actual address A[l:〇] Additional fuse signal FS[n] A[l]-1 A[〇l=〇Α[1]=0 Af〇l=0 A[l]=〇A[ 〇l=l A[l]=l A[〇l=l FS[2] FS[1] FS[0] DT1 2 0 1 3 0 0 0 F[0] DT2 2 0 1 3 0 0 1 F[ l] DT3 2 0 1 3 0 1 0 F[2] DT4 2 0 1 3 0 1 1 F[3] DT5 2 1°-1 3 1 0 0 F[4] DT6 2 0 1丨3 1 0 1 F [5] 14 1342567 The method for selecting redundant bit line repair in the first embodiment of the present invention will be accompanied by 帛5(b), 7(8)-7(c)®, and DT4 in Table 1 below. As described in detail, the memory blocks 211-213 are replaced. First, three sets of logical addresses (2, 〇, ^, the logical address of the memory block 211 (ie 2) of the memory block 211_213 are provided in the regular cell array 21 to provide A[〇]=〇 The bit value of A[1] = 1 'the logical address of the memory block 212 (ie, 〇) provides a bit value of a[〇]=〇 and a[i]=〇, and the memory block 213 The logical address (ie 1) provides the bit value of a[〇]=i and A[l]=〇, where A[〇] and a(1) are at least logical addresses in any memory block. 2 bits. Secondly, 3 sets of additional fuse signals fs[〇]-FS[2] are generated by the three sets of fuse indicating circuits 262' in Fig. 8; among them, 3 sets of additional fuse signals FS [0], FS[1], and FS[2] are 1 (high level), 1 (high level), and 〇 (low level). Furthermore, according to 3 sets of additional refining signal fS[〇]_fs[ 2] Generate a code (obviously, the combination of the three sets of additional fuse signals FS[0]_FS[2] in Table 1 will correspond to a specific code to distinguish the defect state), and the code will correspond to the memory area. The defect state of block 211-213 (DT4). Finally, the three sets of redundant blocks 221-223 in the redundant cell array 22 will be based on the code. It is selected to replace the memory blocks 211-213 in the regular cell array 21. The process of selecting the redundant blocks 221-223 will be detailed below. If enabled in Figure 7(b) When the fuse signal EN is set to a high logic level and the logic states of the bit values a[2]-A[4] are respectively the same as the three sets of fuse state signals FA[2]_FA[4], then the seventh (8) The redundancy enable signal RED in the figure is a high logic level. The memory block 211 has a logical address of "2" and a bit value of A[0]=0 and A[l]=l. (c) The second encoding circuit 263c having the redundancy selection §fL number RY[2] output, the output of the NOR (reverse OR) gate NOR4 will be due to the first signal f[3] (see Tables 1 and 9 ( a) Figure) becomes a low logic level for the high logic level relationship, and the output of the inverter IN14 is a high logic level, which makes the signal RED=1 (high logic level), A[1] =1 (high logic level) and A[0]N=1 (high logic level). According to this, the redundancy selection signal RY[2] will become a high logic level, therefore, the redundant block 221 will be The redundancy selection signal RY[2] is selected to replace the memory block 211. The memory block 212 has Logic address of "0" and bit value of A[0] = 0 and A[1] = 0. Second coding circuit 263c with output of redundant selection signal RY[0], NOR (reverse OR) gate NOR2 The output will be low logic level due to the high signal level relationship of the first signal F[3] (see Table 1 and Figure 9(a)), and the output of the inverter IN10 is a high logic level. It will also make the signal RED=1 (high logic level), A[1]N=1 (high logic level) and A[0]N=1 (high logic level). Accordingly, the redundancy selection signal ry[〇] becomes a high logic level. Therefore, the redundant block 222 is selected by the redundancy selection signal RY[〇] to replace the memory block 212. The memory block 213 has a logical address of "1" and a bit value of A[0] = 1 and A[l] = 。. The second encoding circuit 263c having the redundancy selection signal RY[〇] output, the output of the NOR (reverse) gate NOR3 is high logic due to the first signal F[3] (see Table 1 and Figure 9(a)). The level and the output of the inverter IN12 are in a high logic level and become a low logic level, which makes the signal RED=1 (high logic level), a[1]N=1 (high logic level) And A[0]=1 (high logic level). Accordingly, the 'redundant selection signal RYR' will become a high logic level. Therefore, the redundant block 223 is selected by the redundancy selection signal RY[i] to replace the memory block 213. However, the memory block 214 has a logical address of "3" and a bit value of A[0] = 1 and A[l] = 1. The second encoding circuit 263c 'NOR (reverse OR) gate NOR5 with redundant selection signal Ry[3] output will be triggered by the first signal F[l], F[4], F[5] (see Table 1). It is a high logic level with the relationship of the low logic level in Fig. 9(8)), and the output of the inverter IN16 is a low logic level. According to this, the 'redundant selection signal RY[3] will become the low logic level and the redundant block 224 will not be replaced by the redundant selection signal RY[3] to replace the DT6 in the memory block table 1 (memory area) The operation of blocks 211-214 being replaced) will be detailed below. First, four sets of logical addresses (2, 0, 1, 3) of the memory block 211_214 are provided in the regular cell array. The logical address (i.e., 2) of the memory block 211 provides A[0]=逻辑 and 位[ι]=1 bit value 'The logical address of memory block 212 (ie 〇) will provide bit values of A[0]=0 and A[1]=0, memory block The logical address of 213 (ie 1) will provide the bit value of A[0]=1 and A[1]=0, and the logical address of memory block 214 (ie 3) will provide A[0]= 1 and the bit value of A[l]=l. Next, three sets of additional fuse signals FS[0]_FS[2] are generated by the three sets of fuse indicating circuits 262' in FIG. 8; among them, three sets of additional fuse signals FS[0], FS[ 1] and FS[2] are 1 (high level), 〇 (low level), and ι (high level). Furthermore, a code is generated based on the three sets of additional fuse signals FS[0]-FS[2], and the code corresponds to the defect state (DT6) of the memory blocks 211-214. Finally, the three sets of redundant blocks 221-224 in the redundant cell array 22 are selected according to the code to replace the memory blocks 211-214 in the regular cell array 21. The process of selecting redundant blocks 221-223 will be detailed below. If the enable fuse signal EN in Figure 7(b) is set to a high logic level and the logic state of the bit value a[2]-A[4] is respectively associated with three sets of fuse state signals FA[2 When -FA[4] is the same, then the redundancy enable signal RED in Figure 7(a) is a high logic level. The memory block 211 has a logical address of "2" and a bit value of A[0] = 0 and A[l] = 1. Referring to the second encoding circuit 263c having the output of the redundancy selection signal RY[2] in the figure 9(c), the output of the NOR gate 1342567 N〇R4 will be due to the first signal F[5] (see Table 1). It is a low logic level with the relationship of the high logic level with the 9th (8) diagram and the inverter! The output of Ν14 is a high logic level, which makes the signal RED=1 (high logic level), Α[1]=1 (high logic level), and Α[0]Ν=1 (high logic level). . Accordingly, the redundancy selection signal RY[2] becomes a logic level, and therefore, the redundancy block 221 is selected by the redundancy selection signal RY[2] to replace the memory block 2U. The memory block 212 has a logical address of "0" and a bit value of A[0] = 0 and A[1] = 0. Refer to Section 9(c) • The second encoding circuit 263c with the redundant selection signal RY[〇] output, the output of the NOR (reverse) gate N0R2 will be referred to Table 1 and Figure 9(8) because of the first signal F wind. It becomes a low logic level for a high logic level relationship, and the inverter has a high logic level with an output of 1 ,, which makes the signal (high logic level), A[1]N=1 (high) Logic level) and AtojNi (high logic level). Accordingly, the 'redundant selection signal RY[0] becomes a high logic level. Therefore, the redundant block 222 is selected by the redundancy selection signal RY[0] to replace the memory block 212. The memory block 213 has a logical address of Τ' and a bit value of A[〇]=1 and 八(1)屻. Referring to the figure 9c (c), the output of the second code_circuit 263c 'N0R (reverse OR) gate N0R3 with the redundancy selection signal ^[^ output will be due to the first signal F[5] (see Tables 1 and 9). (a) Figure) becomes a low logic level for a high logic level relationship, and the output of the inverter IN12 is a high logic level, which makes the signal j^£d=1 (high logic level), A[1]N=1 (high logic level) and A[〇]=1 (high logic level). Accordingly, the 'redundant selection signal RY[1] becomes a high logic level, and therefore, the redundant block 223 is selected by the redundancy selection signal RYp] to replace the memory block 213. Memory block 214 has a logical address of "3" and a bit value of Α[〇]=ι and . Referring to the 18th 1342567 second encoding circuit 263c with the redundancy selection signal RY[3] output in the figure 9(c), the rounding of the NOR (reverse OR) gate N〇R5 will be due to the first F[5] (see table). 1 and 9(8)) are low logic levels for the relationship of high logic level, and the output of inverter IN16 is high logic level, which will make RED=1 (high logic level), A(1) ( High logic level) and Α[〇ϋ logic level). Accordingly, the redundancy selection signal RY[3] becomes a high logic level, and therefore, the redundancy block 224 is selected by the redundancy selection signal RY[3] to replace the memory block 214. For the other examples in Table 1, the calculations are very similar to the above operations of DT4 and DT6, and therefore will not be repeated. According to Table 1 and Figure 5(b), there are two adjacent defective memory blocks (such as DT1-DT3) and three adjacent defective memory blocks (such as DT4-DT5) or 4 in the memory block. When adjacent to the defective memory block (e.g., DT6), it can be replaced by the row redundancy selecting circuit 26 having a small number of fuses in the first embodiment of the present invention. Referring to Figure 7(a), if EQ, EQ2, and EQ3 must be used, redundancy will use a different A[2:4] to repair the multiple bit lines. Therefore, only 7 sets of fuses will be used (4 sets of fuses in Figure 7(b) and 3 • group of wires in Figure 8), but the '244 patent (see Figure 6A and Figure 6B) requires 9 sets of fuses. According to this invention, the six defect states in the repairing table 1 will be very elastic. The row redundancy selecting circuit 26' in Fig. 6 is a second embodiment of the present invention, which can be applied to the semiconductor memory device 2' in Fig. 5(c). The redundancy repair enable circuit 261' includes 261 including a redundancy enable circuit 261a' (see FIG. 10), a uniform fuse circuit 261b' (see FIG. 7(b)), and three sets of fuse state circuits. 261c, (see Figure 7(c)). Redundancy enabling circuit 261a, receiving enable 1342567
炼絲訊號ΕΝ、3組熔絲狀態訊號FA[2]-FA[4]、附加熔絲訊號 FS[3]以及記憶體區塊中邏輯位址(如第6圖中之ADD1)的3個 位元A[2]-A[4]。與第7(a)類似的，當位元A[2]等於炼絲狀態訊 號A[2]、位元a[3]等於熔絲狀態訊號A[3]且位元A[4]等於熔 絲狀態訊號A[4]時，邏輯閘EQ6、EQ8與EQ9均會輸出為邏 輯1的訊號。然而，對照第7(a)圖，儘管EQ6閘的輸出為邏輯 0時’加到NA15閘一輸入之FS[3]會啟動NA15閘（第6圖中並 • 未顯示附加熔絲訊號FS[3]的產生過程）。若致能熔絲訊號EN 亦同時被啟動’冗餘致能訊號RED則因此被產生出來。控制、熔 絲電路262’包含有如第8圖所示之4組熔絲指示電路262”，用 以產生4組附加熔絲訊號FS[0]-FS[3]。冗餘解碼電路263,包含 6組第一編碼電路263a’(如第9(a)圖所示）、4組第四編碼電路 263e(如第12圖所示)以及4組第五編碼電路263f-263i(如第第 13(3)-13(^圖所示)。該6組第一編碼電路263a，係根據3組附加 熔絲訊號FS[0]-FS[2]以及由第11圖中反相器電路263b，產生的 3組反相附加熔絲訊號FS[0]N-FS[2]N來產生6組第一訊號 參 F[0]-F[5]。該4組第四編碼電路263e係根據記憶體區塊邏輯位 址的二位元A[0]、A[l]來產生第二訊號β[η]Ν。該第五編碼電 路263f-263i係根據6組第一訊號F[0]-F[5]以及4組第二訊號 B[0]N-B[3]N來產生冗餘選擇訊號RY[〇]-RY[3] 〇該冗餘解碼電 路263’更包含一第八編碼電路263d’(參閱第9(d)圖）’用以根據 冗餘選擇訊號RY[〇]-RY[3]來產生行失能訊號DISY。此外，冗 餘解碼電路263’更包含7個反相器IN21-IN27，用以將4組附 加熔絲訊號F[0]-F[3]以及記憶體區塊(參閱第η圖)邏輯位址的 (S > 20 1342567 位元值A[0]-A[2]反相。 下方之表2揭示記憶體區塊之16種缺陷狀態DTI 1-DT26 以及其對應之附加熔絲訊號FS[0]-FS[3](本發明第二實施例中 行選擇電路26’之操作過程）。參閱第5(c)圖以及表2，以DT11 的例子來說’鄰接記憶體區塊215’、216’(即表2中被框起來的 部份’其邏輯位址分別為2與0，其實際位址係分別為BL[4] 與BL[5])會被其對應之冗餘區塊221’、222,所取代。以DT16 的例子來說，鄰接記憶體區塊215’-218’會被取代；以DT23的 例子來說’二組分隔的鄰接記憶體區塊211’、212,與215,、216, 會被取代；以DT24的例子來說，二組分隔的鄰接記憶體區塊 213’、214’與217’、218’會被取代；以DT25的例子來說，二組 分隔的鄰接記憶體區塊211’、212’與217’、218,會被取代；以 DT26的例子來說，四組鄰接記憶體區塊213’-216,(橫跨A[2]=l 與A[2]=0之二記憶體區域)會被取代。行FS[n]係代表第一訊號 F[0]-F[5] ’其各顯示為向邏輯位準，且係經由第9⑻圖中6組 第一編碼電路263a的附加熔絲訊號FS[0]_FS[2]來產生。 • _ A2 實際位址A[2:0J 缺陷 A[2]=l A[2]=0 附加熔絲訊號 F[n 狀態 A[l]=l A[0]=0 A[l]=〇 A[0]=0 A[1]=0 A[0]=1 A[l]=l A[0]=1 A[1H A[0]=0 A[l]=〇 A[0]=0 A[1]=0 A[0]=1 A[l]=l A[〇H FS[3] FS[2； FS[1] FS[0； DT11 6 4 5 7 2 0 1 3 0 0 0 0 F[0: DT1： 6 4 5 7 2 0 1 3 0 0 0 1 F[l：3 wires of the refining signal ΕΝ, 3 sets of fuse state signals FA[2]-FA[4], additional fuse signals FS[3], and logical addresses in the memory block (such as ADD1 in Fig. 6) Bit A[2]-A[4]. Similar to the seventh (a), when the bit A[2] is equal to the wire state signal A[2], the bit a[3] is equal to the fuse state signal A[3] and the bit A[4] is equal to the fuse When the wire status signal A[4], the logic gates EQ6, EQ8 and EQ9 will output a signal of logic 1. However, in contrast to Figure 7(a), although the output of the EQ6 gate is logic 0, the FS[3] applied to the NA15 gate-input will activate the NA15 gate (in Figure 6 and • the additional fuse signal FS is not shown). 3] the process of production). If the enable fuse signal EN is also activated, the redundant enable signal RED is generated. The control, fuse circuit 262' includes four sets of fuse indicating circuits 262" as shown in Fig. 8 for generating four sets of additional fuse signals FS[0]-FS[3]. The redundant decoding circuit 263 includes 6 sets of first encoding circuits 263a' (as shown in Fig. 9(a)), 4 sets of fourth encoding circuits 263e (as shown in Fig. 12), and 4 sets of fifth encoding circuits 263f-263i (such as the 13th) (3)-13 (shown in the figure). The six sets of first encoding circuits 263a are based on three sets of additional fuse signals FS[0]-FS[2] and by the inverter circuit 263b in FIG. The three sets of inverted additional fuse signals FS[0]N-FS[2]N are generated to generate six sets of first signal parameters F[0]-F[5]. The four sets of fourth encoding circuits 263e are based on memory. The second bit A[0], A[l] of the body block logical address generates a second signal β[η]Ν. The fifth encoding circuit 263f-263i is based on 6 sets of first signals F[0]- F[5] and 4 sets of second signals B[0]NB[3]N are used to generate redundant selection signals RY[〇]-RY[3]. The redundant decoding circuit 263' further includes an eighth encoding circuit 263d. '(Refer to Figure 9(d))' is used to generate the line disabling signal DISY according to the redundancy selection signal RY[〇]-RY[3]. In addition, the redundant decoding power 263' further includes 7 inverters IN21-IN27 for adding 4 sets of additional fuse signals F[0]-F[3] and memory blocks (see the nth figure) logical address (S > 20 1342567 Bit value A[0]-A[2] is inverted. Table 2 below reveals 16 defect states of memory block DTI 1-DT26 and their corresponding additional fuse signals FS[0]-FS[ 3] (Operation procedure of row selection circuit 26' in the second embodiment of the present invention.) Referring to FIG. 5(c) and Table 2, in the example of DT11, 'adjacent memory blocks 215', 216' (ie, table) The framed part of 2 'its logical addresses are 2 and 0, respectively, and the actual address is the redundant blocks 221', 222 to which BL[4] and BL[5] are respectively associated. Substituted. In the case of DT16, contiguous memory blocks 215'-218' will be replaced; in the case of DT23, 'two sets of contiguous memory blocks 211', 212, and 215, 216 , will be replaced; in the case of DT24, two sets of separated adjacent memory blocks 213', 214' and 217', 218' will be replaced; in the case of DT25, two sets of separated adjacent memory Blocks 211', 212' and 217', 218, will be replaced; in the case of DT26, four sets of contiguous memory blocks 213'-216, (across the A[2]=l and A[2]=0 two memory regions) will be replaced . The row FS[n] represents the first signal F[0]-F[5]', each of which is shown as a logical level, and is via the additional fuse signal FS of the six sets of first encoding circuits 263a in the 9th (8) diagram [ 0]_FS[2] to generate. • _ A2 Actual address A[2:0J Defect A[2]=l A[2]=0 Additional fuse signal F[n State A[l]=l A[0]=0 A[l]=〇 A[0]=0 A[1]=0 A[0]=1 A[l]=l A[0]=1 A[1H A[0]=0 A[l]=〇A[0]= 0 A[1]=0 A[0]=1 A[l]=l A[〇H FS[3] FS[2; FS[1] FS[0; DT11 6 4 5 7 2 0 1 3 0 0 0 0 F[0: DT1: 6 4 5 7 2 0 1 3 0 0 0 1 F[l:
21 1342567 DT13 6 4 5 7 2 0 1 3 0 0 1 0 Ff2 DTl^ 6 4 5 7 2 0 1 3 0 0 l 1 F[3 DTlf 6 4 5 7 2 〇 1 3 0 1 0 0 F[4 DTli 6 4 5 7 2 0 1 ! 3 0 1 0 1 F[5 DTI/ 6 4 5 7 2 0 1 3 0 0 0 0 F[0 DTli 6 4 5 7 2 0 1 3 0 0 0 1 F[1 DT1S 6 4 5 7 2 0 1 3 0 0 1 0 F[2 DT2C 6 4 5 7 2 0 1 3 0 0 1 1 F[3 DT21 6 1 4 5 7 2 0 1 3 0 1 0 0 F[4 ΌΤ2： 6 4 5 7 2 0 1 3 0 1 0 1 Ff5 DT22 6 4 5 7 2 0 1 3 1 0 〇 π F[0: — 1 u DT2^ 6 4 5 7 2 0 1 3 1 0 0 1 F[l. DT2i 6 4 5 7 2 0 1 3 1 0 1 0 F[2 DT2i 6 4 5 7 2 0 1 3 0 1 1 F[3: 本發明第二實施例中的冗餘位元線修復之選擇方法，係於 A[2]為低邏輯位準時修復DT11-DT16的缺陷狀態以及於A[2] 為高邏輯位準時修復DT17-DT22的缺陷狀態。因此，熔絲狀態 號FA[2]就需要決定是要根據低邏輯位準或高邏輯位準的 A[2]來進行修復(參閱第10圖)。本發明之第二實施例可於FS[3] 為高邏輯位準時修復DT23-DT26的缺陷狀態，此外，DT23的 狀態 RY[2]、RY[〇]、rY⑴以及 RY[3]係被派定為(6,4,2,〇)，DT24 的狀態會被派定為(5,7，1，3)，0丁25的狀態會被派定為(6,4，1，3)， (S ) 22 1342567 DT26的狀態會被派定為(5,72,〇)，而對〇丁23_〇丁26來說，其對 應之各狀態RY[2]、RY[〇]、RY⑴以及RY[3]係對應到表2中 徑起來之邏輯位址。本發明第二實施例中的冗餘位元線修復之 選擇方法，將於下方伴隨著第5(c)圖、第7(a)-7(c)圖、第8圖、 第9(a)圖、第10-12圖、第π⑻-13(d)圖以及表2中的DT16 加以詳加描述’即記憶體區塊215V218’會被取代。首先，於正 規晶胞陣列21’中提供記憶體區塊215，-218,的4組邏輯位址(2, 〇，1，3)，記憶體區塊215’之邏輯位址(即2)會提供A[0]=0、 A[l]=l與A[2]=0的位元值，記憶體區塊216’之邏輯位址(即〇) 會提供A[0]=0、A[l]=〇與A[2]=0的位元值，記憶體區塊217, 之邏輯位址(即1)會提供A[0]=：l、A[1]=0與A[2]=0的位元值， 記憶體區塊218’之邏輯位址(即3)會提供A[0]=1、A[1]=1與 A[2]=0的位元值。其中，a[0]-A[2]係為任一記憶體區塊中邏輯 位址的至少3個位元。其次’ 4組附加熔絲訊號FS[0]-FS[3]係 藉由第8圖中的4組熔絲指示電路262”所產生；其中，4組附 加熔絲訊號FS[0]、FS[1]、FS[2]以及FS[3]係分別為1(高位準）、 〇(低位準）、1(高位準)以及〇(低位準）。再者，根據4組附加熔 絲訊號FS[0]-FS[3]以及記憶體區塊211，-218,邏輯位址的位元 A[2]產生一代碼(明顯的，表2中4組附加熔絲訊號FS[0]-FS[3] 與位元A[2]的組合會對應到一特定的代碼來區分缺陷狀態），且 該代碼會對應到記憶體區塊21Γ-218’的缺陷狀態(DT16)。最 後’冗餘晶胞陣列22’中的4組冗餘區塊22Γ-224,會根據該代 碼被選擇出來，用以取代正規晶胞陣列21’中的記憶體區塊 215’-218’。此選擇冗餘區塊22Γ-224’的過程將於下詳述。若第 (S ) 1342567 7(b)圖中的致能熔絲訊號EN被設定為高邏輯位準、邏輯閘 EQ6(參閱第1〇圖)之輸出為高邏輯位準且位元值α[2]·α⑷的邏 輯狀態又分別與3組熔絲狀態訊號FaP]-FA[4]相同時，則第 10圖中的冗餘致能訊號RED為高邏輯位準。記憶體區塊215’ 具有”2”之邏輯位址以及a[〇]=〇、a[1]=1與A[0]=0的位元值。 參閱第五編碼電路263h ’ NOR(反或)閘NOR25之輸出會因為 第一訊號F[5](參閱表2與第9⑻圖)為高邏輯位準、反相器IN34 φ 之輸出係為高邏輯位準與FS[3]=0的關係而成為低邏輯位準， 更會令反相器IN35之輸出為低邏輯位準、第二訊號b[2]N為 低邏輯位準(參閱第12圖）以及NOR(反或)閘NOR27之輸出為 高邏輯位準。據此’冗餘選擇訊號RY[2]會成為高邏輯位準。 記憶體區塊216’具有，，〇，，之邏輯位址以及a[0]=〇、A[1]=〇與 A[1]=0的位元值。參閱第五編碼電路263f，NOR(反或)閘NOR9 之輸出會因為第一訊號F[5](參閱表2與第9(a)圖)為高邏輯位 準、反相器IN28之輸出為低邏輯位準與FS[3]=0的關係而成為 低邏輯位準，更會令反相器IN29之輸出為低邏輯位準、第二 # 訊號B[0]N為低邏輯位準(參閱第I2圖）以及NOR(反或)閑 NOR11之輸出為高邏輯位準。據此，冗餘選擇訊號Ry[〇]會成 為高邏輯位準。記憶體區塊217’具有”1”之邏輯位址以及 A[0]=卜A[1]=0與A[l]=〇的位元值。參閱第五編碼電路263g， NOR(反或)閘NOR17之輸出會因為第一訊號ρ[5](參閱表2與 第9(a)圖)為高邏輯位準、反相器拊31之輸出為低邏輯位準^ FS[3]=0的關係而成為低邏輯位準，更會令反相器取32之輸出 為低邏輯位準、第一訊號B[1]N為低邏輯位準(參閱第12圓） 24 1342567 以及NOR(反或)閘N〇R19之輸出為高邏輯位準。據此，冗餘 選擇訊號RY[1]會成為高邏輯位準。記憶體區塊218，具有，，3，，之 邏輯位址以及A[〇]=l、A[l]=l與A[1]=0的位元值。參閱第五 編碼電路263i ’NOR(反或)閘NOR33之輸出會因為第一訊號 F[5](參閱表2與第9(a)圖)為高邏輯位準、反相器Π\[37之輸出 為低邏輯位準與FS[3]=0的關係而成為低邏輯位準，更會令反 相器IN38之輸出為低邏輯位準、第二訊號b[3；]n為低邏輯位 準(參閱第12圖)以及NOR(反或)閘NOR35之輸出為高邏輯位 準。據此’冗餘選擇訊號RY[3]會成為高邏輯位準《故冗餘選 擇訊號RY[0]-RY[3]會藉由DT16之缺陷狀態對應之代碼而被 觸發至兩邏輯位準’而該代碼係根據4組附加溶絲訊號 FS[0]-FS[3]與位元a[2]來產生。因此，冗餘區塊22Γ-224'會被 選出來取代記憶體區塊215，-218、DTll-DT15m3DT17-DT22 的操作狀態均與DT16的非常類似’故不再贅述。 表2中DT24取代記憶體區塊213’-214,與217，-218,的操 作實施例將於下詳述之。首先，於正規晶胞陣列21，中提供記 憶體區塊213’-214,與217’-218,的4組邏輯位址(5, 7, 1，3)，記 憶體區塊213’之邏輯位址(即5)會提供A[0]=、A[1]=0與A[2]=l 的位元值’記憶體區塊214’之邏輯位址(即7)會提供A[0]=1、 ΑΠΗ與A[2]=l的位元值，記憶體區塊217’之邏輯位址(即1) 會提供A[0]=1、A[1]=0與A[2]=0的位元值，記憶體區塊218’ 之邏輯位址(即3)會提供A[0]=卜A[l]=l與A[2]=0的位元值。 其次，4組附加熔絲訊號FS[0]-FS[3]係藉由第8圖中的4組熔 絲指示電路262”所產生；其中，4組附加熔絲訊號FS[0]、 25 1342567 FS[1]、FS[2]以及FS[3]係分別為1(高位準）、〇(低位準）、〇(低位 準)以及丨(高位準）。再者，根據4組附加熔絲訊號fs[0]-FS[3] 以及記憶體區塊213，-214’與217，-218,邏輯位址的位元A[2]產 生一代碼(明顯的，表2中4組附加熔絲訊號FS[0]-FS[3]的組合 會對應到一特定的代石馬來區分缺陷狀態），且該代碼會對應到記 憶體區塊213’-214,與217，-218,的缺陷狀態(DT24)。最後，冗餘 晶胞陣列22’中的4組冗餘區塊221’-224,會根據該代碼被選擇 φ 出來’用以取代正規晶胞陣列21’中的記憶體區塊213，-214,與 217’-218’。此選擇冗餘區塊221，_224’的過程將於下詳述。若第 7(b)圖中的致能炼絲訊號εν被設定為高邏輯位準、邏輯閘 N0R8 (參閱第1〇圖)之輸出為低邏輯位準(當FS[3]為高邏輯位 準)且位元值A[3]-A[4]的邏輯狀態又分別與3組熔絲狀態訊號 FA[2]-FA[4]相同時，則第1〇圖中的冗餘致能訊號j^d為高邏 輯位準。記憶體區塊213,具有”5”之邏輯位址以及a[0]=1、 A[1]=0與A[2]=l的位元值。參閱第五編碼電路263h，NOR(反 或)閘NOR31之輸出會因為訊號FS[3]N、A[2]N、B⑴N以及 • NOR(反或)閘NOR30之輸出為低邏位準的關係而成為高邏輯 位準，更會令冗餘選擇訊號RY[2]會成為高邏輯位準。記憶體 區塊214’具有”7”之邏輯位址以及a[〇]=i、a[1]=1與A[2]=l的 位元值。參閱第五編碼電路263f，NOR(反或)閘NOR15之輸出 會因為訊號FS[3]N、A[2]N、B[3]N以及NOR(反或)閘NOR14 之輸出為低邏位準的關係而成為高邏輯位準，更會令冗餘選擇 訊號RY[0]會成為高邏輯位準。記憶體區塊217’具有”1”之邏輯 位址以及Α[0]=1、A[l]=〇與A[2]=〇的位元值。參閱第五編碼 26 1342567 電路263g，NOR(反或)閘NOR23之輸出會因為訊號FS[3]N、 A[2]N、B[3]N以及NOR(反或)閘NOR22之輸出為低邏位準的 關係而成為高邏輯位準’更會令冗餘選擇訊號會成為高 邏輯位準。記憶體區塊218’具有”3”之邏輯位址以及a[〇]=1、 A[l]=l與A[2]=0的位元值。參閱第五編碼電路263i，NOR(反 或)閘NOR39之輸出會因為訊號FS[3]N、A[2]、B[3]N以及 NOR(反或)閘NOR38之輸出為低邏位準的關係而成為高邏輯 位準，更會令冗餘選擇訊號RY[3]會成為高邏輯位準。故冗餘 選擇訊號RY[〇]-RY[3]會藉由DT24之缺陷狀態對應之代碼而 被觸發至尚邏輯位準，而該代碼係根據4組附加炼絲訊號 FS[0]-FS[3]與位元A[2]來產生。因此，冗餘區塊221，·224，會被 選出來取代記憶體區塊213’-214’與217，-218,。DT23、DT25與 DT26的操作狀態均與DT24的非常類似，故不再贅述。 根據表2以及第5(c)圖，具有二鄰接缺陷記憶體區塊(如 DT11-DT13、DT17-DT19)、三鄰接缺陷記憶體區塊（如 DT14-DT15、DT20-DT21)、四鄰接缺陷記憶體區塊(如DT16、 DT22與DT26)或將四缺陷記憶體區塊全部分成二群組(或二鄰 接缺陷記憶體區塊加上另二鄰接缺陷記憶體區塊)(如T23_T25) 的3己憶體區塊可藉由本發明第二實施例中具有少量炼絲的行冗 餘選擇電路26’所取代。因此’僅有8組熔絲會被使用到（第7(b) 圖中的1組熔絲、第7(c)圖中的3組熔絲以及第8圖中的4組 熔絲）’較’244號專利需要用到9組熔絲少很多。此外，本發明 可以執行彈性化的位元線冗餘修復，即藉由本發明，要被取代 (修復)之記憶體區塊的排列方式可以有多種的類型，包含位元 27 1342567 值A[2] 1與a[2]=〇的二鄰接記憶體區塊、三鄰接記憶體區塊、 四鄰接記憶體區塊以及分成二群組之四記憶體區塊。甚者，本 發明亦可被應用於字元線冗餘修復，只要將第5(b)圖以及5(c) 圖中的記憶體區塊與冗餘區塊修分別改為包含2條字元線與2 條冗餘字元❹卩可。儘管本發明實施例贿各記㈣區塊與冗 餘區塊中具有2條字元線或位元線’但亦可為2條以上，其係 根據記憶體裝置之應用而定。 、’' 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 =發月任何熟習此技藝者，在不脫離本發明之精神和範圍内， 當^作些許之更動與潤飾，因此本發明之保護範圍當視後附之 申請專利範圍所界定者為準。 【圖式簡單說明】 圖，為&知具有儿餘修復半導體記憶體裝置之電路方塊圖。 圖係為第1圖中正規晶胞陣列與冗餘晶胞陣列之電路圖。 圖係為第1圖中缺陷晶胞區塊行冗餘選擇電路之電路圖。 =4(a)嶋為第3圖中缺陷晶胞區塊之行冗餘選擇電路的電路 方塊圖。 圖係為第3圖巾鄰接晶舰塊之行冗餘選擇電路的 方塊圖。 n)圖鱗本發明轉敎憶體裝置執行冗餘元線修復之 功能方塊圖。 =b)圖係為第5⑻圖中半導體記憶體裝置之另—實施例圖。 圖係為第5(a)圖中半導體記憶體裝置之又—實施例圖。 28 1342567 第6圖係為本發明第一實施例與第二實施例之行冗餘選擇電路 的電路方塊圖。 第7(a)圖係為本發明冗餘致能電路之實施例圖。 第7(b)圖係為本發明致能熔絲電路之實施例圖。 第7(c)圖係為本發明熔絲狀態電路之實施例圖。 第8圖係為本發明熔絲指示電路之實施例圖。 第9(a)圖係為本發明6組第一編碼電路之實施例圖。 • 第9(b)圖係為本發明反相器電路之實施例圖。 第9(c)圖係為本發明4組第二編碼電路之實施例圖。 第9(d)圖係為本發明第三編瑪電路之實施例圖。 第10圖係為本發明另一冗餘致能電路之實施例圖。 第11圖係為本發明另一反相器電路之實施例圖。 第12圖係為本發明4組第四編碼電路之實施例圖。 第13(a)-13(d)圖係為本發明4組第五編碼電路之實施例圖。 【主要元件符號說明】 • 1半導體記憶體裝置 11正規晶胞陣列 110-112晶胞區塊 12几餘晶胞陣列 120-121冗餘區塊 13晶胞汲極選擇電路 14行解碼器電路 15缺陷晶胞區塊行冗餘選擇電路 29 1342567 ’ 150-152可程式化熔絲電路 153-154位址選擇電路 155位址解碼電路 156-157可程式化熔絲電路 16鄰接晶胞區塊行冗餘選擇電路 160-165鄰接位址產生電路 166-171位址選擇電路 | 172-173位址解碼電路 2半導體記憶體裝置 2’半導體記憶體裝置 21正規晶胞陣列 21’正規晶胞陣列 211-214記憶體區塊 21Γ-218’‘記憶體區塊 22冗餘晶胞陣列 22’冗餘晶胞陣列 • 221_224冗餘區塊 221’-224’冗餘區塊 23頁緩衝器陣列 24冗餘頁緩衝器陣列 25行解碼器電路 26行冗餘選擇電路 261冗餘修復致能電路 261’冗餘修復致能電路 < S > 30 1342567 261a冗餘致能電路 261a’冗餘致能電路 261b熔絲致能電路 261b’熔絲致能電路 261c熔絲狀態電路 261c’熔絲狀態電路 262控制熔絲電路 262’控制熔絲電路 262”熔絲指示電路 263冗餘解碼電路 263’冗餘解碼電路 263a-263i編碼電路 263a’編碼電路 263b’反相器電路 3121 1342567 DT13 6 4 5 7 2 0 1 3 0 0 1 0 Ff2 DTl^ 6 4 5 7 2 0 1 3 0 0 l 1 F[3 DTlf 6 4 5 7 2 〇1 3 0 1 0 0 F[4 DTli 6 4 5 7 2 0 1 ! 3 0 1 0 1 F[5 DTI/ 6 4 5 7 2 0 1 3 0 0 0 0 F[0 DTli 6 4 5 7 2 0 1 3 0 0 0 1 F[1 DT1S 6 4 5 7 2 0 1 3 0 0 1 0 F[2 DT2C 6 4 5 7 2 0 1 3 0 0 1 1 F[3 DT21 6 1 4 5 7 2 0 1 3 0 1 0 0 F[4 ΌΤ2: 6 4 5 7 2 0 1 3 0 1 0 1 Ff5 DT22 6 4 5 7 2 0 1 3 1 0 〇π F[0: — 1 u DT2^ 6 4 5 7 2 0 1 3 1 0 0 1 F[l DT2i 6 4 5 7 2 0 1 3 1 0 1 0 F[2 DT2i 6 4 5 7 2 0 1 3 0 1 1 F[3: Selection method of redundant bit line repair in the second embodiment of the present invention , fixes the defect state of DT11-DT16 when A[2] is low logic level and repairs the defect state of DT17-DT22 when A[2] is high logic level. Therefore, the fuse status number FA[2] needs to be determined to be repaired according to the low logic level or the high logic level A[2] (see Figure 10). The second embodiment of the present invention can repair the defect state of DT23-DT26 when FS[3] is a high logic level. In addition, the states RY[2], RY[〇], rY(1), and RY[3] of DT23 are sent. When set to (6, 4, 2, 〇), the state of DT24 will be assigned as (5, 7, 1, 3), and the state of 0 butyl 25 will be assigned as (6, 4, 1, 3). (S) 22 1342567 The state of DT26 will be assigned as (5,72,〇), and for Kenting 23_〇丁26, the corresponding states RY[2], RY[〇], RY(1) and RY[3] corresponds to the logical address in Table 2. The method for selecting redundant bit line repair in the second embodiment of the present invention will be accompanied by the fifth (c), seventh (a)-7 (c), eighth, and ninth (a) Fig. 10-12, π(8)-13(d), and DT16 in Table 2 are described in detail, that is, the memory block 215V218' will be replaced. First, four sets of logical addresses (2, 〇, 1, 3) of the memory blocks 215, -218 are provided in the regular cell array 21', and the logical addresses of the memory block 215' (ie 2) A bit value of A[0]=0, A[l]=l and A[2]=0 will be provided, and the logical address (ie, 〇) of the memory block 216' will provide A[0]=0, A[l]=〇 and A[2]=0 bit values, memory block 217, the logical address (ie 1) will provide A[0]=:l, A[1]=0 and A [2] bit value of =0, the logical address of memory block 218' (ie 3) will provide bit values of A[0]=1, A[1]=1 and A[2]=0. . Where a[0]-A[2] is at least 3 bits of a logical address in any memory block. Next, 'four sets of additional fuse signals FS[0]-FS[3] are generated by the four sets of fuse indicating circuits 262" in Fig. 8; among them, four sets of additional fuse signals FS[0], FS [1], FS[2], and FS[3] are 1 (high level), 〇 (low level), 1 (high level), and 〇 (low level), respectively, according to 4 sets of additional fuse signals. FS[0]-FS[3] and memory blocks 211, -218, bit A[2] of the logical address generate a code (obviously, 4 sets of additional fuse signals FS[0] in Table 2 - The combination of FS[3] and bit A[2] will correspond to a specific code to distinguish the defect state), and the code will correspond to the defect state of memory block 21Γ-218' (DT16). The four sets of redundant blocks 22Γ-224 in the remaining cell array 22' are selected according to the code to replace the memory blocks 215'-218' in the regular cell array 21'. The process of the remaining block 22Γ-224' will be detailed below. If the enable fuse signal EN in the figure (S) 1342567 7(b) is set to a high logic level, logic gate EQ6 (see section 1) The output of the graph is a high logic level and the logic state of the bit value α[2]·α(4) When the three sets of fuse state signals FaP]-FA[4] are respectively the same, the redundancy enable signal RED in the figure 10 is a high logic level. The memory block 215' has a logic bit of "2". The address and the bit value of a[〇]=〇, a[1]=1 and A[0]=0. Refer to the fifth encoding circuit 263h 'NOR (reverse OR) gate NOR25 output will be due to the first signal F[ 5] (Refer to Table 2 and Figure 9(8)) for high logic level, the output of inverter IN34 φ is high logic level and FS[3]=0, which becomes low logic level, which will make the opposite The output of the phaser IN35 is a low logic level, the second signal b[2]N is a low logic level (see Figure 12), and the output of the NOR (reverse OR gate) NOR27 is a high logic level. The remaining selection signal RY[2] will become a high logic level. The memory block 216' has a logical address of ,,,,, and a[0]=〇, A[1]=〇 and A[1]= The bit value of 0. Referring to the fifth encoding circuit 263f, the output of the NOR (negative) gate NOR9 is due to the first signal F[5] (see Table 2 and Figure 9(a)) as a high logic level, The output of the phase converter IN28 is a low logic level and a relationship of FS[3]=0, which becomes a low logic level. The output of the phaser IN29 is a low logic level, the second #signal B[0]N is a low logic level (see Figure I2), and the output of the NOR (reverse or idle) NOR11 is a high logic level. The redundancy selection signal Ry[〇] will become a high logic level. The memory block 217' has a logical address of "1" and A[0]=Bu A[1]=0 and A[l]=〇 Bit value. Referring to the fifth encoding circuit 263g, the output of the NOR (reverse) gate NOR17 is due to the first signal ρ[5] (refer to Table 2 and Figure 9(a)) for the high logic level and the output of the inverter 拊31. It becomes a low logic level for the relationship of the low logic level ^ FS[3] = 0, and the output of the inverter is 32 is the low logic level, and the first signal B[1]N is the low logic level. (Refer to the 12th circle) 24 1342567 and the output of the NOR (reverse) gate N〇R19 is a high logic level. Accordingly, the redundancy selection signal RY[1] becomes a high logic level. The memory block 218 has a logical address of , 3, , and a bit value of A[〇]=l, A[l]=l and A[1]=0. Refer to the fifth encoding circuit 263i 'NOR (reverse OR) gate NOR33 output will be high logic level due to the first signal F[5] (see Table 2 and Figure 9(a)), inverter Π\[37 The output is low logic level and FS[3]=0, and becomes a low logic level, which makes the output of inverter IN38 low logic level and second signal b[3;]n low logic. The level (see Figure 12) and the output of the NOR (NOR35) NOR35 are high logic levels. According to this, the 'redundant selection signal RY[3] will become a high logic level. Therefore, the redundancy selection signal RY[0]-RY[3] will be triggered to the two logic levels by the code corresponding to the defect state of DT16. 'The code is generated based on 4 sets of additional melt signal FS[0]-FS[3] and bit a[2]. Therefore, the redundant blocks 22Γ-224' will be selected to replace the memory block 215, and the operation states of -218, DT11-DT15m3DT17-DT22 are very similar to those of DT16, and therefore will not be described again. The operational examples of DT24 in place of memory blocks 213'-214, and 217, -218, in Table 2, will be described in more detail below. First, in the regular cell array 21, the memory blocks 213'-214, and the 217'-218, the four logical addresses (5, 7, 1, 3), the logic of the memory block 213' are provided. The address (ie 5) will provide the bit value of A[0]=, A[1]=0 and A[2]=l. The logical address of the memory block 214' (ie 7) will provide A[ 0]=1, ΑΠΗ and A[2]=l bit values, the logical address of memory block 217' (ie 1) will provide A[0]=1, A[1]=0 and A[ The bit value of 2] = 0, the logical address of memory block 218' (ie 3) will provide the bit value of A[0]=Bu A[l]=l and A[2]=0. Next, four sets of additional fuse signals FS[0]-FS[3] are generated by the four sets of fuse indicating circuits 262" in FIG. 8; wherein, four sets of additional fuse signals FS[0], 25 1342567 FS[1], FS[2], and FS[3] are 1 (high level), 〇 (low level), 〇 (low level), and 丨 (high level), respectively. The silk signal fs[0]-FS[3] and the memory blocks 213, -214' and 217, -218, the bit A[2] of the logical address generate a code (obviously, 4 groups of Table 2 are attached) The combination of fuse signals FS[0]-FS[3] will correspond to a particular generation of horses to distinguish the defect state), and the code will correspond to memory blocks 213'-214, and 217,-218, The defect state (DT24). Finally, the four sets of redundant blocks 221'-224 in the redundant cell array 22' are selected according to the code φ out to replace the memory in the regular cell array 21' Body blocks 213, -214, and 217'-218'. The process of selecting redundant blocks 221, _224' will be described in detail below. If the enable wire signal εν in Figure 7(b) is set For high logic level, the output of logic gate N0R8 (see Figure 1) is low logic When (when FS[3] is a high logic level) and the logic state of the bit value A[3]-A[4] is again the same as the three sets of fuse state signals FA[2]-FA[4], Then, the redundancy enable signal j^d in the first diagram is a high logic level. The memory block 213 has a logical address of "5" and a[0]=1, A[1]=0 and The bit value of A[2] = 1. Referring to the fifth encoding circuit 263h, the output of the NOR gate NOR31 will be due to the signals FS[3]N, A[2]N, B(1)N, and • NOR (reverse). The output of the gate NOR30 is a low logic level and becomes a high logic level, which makes the redundancy selection signal RY[2] a high logic level. The memory block 214' has a logical address of "7". And the bit values of a[〇]=i, a[1]=1, and A[2]=l. Referring to the fifth encoding circuit 263f, the output of the NOR (reverse OR) gate NOR15 is due to the signal FS[3]N The output of A[2]N, B[3]N, and NOR(N) is a low logic level and becomes a high logic level, which makes the redundant selection signal RY[0] high. Logic level. Memory block 217' has a logical address of "1" and a bit value of Α[0]=1, A[l]=〇 and A[2]=〇. See fifth code 26 1342567Circuit 263g, the output of NOR gate NOR23 will be due to the low logic level relationship of the outputs of signals FS[3]N, A[2]N, B[3]N, and NOR (reverse) gate NOR22. Being a high logic level will make the redundant selection signal a high logic level. The memory block 218' has a logical address of "3" and a bit value of a[〇]=1, A[l]=l and A[2]=0. Referring to the fifth encoding circuit 263i, the output of the NOR gate NOR39 is due to the low logic level of the outputs of the signals FS[3]N, A[2], B[3]N, and NOR (reverse) gate NOR38. The relationship becomes a high logic level, and the redundant selection signal RY[3] will become a high logic level. Therefore, the redundancy selection signal RY[〇]-RY[3] is triggered to the logic level by the code corresponding to the defect status of DT24, and the code is based on 4 sets of additional refining signals FS[0]-FS. [3] is generated with bit A[2]. Therefore, redundant blocks 221, .224 will be selected to replace memory blocks 213'-214' and 217, -218. The operating states of DT23, DT25 and DT26 are very similar to those of DT24, so they will not be described again. According to Table 2 and Figure 5(c), there are two adjacent defective memory blocks (such as DT11-DT13, DT17-DT19), three adjacent defective memory blocks (such as DT14-DT15, DT20-DT21), and four adjacent Defect memory blocks (such as DT16, DT22, and DT26) or divide the four defective memory blocks into two groups (or two adjacent defective memory blocks plus two adjacent defective memory blocks) (such as T23_T25) The 3 memory block can be replaced by the row redundancy selection circuit 26' having a small amount of wire in the second embodiment of the present invention. Therefore, 'only 8 sets of fuses will be used (1 set of fuses in Figure 7(b), 3 sets of fuses in Figure 7(c) and 4 sets of fuses in Figure 8)' Less than the 9 sets of fuses required for the '244 patent. In addition, the present invention can perform elasticized bit line redundancy repair, that is, by the present invention, the memory blocks to be replaced (repaired) can be arranged in various types including bit 27 1342567 value A[2 1 and a[2]=〇 two adjacent memory blocks, three adjacent memory blocks, four adjacent memory blocks, and four memory blocks divided into two groups. Moreover, the present invention can also be applied to word line redundancy repair, as long as the memory block and the redundant block in the 5th (b) and 5(c) diagrams are respectively changed to include 2 words. The meta line and 2 redundant characters are available. Although the embodiment of the present invention has two word lines or bit lines ' in the block (4) block and the redundant block, it may be two or more, depending on the application of the memory device. The present invention has been disclosed in the above preferred embodiments. However, it is not intended to limit the skill of the invention, and it is intended to be a matter of modification and refinement without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple description of the drawing] The figure is a block diagram of the circuit of the semiconductor memory device. The figure is a circuit diagram of the regular cell array and the redundant cell array in Fig. 1. The figure is a circuit diagram of the redundant cell selection circuit of the defective cell block row in FIG. = 4 (a) 电路 is a circuit block diagram of the row redundancy selection circuit of the defective cell block in Fig. 3. The figure is a block diagram of the row redundancy selection circuit of the third wafer adjacent to the crystal block. n) Figure Scale The functional block diagram of the redundant meta-line repair performed by the present invention. =b) The figure is a further embodiment of the semiconductor memory device of Figure 5(8). The figure is a further embodiment of the semiconductor memory device in Fig. 5(a). 28 1342567 Fig. 6 is a circuit block diagram showing a row redundancy selecting circuit of the first embodiment and the second embodiment of the present invention. Figure 7(a) is a diagram showing an embodiment of the redundancy enabling circuit of the present invention. Figure 7(b) is a diagram showing an embodiment of the enabling fuse circuit of the present invention. Figure 7(c) is a diagram showing an embodiment of the fuse state circuit of the present invention. Figure 8 is a diagram showing an embodiment of the fuse indicating circuit of the present invention. Figure 9(a) is a diagram showing an embodiment of the six sets of first encoding circuits of the present invention. • Figure 9(b) is a diagram of an embodiment of an inverter circuit of the present invention. Figure 9(c) is a diagram showing an embodiment of four sets of second encoding circuits of the present invention. Figure 9(d) is a diagram showing an embodiment of the third circuit of the present invention. Figure 10 is a diagram showing an embodiment of another redundancy enabling circuit of the present invention. Figure 11 is a diagram showing an embodiment of another inverter circuit of the present invention. Figure 12 is a diagram showing an embodiment of four sets of fourth encoding circuits of the present invention. Figures 13(a)-13(d) are diagrams showing an embodiment of the fourth group of fifth encoding circuits of the present invention. [Main component symbol description] • 1 semiconductor memory device 11 normal cell array 110-112 cell block 12 several cell arrays 120-121 redundant block 13 cell drain selection circuit 14 row decoder circuit 15 Defective cell block row redundancy selection circuit 29 1342567 '150-152 programmable fuse circuit 153-154 address selection circuit 155 address decoding circuit 156-157 programmable fuse circuit 16 adjacent cell block row Redundant selection circuit 160-165 adjacent address generation circuit 166-171 address selection circuit | 172-173 address decoding circuit 2 semiconductor memory device 2' semiconductor memory device 21 regular cell array 21' regular cell array 211 -214 memory block 21Γ-218''memory block 22 redundant cell array 22' redundant cell array•221_224 redundant block 221'-224' redundant block 23 page buffer array 24 redundant Remaining page buffer array 25 row decoder circuit 26 row redundancy selection circuit 261 redundancy repair enabling circuit 261 'redundancy repair enabling circuit < S > 30 1342567 261a redundancy enabling circuit 261a 'redundant enabling Circuit 261b fuse enable circuit 261b' fuse Circuit 261c fuse state circuit 261c' fuse state circuit 262 control fuse circuit 262' control fuse circuit 262" fuse indication circuit 263 redundant decoding circuit 263' redundant decoding circuit 263a-263i encoding circuit 263a' encoding circuit 263b 'Inverter circuit 31