TWI239626B - Structure of electrostatic discharge suppressor and method of stacking package with semiconductor devices - Google Patents

Abstract

The present invention relates to an overlap cascaded package structure of a semiconductor device and a static over-voltage and surge protection circuit. The semiconductor device chip such as a light emitted diode (LED) or an integrated circuit (IC) is overlap cascaded package on a static over-voltage and surge protection circuit. The front side of the static over-voltage protection chip is equipped with two isolated metal layer electrodes. The trenches also cut the semiconductor device into two devices with opposite polarity devices in cascaded. The trenches also act as scribed lines to scribe the wafer into chips. The semiconductor device chip is overlap cascaded die bond on the static over-voltage protection chip.

Description

1239626 V. Description of the invention (1) 1. Technical field to which the invention belongs The present invention relates to a wafer structure of an electrostatic surge protection circuit and a packaging method for stacking the same with a semiconductor device, particularly a semiconductor device such as a light emitting diode, Chips such as integrated circuits are stacked on the packaging structure of the circuit chip with electrostatic surge protection to save space and packaging engineering, and improve the reliability and effectiveness of the protection circuit. 2. In the prior art, the general semiconductor devices such as light-emitting diodes, integrated circuits, etc. have limited resistance to damage, and are easily damaged by electrostatic surges. Especially, light-emitting diodes are used for signal signals, displays, etc., and are easily voltage Factors such as instability, lightning strikes, power outages, etc., make the power source the culprit in the destruction of light-emitting diodes and shorten their life. If it is partially damaged, repair is quite difficult, affecting service quality. If traffic signs give wrong instructions, safety will be affected. Therefore, how to protect the female components of semiconductor devices from being damaged by electrostatic surges is the goal pursued by the industry. Traditionally, the protection of electrostatic surges can use many types of protection circuits, such as monopoles, Zener diodes, and Mos transistors. Figure 1 shows a circuit diagram that traditionally uses two serially connected reverse diodes to protect the light emitting diode. The light emitting diode 102 has its own package 108, and the protective diodes of the protection circuit 〇〇04, 丨 〇6 are also packaged in the package 110, and then soldered to the circuit board of the light emitting diode 102 Package 10

Page 5! 239626 ⑵ " '--------- Feng Meng $ = This occupies the position of a package, which is quite inconvenient for miniaturization, and it needs to double the use of different circuits, which is very uneconomical. Although it can also be a star: the protection circuit protects many light-emitting diodes, but the general light-emitting diodes also control the light on and off. It is very difficult to share a protection circuit. Other integrated circuits have different problems with raindrops. It is not possible to share a protection circuit, so to solve the problem, the existence will occupy more space and consume more materials and processes. This is a problem that is in urgent need. Therefore, there is a need for another good method of protecting circuits and packaging of semiconductor devices to make protection more perfect. 3. SUMMARY OF THE INVENTION ^ The object of the present invention is to provide a wafer structure of an electrostatic surge protection circuit and a packaging method for stacking the same with a semiconductor device. The semiconductor device wafer is stacked and packaged on the electrostatic surge protection circuit chip. The semiconductor device and the protection circuit chip are integrated into one, and the electrostatic surge protection circuit design is used to improve the anti-ESD (Electrostatic Discharge) capability of the semiconductor device and reduce packaging space and engineering. Another object of the present invention is to provide a packaging structure in which a semiconductor device and an electrostatic surge protection circuit are stacked, and a negative electrode of a semiconductor device wafer and a positive electrode of one of the components of the protection circuit wafer are bonded by a die bond, so that Save wiring work.

1239626 V. Description of the invention (3) Protection of circuit chip protection, one% 丨 Di seat 丨 丄 ... Zingbing Increases reliability. The control of the material-controlling conductor device is more reliable. In order to achieve the above purpose and improve the general companionship, it is stronger than the lack of semiconductor components & Shiba, Baoman circuit is separately packaged and then installed with electric surge protection circuit. The first viewpoint teaches a structure of static electricity and Baobian Jade Road, which includes at least one heteropolar: reverse bias breakdown voltage, a 1-rich conductor layer, and spreads around the first type semiconductor semiconductor: body ; An insulating layer, formed in the second type of the diode = body; Delamination; • First and second metal wiring pads, forming the first subordinate wiring, with-protruding blocks for polarity discrimination Li; static wire pads are rectangular; multiple grooves are engraved to form If electric protection 4 circuits: In the cutting line of the film, a trench is formed between every two diodes to isolate the two diodes, so that the two diodes share the first type semiconductor layer. A second aspect of the present invention teaches a semiconductor package and an electrostatic surge protection circuit stack packaging structure, and a semiconductor device wafer is stacked and packaged on the electrostatic surge protection circuit by a wafer bonding method, including at least Yang Yijing 5 The surge protection circuit chip is bonded to the lead frame with the chip, and the front side is provided with a first metal wiring pad and a second metal wiring pad which are isolated from each other; a semiconductor package, and the wafer is stacked with a flip chip In the electrostatic protection circuit, the positive metal wiring pad is directly connected to the first metal wiring pad of the electrostatic surge protection circuit chip, and the second metal wiring pad of the electrostatic surge protection circuit is insulated by an insulating layer, and the negative electrode is The metal terminal pad is made of metal. Page 7 1239626 V. Description of the invention (4) The wire is connected to the second metal terminal pad of the electrostatic surge protection circuit. The first metal terminal pad of the electrostatic protection circuit chip is connected by a metal wire. To the positive pole of the power supply, connect the second metal wiring pad of the electrostatic protection circuit chip to the negative pole of the power supply; the electrostatic surge protection circuit chip on the lead frame Stacked on the semiconductor device wafer thereon encapsulated within the plastic package. A third aspect of the present invention teaches a stacked packaging structure of a semiconductor device and an electrostatic surge protection circuit 'the semiconductor device wafer is stacked on the electrostatic protection circuit wafer' and the metal wiring of the electrostatic surge protection circuit is to Insulation layer insulation 'The metal wiring of the positive pole is connected to the first metal wiring of the electrostatic surge protection circuit chip by a metal wire, and the gold of the negative electrode ^ The wiring pad is also connected to the electrostatic surge protection circuit by a metal wire. Second metal wiring pad. 4. Embodiment The content of the present invention can be disclosed through the following embodiments in conjunction with the related drawings. Referring to FIG. 2, FIG. 2 is a schematic diagram of a semiconductor device chip and a protection circuit chip package according to an embodiment of the present invention. The semiconductor device is, for example, a light emitting diode 丨 02, and the diodes 104 and 106 in reverse series with the protection circuit are packaged in the same protection circuit and light emitting diode package 112, and the diode 10 is The positive pole of the light-emitting diode 102 is connected to the positive pole of the light-emitting diode 102 and the positive pole of the diode 100 is connected to the negative pole of the light-emitting diode -02. The two pins are externally connected to a power source or a signal source.

Page 1239626 V. Explanation of the invention (5) Figure 3 is a protection circuit according to the present invention (in this example, the plan view of the semiconductor device; Figure 3) is a structural diagram of the edge. Figure 3 U Is a sectional view of the line. As shown in Figure 3 (a), the-° plane K 'Figure 3 (c) is the edge BB on the lion, Shi Xiji discusses ii :; the production pole system is determined by Shi Xiji voltage, then, the substrate push: = == Circuit Safety (1)

VB = £ sEm2 / 2qNB where es is the permittivity of the semiconductor: electric field, q is the charge of the electron, and Nb is the doping concentration of the Shi Xi wafer. It can be seen that the doping concentration of NB is low, The collapse voltage is high; conversely, the higher the heart, the lower the collapse voltage. For example, the circuit to be protected can withstand a maximum voltage of 6 volts, and the breakdown voltage should be 8 volts. The doping concentration Nβ should be 2x 101 / 'atom / cm3. For example, the maximum withstand voltage of the protection circuit is 70 volts and the doping concentration. NB should be 1 (Pat 0m / cm3. If it is a MOS transistor, design the threshold voltage between them and set its oxide layer. After determining the doping concentration of the silicon substrate 3 0 3, Then, a PN junction is formed thereon by diffusion or ion implantation of the P-type doped layer 310, and then an oxide layer 306 and an aluminum metal layer 308 are formed by lithography, and then an isolation trench is formed by lithography etching. 4. The plan view of Fig. 3 (a) shows the arrangement of a single double zener diode after cutting. The isolation trench 3 0 4 is used to isolate two transistors. The aluminum metal layer is 1239626. 5. Description of the invention (6) 308 and 309 are used to connect a protected semiconductor device such as a light emitting diode, and the aluminum metal layer 308 is used to connect the positive electrode of a power source and the positive electrode of the protected semiconductor device, and is electrically connected to one of the anode diodes (p-type) Layer). Aluminum metal sound 309 is directly connected to the negative electrode of the protected semiconductor device, and then A wire is connected to the negative electrode of the power supply. The protruding aluminum metal layer 314 is used to identify or connect to other circuits. The oxide layer 306 is used to trap the crystals on the cutting path of the groove 3 () 4 (due to cutting And) is not subject to strong electric field leakage. Figure 4 shows the structure of a semiconductor device according to an embodiment of the present invention. Figure 4 (a) is a plan view, and Figure 4s | (b) is a cross-sectional view. As shown in Fig. * A, the semiconductor device 400 is, for example, a light emitting diode, a wafer connection and a positive electrode connection of a diode. The anode gold electrode pad 410 is used for connection, and the sapphire (A12 n The area occupied by η-money removal should be small, and should be at the corner 隅 or: ϊ 窨: = usually about 100 " mx 100_, the semiconductor device Lm) substrate 408, n-type worm crystal layer 402 and p-type The crystal layer structure, the conductive layer 406 is used for die bond, and the Λ pole of Λ is connected to the semiconductor device 4GG. In addition—the insulation of the insulation layer wire pad braided insulation of the positive electrode and the second metal connection of the protection circuit chip ^ Figure 5 and Figure 6, Figure 5 is an example of the semiconductor dream UJ n 〇 矗 里 w team One Zhiyue I Erling Ling sun and sun film 400 is packaged on the protection circuit chip 302 "~ Figure, Figure 6 is a cross-sectional view showing the dd line of Figure 5. 1239626 V. Description of the invention (7) It can be seen from FIG. 5 that the semiconductor device wafer 400 is bonded to the second metal wiring pad 308 and the first metal wiring pad 309 of the protection circuit wafer 302 by flip chip bonding. Refer to No. 6 In the figure, the positive metal electrode 4 0 of the semiconductor device wafer 400 is directly connected to the first metal wiring pad 30 g of the protection circuit diode 3 on the left side of the protection circuit wafer 3 0 2, but the protection circuit on the right side is conductive. The second metal wiring pad is insulated by the insulating layer 41 2 under the positive metal electrode 4 06 of the semiconductor device wafer, so it is not conductive, so that the negative metal wiring pad 41 of the semiconductor device 400 is wired 502 by a metal wire and the protection circuit on the right Diode second metal wiring pad 3 8 connection and conduction, and then connected to the negative electrode of the power supply by the metal wire wire 504. Therefore, the negative electrode of the power supply is connected to the negative metal wire pad 41 of the semiconductor device 400 through the wire 504 and the second metal wiring pad 308 and wire 502 It then connects to the positive metal electrode 406 through the pn junction of the semiconductor device, and the first metal wiring pad 309 and wire 506 are connected to the positive pole of the power supply. The other path is connected to the protection circuit via the second metal wiring pad 308. The positive electrode of the right diode (refer to Figure 2 and Figure 6) is connected to the positive electrode of the power supply through the np interface and the pn interface to the first metal wiring pad 30 9 of the left diode. The chip 400 is stacked on the protection circuit chip 302, and the positive electrode of the semiconductor device is directly connected to the protection circuit without additional wiring. Only the negative electrode needs to be wired to the negative electrode of the power supply, which not only reduces the complicated work of wiring and separate packaging, and Dispersion can also be quickly dissipated through the first type semiconductor 302 of the circuit chip, and the reliability and durability of the device 400. Fig. 7 is a structure of a semiconductor device 700 according to an embodiment of the present invention.

1239626 Description of the invention (8) Drawing. Fig. 7 (a) is a plan view, and Fig. 7 (b) is a sectional view taken along line £ -E of Fig. 7 (&). The semiconductor device wafer 700 is epitaxially p-type semiconductor epitaxial layer 704 and N-type semiconductor epitaxial layer 706 on a GaAs substrate 702, and then a transparent conductive layer 708 is deposited and a negative wiring pad is formed by lithography. For the purpose of connection, the area occupied should be small, it should be at one corner or one side, and its area is usually about 100 // mx 100 / zm. The GaAs substrate 702 has a positive metal electrode 714 on it for die bonding. The positive electrode of the power source is connected to the positive electrode of the semiconductor device 700, and an insulating layer 712 is provided to insulate the positive electrode of the semiconductor device from the second metal wiring pad 308 of the protection circuit chip. Such a semiconductor device is, for example, a yellow light emitting diode, a red light emitting diode, or the like. FIG. 8 is a schematic plan view showing a semiconductor device wafer 700 stacked and packaged on a protection circuit wafer 302 according to an embodiment of the present invention. Fig. 9 is a sectional view taken along line f-ρ of Fig. 8; This embodiment is epitaxial due to the semiconductor system. The red conductive material is used, so there is no need to invert the chip, and the chip is sealed. Simply place the substrate 70 2 on the protective circuit and send it out from the transparent conductive layer. Others are the same as those in the embodiments of FIG. 5 and FIG.

It is said that although the above embodiments are based on the light emitting diode semiconductor devices 400 and 7 (and the evening moon), but other semiconductor devices such as integrated circuits, So (# ί = 片 u 封 敦) can use the present invention; And the protection circuit is not necessarily used for "up" and can also be used for signal circuits.

.1239626 V. Description of the invention (9) Pu ------- Detailed description of the specific embodiment of the early and better by h fish office yf TU Gu 2, you describe it, the characteristics and spirit of this creation, not the above ^ 2 is more specific and specific examples to limit the scope of the present invention. On the contrary ^ better hope = can cover all kinds of changes and arrangements with equality ς 2: Yes within the scope of patents. Months ~ months to apply for 1239626

5 · _ simple explanation: Figure 1 shows the traditional use of a galvanic protection of light-emitting diodes: electrical circuit-:. The product of serial and reverse connection. Figure 2 is a schematic diagram of a selective circuit chip package according to the present invention + a conductor device chip and protection r electric: d, one of the embodiments is used to package a semiconductor device protection circuit (in this example) It is a structural diagram of the audit diode. Figure 4. The figure shows the structure of a semiconductor device according to an embodiment of the present invention. = 5 The figure shows a schematic plan view of a semiconductor device according to the present invention—a semiconductor device wafer right and sealed / mounted on a protection circuit wafer 302. Fig. 6 is a sectional view taken along line c-c of Fig. 5; FIG. 7 is a structural diagram of a semiconductor device 700 according to an embodiment of the present invention. FIG. 8 is a schematic plan view showing a semiconductor device wafer 70C stacked and packaged on a protection circuit wafer 302 according to an embodiment of the present invention. . FIG. 9 is a cross-sectional view showing the EE line in FIG. 8. Explanation of symbols: 102 light emitting diode 104 accumulator diode 1 06 accumulator diode 1 0 8 package

1239626

Brief description of drawings on page 15 Package 110 Package 302 Chip 303 Silicon substrate 304 Trench 306 Oxide layer 308 Metal layer 309 Metal layer 310 Doped layer 312 Oxide layer 314 Metal layer 400 Semiconductor device 402 n-type substrate 404 Diffusion layer 406 Metal Layer 408 sapphire (Α 12 03) substrate 410 terminal pad 412 oxide layer 502 wire 5 04, 50 6 wire 700 device 702 G a A s substrate 704 P-type semiconductor epitaxial layer 706 N-type semiconductor epitaxial layer 708 transparent conductive layer 710 Terminal pad 712 Insulating layer 714 Positive metal electrode

Claims (1)

1239626 VI. Scope of patent application 1. A kind of static electricity-reverse bias of a first type semipolar body-a second type semi-diode; an insulation layer, the structure of the surge protection circuit, at least: the conductor substrate 'selection Its doping concentration makes the formed two breakdown voltages suitable for the required value; the conductor layer is diffused on the first type semiconductor and is shaped as two window protruding blocks of the first and the edge layer of the isolation layer; The diode common pole pads are formed at a moment every two, two and two are formed around the second type semiconductor of the diode as a metal wiring pad, formed on the second type semiconductor body: pole! No. 1 negative terminal pad, the first-metal wiring identification and wiring, the second metal terminal pad: fine: into the static protection circuit chip cutting track, " 1 'chip slot, used to isolate two diodes To make the first type semiconductor layer. The structure of the item, wherein the etched trench also protects the structure of item 1 of the 12-pole range, wherein the electrostatic surge protection β-man circuit is a diode connected in series with opposite polarity. Yingdian No. 4 Road Application: The structure of Lilienwei Item 1, in which the electrostatic surge protection circuit is a series diode with opposite polarity. 1 · As the scope of patent application No. 1 2 Local oxide layer (LOCOS) is available. 1239626 6. Scope of patent application Failure 5. For the structure of item 3 of the scope of patent application, in which the breakdown voltage of one electrode body of the electrostatic protection call is determined by the doping concentration of the silicon substrate. 6. The structure of item 4 in the scope of patent application, wherein the breakdown voltage of the electrostatic protection diode is determined by the doping concentration of the silicon substrate. 7, ·· Semiconductor device and electrostatic surge protection circuit are stacked and packaged = f The semiconductor device wafer is stacked and packaged on the electrostatic large wave protection circuit by wafer bonding method, including at least: electrostatic surge protection circuit wafer Bonded to the lead frame, the front side is provided with a first metal wiring pad and a second metal wiring pad that are isolated from each other; a semiconductor device wafer, which is flip chip stacked on the 2 electrical protection circuit wafer, and a positive electrode The metal wiring pad is directly connected to the first metal wiring pad of the static and surge protection circuit chip, and the second metal wiring pad of the electrostatic surge protection circuit is insulated by an insulating layer, and the negative metal wiring pad is wired with a metal wire. The connection pads connected to the electrostatic surge protection circuit are: π — Meng Zhilei: ΐ Ϊ Ϊ Connect the first-metal connection pad of the electrostatic protection circuit chip to the positive pole of the power supply, and connect the electrostatic protection circuit chip to the negative pole of the power supply; The genus wiring pads are connected, and the electrostatic surge protection circuit chip and the Nie semiconductor device chip on the lead frame are packaged in a plastic package. And; Shang Pei's 8 · —Semiconductor device and electrostatic surge protection circuit are superimposed and sealed. Page 17 1239626 6. Method of applying for a patent, the front surface of an electrostatic surge protection circuit on a semiconductor-mounted surge protection circuit is isolated from each other. On the first gold-one semiconductor device, the second line of the metal circuit chip of the static positive electrode is connected to the positive metal to the positive of the power source to the negative of the power source. The conductive semiconductor is mounted on a wafer containing a chip to connect it. The second chip circuit crystal electrical surge line placed on the metal wire and the negative electrode will be static, and the pole; the wafer wafer pad and the electrostatic protection wiring pad on the wire rack to the metal-connected wafer, at least Cover the circuit wafer, stack the electrical surge protection circuit connection pads with metal wire-to-metal connection pads, protect the circuit electrical protection, electrostatic static protection, electrostatic surge protection, encapsulated in a plastic package, bonding method, superimposed and packaged on static electricity, and lead frame. Two metal wiring pads protect the circuit chip with an insulation layer, and the electrostatic surge protects the wire pads with metal wires. The second sheet metal of the metal terminal pads connected to the wiring circuit chip and interconnect pads stacked thereon. For example, if the method of the 7th or 8th in the scope of patent application, the static protection circuit is two in series and the polarity is opposite-the polar body is 10. · If the 7th scope of the patent application is inferior, it is ^ ^ Φ ^ ^ Gudi's method of 8 items, in which the electrostatic rush / pico compliance circuit is a series connection and the pole M q is changed to change the opposite diode. 1 1 · For the method of item q g t_ π 舻 > & t \ in the scope of the patent application, wherein the voltage of the _ pole of the electrostatic protection tower is determined by the doping concentration of the y i plate. Page 18 1239626 Page 19