1237441 14563twf.doc/m 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種運算放大器，且特別是有關於一 種具頻率補償電路之運算放大器。 【先前技術】 請參照圖1，圖1係繪示習知一種具頻率補償電路之 運异放大斋電路圖。此習知一種具頻率補償電路之運算放 大器100包含：第一級增益電路10卜第二級增益電路=〇、 第一差動對120、第二差動對15〇、第一電流源13〇、第二 電流源140以及電容160與no。 其中，第一級增益電路101更包括第一電晶體1〇2、 第二電晶體103、第三電晶體104、第四電晶體1〇5、第五 電晶體106以及第六電晶體1〇7。第二級增益電路ιι〇更 包括第一電晶體112與第二電晶體U1。第一差動對12〇 更包括電晶體開關121與122，第二差動對15〇更包括電 晶體開關151與152。 第一級增盈電路101係電性耦接於第一差動對， ^將第-絲對m的絲輸岐A，並作為第二級差動 、子150的差動輸人源。第—電流源13G係電性編妾於第一 =對UG，以驅動第-差動對12G，第二、級增益電路11〇 罢Γί耗接於第二絲對15G，以放大第二差動對150的 產動輸出。 1237組 twf.doc/m 動對120的第一輸出端，另一端係 々、， 15〇的第-輸出端，電容160的禺妾於第二差動對 動對120的第二輸出端，另一端係電性耦接於第-差 二輸出端_作為系於第二差動對 晴參考圖3與圖4，圖3係繪+羽々θ 之運管不白知具頻率補償電路 償電路之谨管妓丰^ 口 4係繪不習知具頻率補 號分析電之分析電路圖，並根據此小訊 刀析桃可料出其躲方程4 (如下所示） -^1 ~ 一 1 j ^ζ/\^ 、卜 a. —個主極點（pole) • I^JL Cc 存在於複數頻率平面（s_d〇main)的左半 平面，所以此主極點是穩定的。 ^ -^.(0 + 02) + ^.(^2-02)-^2-^5 求出其胜从4曰:^ /，-T- " _、 ' 卩 4 gm 5 . cc *(C1 -f C2)) V m2 C22 J + 1 V C2 ) 而從特性方程式中的分子部分（如下所示）1237441 14563twf.doc / m IX. Description of the invention: [Technical field to which the invention belongs] The present invention relates to an operational amplifier, and in particular to an operational amplifier with a frequency compensation circuit. [Prior Art] Please refer to FIG. 1. FIG. 1 is a circuit diagram of a conventional amplifier circuit with a frequency compensation circuit. The conventional operational amplifier 100 with a frequency compensation circuit includes: a first-stage gain circuit 10b, a second-stage gain circuit = 0, a first differential pair 120, a second differential pair 15o, and a first current source 13o. , The second current source 140 and the capacitors 160 and no. The first-stage gain circuit 101 further includes a first transistor 102, a second transistor 103, a third transistor 104, a fourth transistor 105, a fifth transistor 106, and a sixth transistor 10. 7. The second-stage gain circuit includes a first transistor 112 and a second transistor U1. The first differential pair 120 includes transistor switches 121 and 122, and the second differential pair 150 includes transistors 151 and 152. The first-stage gain-increasing circuit 101 is electrically coupled to the first differential pair, ^ inputs the wire of the -th wire pair m to A, and serves as the differential input source of the second-stage differential and sub 150. The first-current source 13G is electrically compiled in the first pair UG to drive the -differential pair 12G, and the second and the stage gain circuit 11 o is connected to the second wire pair 15G to amplify the second difference The output of the dynamic pair is 150. The 1237 sets of twf.doc / m are the first output end of the moving pair 120, the other end is the first output end of ，, the 15 °, and the capacitor 160 is the second output end of the second differential pair 120, The other end is electrically coupled to the -differential second output. As the second differential pair, refer to Figures 3 and 4. Figure 3 is a drawing + feather θ. The operation tube does not have a frequency compensation circuit compensation circuit. Regarding the prostitute ^^ Mouth 4 is a circuit diagram of the analysis circuit with frequency complement number analysis, and according to this small knife analysis, it can be expected to escape equation 4 (shown below)-^ 1 ~ a 1 j ^ ζ / \ ^, bu a. — a main pole (pole) • I ^ JL Cc exists in the left half plane of the complex frequency plane (s_d〇main), so this main pole is stable. ^-^. (0 + 02) + ^. (^ 2-02)-^ 2- ^ 5 Find the victory from 4: ^ / ， -T- " _, '卩 4 gm 5. Cc * (C1 -f C2)) V m2 C22 J + 1 V C2) and from the molecular part in the characteristic equation (shown below)
乂车亚，根可看出有一個零點（zero)在複數頻率平面的 面的2面，此零點是穩定的。而另一個零點在複數頻率平 的右半平面，此右半平面的零點係為系統中的主零點， 1237输 twf.doc/m 而此糸統的主零 因素。 點是造成放大器在使用上會不 穩定的最大 .所述2級放大器電路在使用時均需要傲m、志 償的動作。而在習知枯併φ、δ#Η “ J而要做頻率補 上電容^在2級放大魏之間加 j_Ail的辭補償，此作法軸 的目的，但是在放大器分析其特徵方程式 會發現系統的主零點是位於複數頻率平面的 點合、’此存在於複數解平_右半平面上的主焚 ^3：成线極度的不敎，崎成系統使用上極度的; 【發明内容】 放士發_目的就是在提供—種具辭補償電路之運算 寬^ ’以提高運算放大H的穩定性，並增加系統的頻帶乂 Cheya, the root can be seen that there is a zero point (zero) on the two faces of the complex frequency plane, this zero point is stable. The other zero point is in the right half plane of the complex frequency plane. The zero point of this right half plane is the main zero point in the system. 1237 loses twf.doc / m and the main zero factor of this system. The point is that the amplifier will be the most unstable in use. The two-stage amplifier circuit needs to be proud of the action when it is used. However, in the conventional case, φ, δ # Η "J and the frequency compensation capacitor is added. ^ Compensation of j_Ail is added between the two levels of amplification. The purpose of this method is to analyze the characteristic equation of the amplifier and the system will be found. The main zero point is located on the complex frequency plane, 'this main existence exists in the complex solution flat_right half plane ^ 3: the line is extremely unsteady, and the Sakisei system uses the upper limit; [Summary of the Invention] Shifa_The purpose is to provide a kind of operation width with a compensation circuit ^ 'to improve the stability of the operational amplifier H, and increase the frequency band of the system
本發明提出一種具頻率補償電路之運算放大器電路。 包έ第一屯流源、第二電流源、第一差動放大對、第二差 動放大對、第-頻率補償模組以及第二頻率補償模組了 、其中，第-差動放大對包括第一差動增益電路與第一 差動輸入對。第-差動增益電路，更包括第—級正增益電 路連接端、第-級負增益電路連接端、第—級正放大訊】 輸出端以及第一級負放大訊號輸出端。 ° A 第一差動輸入對，更包括第一電晶體與第二電晶體。 第一電晶體與第二電晶體之閘極端分別電性耦接至輸入電 壓源的正端與負端’第-電晶體與第二電晶體的源極電性 456jtwf.doc/m 麵接至第—電流源，此外第一電曰 第-級正增益電路連接 I3日_ ==搞接至 至第-級負增益電路連接端。^日體的錄端電性麵接 輸入J包括第二差動增益電路與第二差動 輸出端與第二級I放:；；=;包括第二級正放大訊號 第4====?體與第四電晶體。此 端，第四雷減級正放大訊號輸出 出端。第：端電性搞接至第一級負放大訊號輸 二L二一二與弟四電晶體的源極分別電蝴妾至第 訊號輸出端。一的及極祕祕至第二級負放大 弟-擗猶電路，此第―頻率補償電路由第一電容 ^-電_互串翻成。第―頻率補償電路之一端電性 搞接至第-級正增益電路連接端，另—端電性減於 級正放大訊號輸出端。 第二頻率補償電路，.此第二解補償電路由第二電容 與第二電_互串接*成。第二鮮補償電路之—端電性 耦接至第-級負增益電路連接端’另一端電性耦接於該第 二級負放大訊號輸出端。 利用第-頻率補償模組以及第二頻率補償模組的功 能’可將運算放大器之特性方程式中，原本位於複數頻率 平面中左半平面的主零點，將由位於複數頻率平面中右半 twf.doc/m 平面的零點來取代，成為系 頻率響應的穩定性。 ㈣的主令點’以^放大為 植，因，第:頻率補償模組以及第二頻率補償模 1 翻提高電路的穩定性，並可增加系統的頻 f覓度。 ' 為縣I明之上述和其他目的、特徵和優點能更明顯The invention provides an operational amplifier circuit with a frequency compensation circuit. The first current source, the second current source, the first differential amplification pair, the second differential amplification pair, the first frequency compensation module and the second frequency compensation module are included, among which the first differential amplification pair It includes a first differential gain circuit and a first differential input pair. The first-differential gain circuit further includes a first-stage positive gain circuit connection terminal, a first-stage negative gain circuit connection terminal, and a first-stage positive amplification signal output terminal and a first-stage negative amplification signal output terminal. ° A The first differential input pair further includes a first transistor and a second transistor. The gate terminals of the first transistor and the second transistor are electrically coupled to the positive and negative terminals of the input voltage source, respectively. The source of the first transistor and the second transistor are electrically connected to 456jtwf.doc / m. The first current source, in addition, the first electric stage is connected to the positive gain circuit of the third stage. I == is connected to the connection terminal of the negative gain circuit of the first stage. ^ The recording surface electrical input J of the Japanese body includes a second differential gain circuit, a second differential output terminal, and a second stage I amplifier: ;; =; including the second stage positive amplification signal. 4 ==== The body and the fourth transistor. At this end, the fourth mine degrades the positive amplified signal output. The first terminal is connected to the first-stage negative amplifier signal output, and the source terminals of the two L12 and the fourth transistor are respectively connected to the signal output terminal. The first and the extremely secretive to the second stage of the negative-amplifier circuit, the first-frequency compensation circuit is converted from the first capacitor ^ -electrical_mutual series. One end of the first-frequency compensation circuit is electrically connected to the connection end of the first-stage positive gain circuit, and the other end is electrically reduced to the output end of the positive amplification signal. A second frequency compensation circuit. The second decompensation circuit is formed by a second capacitor and a second electrical circuit in series. The-terminal of the second fresh compensation circuit is electrically coupled to the first-stage negative gain circuit connection terminal 'and the other terminal is electrically coupled to the second-stage negative amplified signal output terminal. By using the functions of the first-frequency compensation module and the second-frequency compensation module, the characteristic zero of the operational amplifier in the characteristic frequency equation of the operational amplifier will be located in the complex frequency plane. / m plane zero instead, it becomes the stability of the frequency response of the system. The main command point of ’is based on ^ amplification, because the first: the frequency compensation module and the second frequency compensation module 1 improve the stability of the circuit and increase the frequency f of the system. '' The above and other purposes, features, and advantages of the county I Ming can be more obvious
易憧，下域舉較佳實_，並配合所_式，作詳細說 明如下。 I 【實施方式】 凊參照圖2，圖2係繪示依照本發明一較佳實施例之 具頻^補償電路之運算放Α||電路圖。此频率補償電％ 之運异放大态電路200包括··第一電流源23〇、第二電後 源240、第一差動放大對28〇、第二差動放大對29〇、第〜 頻率補領電路270以及第二頻率補償電路250。其中，第 一差動放大對280包括第一差動增益電路2〇1與第一差動 輸入對220，第二差動放大對29〇包括第二差動增益電略 210與第二差動輸入對260。 其中’弟一差動增益電路201更包括第一電晶體2〇2、 第二電晶體203、第三電晶體204、第四電晶體205、第五 電晶體206以及第六電晶體207。第一電晶體2〇2的源极 端與弟四電晶體205源極端係分別電性搞接於—偏壓^原Ώ 以驅動整個增益電路，上述第一差動增益電路在 上亦可將第一電晶體202與第四電晶體205去除，僅^用 123m twf.d〇Q/r 二電，、第三電晶體204第五電晶體206以及第 電:體207來運作，其功能亦維持不變。 及第 心 汲極端係電性減於第二電晶體 加的沒繼。第二電晶體 第二電晶體加閘極=二4= 接收柜转輪人對22G的差動放大信號端将 二第，體204的難端= 係為第-正=茲:正放大訊號輸出端，其源極端 206 電晶體2〇5的汲極端係電性_於第五電曰® :的=:電 偏壓源。第 生耦接於弟六電晶體2〇7的汲極 的體MS的閘極端係接收一偏屢源。第六電晶體撕 端^以放大對22〇的第二汲極 極端係㈣差動放大信號’而其間 為第一差動增兴2 ί晶體2〇7的沒極端係 源極端係為第 電曰動放大對220更包括電晶體開關221與222。 曰曰-汗關221的汲極端係電性麵接於第三電晶體 ㈣鳊I日曰脰開關222的源極端與電晶體開關 I237HAtwf.doc/m 221的源極端相互遠垃 、， 輸出端，以接收由電性滅於第一電流源230的 雷曰俨PUn 屯机源230所輸入的驅動電流。 關；=二的:^^^ 輸二：將此放大信號放一 關况的、及；^ 230更包括電晶體開關23卜此電晶體開 關231的汲極端係電性叙接 ^ ^ 供-電流源來驅叙笛丄f弟一絲輪入對220，以提 耦接於祕V動第一輸入對220，其源極端係電性 輕接於接地端，而其閘極端係接收-偏壓源。 S”4^f原240更包括電晶體開關24卜此電晶體開 f 241的沒極端係電性輕接於第二差動輸入對260，以提 共:電流源來鷄第二差動輸人對細，其源極端係電性 耦接於接地端’而其閘極端係接收一偏壓源。 第二差動增益電路21〇更包括第一電晶體211與第二 電晶體212，第-電晶體211與第二電晶體212的源極端 ^別電性祕於-偏壓源，以簡整個增益電路。其中， 第-電晶體211之沒極端係為第二差動增益電路21〇的第 二級正放大訊號輸出端，第二電晶體212之汲極端係為第 —差動增益電路210的第二級負放大訊號輸出端。 其中，第-電晶體211的沒極端係電性搞接於第二差 動輸^ 260的第-沒極端1其閉極端健收一偏壓 源。第二電晶體212的沒極端係電_接於第二差動輸入 11 123 7%l twf.doc/m 筻^60的第一汲極端，此第二差動增益電路係接收由 差動輸入對260所輸出的差動放大信號，上述第二差 益電路210，在設計上亦可如第一差動增益電路201 °樣，用多數個電晶體開關來串接運作，其功能維持不變。 兩曰第二差動輸入對26〇更包括電晶體開關261與％2。 開關261的汲極端係電性雛於第一電晶體2ιι的 挪。端，電晶體開關262的汲極端係電性叙接於第_雨曰 一 的汲極端，而其源極端係相互連接並電性耦接於 〜電流源240的輸出端。 差知此第二差動輸人對26G的—輸人端係電性輕接於第一 =盈電路2〇1的第-級正放大訊號輸出端，另一輸入 號輪ί =接於第—差動料電路2G1的第二級負放大訊 輪:_、而。亚根據兩輸出端的信號差做差動放大輸出，並 】差動放大信號至第二差動增益電路21()的輸入端。 f本實施例中’第一頻率補償電路27〇更包括第一電 二=一電阻272。第一電容Μ之一端係電性輕接 益電路210之第二級正放大訊號輪出端，另 性耦接於第一電阻272的第一端，第—電阻奶 增胁I差動增益電路201之第一級正 阻25!，?率補?電路250更包括第二電容251與第二電 千枚〇弟一電谷251之一端係電性耦接於第二差動妗兴 之第二級負放大訊號輸出端，另—端係電性^ ϋ阻252的第一端，第二電阻攻的另—端係電性 12 »twf.doc/m 耦接於第一級差動增益電路2〇1之第一級負增益電路連接 端。 在本實施例中，請參考下列所示之系統特性方程式。 ---~1^·(f2 ·Q(g+Cg+^^Cc)-gn^nB)Yi Yi, the following examples are more practical, and in accordance with the formula, detailed explanation is as follows. I [Embodiment] 凊 Referring to FIG. 2, FIG. 2 is a circuit diagram of an operational amplifier A || with a frequency ^ compensation circuit according to a preferred embodiment of the present invention. This frequency-compensated electrical amplifier circuit 200 includes a first current source 23, a second electric post-source 240, a first differential amplifier pair 28, a second differential amplifier pair 29, and a frequency of ~ The compensation circuit 270 and the second frequency compensation circuit 250. Among them, the first differential amplifier pair 280 includes a first differential gain circuit 201 and a first differential input pair 220, and the second differential amplifier pair 29 includes a second differential gain circuit 210 and a second differential Enter pair 260. Among them, the first differential gain circuit 201 further includes a first transistor 202, a second transistor 203, a third transistor 204, a fourth transistor 205, a fifth transistor 206, and a sixth transistor 207. The source terminal of the first transistor 202 and the source terminal of the fourth transistor 205 are electrically connected to each other—bias voltage ^ YuanΏ to drive the entire gain circuit. The above-mentioned first differential gain circuit can also connect the first The first transistor 202 and the fourth transistor 205 are removed, and only 123m twf.d0Q / r is used to operate the second transistor, the third transistor 204, the fifth transistor 206, and the first transistor 207 are operated, and their functions are maintained. constant. And the first pin terminal is electrically inferior to that of the second transistor. The second transistor The second transistor plus the gate = two 4 = the receiver of the runner to the 22G differential amplified signal end will be second, the difficulty of the body 204 = is the first-positive = here: positive amplified signal output End, the source terminal of the 206 transistor of the drain terminal of the 205 is electrical _ in the fifth electric ® ®: =: electrical bias source. The gate terminal of the body MS, which is coupled to the drain of the second transistor 207, receives a biased source. The sixth transistor has a torn end ^ to amplify the signal of the second drain extreme pair of 22 °, and differentially amplify the signal 'while the first differential boost 2 is in between. The extreme end source of the crystal 2007 is the second current. The dynamic amplification pair 220 further includes transistor switches 221 and 222. The electrical terminal of the drain terminal of Khan Guan 221 is connected to the third transistor. The source terminal of switch 222 and the source terminal of transistor switch I237HAtwf.doc / m 221 are far from each other. In order to receive the driving current inputted by the Lei Yuepu PUntun machine source 230 which is electrically extinguished by the first current source 230. Off; = two: ^^^ Input two: put this amplified signal off, and ^ 230 further includes a transistor switch 23, and the drain terminal of the transistor switch 231 is electrically connected ^ ^- A current source is used to drive the flute into the pair 220 to increase the coupling to the first input pair 220. Its source terminal is electrically connected to the ground terminal, and its gate terminal is receiving-bias voltage. source. The S ”4 ^ f original 240 further includes a transistor switch 24, and the transistor on f 241 is electrically connected to the second differential input pair 260, so as to provide a total current source to the second differential input. For a human pair, its source terminal is electrically coupled to the ground terminal and its gate terminal receives a bias source. The second differential gain circuit 21 includes a first transistor 211 and a second transistor 212. The source terminals of the transistor 211 and the second transistor 212 are not electrically sensitive to the bias source to simplify the entire gain circuit. Among them, the first terminal of the first transistor 211 is the second differential gain circuit 21. The second-stage positive-amplified signal output terminal of the second transistor 212 is the second-stage negative-amplified signal output terminal of the first-differential gain circuit 210. Among them, the negative terminal of the --transistor 211 is electrically Connected to the second differential input ^ 260 of the second differential input 1 and its closed end to receive a bias source. The negative terminal of the second transistor 212 is connected to the second differential input 11 123 7% l twf .doc / m 的 ^ 60 at the first drain terminal, this second differential gain circuit receives the differential amplified signal output by the differential input pair 260, the above second The differential gain circuit 210 can also be designed in the same manner as the first differential gain circuit 201 °, and can be operated in series with a plurality of transistor switches, and its function remains unchanged. The second differential input pair 26 also includes electrical power. The crystal switch 261 and% 2. The drain terminal of the switch 261 is electrically connected to the first transistor, and the drain terminal of the transistor switch 262 is electrically connected to the drain terminal of the first one, and The source terminals are connected to each other and are electrically coupled to the output terminal of the current source 240. The difference is that this second differential input pair is 26G-the input end is electrically connected to the first = surplus circuit 201. The first-stage positive amplification signal output terminal of the other, the other input signal wheel ί = connected to the second-stage negative amplification signal wheel of the first-differential circuit 2G1: _, and. Asia performs differential amplification according to the signal difference between the two output terminals. Output, and] differentially amplify the signal to the input terminal of the second differential gain circuit 21 (). F In this embodiment, the 'first frequency compensation circuit 27o further includes a first electric resistor = a resistor 272. A first capacitor M One end is the output terminal of the second-stage positive amplification signal wheel of the electric light connection circuit 210, and the other end is coupled to the first resistor 272. At the first end, the first-stage positive resistance 25 of the differential gain circuit 201 of the resistance milk booster I, the rate compensation circuit 250 further includes a second capacitor 251 and a second electric capacitor 251. One end is electrically coupled to the second-stage negative amplified signal output terminal of the second differential amplifier, and the other end is electrical ^ The first end of the resistance 252 and the other end of the second resistance tap are electrical 12 »Twf.doc / m is coupled to the first stage negative gain circuit connection end of the first stage differential gain circuit 201. In this embodiment, please refer to the system characteristic equation shown below. --- ~ 1 ^ · (F2 · Q (g + Cg + ^^ Cc) -gn ^ nB)
汄[Q.CL(a+Q).(1+g必碑[CL(a+Q)+Cra]+〆 Q汄 [Q.CL (a + Q). (1 + g 必 Memorial [CL (a + Q) + Cra] + 〆 Q
Rl'RL 從上述系統特性方程式中分母部分（如下列所示） 可以看出系統的主極點並不會因為加入了第一頻率補償電 路270中的第一電阻272與第二頻率補償電路25〇中的第 一電阻252而有所改變。系統主極點（pole)還是維持在 複數，率平面（s_d〇main)左半平面，使系統維持在穩定 的狀態。 〜 而因為加入了第一頻率補償電路270中的第一電阻 與第二頻率補償電路250中的第二電阻252的關係使 得系統新的非主極點位置（如下列所示） 2 "Cc'CHCUC2HUs^R^^^^ 要比原本的非主極點位置要來得低（如下列所示） ^ s Cc.Cl.(a + C2)+4_ [cL (a + c2) + Q ^ ω例2 挪 c 13 twf.doc/m 二义 <丨時’此第-頻率補償電路270 + =所造二===電路25。中的第二電阻 -分子的部分（如下列所示） 可以看出系統原本:主::(C2二 Z(小 所示)2 5 J=f，面的右半平面，此位於複數:率平二 補償雷路25Π击^貝^路中的第一電阻272與第二頻率 Z(iW c中的第二電阻252來加以修正（如下列所示） =)+5伽2仏⑽㈣㈣·㈣ 讲2.g』關係可成立（如下列所示） g gm59R^Cc> gm2-C2 平面中右半平面的主零點’將由位於 交點、以祖，中半平面的零點來取代，成為系統新的主 々.，、、占，以楗向放大器頻率響應的穩定性。 2所述，本發明因採用第一頻率補償模組與第二頻 吴組中的電容與電阻的功用，因此可以提高電路的 疋性，亚可增加系統的頻帶寬度。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 14 3twf.doc/m 和範圍内，當可作些許之更 【圖式簡單說明】 固斤界疋者為準。 圖1繪示為習知具頰率 + 圖。 ί电路之運算放大器電題 圖2繪示為本發明一較 運算放大器電路圖。 貝& 具頻率補償電路之 圖3係繪示習知具頻率補 半電路圖。 路之運异放大器之差動 圖4係繪示習知具頻率 號分析電路圖。 、自“路之運算放大器之小訊 【主要元件符號說明】 ··習知具頻率補償電 9ΠΠ . θ w ^ 兒格之運异放大器電路圖 300. :/率補償電路之運算放大器電路圖 圖脈資知具頻率補償電路之運算放大器之差動半電路 4〇〇:習知具頻率補償電路 電路圖 之運异放大為之小汛號分析 }〇1、201 :第一差動增益電路 110、210:第二差動增益電路 120 ·第一差動對 220 :第一差動輸入對 130、230 ·•第一電流源 140、240 :第二電流源 250 :第二頻率補償電路 twf.doc/m 150 :第二差動對 260 :第二差動輸入對 270 :第一頻率補償電路 102、 112 :第一電晶體開關 103、 111 :第二電晶體開關 104 :第三電晶體開關 105 :第四電晶體開關 106 :第五電晶體開關 107 :第六電晶體開關 121、122、151、152、131、141 :電晶體開關 160、170 :電容 202、 211 :第一電晶體開關 203、 212 ··第二電晶體開關 204 :第三電晶體開關 205 :第四電晶體開關 206 :第五電晶體開關 207 :第六電晶體開關 221、222、231、241、26卜 262 :電晶體開關 271 ： 第一電容 272 ： 第一電阻 251 ： 第二電容 252 ： 第二電阻 280 ： 第一差動放大對 290 ： 第二差動放大對Rl'RL From the denominator part of the above system characteristic equation (as shown below), it can be seen that the main pole of the system will not be caused by adding the first resistor 272 and the second frequency compensation circuit 25 in the first frequency compensation circuit 270. The first resistor 252 is changed. The main pole of the system is still maintained in a complex number, and the left half plane of the rate plane (s_d0main) keeps the system in a stable state. ~ And because the relationship between the first resistor in the first frequency compensation circuit 270 and the second resistor 252 in the second frequency compensation circuit 250 makes the system a new non-primary pole position (as shown below) 2 " Cc ' CHCUC2HUs ^ R ^^^^ is lower than the original non-primary pole position (as shown below) ^ s Cc.Cl. (a + C2) + 4_ [cL (a + c2) + Q ^ ω Example 2 Move c 13 twf.doc / m ambiguous < the first-frequency compensation circuit 270 + = made two === circuit 25. The second resistance-molecule part in (as shown below) can see the original of the system: main :: (C2 two Z (small shown) 2 5 J = f, the right half plane of the face, this is located in the complex number: rate The flat second compensation mine circuit 25II strikes the first resistor 272 and the second frequency Z (the second resistor 252 in iW c to correct it) as shown in the following figure. =) + 5Ga2 仏 ⑽㈣㈣ · ㈣ Talk 2.g ”relationship can be established (as shown below) g gm59R ^ Cc> gm2-C2 The main zero point of the right half plane in the plane will be replaced by the zero point of the ancestral and mid-half planes at the intersection point, and become a new system Mainly, the stability of the frequency response of the amplifier in the direction of 楗. As mentioned above, the present invention uses the functions of the capacitor and resistor in the first frequency compensation module and the second frequency Wu group, so the circuit can be improved. It can increase the bandwidth of the system. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit the present invention. Anyone skilled in this art will not depart from the spirit of the present invention. 14 3twf.doc / m Within the range, you can make a little bit more. [Simplified illustration of the diagram] The person who fixes the weight in the field shall prevail. 1 is shown as a conventional figure with a buccal rate. Figure 2 is a circuit diagram of an operational amplifier of the present invention. Figure 2 is a circuit diagram of a relatively operational amplifier of the present invention. Figure 3 with a frequency compensation circuit is shown with a frequency compensation circuit. Half-circuit diagram. The differential circuit of the differential amplifier of the road 4 is a circuit diagram of the frequency analysis of the conventional known amplifier. "From the small news of the operational amplifier of the road [Description of the main component symbols] ·· The frequency compensation circuit of the conventional learned amplifier 9ΠΠ. θ w ^ Ergonomic amplifier circuit diagram 300 .: / rate compensation circuit op amp circuit diagram pulse differential amplifier circuit with frequency compensation circuit 4 00: custom circuit with frequency compensation circuit Analysis of the small flood numbers of different amplifications. 〇1, 201: First differential gain circuit 110, 210: Second differential gain circuit 120 · First differential pair 220: First differential input pair 130, 230 · • First current sources 140, 240: second current source 250: second frequency compensation circuit twf.doc / m 150: second differential pair 260: second differential input pair 270: first frequency compensation circuits 102, 112: First transistor switches 103, 111: second transistor Switch 104: third transistor switch 105: fourth transistor switch 106: fifth transistor switch 107: sixth transistor switch 121, 122, 151, 152, 131, 141: transistor switch 160, 170: capacitor 202 , 211: first transistor switch 203, 212 ·· second transistor switch 204: third transistor switch 205: fourth transistor switch 206: fifth transistor switch 207: sixth transistor switch 221, 222, 231, 241, 26 and 262: transistor switch 271: first capacitor 272: first resistor 251: second capacitor 252: second resistor 280: first differential amplifier pair 290: second differential amplifier pair