TWI237357B - Singulation method used in leadless packaging process - Google Patents

Abstract

A singulation method used in leadless packaging process is disclosed. An array of molded products on an upper surface of a lead frame is utilized in the singulation method. The lead frame has a plurality of dambars between the molded products. The lower surface of the lead frame is attached with a tape. Each of the molded products includes a semiconductor chip encapsulated in a package body and electrically coupled to the upper surface of the lead frame. The singulation method is accomplished by etching the upper surface of the lead frame with the package bodies as mask until each dambar is etched away.

Description

1237357 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a process for manufacturing a leadless semiconductor package structure, and particularly relates to a process for a leadless package process. Cut it into individual pieces. [Prior art]

Due to its low cost and high reliability, lead frame packaging structures have been used in integrated circuit packaging for a long time. However, with the ever-increasing speed and downsizing of integrated circuit products, the traditional lead frame package structure has gradually become obsolete, at least for some integrated circuit products that pay attention to performance. Therefore, the 'ball grid array package structure (b a 1 1 g r d a r r a y, B G A) and the chip scale package (CSP) have gradually become the new = packaging options. BGA is widely used in chips with high pin count (I / 0s), as well as those requiring better electrical and thermal performance (such as central processing units and graphics chips). CSP has also been widely used in portable products. Footprint, package size, and packaging are the main considerations.

However, the lead frame package structure still has a low market share for low pin count (I / 〇s) chips, because it provides a cost-effective solution. K = has a relatively long inner lead ) And external pins (〇u ^ Two private lead frame package structure · Can not provide chip & inch, primary, two outline solutions. Therefore, the semiconductor packaging industry has developed a picture-outer pin package structure 1 : Tian Zhi's v-vision, gUl1-wing, and J-leaded

1237357 V. Description of the invention (2) type) Package structure, the outer pin package structure immortal system is located at the bottom. The outer-lead package structure 丨 〇 The chip /, pin 1 1 a = The bottom of the 1-package structure to provide better heat dissipation:? System 2 = The pin package structure 10 is provided with four supporting ribs (tle 3Γ) C connected to the wafer holder 1 lb. The wafer holder is a direct soldering technique. "The mating heat sink on the external printed circuit board provides a low thermal impedance: J 迢 generated by a semiconductor wafer connected to the wafer holder in a word:" belt = go to the bow " : Feet, no-lead package structure has a low round; of course; furthermore, the resistance and the electric quantity κ1 due to the reduction of the pin length (the reduction makes the no-lead package structure 10 very suitable: Yu Η; 'SeVei: al GlgaHertz) to tens of gigahertz (tens of == RF package structure. Due to the use of existing developed packaging technology. The above characteristics :: = is a highly competitive price seal "eg 4 Electricity; two: 2 ?: mounting is very suitable for communication products (off), digital cameras, and data: household electrical appliances ^ The conventional outer-lead packaging process includes the following steps: first imide (Polymide) tape To the bottom of the metal lead frame, it is used to prevent the occurrence of glue overflow during the sealing process. Generally speaking, the lead frame 15 (Moxibustion Figure 2) contains a plurality of units n. Each unit u contains a plurality of, The bow U a is disposed around a wafer holder i lb. Each wafer holder , 1 lb is connected by a line lc Shu four supporting ribs to the lead frame 15. Next, using silver paste (S1 lver epoxy)) the wafer 12 to the wafer bearing

1237357 V. Description of the invention (3) Block 1 1 b (refer to the third figure), and the silver glue is cured after the wafer bonding process. Then, a plurality of pins 1 1 a of the silicon wafer 12 and the lead frame 15 are connected by a conventional wire bonding process. After the wiring is completed, the lead frame 15 and the wafer 12 attached to it are enclosed in a colloid 13. Generally speaking, an array molding process (MAP (mold array package) molding process) is used to form a sealant. The polySi & imine tape was removed after sealing. Finally, curing is performed after sealing and cutting into a single step (singulation step) to complete the entire packaging process. The step of cutting into single pieces generally uses a resin-bond saw blade to cut the encapsulated molded product into individual units along a predetermined cutting line (dicing 1 ine) to obtain the blank. The outer arch 丨 foot package constructs the final product. Generally, the leadless semiconductor package structure 10 is mounted on a substrate using a conventional surface mount process (SMT) such as a printed circuit board. One of the main problems of the aforementioned packaging process occurs in a single step. Due to. Hailu blade is cutting two different materials (that is, the metal lead frame and plastic sealant), so it will not only shorten the saw blade life but also lead quality problems, such as the cutting end 1 of lead 1 1 a 4 generate metal burrs-and this will cause the problem of poor coplanarity of the final packaged product, thus complicate the subsequent surface bonding technology (SMT) and reduce its yield. SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a method for singulating a single chip for an outer-lead-free packaging process, thereby overcoming or at least improving the aforementioned problems in the prior art.

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Page 8 1237357 V. Description of the invention (4) The other f: the purpose is to provide-a kind of external pin packaging process so that the completed external pin sealing ^ will not produce metal burrs when it is formed into early particles ^ ^, Μ 丨 foot package structure has better coplanarity. Basin: /, for his purpose, the present invention provides a single cut of 2 3 3) providing a plurality of moldings arranged in an array on the surface of a V-line mining, the lead frame has a plurality of partitions' (in d · b), ^, and the car pile II U'mo plastic part includes a semiconductor wafer covered in a sealing compound and electrically = the upper surface of the lead frame; and (b) using electricity:

Jt = engraving the upper surface of the lead frame for the surname of the mask until every eighth spacer was engraved by the worm. n

Check 5 Yu: The method of forming soap particles is to etch away the spacer of the lead frame. '4 The completed outer-lead package structure will not be mechanically affected; S This: Bu: In the silver engraving step There will be no metal burrs, because =;:;: 1 The package structure will have good flatness, which will increase the yield of the surface bonding process. 3 W, plus and ::::: The other two implementations {column, each divider has a first-part in the eclipse: will t? The first part is connected to an adjacent molded part, and in the etching step, every second part of the $ knife is etched away and the first part of the knives is kept at $ 1,000. Roughly complete. Process, 3 supply—a kind of complicated process for manufacturing a plurality of outer-lead-free package structures, which includes the following steps: (a) Provide a lead rod, one upper surface and one lower surface of iC, the derivative, and units with opposite columns And a number of separators m dagger 3 have several blades in an array row of one knife partition a and again between 5 Haizaowu.

1237357

A wafer holder and a plurality of pins are located around the wafer holder; (b) a wafer holder for bonding a plurality of wafers to the lead frame; (c) the wafer. Electrically connected to the lead frame pins; (d) Adhesive—Adhesive tape is placed on the lower surface of the lead frame. '(E) The sealant covers the chip on the upper surface of the lead frame with a plurality of sealants, each covering one. Wafer; (f) etching the upper surface of the lead frame with the sealing compound as mask (mas k) until each spacer is etched [embodiment]

The first and fourth figures do not show / are a plurality of moldings 50 arranged in an array. In the fourth figure, the moldings 50 are covered with shadows to help understanding. The molding 50 is set on the previous line killer 100. The lead frame 100 has an upper surface and a lower surface relative to the dead surface. The lead frame 100 includes a plurality of cells 1 丨 0. Each cell 1 10 includes a plurality of pins 11 a and is disposed around a wafer holder ib. The units 11 () of the lead frame 100 are separated from each other by a plurality of spacers 11 lc. The spacers 1 lie form a rectangular grid approximately on the lead frame 100. In detail, the spacer 111c is defined between the pins 丨 la around the wafer holder 111b. The lead frame 丨 〇〇 is generally made of copper-based alloy or copper or copper-containing alloy as a material and stamped or worm carved. There are three types of lead surface treatments suitable for the lead frame, post plated SnPb and Matte tin of the present invention, as well as the front ore record / 1 bar and a thin layer of gold (that is, the pre-plated lead frame)

Lead Frame (referred to as ρρρ)). 5 to 8 are diagrams illustrating a manufacturing process for manufacturing a plurality of non-lead semiconductor package structures according to an embodiment of the present invention.

1237357 V. Description of the invention (6) Referring to Fig. 5, a polyimide tape (13〇] ^ 111] 1 (16) 2 0 0 is pasted on the surface of the lead frame 100 to prevent The glue process caused the glue to overflow. Then, the semiconductor wafer 1 40 was made of silver glue (not shown) and pasted to the wafer holder 1 1 1 b, and the silver glue was applied after the wafer 1 40 was pasted. After curing, a conventional wire bonding process is performed to connect the semiconductor wafer 140 and the lead frame to each other! The pins of 〇〇! J J a.

Referring to FIG. 6, an encapsulant covers the wafer on the upper surface of the lead frame 丨 〇 4 to form the aforementioned molding 50. After sealing, each wafer is covered with a gel 150. In this embodiment, each divider of the lead frame has two grooves 111 d on the lower surface of the lead frame and is adjacent to the arch 11 a. Each divider 1 nc has a first portion 1116 and a second portion 11 If connecting the first portion 1 lie to an adjacent molding 50.

Then, a single step is performed to cut the assembly shown in FIG. 6 into an independent outer-lead-free semiconductor package structure on the polyimide tape 200. Referring to FIG. 7, the step of cutting into individual pieces is achieved by removing the second part 丨 i 丨 f of the spacer 111 C by an etching process. In detail, ‘the # engraving process is achieved by engraving the upper surface of the lead frame 100 with the sealant 150 as a mask #. It should be noted that the part 11 1 e of the spacer 11 1 c after the etching operation remains substantially intact. Since the step of cutting into a single piece is achieved by etching away the first blade 111e of the spacer 丨 lc, there is no mechanical stress applied to the completed outer leadless package structure. In addition, no metal burrs will be generated during the etching step. Therefore, the finished outer package structure will have a good flatness, thereby increasing the yield of the surface mount (SMT) process.

1237357

V. Description of the invention (7) According to Fig. 8, the polyimide tape 2000 is removed after the cutting step. The completed outer-lead-free semiconductor package structure can be mounted on a board in a similar manner to other lead-less devices, such as a printed circuit board. The printed circuit board may be screen-printed with solder paste into a plurality of patterns corresponding to the bottom of the package structure. The package structure can then be re-soldered on the printed circuit board using a conventional surface mount technology (SMT). In addition, a plurality of pins exposed at the bottom of the package structure can also be printed with solder paste before being mounted on a printed circuit board. Preferably, a tin / lead plating step is performed before soldering the two package structure to the printed circuit board, thereby increasing solderability. Specifically, a layer of tin / lead is plated on a plurality of pins exposed at the bottom of the package structure. Although the present invention is discussed in detail with respect to a lead frame having two grooves formed in each of its partitions (preferably not shown in FIG. 9), the present invention can be applied to a variety of different partition designs (such as the following Description). For example, each ~ divider may have only one groove so that the thickness of each divider is smaller than the thickness of other parts of the conductive frame. As shown in FIG. 10, the partition 11 1 c may have a groove 11 3 formed on a lower surface of the lead frame. As shown in FIG. 11, the δH spacer 111c may have a groove 115 formed on the upper surface of the lead frame. As shown in FIG. 12, the partition member 11lc may have a through hole 117 formed therein. As shown in Fig. 13, the spacer lllc may have a groove formed on a side surface of the spacer. The grooves or through holes help to improve the "undercut" problem caused by the isotropic money engraving process in the single cutting step. If it has the points shown in Figure 10-Η

00683. ptd Page 12 1237357 V. Description of the invention (8) The lead frame of the spacer design is used in the present invention, and the side divider should be completely engraved with money in this single step of cutting. The grooves or through holes as described can be formed by engraving each of the spacers of the lead frame. In detail, "ha 1 f-etching" may include: (a) forming a photoresist layer on the lead frame using a conventional technique (such as photoresist dry film lamination); (B) the photoresist layer is first photochemically defined using a photo mask, and then developed so that the area f on the surface of the lead frame where grooves or through holes are to be formed is not covered by the photoresist layer Covering; (c) etching the lower surface of the lead frame exposed on the remaining photoresist layer to form the trench or through hole; and (d) removing the photoresist in a conventional manner. It is worth noting that the half-etching referred to here does not only mean that the half of the thickness of the lead frame exposed by the photoresist is accurately removed by etching, but includes the need to remove the thickness of the lead frame through partial etching> idea What is achieved is that the partition of the cutting frame of the present invention is achieved. Therefore, no mechanical stress is applied to solve the problem related to the encapsulation process of the separator. The step of forming a single piece is to etch away the wire, which will provide better package integrity for the completed outer leadless package. In addition, the conventional cutting step can be omitted by the present invention.

Although the present invention has been formulated according to the foregoing, any familiarity with this example is disclosed in the examples, but it is not intended to be used within a limited scope, and it can be used as a variety of insects without departing from the spirit and scope of the invention Patents and amendments. Therefore, the protection scope of the present invention is the one defined by the siege.

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1237357 Schematic description [Schematic description] In order to make the above and other objects, features, and advantages of the present invention more apparent, the following description will be described in detail with the accompanying drawings. Fig. 1: A bottom view of a conventional non-lead semiconductor package structure; Fig. 2: A top view of a conventional lead frame used to form a non-lead semiconductor package structure; Fig. 3: Fig. 1 A cross-sectional view of an outer leadless package structure; FIG. 4 is a top view of a plurality of moldings arranged in an array on a lead frame according to an embodiment of the present invention; FIGS. 5 to 8 are used for: A process for manufacturing a plurality of non-lead semiconductor package structures according to an embodiment of the present invention is illustrated; FIG. 9 is a cross-sectional view taken along line 9-9 of FIG. 4, which illustrates an implementation according to the present invention Figure 10: A cross-sectional view of another divider design according to another embodiment of the present invention, FIG. 11: a cross-sectional view of another divider design according to another embodiment of the present invention, FIG. 1 FIG. 2 is a top view of another partition design according to another embodiment of the present invention, and FIG. 13 is a cross-sectional view of another partition design according to another embodiment of the present invention. Drawing number description: 10 no-lead package structure 11 units

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Brief description of the drawing 11a Pin 1 lb Wafer socket lie Support ribs 12 Wafer 13 Sealant 14 Cut end 15 Lead frame 50 Molded part 100 Lead frame 110 Early 111a Pin 111b Wafer holder 111c Divider 1 1 Id groove Slot 1 1 le first part 1 11 f second part 1 13 groove 115 groove 1 17 through hole 119 groove 140 chip 150 sealing compound 200 tape 00683. ptd page 15

Claims (1)

1237357 No. 1 92116437 VI. Scope of patent application Each molded part includes a semiconductor wafer covered in a sealing compound and electrically connected to the upper surface of the lead frame; and the sealing compound is used to etch the mask The upper surface of the wire is engraved until 1¾ of each knife is touched off. 4. The method for cutting a plurality of non-lead-free semiconductor package structures as described in item 3 of the scope of patent application, wherein each of the spacers has at least one trench formed therein. 5. As described in item 4 of the patent scope, a method for cutting a plurality of non-lead semiconductor package structures into a single piece, wherein each of the trenches is half-etched The lead frame is formed by the partition. 6. As described in item 4 of the scope of the patent application, solid = outer-lead semiconductor package is cut into a single method, and the groove of the blade is formed on the upper surface of the lead frame or No surface η », 4- Tian Yu manufactures a number of external leads 7 7. The method of use as described in item 4 of the scope of patent application, = Two-lead semiconductor package structure cutting method into a single piece, wide. The blade grooves of the wire mesh member are formed on the side surfaces of the separator. 8. As described in item 3 of the scope of patent application-for = several f: pins, the method of cutting the semiconductor package structure into single pieces:. &quot; Mother ’s knife spacer is less thick than the conductive frame 00683-TW-Amendment 20050512.ptc No. 17 Buy 1237357 Amendment No. 92116437 VI. Application for Patent Scope 9, as described in item 3 of the Patent Application Scope for manufacturing a plurality of non-lead semiconductor package structures Method, wherein each of the separators has at least a through hole formed therein. 〇 Kinds of processes for manufacturing a plurality of outer-lead-free semiconductor package structures, including: Gati, a lead frame, which has opposite upper and lower surfaces, and each of the wires has a wafer holder for receiving. Every week: The divider has two abutting pieces. A knife and-the second part connects the-part to an adjacent wafer holder which glues a plurality of wafers to the lead frame; the wafers are electrically connected to the leads of the lead frame; an adhesive tape is stuck On the lower surface of the lead frame; encapsulant covers the wafer on the upper surface of the lead frame to cover a wafer; ~ several sealant bodies each. The Haifeng colloid etched the wire for the mask. The second part of the divider was cleared and: the surface of the person up to each part remained substantially intact; with &amp;. The first removal of the mother-divider has the first portion of each of the spacers, the outer-lead semiconductor package structure. ^ f to get these zero% 83-TW-Amendment 20050512. ptc Page 18 1237357 Case No. 92116437 VI. Application for Amendment of the Patent Scope 11. The manufacturing process for manufacturing the conductor package structure as described in Item 10 of the scope of the patent application, Wherein the groove ";; outer pin + etChing) The half-position of the spacer of the lead frame. 卞 <knife 丨 net 仟 is formed in the vicinity of the molded part 1 2, a manufacturing multiple No external citations include: a process for providing a lead frame to be packaged on the single pin and placing a plurality of the crystals on a plastic-footed semiconductor package structure, and covering the lead frame by removing the lead frame with each separation An electric tape containing the wafers between the restorations is covered with the guide tape; the colloid is an etched tape having a plurality of phases in an array, and the periphery of each single seat is adhered to the guide and connected to the guide. Conductor: The upper surface of the lead frame is engraved with a mask; and the upper and lower surfaces of the unpaired one are obtained, and the queued unit and the plurality of partition elements have a wafer holder and a plurality of On the wafer holder of the wire frame; the pins of the frame; the lower surface; the wafer to form a plurality of sealing gels, each of which is engraved on the upper surface of the lead frame until 1 3, as described in the patent application scope No. 丨 2 conductor package structure A manufacturing process in which a groove is formed therein. An outer-lead semiconductor encapsulation structure is described. A plurality of non-outer-lead halves are described, and each of the spacers has at least one groove. 00683-T1V-Amendment 20050512. Page 19