1237183 3r : 〜 玖、發明說明： 【發明所屬之技術領域】 本發明係關於一種指定硬體位址之方法與系統，尤指 種適用於可自動指定硬體位址之方法與系統。 【先前技術】 10 15 在一般之電腦系統中，均具有多種不同功能之電子元件 至’並以匯流排來將該等元件連接，達到相互通訊之目的， 如圖1所示，電腦10中係使用相互之整合電路（ imer-Integrated Circuit，以）匯流排，其為一種雙向、二條 線之匯流排結構，可讓不同功能之電子元件連接至以匯流 排’達到相互通訊之目的。其中，12。匯流排具有一條序列 資料匯流排（SedalData，SDA)以及—條序列時脈匯流排 SenalClock，SCL) ’其中，序列資料匯流排可以用以傳 =與接收資料/命令訊號。由此可知，作匯流排係採用序列 二料傳輸之方式。不同功能之電子元件，各別將其資料線連 …至SDA以接收或傳送資料/命令信號；且將其時脈線連結 ^以傳輸時脈訊號。主微處理器12藉由主端（Master) ;曰：:3而連結至!:C匯流排，其餘電子元件藉由客端（_ 二❿連了至I C。同-時間_，主微處理器⑵堇能從其 ，電子το件中接收或傳送資料/命令信號。询如，主微 處理器12欲傳送圖形資料$、六 + + α办貝科至液晶顯示器（LCD)驅動器14時 13猎由1c匯流排以傳送圖形資料至客端晶片15，客端晶片 20 Ϊ237183 …..........，.： :， ' ::::形資料傳送至LCD驅動器14。如果’主微處理器12 存媒體16中讀取資料信號時，主端晶片13傳送命令信 H端晶片17，命令其傳送資料信號，然後儲存媒體16 端C號ΐ客端晶片17’客端晶片17傳送資料信號至主 曰曰、3，主端晶片13再傳送資料信號至主微處理器a。 10 為—了使主微處理器12以及其餘電子元件皆在以上正常 广你二纟端晶片皆具有一組彼此不同之硬體位址，並儲 ::端晶片中，當接收或傳送資料/命令信號時，每一客 :曰'片將進仃硬體位址之比對，並由符合硬體位址之電子元 牛進行傳送與择收資料/命令信號。 當需使用多個相同之客端晶片時，將會發 情況(設定值相同），另，如不同客丄 ”同商所製造時，亦可能會發生兩個以上客端曰 係對應至相同硬體位址之情π。 . ^各知日日片 15 況發生，需變更客端晶片=體::二為避免上述之情 而曰曰月之硬體位址，其有下列兩種方式： 種方式為令客端晶片提供多組較之硬體位址，如圖2 所不一，客端晶片15、17、19、及21係具有數支位址腳位（例 士 一支位址腳位）’藉&分別設定位址腳位之電壓準位（例 如，使用上拉或下拉電阻）以分別改變客端晶片& … 2〇及21之硬體位址。此方式之缺點為，客端晶片15、17、19、 及21之位址腳位數目有限，使客端晶片i5 u、及^ 無法提供較豐富之硬體位址，這亦限制電腦中客端晶片Η、.： 17、19、及21所對應之雷工- 端晶片係提供多_定之方式為令客 之更體位址，如圖3所示，客端晶片 1237183 ’ i舉1237183 3r: ~ 玖, Description of the invention: [Technical field to which the invention belongs] The present invention relates to a method and system for specifying a hardware address, and more particularly to a method and system for automatically specifying a hardware address. [Prior technology] 10 15 In general computer systems, there are a variety of electronic components with different functions, and these components are connected by a bus to achieve the purpose of mutual communication. As shown in FIG. The use of mutual integrated circuit (imer-Integrated Circuit) bus, which is a two-way, two-line bus structure, allows electronic components with different functions to be connected to the bus to achieve the purpose of mutual communication. Among them, 12. The bus has a serial data bus (SedalData, SDA) and a serial clock bus SenalClock (SCL) ′, where the serial data bus can be used to transmit and receive data / command signals. It can be known that the serial bus is adopted for the bus system. For electronic components with different functions, connect their data lines to SDA to receive or send data / command signals; and connect their clock lines ^ to transmit clock signals. The main microprocessor 12 is connected to the!: C bus by the master (Master); said:: 3, and the remaining electronic components are connected to the IC by the client (_ Erji). Same-time_, the main micro processor The device can receive or transmit data / command signals from its electronic components. For example, the main microprocessor 12 wants to send graphic data $, six + + α to Beko to the liquid crystal display (LCD) driver 14:13 The 1c bus is used to send the graphic data to the client chip 15, and the client chip 20 Ϊ237183… ..........,.::, ':::: Shape data is transmitted to the LCD driver 14. If 'When the main microprocessor 12 reads the data signal from the storage medium 16, the main chip 13 sends a command letter H chip 17 and instructs it to transmit the data signal, and then stores the medium 16 C number and the client chip 17' 17 sends the data signal to the master, 3, and the master chip 13 sends the data signal to the main microprocessor a. 10 is to make the main microprocessor 12 and the rest of the electronic components above the normal range. Each has a different set of hardware addresses and is stored in the :: end chip when receiving or transmitting data / command signals Every guest: "The film will be compared with the hardware address, and the electronic bulls that match the hardware address will be used to transmit and receive data / command signals. When multiple identical client chips are required, the The situation will be the same (set values are the same). In addition, if different customers are manufactured by the same company, two or more clients may correspond to the same hardware address π.. ^ Each day 15 If this happens, the client chip = body :: To avoid the above situation, the hardware address of the moon is described in the following two ways: One way is to provide the client chip with multiple sets of hardware addresses. As shown in Figure 2, the client chips 15, 17, 19, and 21 have several address pins (for example, one address pin). "Borrow & set the voltage level of the address pins separately. (For example, using pull-up or pull-down resistors) to change the hardware address of the guest chip & 20 and 21 respectively. The disadvantage of this method is that the address pins of the guest chip 15, 17, 19, and 21 are The number of bits is limited, making the client chip i5 u and ^ unable to provide richer hardware addresses, which also limits the client in the computer Sheet Η,:. 17,19, and 21 corresponding to the mine workers - _ multi-terminal chip is provided so as prescribed manner of passengers more member addresses, as shown, the guest wafer 1237183 'i shown in FIG. 3 give
LiL—j 日丨 15、17、19、及21之硬體位址係可設定（由製造商設定）， 此方式須配合一個多工器92，由多工器92來控制具有相同硬 體位址之客端晶片15、17、19、及21與以匯流排之連接， 、不淪客端晶片15、17、19、及21之硬體位址是否相同， 5多工器92皆能將客端晶片15、Π、19、及21適時地連接至fc 匯流排。此方式之缺點為其成本較高（額外之多工器”）， 且其結構亦違反部份I2C匯流排之通信協定。 【發明内容】 10 本發明之主要目的係在提供一種可自動指定硬體位址 之方法與系統，俾能自動設定電子元件之硬體位址。 本發明之另一目的係在提供一種可自動指定硬體位址 之方法與系統，俾能降低電子元件所需之外接針腳之數目。 為達成上述目的，本發明揭露一種自動指定硬體位址之 15方法，包括下列步驟：（A )關閉系統中至少一開關電晶體； (B)指定連接至fc匯流排之第一客端晶片對應之硬體位 址；以及（C)依序導通至少一開關電晶體，以使其對應之 至少一第二客端晶片依序連接至Pc匯流排，並依序指定其 對應之硬體位址，其中第一客端晶片與至少一第二客端晶片 20 之對應之硬體位址係彼此不同。 為達成上述目的，本發明揭露一種可自動指定硬體位址 之糸、、先包括· I c匯μ排，主端晶片，係連接至pc匯流排； 第一客端晶片，係連接至I2C匯流排；至少一開關電晶體， 係連接至I2C匯流排·，以及至少一第二客端晶片，係分別連 1237183 接至至少一開關電晶體；其中，主端晶片指定第一客端晶片 對應之硬體位址’並依序導通至少—開關電晶體以依序指定 至少一第二客端晶片對應之硬體位址。 ' :·:於本發明中，由於第一客端晶片以及第二客端晶片係依 5序被指定對應之硬體位址，其對應之硬體位址係彼此不同， 而其過程為自純，且第一客端晶片以及第二客端晶片不需 額外之針腳，故能達到本發明之目的。 【實施方式】 1〇 有關本發明之可自動指定硬體位址之方法與系統，請先 參照如圖4所不之系統架構圖，其中，主端晶片13及客端晶 片丨5、17、19及21透過匯流排4〇互相通訊，該匯流排4〇較佳 ，為I C匯μ排，客端晶片丨5、丨7以及丨9分別連接至開關 7晶體30、31以及32。開關電晶體3〇、31以及32分別接收主 15端晶片13之開關信號以分別選擇是否將客端晶片15、17及19 連接至I C。其中，客端晶片2丨係直接連接至J2C，而主端晶 片13與客端晶片15、17、19以及21可為相同種類之晶片。 當電腦10初始化時，主端晶片13傳送低電壓準位之開關 ^唬來將開關電晶體3〇、3丨以及32關閉，以中止客端晶 2〇 以及19連接至以。並傳送命令信號至以，並由連接 至I C之客端晶片21所接收。客端晶片21接收命令信號後， 從命令信號中取得對應之硬體位址（例如，硬體位址1)並 儲存之，爾後，客端晶片21依據硬體位址丨與主端晶片13進 行資料/命令信號之傳送與接收。然後，主端晶片13傳送高 1237183 電壓準位之開關信號以導通其中之一開關電晶體，例如，主 柒阳片13傳送咼電壓準位之開關信號至開關電晶體3〇來將 開關電晶體30導通，使客端晶片15連接至pc，主端晶片13 、傳$另一命令信號至Pc，並由連接至之客端晶片15所接 5收（因為另一命令#號所對應之硬體位址不同，所以客端晶 片21不會接收另一命令信號），客端晶片。從另一命令信號 中取得另一對應之硬體位址（例如，硬體位址2 )並儲存之， 爾後，客端晶片15依據硬體位址2與主端晶片13進行資料/命 令信號之傳送與接收。 10 15 之後，主端晶片13依序分別傳送高電壓準位之開關信號 f開關電晶體31以及32，使客端晶片17以及19分別連接至 1C’、主端晶片13依序分別傳送不同之命令信號至斤，並依 序由連接至代之客端晶片17以及19所分別接收。客端晶片 P以及19分別接收不同之命令信號後，從不同之命令信號中 取得不同之韻之㈣他（例如，客端W 17取得硬體位 =客端晶片19取得硬體位址4)並儲存之，爾後，客端晶 料/人1^分別依據硬體位址3以及4與主端晶片13進行資 傳送與接收。如此-來，每一客端晶片皆取 = -二二之對應之硬體位址，所以主微處理器讲與連接 能確進㈣料7命令錢之傳送與接收，並 月匕罐保電腦10正常運作。 情況上咖於電腦1G中佳制較少電子元件之 滑况因為所有之開關信號皆由主端 > 開關信號須對應至主端晶片13之一支針腳，、:：，母一個 又对卿’廷將造成主端晶 20 1237183 B ;: λ/ / ν ^ 片13需要許多之針腳來傳送開關信號，故適用於具有較少電 子元件之系統。 如圖5所示，本發明另一實施例係由客端晶片傳送開關 信$，例如，客端晶片21可傳送開關信號至開關電晶體32， 5以切換客端晶片19與I2C之連接狀態；客端晶片19可傳送開 關信號至開關電晶體31，以切換客端晶片17與12〇之連接狀 態；客端晶片17可傳送開關信號至開關電晶體3〇，以切換客 端晶片15與I2C之連接狀態。 當電腦10初始化時，每一開關電晶體之預設狀態係為關 10閉，所以客端晶片15、17以及19係不連接至i2c，唯有客端 晶片21連接至fc。主端晶片13傳送命令信號sfc，並由連 接至i2c之客端晶片21所接收。客端晶片21接收命令信號 後，從命令信號中取得對應之硬體位址（例如，硬體位址〇 並儲存之’爾後’客端晶片21依據硬體位址1與主端晶片13 15進仃資料/命令信號之傳送與接收。然後，主端晶片13傳送 命令信號至客端晶片21，命令其傳送高電壓準位之開關信號 以導通開關電晶體32，使客端晶片19連接至fC，主端晶片 13傳送另一命令信號至fc，並由連接至fc之客端晶片19所 接收（因為另一命令信號所對應之硬體位址不同，所以客端 20晶片21不會接收另一命令信號），客端晶片19從另一命令信 旎中取得另一對應之硬體位址（例如，硬體位址2)並儲存 之爾後，客端晶片15依據硬體位址2與主端晶片13進行資 料客‘晶片21之傳送與接收。之後，主端晶片13傳送命令信 旎至客端晶片19,命令其傳送高電壓準位之開關信號以導通 1237183LiL-j days 15, 17, 19, and 21 hardware addresses can be set (set by the manufacturer). This method must be used with a multiplexer 92, which is controlled by the multiplexer 92 with the same hardware address. Whether the client chips 15, 17, 19, and 21 are connected to the bus, and whether the hardware addresses of the client chips 15, 17, 19, and 21 are the same. 5 The multiplexer 92 can connect the client chips. 15, Π, 19, and 21 are connected to the fc bus in a timely manner. The disadvantage of this method is its higher cost (extra multiplexer), and its structure violates some I2C bus communication protocols. [Summary of the Invention] 10 The main purpose of the present invention is to provide a hardware that can be automatically specified. The method and system of the physical address can not automatically set the hardware address of the electronic component. Another object of the present invention is to provide a method and system that can automatically specify the hardware address, which can reduce the external pins required by the electronic component. In order to achieve the above objective, the present invention discloses a method for automatically designating a hardware address, which includes the following steps: (A) turning off at least one switching transistor in the system; (B) designating a first client terminal connected to the fc bus The corresponding hardware address of the chip; and (C) sequentially turning on at least one switching transistor, so that its corresponding at least one second client chip is sequentially connected to the Pc bus, and its corresponding hardware address is sequentially specified The corresponding hardware addresses of the first client chip and the at least one second client chip 20 are different from each other. In order to achieve the above purpose, the present invention discloses a hardware that can be automatically designated. The address of the address includes the IC bus μ, the main chip, which is connected to the PC bus; the first client chip, which is connected to the I2C bus; at least one switching transistor, which is connected to the I2C bus Row and at least one second client chip are connected to 1237183 to at least one switch transistor respectively; wherein the master chip designates the hardware address corresponding to the first client chip 'and sequentially turns on at least-the switch transistor The hardware addresses corresponding to at least one second client chip are designated in order. '::: In the present invention, since the first client chip and the second client chip are designated in the order of 5 corresponding hardware addresses, The corresponding hardware addresses are different from each other, and the processes are self-pure, and the first client chip and the second client chip do not need additional pins, so the purpose of the present invention can be achieved. [Embodiment] 10 Relevant The method and system for automatically specifying the hardware address of the present invention, please refer to the system architecture diagram shown in FIG. 4 first. Among them, the master chip 13 and the guest chip 丨 5, 17, 19, and 21 pass through the bus 4. Communication with each other, the busbar 40 is better For the IC sink μ row, the client chips 丨 5, 丨 7, and 丨 9 are connected to the switch 7 crystals 30, 31, and 32, respectively. The switching transistors 30, 31, and 32 receive the switching signals of the main 15-terminal chip 13 to respectively Choose whether to connect the client chip 15, 17, and 19 to the IC. Among them, the client chip 2 is directly connected to J2C, and the master chip 13 and the client chip 15, 17, 19, and 21 can be the same kind of chip When the computer 10 is initialized, the main-end chip 13 transmits a low-voltage level switch ^ to turn off the switching transistors 30, 3, and 32, so as to stop the connection of the guest crystals 20 and 19, and transmit the command. The signal comes first and is received by the client chip 21 connected to the IC. After the client chip 21 receives the command signal, it obtains the corresponding hardware address (for example, hardware address 1) from the command signal and stores it, and then, The client chip 21 transmits and receives data / command signals with the host chip 13 according to the hardware address. Then, the main-end chip 13 transmits a switching signal with a high 1237183 voltage level to turn on one of the switching transistors. For example, the main solar cell 13 transmits a switching signal of the high-voltage level to the switching transistor 30 to switch the switching transistor. 30 is turned on, so that the client chip 15 is connected to the pc, the master chip 13 transmits another command signal to Pc, and is received by the client chip 15 connected to it (because of the hardness corresponding to another command #) The body address is different, so the client chip 21 will not receive another command signal), the client chip. Obtain another corresponding hardware address (for example, hardware address 2) from another command signal and store it. Thereafter, the client chip 15 transmits data and command signals according to the hardware address 2 and the master chip 13. receive. After 10 15, the main-end chip 13 transmits the high-voltage level switching signals f and the switching transistors 31 and 32, respectively, so that the client-side chips 17 and 19 are connected to 1C ′, and the main-end chip 13 sequentially transmits different signals. The command signal is transmitted to the receiver and is sequentially received by the client chips 17 and 19 connected to it. After receiving different command signals, the client chips P and 19 obtain different rhymes from different command signals (for example, the client W 17 obtains the hardware position = the client chip 19 obtains the hardware address 4) and stores them. After that, the guest crystal / person 1 ^ transmits and receives data to and from the master chip 13 according to the hardware addresses 3 and 4, respectively. So-come, each client chip takes the corresponding hardware address =-22, so the main microprocessor speaks and connects to confirm the data 7 to send and receive money, and to protect the computer 10 working normally. In the case of the computer, there are fewer electronic components in 1G because all the switching signals are from the master terminal. The switching signals must correspond to one of the pins of the master chip 13, and the mother one is opposite to the other. 'Ting will cause the main terminal 20 1237183 B;: λ / / ν ^ The chip 13 needs many pins to transmit the switching signal, so it is suitable for systems with fewer electronic components. As shown in FIG. 5, another embodiment of the present invention transmits a switch signal $ from a client chip. For example, the client chip 21 may transmit a switch signal to the switch transistor 32, 5 to switch the connection state between the client chip 19 and I2C. ; The client chip 19 can send a switching signal to the switching transistor 31 to switch the connection state of the client chip 17 and 120; the client chip 17 can send a switching signal to the switching transistor 30 to switch the client chip 15 and I2C connection status. When the computer 10 is initialized, the default state of each switching transistor is off 10, so the client chips 15, 17, and 19 are not connected to i2c, only the client chip 21 is connected to fc. The master chip 13 transmits a command signal sfc and is received by the guest chip 21 connected to i2c. After receiving the command signal, the client chip 21 obtains the corresponding hardware address from the command signal (for example, the "later" hardware address 0 and stored therein). The client chip 21 enters the data according to the hardware address 1 and the master chip 13 15 / Command signal transmission and reception. Then, the master chip 13 sends a command signal to the client chip 21, and instructs it to transmit a high-voltage level switching signal to turn on the switching transistor 32, so that the client chip 19 is connected to fC. The terminal chip 13 transmits another command signal to the fc and is received by the client chip 19 connected to the fc (because the corresponding hardware address of the other command signal is different, the client 20 chip 21 will not receive another command signal ), The client chip 19 obtains another corresponding hardware address (for example, hardware address 2) from another command message and stores it, and then the client chip 15 performs data according to the hardware address 2 and the master chip 13 Transmission and reception of the guest chip 21. After that, the master chip 13 transmits a command message to the guest chip 19, and instructs it to transmit a high-voltage level switching signal to turn on 1237183.
開關電晶體31，使客端晶片17連接至fc，主端晶片13傳送 另一命令信號至I2C以指定客端晶片19之對應之硬體位址。 以下依此類推。由於每一客端晶片僅需傳送一個開關信號， 、只g使用一支針腳，這將不會造成客端晶片額外之負擔。 5 一般而言，由於主端晶片13以及客端晶片15、17、19 以及21皆具有少數（例如，三支）一般目的輸入/輸出（GeneralThe transistor 31 is switched on and off, so that the guest chip 17 is connected to the fc, and the master chip 13 transmits another command signal to the I2C to specify the corresponding hardware address of the client chip 19. And so on. Since each client chip only needs to transmit one switch signal, and only one pin is used, this will not cause additional burden on the client chip. 5 In general, since the master chip 13 and the guest chips 15, 17, 19, and 21 each have a small number (for example, three) of general purpose input / output (General
Purpose Input/Output ，GPIO)針腳，經使用者設定之後， 皆成用以傳送不同電壓準位之開關信號，所以本發明可自動 指定硬體位址之方法或系統，可適用於所有主端晶片13以及 10 客端晶片15、1.7、19以及21。 月il述開關電晶體3 0、3 1以及3 2較佳為金屬氧化半導體 (M0S)製成之開關器，當然，亦可由其他具有開關功能之 電子元件所替代。除了電腦1〇之外，亦能以其他電子系統來 替代，例如：行動電話、個人數位助理（PDA)，智慧型電 15話（smartphone)，數位相機、導航系統等等，不以上述所 提之電子系統為限。 上述貫施例僅係為了方便說明而舉例而已，本發明所主 張之權利範圍自應以申睛專利範圍所述為準，而非僅限於上 述實施例。 20 【圖式簡單說明】 圖1係習知I2C匯流排與電子元件之示意圖。 圖2係習知I2c匯流排系統中決定位址之_方式。 圖3係習知I2C匯流排系統中決定位址之另—方式。 11Purpose Input / Output (GPIO) pins, after being set by the user, are used to transmit switching signals of different voltage levels, so the method or system for automatically specifying the hardware address of the present invention can be applied to all master chips 13 And 10 guest chips 15, 1.7, 19 and 21. The switching transistors 30, 31, and 32 are preferably switches made of metal oxide semiconductor (MOS). Of course, they can also be replaced by other electronic components with switching functions. In addition to the computer 10, it can also be replaced by other electronic systems, such as: mobile phones, personal digital assistants (PDAs), smart phone 15 (smartphone), digital cameras, navigation systems, etc., not mentioned above The electronic system is limited. The above-mentioned embodiments are merely examples for the convenience of description. The scope of rights claimed in the present invention should be based on the scope of the patent application, but not limited to the above-mentioned embodiments. 20 [Schematic description] Figure 1 is a schematic diagram of a conventional I2C bus and electronic components. Figure 2 shows the method of determining addresses in the conventional I2c bus system. Figure 3 shows another way to determine the address in the conventional I2C bus system. 11
1237183 圖4係本發明I2C匯流排與電子元件之示意圖。 圖5係本發明另一 I2C匯流排與電子元件之示意圖。 10電腦 12 主微 14 LCD驅動器 15 客端 Π客端晶片 18 轉換 20溫度偵測器 21 客端 3 1開關電晶體 32 開關 92多工器 處理器 13 主端晶片 晶片 16 儲存媒體 器 19 客端晶片 晶片 30 開關電晶體 電晶體 91 客端晶片1237183 FIG. 4 is a schematic diagram of the I2C bus and electronic components of the present invention. FIG. 5 is a schematic diagram of another I2C bus and electronic components according to the present invention. 10 computer 12 main micro 14 LCD driver 15 client Π client chip 18 conversion 20 temperature detector 21 client 3 1 switch transistor 32 switch 92 multiplexer processor 13 main chip chip 16 storage media 19 client Wafer Wafer 30 Switching Transistor Transistor 91 Client Wafer
1212