TWI236757B - Leadframe without outer leads for semiconductor package - Google Patents
Leadframe without outer leads for semiconductor package Download PDFInfo
- Publication number
- TWI236757B TWI236757B TW093108963A TW93108963A TWI236757B TW I236757 B TWI236757 B TW I236757B TW 093108963 A TW093108963 A TW 093108963A TW 93108963 A TW93108963 A TW 93108963A TW I236757 B TWI236757 B TW I236757B
- Authority
- TW
- Taiwan
- Prior art keywords
- pins
- pin
- lead
- pads
- item
- Prior art date
Links
Classifications
-
- H10W90/756—
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
12367571236757
五、發明說明(1) 【發明所屬之技術領域】 本發明係有關於一種 別係有關於一種半導體封 【先前技術】 運用在半導體封裝之導線架 裝之無外引腳式導線架。 ,特 在習知半導體封装技術中一晶片係以一導線架 ,,並以一封膠體密封該晶片,為了縮小封裝構造之尺 :膠C設計為無外引腳型態’以内引腳顯露在 ,底面之外接墊取代習知之外引腳,例如四方扁平益 外引腳封裝(Quad Flat Non-leaded package,㈣),: 封裝高端子數(I/O)之晶片時,導線架之内引腳將高密^ 排列而呈扇出結構,使得封裝構造之尺寸增大。V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a semiconductor package [prior art] An outer lead type lead frame used in a lead frame of a semiconductor package. In the conventional semiconductor packaging technology, a chip is a lead frame, and the chip is sealed with a gel. In order to reduce the size of the package structure: the glue C is designed to have no outer pin type. The external pads on the bottom surface replace conventional non-lead pins, such as the Quad Flat Non-leaded package (㈣): when packaging high-terminal-count (I / O) chips, the internal lead of the lead frame The feet are arranged in high density ^ to form a fan-out structure, which increases the size of the package structure.
美國專利第2003/0168719號揭示有一種無外引腳式多 排導線架(multi - row leadframe),在中央承座環(paddle ring)之四周邊設有多排端子墊,内外排的端子墊係為兩 兩對向排列,無法以内引腳連接至該導線架同一侧之框 架,為了在製程中固定内排端子墊,請參閱美國專利第 2003/0 1 6871 9號之FIG. 9及FIG· 1〇(即該前案之第9及1〇 圖)’該些内排端子墊係以一連接部連接至該承座環,該 些外排端子墊係連接至該導線架之框架,在晶片黏結、打 線連接與封膠體形成之後,需要一道化學蝕刻步驟,將該 些内排端子塾與該承座%之間的連接部去除,使得封裝製 程變得複雜。此外,該些内外排端子墊與該封膠體之結合 力略顯薄弱。 ""口 【發明内容】U.S. Patent No. 2003/0168719 discloses a multi-row leadframe with no outer pins. There are multiple rows of terminal pads on the four perimeters of the central paddle ring, and the inner and outer rows of terminal pads. It is arranged in pairs, and the inner pins cannot be connected to the frame on the same side of the lead frame. In order to fix the inner row terminal pad in the manufacturing process, please refer to FIG. 9 and FIG. Of US Patent No. 2003/0 1 6871 9. · 10 (that is, Figures 9 and 10 of the previous case) 'The inner row terminal pads are connected to the socket ring with a connection portion, and the outer row terminal pads are connected to the frame of the lead frame, After wafer bonding, wire bonding and sealing compound formation, a chemical etching step is required to remove the connection between the inner row terminals 塾 and the socket%, which complicates the packaging process. In addition, the bonding force between the inner and outer row terminal pads and the sealing compound is slightly weak. " " Mouth [Inventive Content]
12367571236757
五、發明說明(2) „ 心 個第一内引腳與複數個第二内引腳係 間隔排列並連接在一框牟,I^ ^ ^ 丨腳係 引腳之間距係為固$,; — ::?:内!1腳與相鄰第二内 第-外接墊至該框架,以使η-第-内引腳之 之距離係大於在該第二内引 興4框木間 距離,並使該些第—外接::;第:接墊與該框架間之 間隔錯位排列,且該也第4引:之第二外接塾為 -内引腳與相鄰第二;^腳部寬度係大於第 要扇出設計而能達到高密度排列。仔。亥些内引腳不需 本發明之主要目的係在於提供一種半導體封求益 本發明之次一目的将尤於4a M ^ r ^ 弓丨腳4勺係在於棱供一種半導體封裝之無外 ::式導線架’在母一第一内引腳 張 錯位,該些第-内引腳與ί =二擴張打線塾係為間隔 並且在哕此m,第一内引腳間之間距係為相同, 間的間距係等於在該此第内引腳之延伸部之 之連接部之間的間距:::;=墊與相鄰第-内引腳 N捃度排列該些内引腳。 本發月之再一目的係在於提供一錄主道胁以壯> P 引腳式導線架,每一第一内引2料導體封裝之無外 外掊執,佶π兮此够 内引腳係以一連接部連接蹿第一 Α夕M pgiu : ^二第一外接墊與第二内引腳之第二外接墊丨 接右一 Μ仙# ^ ^ α。亥些第一内引腳之第二外接墊係連 传八別π成H笛糸通離該金屬框架,複數個半餘刻缺口 腳一内ϋ腳之連接部下表面與該第二内引 腳之延伸。Ρ下表面’以增進該些第—外接塾與第二外接墊 !236757V. Description of the invention (2) „The first inner pins and the plurality of second inner pins are arranged at intervals and connected to a frame, and the distance between the pins of the feet is fixed. —::?: Inner! 1 foot and the adjacent second inner-outer pad to the frame so that the distance between the η-th-inner pin is greater than the distance between the four frames in the second inner boom. And make these first-external ::; the first: the gap between the pad and the frame are misaligned, and this is also the fourth lead: the second external 塾 is-the inner pin and adjacent second; It is larger than the first fan-out design and can achieve high-density arrangement. The main purpose of the present invention is to provide a semiconductor package. The second purpose of the present invention is to be especially 4a M ^ r ^ The bow and foot 4 scoops are located on the edge for a semiconductor package without the outside :: The type lead frame is misplaced on the female first first pins, and the first-inner pins are spaced apart from the two expansion wires. Here, the distance between the first inner pins is the same, and the distance between them is equal to the distance between the connecting portions of the extensions of the second inner pins. ::: ; = The pad and the adjacent first-inner pin N are arranged in an array of these inner pins. Another purpose of this month is to provide a recorded main channel to strengthen > P-pin lead frame, Each first inner lead has no outer outer conductor package, and the inner pins are connected by a connecting part. First first evening M pgiu: ^ two first outer pad and second inner lead The second external pad of the foot is connected to the right one Μ 仙 # ^ ^ α. The second external pads of the first inner pins are successively transmitted into eight different pi into H flutes and pass away from the metal frame. The lower surface of the connecting part of the notch foot and the inner leg is extended with the second inner pin. The lower surface is used to enhance the first and second external pads and the second external pad! 236757
發明說明(3) 在封膠後之固定。 依本發明之i L <無外引腳 木、複數個第_肉2丨 _ 内弓丨腳及 係具有至少—聞 .ΒΒ 開口 ,該些第一内 為間隔排列於該開口周邊 内引腳之下表面係具有一 下表面係具有一第二外接 式導線架,其係 第二内引 引腳與該 至該金屬 複數個 並連接 包含有 腳,該 些第二 框架, 第一外接墊,每一第二 有一連接部,其係連接該 知在該些第一外接墊與該 些第二外接墊與該金屬框 列’並且每一第一内引腳 定,該些第一内引腳之連 相鄰第^一内引腳之間距, 位排列並且不需設計扇出 架。 墊,其中,每一第 内 些第一外接墊與 金屬框架之間的 架之間的距離, 與相鄰第二内引腳之間 接部寬度係大於該第一 以達到多排外接墊高密 内引腳連接至同一側之 該金屬 距離係 而呈間 一金屬框 金屬框架 内引腳係 每一第一 内引腳之 引腳係具 框架,使 大於在該 隔錯位排 距係為固 内引腳與 度間隔錯 金屬框 【實施方式】 參閱所附圖式’本發明將列舉以下實施例說明。 •依據本發明之一具體實施例,第丨圖係為一種無外引 腳式導線架之上表面局部示意圖,第2圖係為一種無外弓丨 腳式導線架之下表面局部示意圖,該無外引腳式導線架係· 主要包含有一金屬框架1〇、複數個第一内引腳2〇及複數個 第二内引腳3 0,對應於每一封裝單元,該金屬框架丨〇係具 有至少一開口 11,該些第一内引腳2〇與該些第二内引腳3〇 係間隔排列於該開口 11之周邊而連接於該金屬框架1 〇,在Description of the invention (3) Fixing after sealing. According to the present invention, i L < no outer pin wood, a plurality of _ flesh 2 丨 _ inner bow 丨 feet and at least-smell. Β openings, the first inside are arranged at intervals in the periphery of the opening to lead The lower surface of the foot has a lower surface with a second external lead frame, and the second internal lead pin is connected to the plurality of metal and includes a foot, the second frames, a first external pad, Each second has a connecting portion, which connects the first external pads, the second external pads, and the metal frame column, and each first inner pin is fixed, and the first inner pins are connected. The distance between adjacent first inner pins is arranged in a row and there is no need to design a fan-out frame. Pads, wherein the distance between each of the first inner pads and the frame of the metal frame, and the width of the junction between the first inner pads and the adjacent second inner pins are larger than the first pads to achieve a high density of multiple rows of outer pads. The metal distance between the pins connected to the same side is a metal frame with a metal frame. The inner pins are the frames of each of the first inner pins. Feet and Degree Spaced Metal Frame [Embodiment] Referring to the attached drawings, the present invention will enumerate the following embodiments. • According to a specific embodiment of the present invention, FIG. 丨 is a partial schematic diagram of the upper surface of a leadless lead frame without external pins, and FIG. 2 is a partial schematic diagram of the lower surface of a leadless leadframe with external leads. Leadless lead frame system · Mainly includes a metal frame 10, a plurality of first inner pins 20, and a plurality of second inner pins 30, corresponding to each packaging unit. The metal frame It has at least one opening 11. The first inner pins 20 and the second inner pins 30 are spaced apart from each other around the opening 11 and connected to the metal frame 10.
1236757 五、發明說明(4) 二施rtN該—導線架係以四方爲平無外㈣ 〇n leaded leadframe)說明。 每一内引腳20之下表面係具有-第-外接墊21, 外部電性導接,該些第一外接 :卜接=墊= 隔,列,…施例係以^二卜;= ί二ΠΓ與該些第二内引腳3。,其中,每 該金屬框j丨接部23 ’其係連接該些第—外接墊21與 二使得在該些第—外接墊21與該金屬框架10 待且右丄 較佳地,每-第二内引腳3〇 部3i,其係連接對應之第二外接墊31並遠離 等長,以拗1史得該些第一内引腳20與第二内引腳30為 此聯姓尸4^、電性功能,而在兩側第二内引腳3〇因配合該 二聯〜杯41之配置可不具有延伸部33。 再請參閱第1及2圖,該些第—内引腳2〇係與該些第二 内引腳30為間隔連接於該金屬框架1〇 一 == 鄰第二内引腳30之間距係為固定,該丄= =:?〜〇.3mmtt據之其中之-,又以固定在0.15丽| '1 二坠第一内引腳20之連接部23之寬度W1係為〇. 23mm i 、係大於每一第一内引腳20與相鄰第二内引腳30之 „ 4 上2(印參閱第1、3及4圖所示),再請參閱第i、3 及4圖’母一第一内引腳20之上表面係形成有一第一擴張1236757 V. Description of the invention (4) Ershi rtN This—The lead frame is based on the square as flat without outer lead (0n leaded leadframe). The lower surface of each inner pin 20 is provided with a first-external pad 21, which is electrically connected externally, and these first external pads are connected: pads = pads = partitions, columns, ... The embodiment is based on ^ two buds; = ί Two ΠΓ and the second inner pins 3. Wherein, each of the metal frame joints 23 ′ is connected to the first and second external pads 21 and 2 so that the first and second external pads 21 and the metal frame 10 are left and right, preferably, each The two inner pins 30, part 3i, are connected to the corresponding second outer pad 31 and away from the equal length, and the first inner pins 20 and the second inner pins 30 are obtained as the joint name 4 ^ Electrical functions, and the second inner pin 30 on both sides may not have the extension portion 33 due to the configuration of the coupler ~ cup 41. Please refer to FIGS. 1 and 2 again. The first-inner pins 20 and the second inner-pins 30 are connected to the metal frame at a distance from the first inner-pins 30 to the second inner-pins 30. For fixing, the 丄 = = :? ~ 0.3mmtt is based on one of them, and the width W1 of the connecting portion 23 of the first inner pin 20 is fixed at 0.15 Li | It is larger than 4 on 2 of each first inner pin 20 and adjacent second inner pin 30 (printed as shown in Figures 1, 3 and 4), and then please refer to Figures i, 3 and 4 ' A first expansion is formed on the upper surface of a first inner pin 20
12367571236757
打線塾2 2,其係對應於第一外接墊2 1且具有較大之面積, 並且每一第二内引腳30之上表面係形成有一第二擴張打線 墊32,其係對應於第二外接墊31且具有較大之面積,以供 打線銲線之連接,在本實施例中,請參閱第丨圖,該些第 一擴張打線墊22係與鄰近之第二擴張打線墊32係為間隔錯 位排列,使得在該些第一擴張打線墊22與相鄰第二内引腳 30之延伸部33之間的水平間距D1 (如第3圖所示)係等於在 該些第二擴張打線墊32與相鄰第一内引腳2〇之連接部2 3之 間的水平間距D2 (如第4圖所示),因此,較内排之第一外 接墊21與較外排之第二外接墊3丨將可高密度間隔錯位排列 並且能以無扇出型態等間距之第一内引腳2〇與第二内引腳L 3 0連接至同一側之金屬框架1 〇,此外,該些第一内^丨腳2 〇 之連接部23下表面係形成有一半钮刻缺口24(如第2及5圖 所示),並且該些第二内引腳3〇之延伸部33下表面亦形成 有一半蝕刻缺口 34 (如第2及6圖所示),以避免該些第一外 接塾21與第二外接墊31之電性短路,並且該些半蝕刻缺口 24、34能被一封膠體7〇密封,以增進第一内引腳2〇與第二 内引腳30在封裝構造内之固定。 請參閱第1、5及6圖,在本實施例中,該導線架另包 含有一晶片承座40,可以任意之形狀,如矩形或環狀,以 供晶片之黏貼,該晶片承座4〇係形成在該開口 1 i之中,並 且以複數個聯結桿41連接至該金屬框架1 〇。 請參閱第7圖,以上述之導線架製作一半導體封裝構 造時,一半導體晶片50係貼設於該導線架之晶片承墊4〇,The wire bonding pad 22 corresponds to the first external pad 21 and has a large area, and a second expanded wire bonding pad 32 is formed on the upper surface of each second inner pin 30, which corresponds to the second The external pad 31 has a large area for connection of wire bonding wires. In this embodiment, please refer to FIG. 丨, the first expansion wire bonding pads 22 and the adjacent second expansion wire bonding pads 32 are The spacing is arranged so that the horizontal distance D1 (as shown in FIG. 3) between the first expansion bonding pads 22 and the extensions 33 of the adjacent second inner pins 30 is equal to the number of the second expansion bonding wires. The horizontal distance D2 between the pad 32 and the connecting portion 23 of the adjacent first inner pin 20 (as shown in FIG. 4). Therefore, the first outer pad 21 and the second outer pad 21 The external pad 3 丨 will arrange the first inner pins 20 and the second inner pins L 3 0 which can be arranged at high density and are staggered and can be equally spaced in a fan-out type to the metal frame 1 0 on the same side. In addition, The lower surface of the connecting portions 23 of the first inner feet 2 0 is formed with a half button notch 24 (as shown in Figs. 2 and 5), and Half-etching notches 34 are also formed on the lower surfaces of the extensions 33 of the second inner pins 30 (as shown in Figures 2 and 6) to avoid the electrical properties of the first external pads 21 and the second external pads 31. Short circuit, and the half-etched notches 24 and 34 can be sealed by a gel 70 to improve the fixing of the first inner pin 20 and the second inner pin 30 in the package structure. Please refer to FIGS. 1, 5 and 6. In this embodiment, the lead frame further includes a wafer holder 40, which can be of any shape, such as rectangular or ring shape, for the adhesion of the wafer. The wafer holder 4 〇 A tie is formed in the opening 1 i and is connected to the metal frame 10 with a plurality of coupling rods 41. Please refer to FIG. 7. When a semiconductor package structure is manufactured by using the lead frame described above, a semiconductor wafer 50 is a wafer pad 40 attached to the lead frame.
第12頁 1236757 五、發明說明(6) 該晶片50係具 銲墊51係以複 2 2,以複數個 二内引腳30之 體70密封該晶 該晶片50、該 體7 0係包覆該 24、該些第二 導線架之其它 墊21與第二外 隔錯位排列, 側邊72切割分 形成之半導體 下得到高密度 第二内引腳30 内引腳20與第 較佳的電性功 因其連接部2 3 更能穩固地結 接部姓刻去除 本發明之 為準’任何熟 圍内所作之任 有複數個在其主動面之銲塾51 數個第一銲線6 1連接至之第一 第二銲線62連接該晶片50之其 第二擴張打線塾32,再以一電 片50與該些第一銲線61、第二 些第一内引腳20及該些第二引 些第一内引腳20之連接部23之 内引腳30之延伸部33之半触刻 半蚀刻部位,該些間隔錯位排 接墊22係顯露於該封膠體7〇之 在該封膠體7 0固化之後,沿著 離該些第一内引腳20與第二内 封裝構造係可在一微小無外引 排列之外接墊21、2 2,該些第 不需要作扇出設計,並且在該 二内引腳3 0之間的間距係為固 能’同時該些第一内引腳2〇與 之半蚀刻缺口 24與延伸部33之 合於該封膠體7〇,製程上也不 步驟’顯具實用性。 保護範圍當視後附之申請專利 知此項技藝者,在不脫離本發 何變化與修改,均屬於本發明 ’其中部份之 擴張打線墊 它銲墊51至第 絕緣性之封膠 銲線62並固定 腳3 0,該封膠 半触刻缺口 缺口 34以及該 列之第一外接 底面71且呈間 該封膠體70之 引腳30,最後 腳之封裝尺寸 一内引腳20與 些間隔之第一 定,將可表現 第二内引腳30 半姓刻缺口 3 4 需要額外的連 I 範圍所界定者 明之精神和範 之保護範圍。Page 12 1236757 V. Description of the invention (6) The wafer 50 is provided with pads 51 and 22, and the body 70 with a plurality of two inner pins 30 is used to seal the wafer 50 and the body 70. The 24, the other pads 21 of the second lead frames are arranged in a misalignment with the second outer spacer, and a semiconductor formed by cutting the side 72 to obtain a high-density second inner pin 30, the inner pin 20, and the first better electrical properties. The function is because the connecting part 2 3 can be more securely connected to the last part. The name of the present invention is removed. Anything made in any enclosure is a plurality of welding pads on its active side. 51 Several first welding wires 6 1 connection The first and second bonding wires 62 are connected to the second expanded bonding wire 32 of the chip 50, and then an electric chip 50 is connected to the first bonding wires 61, the second first inner pins 20, and the first bonding wires 62. The two half-etched and half-etched parts of the extension part 33 of the inner lead 30 of the first inner lead 20 and the lead part 30 are exposed in the sealant 70 in the seal. After the gel 70 is cured, the pads 21 and 22 can be arranged along a small non-lead-out arrangement along the first inner pins 20 and the second inner package structure. These sections do not need to be fan-out design, and the distance between the two inner pins 30 is solid energy. At the same time, the first inner pins 20 and the half-etched notch 24 and the extension 33 are combined. The sealant 70 has no practical steps in the manufacturing process. The scope of protection is subject to the attached patent application knowing that this artisan, without departing from the changes and modifications of the present invention, is part of the invention's part of the expanded wire bonding pad, its bonding pad 51 to the insulating sealing wire 62 and fixed foot 30, the sealant half touches the notch 34 and the first external bottom surface 71 of the row with the pins 30 of the sealant 70, and the package size of the last foot is an inner pin 20 with some spaces The first determination will be able to express the second inner pin 30 half surname carved gap 3 4 need additional even the spirit and scope of protection as defined by the I range.
第13頁 1236757Page 13 1236757
1 〇金屬框架 20 第〆内引腳 23連接部 30 第二内引腳 33延伸部 40 晶片承座 50晶片 61第一銲線 71底面 D1 間距 11 開 〇 21 第 外接 24 半 刻缺 31 第 外接 34 半 4k 刻缺 41 聯 結 桿 51 銲 墊 62 第 鮮線 72 側 邊 D2 間 距 張打線塾 張打線塾 Φ 墊 口 22 第一 墊 32 第二 〇 70 封膠 W1 寬度1 〇 Metal frame 20 First inner pin 23 connection portion 30 Second inner pin 33 extension portion 40 Wafer socket 50 Wafer 61 First bonding wire 71 Bottom surface D1 Pitch 11 Open 〇21 External connection 24 Half-cut 31 External connection 34 half 4k notch 41 connecting rod 51 solder pad 62 first fresh line 72 side D2 pitch Zhang Dian 塾 Zhang Dian 塾 Φ gasket opening 22 first gasket 32 second 〇70 sealant W1 width
Claims (1)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093108963A TWI236757B (en) | 2004-03-31 | 2004-03-31 | Leadframe without outer leads for semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW093108963A TWI236757B (en) | 2004-03-31 | 2004-03-31 | Leadframe without outer leads for semiconductor package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| TWI236757B true TWI236757B (en) | 2005-07-21 |
| TW200532881A TW200532881A (en) | 2005-10-01 |
Family
ID=36675037
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| TW093108963A TWI236757B (en) | 2004-03-31 | 2004-03-31 | Leadframe without outer leads for semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| TW (1) | TWI236757B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114864531A (en) * | 2021-02-03 | 2022-08-05 | 瑞昱半导体股份有限公司 | Integrated circuit lead frame and semiconductor device thereof |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI761052B (en) * | 2021-01-28 | 2022-04-11 | 瑞昱半導體股份有限公司 | Integrated circuit lead frame and semiconductor device thereof |
-
2004
- 2004-03-31 TW TW093108963A patent/TWI236757B/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114864531A (en) * | 2021-02-03 | 2022-08-05 | 瑞昱半导体股份有限公司 | Integrated circuit lead frame and semiconductor device thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW200532881A (en) | 2005-10-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TWI270966B (en) | Leadframe, resin-molded semiconductor device including the leadframe, method of making the leadframe and method for manufacturing the device | |
| TWI252573B (en) | Process for manufacturing leadless semiconductor packages including an electrical test in a matrix of a leadless leadframe | |
| CN103155136B (en) | Singulation of IC packages | |
| US8736042B2 (en) | Delamination resistant device package having raised bond surface and mold locking aperture | |
| JP2007503721A (en) | Reversible leadless package and its manufacture and use | |
| US9679833B2 (en) | Semiconductor package with small gate clip and assembly method | |
| TW563232B (en) | Chip scale package and method of fabricating the same | |
| CN104241238B (en) | Semiconductor die package based on lead frame | |
| CN101308830A (en) | Lead frames for semiconductor packaging | |
| CN110690123A (en) | Thermal leadless array package with die attach pad locking feature | |
| TWI792588B (en) | Semiconductor package | |
| TWI485819B (en) | Package structure and manufacturing method thereof | |
| TW202101618A (en) | Semiconductor package and electronic system | |
| TW533566B (en) | Short-prevented lead frame and method for fabricating semiconductor package with the same | |
| CN103681585A (en) | Lead frame, QFN (Quad Flat No Lead) packaging body, and method for forming QFN packaging body | |
| TWI226122B (en) | Multi-chip package with electrical interconnection | |
| TWI236757B (en) | Leadframe without outer leads for semiconductor package | |
| JP2008532277A (en) | Integrated circuit package device with improved bonding pad connection, lead frame and electronic device | |
| JPH08139257A (en) | Surface mount semiconductor device | |
| CN101091247B (en) | Dual Flat No Lead Semiconductor Package | |
| CN103311210A (en) | Lead frame used for assembling semiconductor device | |
| JPS5927558A (en) | Lead frame for semiconductor device | |
| TWI301316B (en) | Chip package and manufacturing method threrof | |
| CN213401157U (en) | An in-line semiconductor device with pin-cut ribs | |
| CN113394187A (en) | Leadless semiconductor package and method of manufacture |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| MK4A | Expiration of patent term of an invention patent |