TWI236100B - Method of forming a dual damascene copper wire - Google Patents

Abstract

The present invention provides a method for forming at least one wire on a substrate. The substrate includes at least one conductive region. An insulating layer is disposed on the substrate. At least one recess in the insulating layer exposes the conductive region. A barrier layer is formed on a surface of the insulating layer and the recess first. A continuous and uniform conductive layer is then formed on a surface of the barrier layer. A seed layer is thereafter formed on a surface of the conductive layer. Finally, a metal layer filling up the recess is formed on a surface of the seed layer.

Description

1236100 V. Description of the Invention (1) [Technical Field] The present invention provides a method for manufacturing a dual-inlaid copper wire, particularly a method that can provide good copper filling (C ugap-fi 1 1 ing) capability and can expand the process window ( processwindow) manufacturing method. [Previous technology] The dual damascene process is a method that can simultaneously form a metal wire and a plug above and below a stacked structure in a dielectric layer. The dual damascene structure mainly includes an upper trench (t re nch) and the following Layer contact holes (via ho 1 e), used to connect different components and wires between layers in a semiconductor wafer, and use the inner interlayer dielectric | materials (int er-1 ay er die 1 ectrics) to isolate them from other components 隹. Because the resistance value of copper is smaller than that of Shao, it can carry a larger current on a smaller surface area, allowing manufacturers to produce faster, denser circuits, and improve the efficiency of about 30-4 0% chips. Therefore, it has become a mainstream technology to use a dual damascene structure to fill copper to produce a dual damascene copper wire. As the development of integrated circuits becomes more sophisticated and complex, how to effectively reduce the complexity of the process and increase the yield of the dual mosaic structure without increasing the cost of production is a very important issue in the current integrated circuit manufacturing process. Please refer to Fig. 1 to Fig. 7. Fig. 1 to Fig. 7 are schematic diagrams of a conventional method for making a pair of inlaid copper wires. As shown in Figure 1, the semiconductor wafer 10 contains

1236100 V. Description of the invention (2) A substrate 12 is provided. A conductive layer 14 is disposed in a predetermined area of the surface layer of the substrate 12 and the surface of the conductive layer 14 is covered with silicon nitride.的 保护 层 16。 The protective layer 16. Since the other components of the base 12 calendar are not the focus of the dual damascene process, for the convenience of explanation, other components of the base 12 surface are not shown in Figure 1 and other illustrations. In addition, the taste surface of the semiconductor wafer 1 further includes a low dielectric constant material layer 18, a protective layer (passivati ○ 1 ayer) 2 〇, a low dielectric constant material layer 22, and a hard cover curtain layer 2 4 Sequentially stacked on the surface of the protective layer. The low dielectric constant material layers 18 and 22 are generally spin-coated (31) 111 ^ a coat i ng) low dielectric constant materials, such as HSQ or FLARE, for low dielectric constant materials (especially organic low dielectric constant). Material ^ it box is made of a dense material with a protective layer MG electric hardness of 18. The same reason, for silicon or nitrogen oxidation to re; 〖· human 疋 by ammoniated 'silicon (si 14 con oxy -nitrih ❿. ί ί :::: After forming the stacked structure as shown in Figure 1, then ^ City Shadow and Etching Process is opened on the hard cover, Meng Qianzhe = Material layer 2 ... As shown in FIG. 3, another photolithography process is performed on the photoresist layer 26 in the soil.

1236100 V. Description of the invention (3) ~ 'An opening 27 is formed in the photoresist layer 26 and reaches the surface of the low dielectric constant material layer 22. Because the opening 27 is used to define a double-layered mosaic; the pattern of the hole 'so the width of the opening 27 must be smaller than the width of the opening μ, and the opening 27 is provided inside the opening 25 to facilitate subsequent use ^ ^ Aligned contact (sel fa 1 igned contact) etching process to form a dual private structure. Then, as shown in FIG. 4, a first etching process is performed, for example, an anisotropic (dry isoetch) dry etch process. The doorway is directly removed and not covered by the photoresist layer 26. And a protective layer 20 to form an opening 28 that reaches the surface of the low-dielectric-constant material. Subsequently, a photoresist stripping process is performed to completely remove the first resist, as shown in Figure 5 and 20, as well as being protected by a hard cover. The material layer 20, the protection 22, and the protection and the upper layer 1 8 The contact hole engraving process uses a protective layer (layer), and simultaneously removes the protective layer covered by the uncovered layer 22 and the low dielectric constant curtain layer 24 and penetrates the trench 30 of the low dielectric constant material layer. The dual-mosaic structure of the dielectric constant material surface is shown below. Next, a second dielectric layer 16 is used as a stop layer (st oop layer 24 and the low dielectric constant material 18 'is covered before removing the unhardened cover. The protective layer 16 forms a protective layer 16 by self-alignment under the upper-layer trench 30 of the dual damascene structure of a consistent layer 20 at the same time to the conductive layer 丨 4 (via ho 1e) 31.

Page 10 1236100 V. Description of the invention (4) As shown in FIG. 6, a deposition process is then performed to form a barrier layer 32 on the surface of the semiconductor wafer. The barrier layer 32 is composed of silicon nitride to prevent the copper (copper, Cu) or tungsten (tungsten, W) from each conductive layer from diffusing into the silicon, and the barrier layer 32 may also be It is composed of silicon nitride and tantalum / titanium / titanium nitride (butyl 3/1 ^ / 1 ^^) composite materials to increase the subsequent coverage between the metal layer on the dual damascene structure and the dual damascene structure. Adhesive force. After that, a re-spu 11 er process is performed repeatedly to remove a part of the barrier layer 32 covering the surface of the conductive layer 14 so that the surface of the conductive layer [4] is blown out. Another physical A vapor deposition (Physi Ca 1 Vapor deposition, PVD) process is used to form a Cu seed layer 34 on the i-side of the semiconductor wafer, so that the copper seed layer 34 covers and is exposed. Conductive layer 14 and barrier layer 32. In addition to providing a current-conducting path (conductjvepath), the purpose of making the copper seed layer 34 is to provide a copper nucleation layer in advance to facilitate subsequent electrical bond copper. Can be nucleated and grown on it. Then a copper electric forging is performed. (ECP) process, a metal layer 36 is formed on the surface of the copper seed layer 34, and gold I and the lower contact hole 31 are formed. As shown in FIG. 7, a chemical mechanical polishing process is then performed, using the barrier layer 32 as the End point of polishing (end — p int), remove the areas covering the upper trench 30 and the lower contact hole 3 丨 metal layer 36 and copper seed layer 34, and leave the upper trench 30 and the lower layer The surface of the metal layer 3 6 in the contact hole 3 丨 is approximately tangent to the surface of the barrier layer 3 2 outside the upper trench 30 0. 1236100 V. Description of the invention (5) Finally, a protective layer is formed on the surface of the semiconductor wafer 10 38, such as a silicon nitride layer, to complete the production of dual-inlaid copper wires. Although the low-dielectric constant material and the low-resistance copper wire form a perfect match in terms of material properties, it will be able to Effectively reduce the RC delay (RC de 1 ay) effect caused by signal transmission between wires when the component size is miniaturized. However, such a perfect material combination has encountered a great bottleneck in the manufacturing process. Due to the copper seed layer 3 4 series were physically vapor deposited The thin film produced by the physical deposition process and the physical vapor deposition process does not provide good step coverage to cause overhang, which causes the copper seed layer 34 to be discontinuous and non-uniform ( not con ti nuous and no t un if 〇rm) / ^ ^ ^ ^ ^ A. ^ ^ voids are generated in the metal layer 36 to be structured, which is the so-called copper filling in the industry (C ugap-fi 1 1 ing) Bad problems, and the poor adhesion force of the seed layer 34 to the barrier layer 32 caused by copper b often causes the metal layer 36 to peel off during subsequent chemical mechanical polishing (pee 1 i ng) ) Phenomenon, the yield of King 4 ring double inlaid copper wire is huge. Please refer to Fig. 8. Fig. 8 is a schematic diagram showing a defect caused by a pair of inlaid copper wires. As shown in Figure 8, the phenomenon of overhanging the copper seed layer 42 is most likely to occur at the opening of the contact hole 44 and is prone to discontinuities at the bottom of the contact hole 44. Therefore, the growth of the lower layer and the bottom layer is often caused when copper plating It is slower, and the 4% \ Λ method becomes the bottom up filling behavior. Therefore, after the power ore is completed, holes 48 will be generated in the metal layer 46.

Page 1236100 V. Explanation of the invention (6) Therefore, how can a new method of making double-inlay copper wire be developed, which can be used in small line width without increasing the complexity of the process? ) And the double-inlaid structure with high aspect ratio, the copper conductive layer is successfully filled, and the double-inlaid copper wire with low resistance, low surface roughness, and excellent adhesion is produced. Important subject.

Page 13 1236100 V. Description of the invention (7) Overhang phenomenon, therefore, the continuity and uniformity of the copper seed layer, and the ability of the copper seed layer to adhere to the barrier layer will be improved. In addition, the conductive layer itself has excellent continuity, uniformity and good current conduction capacity. In the subsequent copper electroplating process, the phenomenon of overall conduction unevenness will be significantly improved, making the current distribution very uniform, and Improve copper filling capacity. At the same time, under the premise that the current conduction of the conductive layer is very uniform, the process window of the subsequent copper electroplating process can also be significantly enlarged. In addition, when the copper seed layer is an alloy layer, the alloy atoms in it will be adsorbed on the grain boundaries, which will effectively prevent the diffusion of steel atoms along the grain boundaries, which will greatly improve the reliability of the product (re 1 iabi 1 ity) performance. [Implementation method] Please refer to FIGS. 9 to 15, which are schematic diagrams of a method for manufacturing a pair of inlaid copper wires according to the present invention. As shown in FIG. 9, the semiconductor wafer 100 includes a substrate 102, a conductive layer 104 is disposed in a predetermined area of a surface layer of the substrate 102, and a surface of the conductive layer 104 is covered with a passivation layer 106. Since other components on the surface of the substrate 102 are not the focus of the dual damascene process, they are not shown in Figures 9 to 15 for easy explanation. In addition, the surface of the semiconductor wafer 100 further includes a low-dielectric-constant material layer 108, a protective layer 112, a low-dielectric-constant material layer 1 1 4 and a hard mask layer 1 1 6 sequentially stacked on the protective layer. 1 0 6 surface. The protective layer 106 is generally composed of silicon nitride, and is used as an etch stop layer (e t c h s t ο p 1 a y e r), so that when the contact hole # is etched to the bottom,

1236100 on page 14 -------- ss V. Description of the invention (8) Excessive description of r's extension ο ----------___ ^ — --------- ------- 一-〇ver etch) and severe damage to the lower layer of the coating. Low coating: low dielectric constant material layer 114 is usually caused by the possibility of fusing and f ί t. ^ Called or FLARET, but

Constant material d 1 day | I _ thousand; 'Earth product (CVD) formed. Because of the low-dielectric IU, it must be formed in the dense layer of low-density and low-density clothing. The surface is covered with a hard stomach produced by a lower dielectric constant material layer 108 such as lice The silicon layer is reinforced with 1 14 and the surface is also covered with ΪI. The low-dielectric constant material layer hard covers the curtain layer 1 16 and the hard if ^ i 1 ^ is used as shown in Fig. 10, and the formation is shown in Fig. 9 The teaching of the blasting of prisoners was carried out-lithography and rice engraving process on the hard cover layer ^ 6 °, or the constant material layer ⑽ ^ = the pattern of the grooves above the structure. Subsequently, as shown in FIG. 10, a photoresist layer i! 8 is coated on the surface of the ^ f two-body wafer 100, and another two steps are performed to form a surface of the photoresist layer 11 8 that reaches the mouth of the low dielectric constant material. Opening Η 7. Since the mouth π 7 hurts the field—the sound of the pen material layer 1 1 4 in η μ solid & 1 is used to define a double mosaic structure 夂 I :, so the width of the opening σ 117 must be less than The opening is seen from the ιΛΙ port 117 and is placed inside the opening 115 to facilitate the rear, back, and back. The self-aligned contact etching process is used to form a dual damascene structure.

Page 15 1236100. ~ ^-. ~~~-^ ______ V. Description of the invention (9) Shitu X—shown 'Next, dry etching f * is performed one by one, and π is etched by the day's brother.' The dielectric layer covered by a non-finding layer 18 is removed vertically and the photoresist layer is not lowered; the cladding / material layer 1 1 4 and the protective layer 1 2 are in the form of -1, >low; The openings 1 2 2 on the surface of the material layer 108. The photoresist layer 118 is subsequently removed. (Resist stripping), in order to completely go into the next m— / jinbu // then perform a second 1 insect engraving process, and use the protective layer 106 as a stop layer (stoop iayer), At the same time, the low dielectric constant material layer 114 and the electrical material layer covered by the mask layer 116 are removed at the same time. Then, the unprotected layer 112 and the protective layer 1 dielectric constant material layer are removed. 4 and the protective layer U 2 of the double-Qin ^ slot 1 2 4, and the upper layer, the constant material layer 1 08 and the protective layer 1 0__ contact hole i 26 of the lower layer of the mosaic structure. In fact, the middle protection “112” is also used as an etch stop layer, so that the depth of the groove 24 can be accurately controlled and uniformized. If the ending layer of this name is not added, due to the non-uniformity of dry and insect carving (n 〇 n _ u n 丨 f 〇 r m i t y), microloading effect and aspect ratio effect (aspeci

ratio dependence etching effect, ARDE effect), etc., often make the depth of the trenches 1 2 4 difficult to control and inconsistent.

1236100 V. Description of the Invention (ίο) As shown in FIG. 14, a deposition process is then performed to form a barrier layer 1 2 8 on the surface of the semiconductor wafer i 00. The barrier layer 1 2 8 is used to prevent the copper (Cu) or tungsten (tungsten, w) in each conductive | from diffusing into the silicon. The barrier layer 1 2 8 may be a silicon nitride layer. May be a titanium nitride layer (TiN layer), a nitride nitride layer (TaN layer), or a nitride button / button (tanta 1 um, Ta) composite metal layer, used to Increase the adhesion between the metal layer and the dual-mosaic structure that subsequently cover the dual-mosaic structure. After that, a repeated sputtering process is performed to remove a part of the barrier layer 128 covering the surface of the conductive layer 104 so that the surface of the conductive layer 104 is exposed. Can then perform a chemical vapor deposition process or a layer deposit ion process to open a continuous conductive layer (cont i nuous and un if orm) on the surface of the barrier layer 128 (conduc ti ve 1 ay er) 1 3 2 and the conductive layer 1 3 2 covers the exposed conductive layer 104. The conductive layer 13 2 is usually an aluminum layer (a ^ = 1 ay er) or a crane layer (tungs t en 1 ay er), and the thickness of the conductive layer 13 2 is between 5 and 4 0 0 angstroms ( A) between. In fact, the temperature of any process is below 400. C. Films with good conductivity and step coverage and excellent adhesion to the barrier layer 1 2 8 may be used as the conductive layer 1 3 2. A physical vapor deposition process is further performed to form a copper seed layer 134 having a thickness of 5 to 2000 angstroms on the surface of the semiconductor wafer 1000 so that the copper seed layer 134 covers the conductive layer 132. The copper seed layer 134 is composed of pure copper or a copper alloy. The purpose of making copper seed layer 13 4 is

1236100 V. Description of the invention (11) One-~ ____________ ^ is to provide current in addition to a conductive path, and ^ to provide a nucleation layer of copper for subsequent electroplating ^, the purpose is to be the leader. Then, a steel electroplating process is performed, and a metal layer 136 is nucleated and formed on θ = j, and the surface of the metal layer 134 is in contact with the hole 126. Full upper trench 124 and lower At this time, since the conductive layer 132 has been advanced first, the chemical vapor deposition process fights the conductive layer of the copper seed layer 1 34! 32 has better step coverage, and the thickness of the sublayer can be reduced accordingly. Therefore, it is changed to ^ ^ 13 ^ ^ ^ ^ ^ ^, which is a layer 13 that uses the private and copper sun seed layer 134. . In addition, the conductive layer 1 3 2 has a very good I degree. When the copper power mining process is performed later, the overall conductivity unevenness will be significantly improved. 'Make the current distribution uniform, and then improve the copper filling capacity. As shown in Fig. 15, a chemical mechanical polishing process is then performed, using the barrier layer 1 2 8 as the polishing end point, and removing the metal layer 1 36 and the copper crystal covering the areas other than the upper trenches 1 2 4 and the lower contact holes 1 2 6 The seed layer 1 3 4 and the conductive layer 1 3 2 ′ and the surface of the gold lip layer 136 remaining in the upper trench 1 2 4 and the lower contact hole 1 2 6 are approximately similar to the surface of the barrier layer 128 outside the upper trench 124. Qi Qi. Finally, a protective layer 138 is formed on the surface of the semiconductor wafer 100, such as a silicon layer, to complete the fabrication of the dual damascene copper wires.

Page 1236100 V. Description of the invention (12) It is worth mentioning that the 'conductive layer 1 0 4 is not limited to the shape and position shown in FIG. 9 to FIG. 15. Since the conductive layer 1 0 4 may be a transistor (transi S t 〇r) source (s 〇 urce), a transistor's gate (gate), electric solar and solar cells> and drain (lower level wire), a The ianding pad is a resistor, so its shape and position can be changed accordingly. In addition, the method of the present invention can be applied to a trench first dual-embedding process as shown in FIGS. 9 to 15 as well as a via first dual-embedding process. The pattern of the copper plug is etched first, and then the pattern of the copper wire is etched, and the other parts are similar to the embodiment of the present invention. At the same time, the B-month method of the present invention can also be applied to the double-embedding process of auto-alignment (se 1 f -a 1 i gned). The rest of the graphics required for the contact hole are similar to those of the dual-embedding process for the trench first and the dual-embedding process for the dielectric window first. In addition, the method of the present invention can also be applied to a s1 substrate, a SOI substrate. Because the method of making a dual-inlaid copper wire in the present invention is to form a conductive layer with excellent conductivity and better step coverage below the copper seed layer to reduce the thickness of the copper seed layer and further improve The overhang phenomenon of the copper seed layer, so that the continuity and uniformity of the copper seed layer, and the adhesion ability of the copper seed layer to the barrier layer will be improved. Plus

Page 1236100 V. Explanation of the invention (13) The conductive layer itself has excellent continuity, uniformity and good current conduction capacity. In the subsequent copper electroplating process, the phenomenon of overall uneven conduction will be significantly improved. Make the current distribution uniform, and then improve the copper filling ability. When the method of the present invention is applied in actual production, the copper filling ability of the dual-mosaic structure with small line width and high aspect ratio can be improved, and a dual-mosaic copper wire with low resistance, low surface roughness, and excellent adhesion can be produced. Compared with the conventional technology, the method for making a dual-inlaid copper wire according to the present invention is to form a conductive layer with excellent conductivity and better step coverage under the copper seed layer to reduce the thickness of the copper seed layer. , And thus improve the overhang of the copper seed layer. Therefore, the continuity and uniformity of the copper seed layer, and the adhesion ability of the copper seed layer to the barrier layer will be improved. In addition, the conductive layer itself has excellent continuity, uniformity, and good current conduction capacity. Therefore, in the subsequent copper electroplating process, the overall conductivity unevenness will be significantly improved, making the current distribution very uniform. This improves copper filling capacity. At the same time, under the premise that the current conduction of the conductive layer is very uniform, the process window of the subsequent copper electroplating process can also be significantly enlarged. In addition, when the copper seed layer is an alloy layer, the alloy atoms therein will be adsorbed on the grain boundaries, thereby effectively preventing the diffusion of copper atoms along the grain boundaries, which will greatly improve the reliability of the product (re 1 iabi 1 ity) Performance 0 The above description is only a preferred embodiment of the present invention. Any equivalent changes and modifications made in accordance with the scope of the invention (14) in accordance with the application of the present invention 1236100 shall be covered by the patent of the present invention. range. 1236100 Brief description of the drawings Brief description of the drawings Figures 1 to 7 are schematic diagrams of a conventional method for making a pair of inlaid copper wires. FIG. 8 is a schematic diagram showing defects caused by a conventional double-inlaid copper wire. Figures 9 to 15 are schematic diagrams of a method of making a double inlaid copper wire according to the present invention. Explanation of symbols of the drawings 1 10 semiconductor wafer 12 substrate 14 conductive layer 16 protective layer 18 low dielectric constant material layer 20 protective layer 22 low dielectric constant material layer 24 hard mask layer 2 6 photoresist layer 2 8 opening 30 groove Slot 31 Contact hole 32 Barrier layer 3 4 Copper seed layer 36 Metal layer 3 8 Protective layer 42 Copper seed layer 44 Contact hole 46 Metal layer 48 Hole 100 Semiconductor wafer 102 Substrate 104 Conductive layer 106 Protective layer 108 Low dielectric Constant material layer 112 Protective layer 115 Low dielectric constant material layer 115 On a

Page 22 1236100 117 Opening 122 Opening 1 2 6 Contact hole 132 Conductive layer 13.6 Metal layer pattern simple description 1 1 6 Hard cover curtain layer 1 1 8 Photoresist layer 1 2 4 Trench 1 2 9 Barrier layer 1 3 4 Copper seed layer 1 3 8 Protective layerlimi Page 23

Claims (1)

1236100 VI. Scope of Patent Application '1 · A method for making at least one wire on a substrate, the substrate includes at least one conductive region, an insulating layer is disposed on the substrate, and the insulating layer includes There is at least one recess that exposes the conductive region. The method includes the following steps: forming a barrier layer on the surface of the insulating layer and the recess; and forming a barrier layer on the surface of the barrier layer A continuous and uniform conductive layer; forming a seed layer (seed 1 ay er) on the surface of the conductive layer; and forming a metal layer on the surface of the seed layer, And the metal layer completely fills the C3 slot. 2. A method such as applying for patent No. 1 in the scope of a semiconductor semiconductor wafer (semi conductor wafer) or a silicon substrate (si 1i c0n-〇n-i nsu1 a tor subs trate, SO I substraΐe). 3. The method according to item 1 of the patent application range, wherein the conductive region includes a source (sour ce) of a transistor, a gate of a transistor, and a drain of the transistor Extremely diligently "lower level wire (lower * level wire), -ianding pad (resisting pad) or a resistance (res i stor) 0 4" method of the scope of patent application, where the concave The trough is a pair of via holes (dual damascene). Page 24 1236100 6. Application for Patent Scope 5. The method of applying for the scope of patent application item 1, wherein the barrier layer includes a silicon nitride layer, a titanium nitride layer (TiN) layer), a nitride group layer (TaNum layer), or a nitride group / Group (Tatalum, Ta) composite metal layer. 6. The method of claim 1, wherein the conductive layer is an aluminum layer or a tungsten layer. 7. The method of claim 1 in which the thickness of the conductive layer is between 5 and 400 angstroms (A). 8. The method according to item 7 of the scope of patent application, wherein the method for forming the conductive layer comprises chemical vapor deposition (CVD) or atomic layer deposition (CVD). 9. The method of claim 1, wherein the seed layer is a copper layer formed by a physical vapor deposition (PVD) process. 10. The method according to item 1 of the scope of patent application, wherein the seed layer is a copper alloy layer formed by a physical vapor deposition process. Page 25 1236100 6. Scope of Patent Application 1 1 The method of the first scope of patent application, wherein the thickness of the seed layer is between 5 and 2000 angstroms (A). 1 2 · The method according to item 1 of the patent application scope, wherein the metal layer is formed by an electric copper plating (ECP) process. 13. · A method of making at least one dual damascene wire (wire) on a substrate, the substrate including at least one conductive region, an insulating layer disposed on the substrate, and the insulating layer The method includes at least one trench pattern (tr ench pa 11 er η) and a contact hole pattern (via ho 1 e pattern) stacked on top of each other and exposing the conductive region. The method includes the following steps: in the insulating layer, the trench A barrier layer is formed on the surface of the pattern and the contact hole pattern; a continuous and uniform (cont i nuous and uniform) conductive layer (c ο nducti V e 1 ayer) is formed on the surface of the barrier layer. Forming a seed layer (seed 1 ayer) on the surface of the conductive layer; and forming a metal layer on the surface of the crystal hawthorn layer, and the metal layer completely fills the trench pattern and the contact hole pattern. 1 4. The method according to item 13 of the scope of patent application, wherein the substrate comprises a semiconductor conductor wafer or a silicon-on-insulator substrate (SOI substrate). Page 26 1236100 6. Application for Patent Scope 15: The method of item 13 of the patent application scope, wherein the conductive area includes a source of a transistor and a gate of a transistor ), A transistor drai η, a lower level wire, a landing pad, or a resistor. 16. The method according to item 13 of the patent application scope, wherein the barrier layer comprises a silicon nitride layer, a titanium nitride layer (TiN layer), and a tantalum nitride layer Layer (t an ta 1 um nitri de 1 ay er, TaN 1 ay er) or a tantalum nitride / tantalum (Tatalum, Ta) composite metal layer. 17. The method according to item 13 of the scope of patent application, wherein the conductive layer is a coating layer (a 1 um i num 1 ay er) or a tungsten layer (tungU 1 8). The method of 3, wherein the method of forming the conductive layer includes chemical vapor deposition (CVD) or atomic layer depositi (n), and The thickness is between 5 and 400 Angstroms (A). 1236100 6. Scope of patent application (A). 20. The method according to item 13 of the patent application range, wherein the seed layer is a copper alloy layer formed by a physical vapor deposition process, and the thickness of the seed layer is between 5 and 2 0 0 Egypt (A). 2 1. The method according to item 13 of the scope of patent application, wherein the metal layer is formed by an electric copper plating (ECP) process. Page 28